STM32L562xx
Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,
165DMIPS, up to 512KB Flash, 256KB SRAM, SMPS, AES+PKA
Datasheet - production data
Features
Ultra-low-power with FlexPowerControl
• 1.71 V to 3.6 V power supply
UFQFPN48 (7 x 7 mm)
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
LQFP100(*) (14 x14 mm)
LQFP144 (20 x 20mm)
• -40 °C to 85/125 °C temperature range
• Batch acquisition mode (BAM)
• 187 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
• 17 nA Shutdown mode (5 wakeup pins)
FBGA
UFBGA132 (7 x 7 mm)
• 108 nA Standby mode (5 wakeup pins)
WLCSP81 (4.36 x 4.07 mm)
(*): Silhouette shown above.
• 222 nA Standby mode with RTC
• 3.16 μA Stop 2 with RTC
Memories
• 106 μA/MHz Run mode (LDO mode)
• Up to 512-Kbyte Flash, two banks read-whilewrite
• 62 μA/MHz Run mode @ 3 V
(SMPS step-down converter mode)
• 5 µs wakeup from Stop mode
• 256 Kbytes of SRAM including 64 Kbytes with
hardware parity check
• Brownout reset (BOR) in all modes except
Shutdown
• External memory interface supporting SRAM,
PSRAM, NOR, NAND and FRAM memories
Core
• OCTOSPI memory interface
• Arm® 32-bit Cortex®-M33 CPU with
TrustZone® and FPU
Security
• Arm® TrustZone® and securable I/Os,
memories and peripherals
ART Accelerator
• 8-Kbyte instruction cache allowing 0-wait-state
execution from Flash memory and external
memories; frequency up to 110 MHz, MPU,
165 DMIPS and DSP instructions
• Flexible life cycle scheme with RDP (readout
protection)
• Root of trust thanks to unique boot entry and
hide protection area (HDP)
Performance benckmark
• SFI (secure firmware installation) thanks to
embedded RSS (root secure services)
• 1.5 DMIPS/MHz (Drystone 2.1)
• Secure firmware upgrade support with TF-M
• 442 CoreMark® (4.02 CoreMark®/MHz)
Energy benchmark
• 370 ULPMark-CP® score
• 54 ULPMark-PP® score
• 27400 SecureMark-TLS® score
September 2020
This is information on a product in full production.
• AES coprocessor
• Public key accelerator
• On-the-fly decryption of Octo-SPI external
memories
• HASH hardware accelerator
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STM32L562xx
• Active tamper and protection against
temperature, voltage and frequency attacks
• True random number generator NIST SP80090B compliant
Up to 19 communication peripherals
• 1x USB Type-C™/ USB power delivery
controller
• 96-bit unique ID
• 1x USB 2.0 full-speed crystal less solution,
LPM and BCD
• 512-byte OTP (one-time programmable) for
user data
• 2x SAIs (serial audio interface)
General-purpose input/outputs
• 6x USARTs (ISO 7816, LIN, IrDA, modem)
• Up to 114 fast I/Os with interrupt capability
most 5 V-tolerant and up to 14 I/Os with
independent supply down to 1.08 V
• 3x SPIs (7x SPIs with USART and OCTOSPI in
SPI mode)
• 4x I2C FM+(1 Mbit/s), SMBus/PMBus™
• 1x FDCAN controller
• 1x SDMMC interface
Power management
• Embedded regulator (LDO) with three
configurable range output to supply the digital
circuitry
2 DMA controllers
• Embedded SMPS step-down converter
Up to 22 capacitive sensing channels
• External SMPS support
• Support touch key, linear and rotary touch
sensors
Clock management
• 14 DMA channels
Rich analog peripherals (independent
supply)
• 4 to 48 MHz crystal oscillator
• 32 kHz crystal oscillator for RTC (LSE)
• Internal 16 MHz factory-trimmed RC (±1%)
• Internal low-power 32 kHz RC (±5%)
• Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25% accuracy)
• Internal 48 MHz with clock recovery
• 3 PLLs for system clock, USB, audio, ADC
• 2x 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
• 2x 12-bit DAC outputs, low-power sample and
hold
• 2x operational amplifiers with built-in PGA
• 2x ultra-low-power comparators
• 4x digital filters for sigma delta modulator
CRC calculation unit
Up to 16 timers and 2 watchdogs
• 16x timers: 2 x 16-bit advanced motor-control,
2 x 32-bit and 5 x 16-bit general purpose, 2x
16-bit basic, 3x low-power 16-bit timers
(available in Stop mode), 2x watchdogs, 2x
SysTick timer
Debug
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
(ETM)
• RTC with hardware calendar, alarms and
calibration
Table 1. Device summary
Reference
STM32L562xx
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Part numbers
STM32L562CE, STM32L562ME, STM32L562QE, STM32L562RE, STM32L562VE,
STM32L562ZE
DS12736 Rev 4
STM32L562xx
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Arm® Cortex®-M33 core with TrustZone® and FPU . . . . . . . . . . . . . . . . . 20
3.2
Art Accelerator – instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . 20
3.3
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7
Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8
TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8.1
3.9
TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.4
SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.9.5
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.9.6
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.9.7
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9.8
PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.10
Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.11
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.13
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.14
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.15
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.16
DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.17
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.17.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 57
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3.17.2
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Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 57
3.18
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 58
3.19
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.20
Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.21
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.21.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.22
Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.23
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.24
Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.25
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.26
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 64
3.27
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.28
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.29
Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 67
3.30
HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.31
Public key accelerator PKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.32
On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.33
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.33.1
Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.33.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.33.3
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.33.4
Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 71
3.33.5
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.33.6
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.33.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.34
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.35
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.36
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.37
Universal synchronous/asynchronous receiver transmitter (USART) . . . 76
3.38
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 77
3.39
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.40
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Contents
3.41
Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 78
3.42
Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.43
Universal serial bus (USB FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.44
USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 79
3.45
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.45.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.45.2
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.3.2
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.3.3
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 150
5.3.4
Embedded reset and power control block characteristics . . . . . . . . . . 150
5.3.5
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.3.7
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.3.8
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.3.9
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.3.10
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
5.3.11
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
5.3.12
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
5.3.13
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
5.3.14
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
5.3.15
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
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STM32L562xx
5.3.16
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
5.3.17
Extended interrupt and event controller input (EXTI) characteristics . . 239
5.3.18
Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
5.3.19
Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 241
5.3.20
Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 254
5.3.21
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 259
5.3.22
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.3.23
Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.3.24
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
5.3.25
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
5.3.26
Temperature and VDD thresholds monitoring . . . . . . . . . . . . . . . . . . . 268
5.3.27
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
5.3.28
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
5.3.29
Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 272
5.3.30
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
5.3.31
OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
5.3.32
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 306
5.3.33
UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
6.1
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
6.2
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
6.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
6.4
WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
6.5
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
6.6
UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
6.7
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
6.8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
6.8.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.8.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 333
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32L562xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes when TrustZone is disabled (TZEN=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Boot modes when TrustZone is enabled (TZEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Example of memory map security attribution vs SAU configuration regions . . . . . . . . . . . 27
Securable peripherals by TZSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TrustZone-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SMPS external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32L562xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32L562xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
STM32L562xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SMPS modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 150
Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . 155
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . 156
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE disabled and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Current consumption in Run and Low-power run modes, code with data processing
DS12736 Rev 4
7/342
11
List of tables
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
8/342
STM32L562xx
running from Flash in dual bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE disabled and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Current consumption in Run mode, code with data processing running
from SRAM1 and power supplied by internal SMPS step down converter . . . . . . . . . . . . 168
Current consumption in Run and Low-power run modes, code with data processing
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Current consumption in Run mode, code with data processing
running from SRAM2 and power supplied by internal SMPS step down converter . . . . . 170
Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (2-way) . . . . . . . . . . . . . . . . . . . . . 171
Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (2-way) . . . . . . . . . . . . . . . . . . . . . 172
Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (1-way) . . . . . . . . . . . . . . . . . . . . . 173
Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (1-way) . . . . . . . . . . . . . . . . . . . . . 174
Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 175
Typical current consumption in Run mode with internal SMPS,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 176
Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 181
Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 182
Current consumption in Sleep mode,
Flash ON and power supplied by internal SMPS step down converter . . . . . . . . . . . . . . 183
Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 2-way and power supplied by external SMPS . . . . . . . . . 184
Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 1-way and power supplied by external SMPS . . . . . . . . . 185
Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE disabled and power supplied by external SMPS . . . . . . . . . . . . 186
DS12736 Rev 4
STM32L562xx
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
List of tables
Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 2-way and power supplied by external SMPS . . . . . . . . . . . 187
Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 1-way and power supplied by external SMPS . . . . . . . . . . . 188
Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE disabled and power supplied by external SMPS. . . . . . . . . . . . . . 189
Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Current consumption in Sleep mode, Flash ON and power supplied by external SMPS . 192
Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (2-way) and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . 193
Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (1-way) and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . 194
Current consumption in Run mode, code with data processing running from Flash,
ICACHE disabled and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . 195
Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
I/O AC characteristics (All I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
FT_c I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DS12736 Rev 4
9/342
11
List of tables
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
10/342
STM32L562xx
EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
DAC accuracy ranges 0/1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Temp and VDD monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
DFSDM measured timing 1.71 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
WWDG min/max timeout value at 110 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 283
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 283
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 284
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 285
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 286
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 288
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 294
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 299
OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
OCTOSPI characteristics in DTR mode (with DQS)/Octal and HyperBus . . . . . . . . . . . . 302
Dynamics characteristics: delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Dynamics characteristics: SD / eMMC characteristics,
VDD=2.7V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V . . . . . . . . . . . . . . 307
UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
WLCSP81 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
WLCSP81 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
DS12736 Rev 4
STM32L562xx
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
List of tables
LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 326
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
STM32L562xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
DS12736 Rev 4
11/342
11
List of figures
STM32L562xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
12/342
STM32L562xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L562xxxxP power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L562xxxxQ power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SMPS step down converter power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32L562xx clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
STM32L562xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
STM32L562xxxxP LQFP48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
STM32L562xx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
STM32L562xxxxP UFQFPN48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
STM32L562xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
STM32L562xxxxQ LQFP64 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . . 83
STM32L562xxxxP LQFP64 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
STM32L562xxxxQ WLCSP81 SMPS step down converter ballout . . . . . . . . . . . . . . . . . . 84
STM32L562xxxxP WLCSP81 external SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
STM32L562xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
STM32L562xxxxQ LQFP100 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 86
STM32L562xx UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
STM32L562xxxxQ UFBGA132 SMPS step down converter ballout. . . . . . . . . . . . . . . . . . 87
STM32L562xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
STM32L562xxxxQ LQFP144 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 89
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
STM32L552xx and STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . 141
STM32L552xxxP and STM32L562xxxP power supply overview . . . . . . . . . . . . . . . . . . . 142
STM32L552xxxQ and STM32L562xxxQ power supply overview . . . . . . . . . . . . . . . . . . . 143
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
External components for SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
VREFBUF in case VRS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
VREFBUF in case VRS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
DS12736 Rev 4
STM32L562xx
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
List of figures
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
USART master mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
USART slave mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 282
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 284
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 285
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 287
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 293
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 298
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 298
OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
LQFP48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Example of LQFP48 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 312
UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Example of UFQFPN48 package marking (package top view). . . . . . . . . . . . . . . . . . . . . 315
LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Example of LQFP64 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 318
WLCSP81 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
WLCSP 81 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Example of WLCSP81 package marking (package top view . . . . . . . . . . . . . . . . . . . . . . 321
LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Example of LQFP100 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 324
UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Example of UFBGA132 package marking (package top view) . . . . . . . . . . . . . . . . . . . . 327
LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Example of LQFP144 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 331
DS12736 Rev 4
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13
Introduction
1
STM32L562xx
Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32L562xx microcontrollers.
This document should be read in conjunction with the STM32L552xx and STM32L562xx
reference manual (RM0438).
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
14/342
DS12736 Rev 4
STM32L562xx
2
Description
Description
The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5
Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate
at a frequency of up to 110 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports
all the Arm® single-precision data-processing instructions and all the data types. The
Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions
and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes
of SRAM), a flexible external memory controller (FSMC) for static memories (for devices
with packages of 100 pins and more), an Octo-SPI Flash memories interface (available on
all packages) and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L5 Series devices offer security foundation compliant with the trusted based
security architecture (TBSA) requirements from Arm. They embed the necessary security
features to implement a secure boot, secure data storage, secure firmware installation and
secure firmware upgrade. Flexible life cycle is managed thanks to multiple levels of readout
protection. Firmware hardware isolation is supported thanks to securable peripherals,
memories and I/Os, and also to the possibility to configure the peripherals and memories as
“privilege”.
The STM32L562xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, secure and hidden protection
areas.
The STM32L562xx devices embed several peripherals reinforcing security:
- One AES coprocessor
- One public key accelerator (PKA)
- One on-the-fly decryption engine for Octo-SPI external memories
- One HASH hardware accelerator
- One true random number generator
The STM32L5 Series devices offer active tamper detection and protection against transient
and environmental perturbation attacks thanks to several internal monitoring which generate
secret data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications. These devices offer two fast 12-bit ADC (5 Msps), two comparators, two
operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power
RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control,
seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support
four digital filters for external sigma delta modulators (DFSDM). In addition, up to 22
capacitive sensing channels are available.
STM32L5 Series also feature standard and advanced communication interfaces such as:
- Four I2Cs
- Three SPIs
- Three USARTs, two UARTs and one low-power UART
DS12736 Rev 4
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80
Description
STM32L562xx
- Two SAIs
- One SDMMC
- One FDCAN
- USB device FS
- USB Type-C / USB power delivery controller
The STM32L562xx devices embed an AES, PKA and OTFDEC hardware accelerator.
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to
14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows the
backup of the RTC and the backup of the registers.
The STM32L562xx devices offer seven packages from 48-pin to 144-pin.
Flash memory (Kbyte)
SRAM
16/342
Backup (byte)
128
No
Yes
1
Advanced control
2 (16-bit)
General purpose
5 (16-bit)
2 (32-bit)
Basic
2 (16-bit)
Low power
3 (16-bit)
SysTick timer
1
Watchdog timers
(independent,
window)
2
DS12736 Rev 4
STM32L562ZE/
STM32L562ZExxQ
STM32L562QE/
STM32L562QExxP/
STM32L562QExxQ
STM32L562VE/
STM32L562VExxQ
256 (192+64)
OCTOSPI
Timers
STM32L562MExxQ
512
System (Kbyte)
External memory controller for static
memories (FSMC)
STM32L562MExxP/
STM32L562RExxP/
STM32L562RExxQ
STM32L562RE/
STM32L562CE/
Peripherals
STM32L562CExxP
Table 2. STM32L562xx features and peripheral counts
STM32L562xx
Description
4
USB FS
Yes
No
Yes
Yes/No/Yes
Digital filters for sigmadelta modulators
Yes (4 filters)
Number of channels
8
Real time clock (RTC)
Yes
3
4/3
3
True random number generator
Yes
AES
Yes
PKA
Yes
HASH (SHA-256)
Yes
On-the-fly decryption for OCTOSPI
1
OCTOSPI memory encryption
1
Capacitive sensing
Number of channels
38/36
3
0
52/50/47
4/3/3
0
54/51
3
6
83/79
5/4
0
110/108/105
5
13/13/10
115 /111
5/4
14/13
5
10/10/9
10
19/18
22
22/21
16/14
16
16/14
12-bit ADC
ADC
DAC
Number of
channels
8/7
2
1
GPIOs
Wakeup pins
Nb of I/Os down to 1.08 V
5
3/2 (2)
2
1
FDCAN
Tamper pins
STM32L562ZE/
STM32L562ZExxQ
I2C
SDMMC
STM32L562QE/
STM32L562QExxP/
STM32L562QExxQ
3
USART(1)/UART
UART
Communication LPUART
interfaces
SAI
5/4
STM32L562VE/
SPI
STM32L562VExxQ
STM32L562MExxQ
STM32L562MExxP/
STM32L562RExxP/
STM32L562RExxQ
STM32L562RE/
STM32L562CE/
Peripherals
STM32L562CExxP
Table 2. STM32L562xx features and peripheral counts (continued)
2
9
16/16/15
16/15
12-bit DAC
1
Number of
channels
2
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80
Description
STM32L562xx
Internal voltage
reference buffer
2
Operational amplifiers
2
Max. CPU frequency
110 MHz
Operating voltage
Package
STM32L562ZE/
STM32L562ZExxQ
STM32L562QE/
STM32L562QExxP/
STM32L562QExxQ
STM32L562VE/
Yes
Analog comparator
Operating temperature
STM32L562VExxQ
STM32L562MExxQ
STM32L562MExxP/
STM32L562RExxP/
STM32L562RExxQ
STM32L562RE/
STM32L562CE/
Peripherals
STM32L562CExxP
Table 2. STM32L562xx features and peripheral counts (continued)
1.71 to 3.6 V
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Junction temperature: -40 to 105 °C / -40 to 130 °C
LQFP48,
UFQFPN48
LQFP64
WLCSP81 LQFP100(2) UFBGA132
LQFP144
1. USART3 is not available on STM32L562CExxP devices.
2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.
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STM32L562xx
Description
Figure 1. STM32L562xx block diagram
CLK, NE[4:1], NL, NBL[1:0], A[25:0],
D[15:0], NOE, NWE, NWAIT, NCE, INT as
AF
Flexible static memory controller (FSMC): SRAM,
PSRAM, NOR Flash,FRAM, NAND Flash
MPU
ETM
NVIC
Arm Cortex-M33
C-BUS
110 MHz TrustZone FPU
RNG
AES
HASH
Flash up to 512KB
S-BUS
AHB bus-matrix
PKA32
SDMMC1
@ VDDUSB
SRAM 192 KB
FIFO
FIFO
D[7:0], D[3:1]dir
CMD, CMDdir,CK,
CKin D0dir, D2dir
IO[7:0],
CLK, NCLK, NCS. DQS
Octo SPI1 memory interface
Icache 8KB
TRACECLK
TRACED[3:0]
SRAM 64 KB
DMA1
USB FS
Voltage regulator
LDO and SMPS
3.3 to 1.2 V
VDDIO, VDDUSB
Int
BOR
VDDA, VSSA
RC LSI
GTZC
PC[15:0]
GPIO PORT C
PD[15:0]
GPIO PORT D
PE[15:0]
GPIO PORT E
PF[15:0]
GPIO PORT F
PG[15:0]
GPIO PORT G
PH[1:0]
GPIO PORT H
114 AF
EXT IT. WKUP
IWDG
Standby
interface
Reset
and clock
control
@VBAT
XTAL 32 kHz
RTC_TS
RTC_TAMP[8:1]
RTC_OUT
AWU
Backup register
VBAT = 1.55 to 3.6 V
CRC
@ VDD
U STemperature
AR T 2 M B
ps
sensor
16xIN
OSC32_IN
OSC32_OUT
RTC
PCLKx
GPIO PORT B
OSC_IN
OSC_OUT
XTAL OSC
4- 16MHz
FCLK
GPIO PORT A
@VDD
HCLKx
PA[15:0]
PB[15:0]
VDD, VSS, NRST
PVD, PVM
PLL 1&2&3
AHB1 110AHB1
MHz 110 MHz
Touch sensing controller
VSS
Supply
supervision
reset
MSI
RC HSI
8 groups of sensing channels as AF
VDD = 1.71 to 3.6 V
@ VDD
@ VDD
DMAMUX1
DP
DM
Power management
VDD
AHB2 110 MHz
DMA2
PHY
JTAG & SW
OTFDEC
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
TIM2
32b
4 channels, ETR as AF
TIM3
16b
4 channels, ETR as AF
TIM4
16b
4 channels, ETR as AF
TIM5
32b
4 channels, ETR as AF
@ VDDA
ADC1
ITF
USART2
smcard
irDA
RX, TX, CK, CTS, RTS as AF
USART3
smcard
irDA
RX, TX, CK, CTS, RTS as AF
ADC2
AHB/APB1
AHB/APB2
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), ETR, BKIN,
BKIN2 as AF
TIM1 / PWM
3 compl. Channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), ETR, BKIN,
BKIN2 as AF
TIM8 / PWM
16b
2 channels, 1 compl. channel,
BKIN as AF
TIM15
16b
1 channel, 1 compl. channel,
BKIN as AF
TIM16
16b
RX, TX, CTS, RTS as AF
UART5
RX, TX, CTS, RTS as AF
16b
SPI2
WWDG
16b
SCL, SDA, SMBA as AF
I2C2/SMBUS
SCL, SDA, SMBA as AF
I2C3/SMBUS
SCL, SDA, SMBA as AF
I2C4/SMBUS
SCL, SDA, SMBA as AF
SAI1
SAI2
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
DFSDM
TIM6
16b
TIM7
16b
P B 1(max)
3 0M Hz
APB1 110AMHz
SPI1
A
60P
M
B Hz
2 110MHz
APB2
USART1
MOSI, MISO,
SCK, NSS as AF
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
CRS
MOSI, MISO, SCK, NSS as AF
I2C1/SMBUS
FDCAN1
FIFO
TIM17
smcard
irDA
MOSI, MISO, SCK, NSS as AF
SPI3
TX, RX as AF
@VDDA
OpAmp1
OUT, INN, INP
OpAmp2
OUT, INN, INP
SYSCFG
@ VDDUSB
UCPD1
UCPD1
PHY
1 channel, 1 compl. channel,
BKIN as AF
RX, TX, CK,CTS,
RTS as AF
UART4
DP
DM
@ VDDA
VREF+
VREF Buffer
LPUART1
@ VDDA
@ VDDA
CH1
INP, INN, OUT
COMP1
DAC1
CH2
INP, INN, OUT
LPTIM1
IN1, IN2, OUT, ETR as AF
RX, TX, CTS, RTS as AF
LPTIM2
IN1, OUT, ETR as AF
LPTIM3
IN1, OUT, ETR as AF
COMP2
OUT1
OUT2
32-bits AHB bus
32-bits APB bus
VDDIO2 power domain
VDD power domain
VBAT power domain
VDDA power domain
VDDUSB power domain
MSv49330V7
1. AF: alternate function on I/O pins.
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Functional overview
STM32L562xx
3
Functional overview
3.1
Arm® Cortex®-M33 core with TrustZone® and FPU
The Cortex®-M33 with TrustZone and FPU is a highly energy efficient processor designed
for microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex®-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. it features:
•
Arm® TrustZone® technology, using the Armv8-M main extension supporting secure
and non-secure states
•
Memory protection units (MPUs), 8 regions for secure and 8 regions for non secure
•
Configurable secure attribute unit (SAU) supporting up to 8 memory regions
•
Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex®-M33 processor supports the following bus interfaces:
•
System AHB bus:
The System AHB (S-AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
•
Code AHB bus
The Code AHB (C-AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32L562xx family devices.
3.2
Art Accelerator – instruction cache (ICACHE)
The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex®-M33
processor to improve performance when fetching instruction (or data) from both internal and
external memories.
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STM32L562xx
Functional overview
ICACHE offers the following features:
•
•
3.3
Multi-bus interface:
–
slave port receiving the memory requests from the Cortex®-M33 C-AHB code
execution port
–
master1 port performing refill requests to internal memories (FLASH and SRAMs)
–
master2 port performing refill requests to external memories (external
FLASH/RAMs through Octo-SPI/FMC interfaces)
–
a second slave port dedicated to ICACHE registers access.
Close to zero wait states instructions/data access performance:
–
0 wait-state on cache hit
–
hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
–
critical-word-first refill policy, minimizing processor stalls on cache miss
–
hit ratio improved by 2-ways set-associative architecture and pLRU-t replacement
policy (pseudo-least-recently-used, based on binary tree), algorithm with best
complexity/performance balance
–
dual master ports allowing to decouple internal and external memory traffics, on
Fast and Slow buses, respectively; also minimizing impact on interrupt latency
–
optimal cache line refill thanks to AHB burst transactions (of the cache line size).
–
performance monitoring by means of a hit counter and a miss counter.
•
Extension of cacheable region beyond Code memory space, by means of address
remapping logic that allows to define up to 4 cacheable external regions
•
Power consumption reduced intrinsically (most accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default 2-ways set-associative mode)
•
TrustZone® security support
•
Maintenance operation for software management of cache coherency
•
Error management: detection of unexpected cacheable write access, with optional
interrupt raising.
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 regions for secure and 8
regions for non secure state.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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Functional overview
3.4
STM32L562xx
Embedded Flash memory
The devices feature 512 Kbytes of embedded Flash memory which is available for storing
programs and data.
The Flash interface features:
•
Single or dual bank operating modes
•
Read-while-write (RWW) in dual bank mode
This feature allows a read operation to be performed from one bank while an erase or
program operation is performed to the other bank. The dual bank boot is also supported.
Each bank contains 128 pages of 2 or 4 Kbytes (depending on the read access width). The
Flash memory also embeds 512 bytes OTP (one-time programmable) for user data.
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Four levels of protection are
available:
– Level 0: no readout protection
– Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-secure Flash
memory are possible. The Debug access to secure area is prohibited. Debug access
to non-secure area remains possible.
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected. If TrustZone is enabled, the non-secure debug is possible and the boot in
SRAM is not possible.
– Level 2: chip readout protection; the debug features (Cortex®-M33 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•
Write protection (WRP): the protected area is protected against erasing and
programming:
–
In single bank mode, four areas can be selected with 4-Kbyte granularity.
–
In dual bank mode, two areas per bank can be selected with 2-Kbyte granularity.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•
Single error detection and correction
•
Double error detection
•
The address of the ECC fail can be read in the ECC register.
TrustZone security
When the TrustZone security is enabled, the whole Flash is secure after reset and the
following protections are available:
•
•
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Non-volatile watermark-based secure Flash area: the secure area can be accessed
only in secure mode.
–
In single bank mode, four areas can be selected with a page granularity.
–
In dual bank mode, one area per bank can be selected with a page granularity.
Secure hidden protection area: it is part of the Flash secure area and it can be
protected to deny an access to this area by any data read, write and instruction fetch.
DS12736 Rev 4
STM32L562xx
Functional overview
For example, a software code in the secure Flash memory hidden protection area can
be executed only once and deny any further access to this area until next system reset.
•
3.5
Volatile block-based secure Flash area. In a block-based secure area, each page can
be programmed on-the-fly as secure or non-secure.
Embedded SRAM
The devices feature 256 Kbytes of embedded SRAM. This SRAM is split into three blocks:
•
192 Kbytes mapped at address 0x2000 0000 (SRAM1).
•
64 Kbytes located at address 0x0A03 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2003 0000 offering a contiguous address
space with the SRAM1.
This block is accessed through the C-bus for maximum performance. Either 64 Kbytes
or upper 4 Kbytes of SRAM2 can be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
TrustZone security
When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can
be programmed as non-secure by block based using the MPCBB (memory protection
controller block based) in GTZC controller. The granularity of SRAM secure block based is a
page of 256 bytes.
3.6
Boot modes
At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] / SECBOOTADD0[24:0] option
bytes are used to select the boot memory address which includes:
•
Boot from any address in user Flash
•
Boot from system memory bootloader
•
Boot from any address in embedded SRAM
•
Boot from Root Security service (RSS)
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on
the value of a user option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device
firmware upgrade).
The bootloader is available on all devices. Refer to the application note STM32
microcontroller system memory boot mode (AN2606) for more details.
The root secure services (RSS) are embedded in a Flash memory area named secure
information block, programmed during ST production.
The RSS enables for example the secure firmware installation (SFI) thanks to the RSS
extension firmware (RSSe SFI).
This feature allows the customers to protect the confidentiality of the firmware to be
provisioned into the STM32 device when the production is subcontracted to a third party.
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Functional overview
STM32L562xx
The RSS is available on all devices, after enabling the TrustZone through the TZEN option
bit.
Refer to the application note Overview secure firmware install (SFI) (AN4992) for more
details.
Refer to Table 3 and Table 4 for boot modes when TrustZone is disabled and enabled
respectively.
Table 3. Boot modes when TrustZone is disabled (TZEN=0)
nBOOT0
BOOT0
nSWBOOT0
Boot address optionbytes selection
Boot area
ST programmed
default value
FLASH_
OPTR[27]
pin PH3
FLASH_
OPTR[26]
-
0
1
NSBOOTADD0[24:0]
Boot address defined by
user option bytes
NSBOOTADD0[24:0]
Flash: 0x0800 0000
-
1
1
NSBOOTADD1[24:0]
Boot address defined by
user option bytes
NSBOOTADD1[24:0]
System bootloader:
0x0BF9 0000
1
-
0
NSBOOTADD0[24:0]
Boot address defined by
user option bytes
NSBOOTADD0[24:0]
Flash: 0x0800 0000
0
-
0
NSBOOTADD1[24:0]
Boot address defined by
user option bytes
NSBOOTADD1[24:0]
System bootloader:
0x0BF9 0000
When TrustZone is enabled by setting the TZEN option bit, the boot space must be in
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.
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STM32L562xx
Functional overview
Table 4. Boot modes when TrustZone is enabled (TZEN=1)
BOOT_
LOCK
nBOOT0 BOOT0 nSWBOOT0
Boot address
RSS
FLASH_
pin
option-bytes
FLASH_
command
OPTR[27]
PH3
selection
OPTR[26]
-
0
1
0
-
1
1
0
0
1
Boot area
Secure boot address
SECBOOTAD defined by user option
bytes
D0[24:0]
SECBOOTADD0[24:0]
N/A
RSS: 0x0FF8 0000
Secure boot address
SECBOOTAD defined by user option
D0[24:0]
bytes
SECBOOTADD0[24:0]
ST
programmed
default value
Flash:
0x0C00 0000
RSS:
0x0FF8 0000
Flash:
0x0C00 0000
1
-
0
0
0
-
0
0
N/A
RSS: RSS:
0x0FF8 0000
RSS:
0x0FF8 0000
-
-
-
≠0
N/A
RSS: RSS:
0x0FF8 0000
RSS:
0x0FF8 0000
-
-
-
-
Secure boot address
SECBOOTAD defined by user option
D0[24:0]
bytes
SECBOOTADD0[24:0]
Flash:
0x0C00 0000
The boot address option bytes enables the possibility to program any boot memory address.
However, the allowed address space depends on Flash read protection RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot fetch address is forced to:
•
0x0800 0000 (when TZEN = 0)
•
RSS (when TZEN = 1)
Refer to Table 5.
Table 5. Boot space versus RDP protection
RDP
0
TZEN = 1
Any boot address
TZEN = 0
Any boot address
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Functional overview
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Table 5. Boot space versus RDP protection (continued)
RDP
TZEN = 1
0.5
N/A
1
Any boot address
Boot address only in:
– RSS
– or secure Flash: 0x0C00 0000 0x0C07 FFFF
2
Otherwise boot address forced to RSS
3.7
TZEN = 0
If boot is configured for NSBOOTADD0 and
NSBOOTADD0 in the range 0x0800 0000 0x0807 FFFF: boot at the address stored in
NSBOOTADD0
If boot is configured for NSBOOTADD1 and
NSBOOTADD1 in the range 0x0800 0000 0x0807 FFFF: boot at the address stored in
NSBOOTADD1
Otherwise boot address is forced at
0x0800 0000
Global TrustZone controller (GTZC)
The GTZC includes three different sub-blocks:
•
TZSC: TrustZone® security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
1.
MPCBB: block-based memory protection controller
This sub-block controls secure states of all blocks (256-byte pages) of the associated
SRAM.
2.
TZIC: TrustZone illegal access controller
This sub-block gathers all illegal access events in the system and generates a secure
interrupt towards NVIC.
These sub-blocks are used to configure TrustZone and privileged attributes within the full
system.
The GTZC main features are:
•
3 independent 32-bit AHB interface for TZSC, MPCBB and TZIC
•
MPCBB and TZIC accessible only with secure transactions
•
Secure and non-secure access supported for priv/non-priv part of TZSC
•
Register set to define security settings:
•
26/342
–
Secure blocks for internal SRAM
–
Non-secure regions for external memories
–
Secure/privilege access mode for securable and TZ-aware peripherals
Secure/privilege access mode for securable legacy masters.
DS12736 Rev 4
STM32L562xx
3.8
Functional overview
TrustZone security architecture
The security architecture is based on Arm® TrustZone® with the Armv8-M Main Extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) defines the access permissions based on secure
and non-secure state.
•
SAU: Up to 8 SAU configurable regions are available for security attribution.
•
IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and the
higher security state is selected.
Based on IDAU security attribution, the Flash, system SRAMs and peripherals memory
space is aliased twice for secure and non-secure state. However, the external memories
space is not aliased.
Table 6 shows an example of typical SAU regions configuration based on IDAU regions.
The user can split and choose the secure, non-secure or NSC regions for external
memories as needed.
Table 6. Example of memory map security attribution vs SAU configuration regions(1) (2)
Region
description
Code - external
memories
Code - Flash and
SRAM
Code - external
memories
SRAM
Peripherals
External memories
Address range
IDAU security
attribution
SAU security
attribution typical
configuration
Final security
attribution
0x0000_0000
0x07FF_FFFF
Non-secure
Secure or nonsecure or NSC
Secure or nonsecure or NSC
0x0800_0000
0x0BFF_FFFF
Non-secure
Non-secure
Non-secure
0x0C00_0000
0x0FFF_FFFF
NSC
Secure or NSC
Secure or NSC
0x1000_0000
0x17FF_FFFF
0x1800_0000
0x1FFF_FFFF
Non-secure
Non-secure
0x2000_0000
0x2FFF_FFFF
Non-secure
0x3000_0000
0x3FFF_FFFF
NSC
Secure or NSC
Secure or NSC
0x4000_0000
0x4FFF_FFFF
Non-secure
Non-secure
Non-secure
0x5000_0000
0x5FFF_FFFF
NSC
Secure or NSC
Secure or NSC
0x6000_0000
0xDFFF_FFFF
Non-secure
Secure or nonsecure or NSC
Secure or nonsecure or NSC
1. NSC = non-secure callable.
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Functional overview
STM32L562xx
2. Different colors highlights the different configurations
Pink: Non-secure
Green: NSC (non-secure callable)
Lighter green: Secure or non-secure or NSC
3.8.1
TrustZone peripheral classification
When the TrustZone security is active, a peripheral can be either Securable or TrustZoneaware type as follows:
•
Securable: a peripheral is protected by an AHB/APB firewall gate that is controlled from
TZSC controller to define security properties.
•
TrustZone-aware: a peripheral connected directly to AHB or APB bus and is
implementing a specific TrustZone behavior such as a subset of registers being secure.
The tables below summarize the list of Securable and TrustZone aware peripherals within
the system.
Table 7. Securable peripherals by TZSC
Bus
AHB3
Peripheral
OCTOSPI1 registers
FMC registers
SDMMC1
RNG
AHB 2
HASH
AES
ADC
ICACHE registers
AHB1
TSC
CRC
DFSDM1
SAI2
SAI1
TIM17
TIM16
APB2
TIM15
USART1
TIM8
SPI1
TIM1
COMP
VREFBUF
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Functional overview
Table 7. Securable peripherals by TZSC (continued)
Bus
Peripheral
UCPD1
USB FS
FDCAN1
LPTIM3
LPTIM2
I2C4
LPUART1
LPTIM1
OPAMP
DAC1
CRS
I2C3
I2C2
APB1
I2C1
UART5
UART4
USART3
USART2
SPI3
SPI2
IWDG
WWDG
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
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Functional overview
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Table 8. TrustZone-aware peripherals
Bus
Peripheral
GPIOH
GPIOG
GPIOF
AHB2
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
AHB2
OTFDEC1
MPCBB2
MPCBB1
MPCWM2
MPCWM1
TZIC
AHB1
TZSC
EXTI
Flash memory
RCC
DMAMUX1
DMA2
DMA1
APB2
APB1
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SYSCFG
PWR
RTC
DS12736 Rev 4
STM32L562xx
Functional overview
Default TrustZone security state
The default system security state is:
•
CPU:
–
•
Memory map:
–
•
•
–
Flash security area is defined by watermark user options.
–
Flash block based area is non-secure after reset.
SRAMs:
Note:
All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
External memories:
–
•
SAU: is fully secure after reset. Consequently, all memory map is fully secure. Up
to 8 SAU configurable regions are available for security attribution.
Flash:
–
•
Cortex®-M33 is in secure state after reset. The boot address must be in secure
address.
FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) are secure
Peripherals
–
Securable peripherals are non-secure after reset.
–
TrustZone-aware peripherals (except the GPIO) are non-secure after reset. Their
secure configuration registers are secure.
Refer to Table 7 and Table 8 for a list of Securable and TrustZone-aware peripherals.
•
All GPIO are secure after reset.
•
Interrupts:
–
NVIC: All interrupts are secure after reset. NVIC is banked for secure and nonsecure state.
–
TZIC: All illegal access interrupts are disabled after reset.
DS12736 Rev 4
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80
Functional overview
3.9
STM32L562xx
Power supply management
The power controller (PWR) main features are:
•
•
•
•
3.9.1
Power supplies and supply domains
–
Core domains (VCORE)
–
VDD domain
–
Backup domain (VBAT)
–
Analog domain (VDDA)
–
VDDIO2 domain
–
VDDUSB for USB transceiver
System supply voltage regulation
–
SMPS step down converter
–
Voltage regulator (LDO)
Power supply supervision
–
POR/PDR monitor
–
BOR monitor
–
PVD monitor
–
PVM monitor (VDDA, VDDUSB, VDDIO2)
–
Temperature thresholds monitor
–
Upper VDD voltage threshold monitor
Power management
–
Operating modes
–
Voltage scaling control
–
Low-power modes
•
VBAT battery charging
•
TrustZone security
Power supply schemes
The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
•
VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
32/342
VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage and should preferably be connected to VDD when
these peripherals are not used.
DS12736 Rev 4
STM32L562xx
Note:
Functional overview
•
VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is
provided externally through VDDSMPS supply pin, and shall be connected to the same
supply as VDD.
•
VLXSMPS is the switched SMPS step down converter output.
•
V15SMPS are the power supply for the system regulator. It is provided externally
through the SMPS step down converter VLXSMPS output.
The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
•
VDD12 = 1.05 to 1.32 V
VDD12 is the external power supply bypassing the internal regulator when connected
to an external SMPS. It is provided externally through VDD12 pins and only available
on packages with the external SMPS supply option. VDD12 does not require any
external decoupling capacitance and cannot support any external load.
•
VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage and should preferably be
connected to VDD when the USB is not used.
•
VDDIO2 = 1.08 V to 3.6 V
•
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage
level is independent from the VDD voltage and should preferably be connected to VDD
when PG[15:2] are not used.
•
VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
•
VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V VREF+ must be equal to VDDA.
When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
–
VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
–
VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled (refer to datasheet for
packages pinout description).
VREF- must always be equal to VSSA.
An embedded linear voltage-regulator is used to supply the internal digital power VCORE.
VCORE is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash is
supplied by VCORE and VDD.
DS12736 Rev 4
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80
Functional overview
STM32L562xx
Figure 2. STM32L562xx power supply overview
VDDA domain
VDDA
VSSA
VDDUSB
VSS
VDDIO2
VSS
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
USB transceivers
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temp. sensor
3 x PLL, HSI, MSI
VSS
VDD
Standby circuitry
(Wakeup logic,
IWDG)
Core
SRAM1
SRAM2
VCORE
Digital
peripherals
Voltage regulator
Low voltage detector
Flash memory
Backup domain
VBAT
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
MSv49301V1
34/342
DS12736 Rev 4
STM32L562xx
Functional overview
Figure 3. STM32L562xxxxP power supply overview
VDDA domain
VDDA
VSSA
VDDUSB
VSS
VDDIO2
VSS
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
USB transceivers
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temp. sensor
Core
3 x PLL, HSI, MSI
VSS
VDD
Standby circuitry
(Wakeup logic,
IWDG)
Voltage regulator
2x VDD12
SRAM1
SRAM2
Digital
VCORE
peripherals
Flash memory
Low voltage detector
Backup domain
VBAT
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
MSv49336V1
DS12736 Rev 4
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80
Functional overview
STM32L562xx
Figure 4. STM32L562xxxxQ power supply overview
VDDA domain
VDDA
VSSA
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
VDDUSB
VSS
USB transceivers
VDDIO2 domain
VDDIO2
VDDIO2
VSS
I/O ring
VDD domain
VDDIO1
I/O ring
Reset block
Temp. sensor
3 x PLL, HSI, MSI
VSS
VDD
VCORE domain
Standby circuitry
(Wakeup logic,
IWDG)
Core
Voltage regulator
2 x V15SMPS
VLXSMPS
VDDSMPS
VSSSMPS
MR
VCORE
SRAM1
SRAM2
Digital
SMPS
Low voltage detector
LPR
peripherals
Flash memory
Backup domain
VBAT
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
MSv49332V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
36/342
•
When VDD is below 1 V, other power supplies (VDDA, VDDIO2 and VDDUSB) must remain
below VDD +300 mV.
•
When VDD is above 1 V, all power supplies are independent.
•
During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ; this allows external
decoupling capacitors to be discharged with different time constants during the powerdown transient phase.
DS12736 Rev 4
STM32L562xx
Functional overview
Figure 5. Power-up/down sequence
V
3.6
VDDX(1)
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDIO2 and VDDUSB.
3.9.2
Power supply supervisor
The devices have an integrated ultra-low-power Brownout reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the devices after poweron and during power down. The devices remain in reset mode when the monitored supply
voltage VDD is below a specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD
is higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor which compares the
independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure
that the peripheral is in its functional supply range.
3.9.3
Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
•
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
•
The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 64 Kbytes or only 4 Kbytes of SRAM2 in standby with SRAM2
retention.
•
Both regulators are in power-down while they are in standby and Shutdown modes: the
regulator output is in high impedance, and the kernel circuitry is powered down thus
inducing zero consumption.
DS12736 Rev 4
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80
Functional overview
STM32L562xx
The ultra-low-power STM32L562xx devices support dynamic voltage scaling to optimize its
power consumption in Run mode. The voltage from the main regulator that supplies the
logic (VCORE) can be adjusted according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
•
Range 0 with the CPU running at up to 110 MHz.
•
Range 1 with the CPU running at up to 80 MHz.
•
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
•
3.9.4
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by the HSI16.
SMPS step down converter
The built-in SMPS step down converter is a highly power-efficient DC/DC non-linear
switching regulator that improves low-power performance when the VDD voltage is high
enough. This SMPS step down converter automatically enters in bypass mode when the
VDD voltage falls below 2 V in Range 0 and Range 1.
Note:
There is no automatic SMPS bypass in Range 2.
The SMPS step down converter can be configured in:
•
High-power mode (HPM): achieving a high efficiency at high current load. It is the
default selected mode after POR reset.
•
Low power mode achieving very high efficiency at low load
•
Bypass mode
The SMPS step down converter can be switched in bypass mode at any time by the
application software.
Note:
The SMPS step down converter is available only on specific package.
SMPS step down converter power supply scheme
The SMPS step down converter requires an external coil with typical value of 4.7 μH to be
connected between the VLXSMPS and the V15SMPS pins and a 4.7μF capacitor to be
connected between the V15SMPS to VSSSMPS pins. It can be switched OFF by selecting
the Bypass mode by software. Thus, only main regulator is used by the application.
38/342
DS12736 Rev 4
STM32L562xx
Functional overview
Figure 6. SMPS step down converter power supply scheme
VDD
VDDSMPS
VLXSMPS
V15SMPS
SMPS
Step Down
Converter
V15SMPS
VCORE
Main
regulator
VDD
VSSSMPS
VSS
MSv49346V1
If the selected package is with the SMPS step down converter option but it is never used by
the application, it is recommend to set the SMPS power supply pins as follows:
•
VDDSMPS and VLXSMPS connected to VSS
•
V15SMPS connected to VDD
Table 9. SMPS external components
Component
Description
C
SMPS output
capacitor(1)
SMPS inductance(2)
L
Value
4.7 µF
4.7 µH
1. For example GRM155R60J475ME87J and GRM21BR71E475KA73L.
2. For example TDK MLP2016H4R7MT.
SMPS step down converter fast startup
After POR reset, the SMPS step down converter starts in High-power mode and in Low
startup mode. The low-startup feature is selected to limit the inrush current after power-on
reset.
However, it is possible to configure a faster startup on the fly and it is applied for next startup
either after a system reset or wakeup from low-power mode except Shutdown and VBAT
modes. The fast startup is selected by setting the SMPSFSTEN bit in the PWR_CR4
register.
DS12736 Rev 4
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80
Low-power modes
The ultra-low-power STM32L562xx devices support seven low-power modes to achieve the best compromise between low-power
consumption, short startup time, available peripherals and available wake-up sources. Table 11 shows the related STM32L562xx
modes overview.
Table 10. STM32L562xx modes overview
Mode
Run
DS12736 Rev 4
LPRun
Sleep
LPSleep
Stop 0(5)
Regulator and SMPS
mode(1)
Ranges 0/1
SMPS HP mode
Range 2
SMPS LP or HP mode
LPR
Ranges 0/1
SMPS HP mode
Range 2
SMPS LP or HP mode
LPR
Ranges 0/1/2
CPU
Flash
SRAM
Clocks
Yes
ON(3)
ON
Any
DMA and Peripherals(2)
Functional overview
40/342
3.9.5
Wakeup source
All
N/A
All except USB_FS, RNG
Yes
ON(3)
ON
No
ON(3)
ON(4)
Any
except PLL
All except USB_FS, RNG
N/A
All
Any
Any interrupt or event
All except USB_FS, RNG
No
No
ON(3)
Off
ON(4)
ON
All except USB_FS, RNG
Any interrupt or event
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
All other peripherals are frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
USB_FS(8)
STM32L562xx
Any
except PLL
Mode
Stop 1
DS12736 Rev 4
Stop 2
Regulator and SMPS
mode(1)
LPR
LPR
CPU
No
No
Flash
Off
Off
SRAM
ON
ON
Clocks
DMA and Peripherals(2)
Wakeup source
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
All other peripherals are frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
USB_FS(8)
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LPTIMx (x= 1,3)
***
All other peripherals are frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LPTIMx (x= 1,3)
STM32L562xx
Table 10. STM32L562xx modes overview (continued)
Functional overview
41/342
Mode
Regulator and SMPS
mode(1)
CPU
Flash
LPR
Standby
Shutdown
OFF
OFF
SRAM
DS12736 Rev 4
Clocks
DMA and Peripherals(2)
Wakeup source
LSE
LSI
BOR, RTC, IWDG
***
All other peripherals are powered
off
***
I/O configuration can be floating,
pull-up or pull-down
Reset pin
5 I/Os (WKUPx)(9)
BOR, RTC, IWDG
LSE
RTC
***
All other peripherals are powered
off
***
I/O configuration can be floating,
pull-up or pull-down(10)
Reset pin
5 I/Os (WKUPx)(9)
RTC
SRAM2 ON
Powered
Off
Powered
Off
Off
Off
Powered
Off
Powered
Off
Functional overview
42/342
Table 10. STM32L562xx modes overview (continued)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
4. The SRAM1 and SRAM2 clocks can be gated on or off independently.
5.
SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. USB_FS wakeup by resume from suspend and attach detection protocol event.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
STM32L562xx
STM32L562xx
Functional overview
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•
Low-power sleep mode
This mode is entered from the Low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.
•
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode
to detect their wake-up condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL,
the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The Brownout reset (BOR) always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, the full SRAM2 or 4 Kbytes can
be retained in Standby mode, supplied by the low-power regulator (standby with RAM2
retention mode).
DS12736 Rev 4
43/342
80
Functional overview
STM32L562xx
The BORL (brown out detector low) can be configured in ultra-low-power mode to
further reduce power consumption during standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
•
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the
HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
44/342
DS12736 Rev 4
STM32L562xx
Functional overview
Table 11. Functionalities depending on the working mode(1)
-
-
Y
-
Y
-
-
-
-
-
-
-
-
-
-
O(2)
O(2)
O(2)
O(2)
-
-
-
-
-
-
-
-
-
SRAM1
(192 Kbytes)
Y
Y(3)
Y
Y(3)
Y
-
Y
-
-
-
-
-
-
SRAM2 (64 Kbytes)
Y
Y(3)
Y
Y(3)
Y
-
Y
-
O(4)
-
-
-
-
FSMC
O
O
O
O
-
-
-
-
-
-
-
-
-
OCTOSPI
O
O
O
O
-
-
-
-
-
-
-
-
-
OTFDEC
O
O
O
O
-
-
-
-
-
-
-
-
-
Backup registers
Y
Y
Y
Y
Y
-
Y
-
Y
-
Y
-
Y
Brownout reset
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
Programmable
voltage detector
(PVD)
O
O
O
O
O
O
O
O
-
-
-
-
-
Peripheral voltage
monitor (PVMx;
x=1,2,3,4)
O
O
O
O
O
O
O
O
-
-
-
-
-
DMA
O
O
O
O
-
-
-
-
-
-
-
-
-
High speed internal
(HSI16)
O
O
O
O
(5)
-
(5)
-
-
-
-
-
-
Oscillator HSI48
O
O
-
-
-
-
-
-
-
-
-
-
-
High speed external
(HSE)
O
O
O
O
-
-
-
-
-
-
-
-
-
Low speed internal
(LSI)
O
O
O
O
O
-
O
-
O
-
-
-
-
Low speed external
(LSE)
O
O
O
O
O
-
O
-
O
-
O
-
O
Multi speed internal
(MSI)
O
O
O
O
-
-
-
-
-
-
-
-
-
Clock security
system (CSS)
O
O
O
O
-
-
-
-
-
-
-
-
-
Clock security
system on LSE
O
O
O
O
O
O
O
O
O
O
-
-
-
Peripheral
CPU
Flash memory
(512 Kbyte)
Run
Sleep
Lowpower
run
Lowpower
sleep
-
DS12736 Rev 4
Wakeup capability
-
Wakeup capability
Standby Shutdown
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
45/342
80
Functional overview
STM32L562xx
Table 11. Functionalities depending on the working mode(1) (continued)
-
-
VDD voltage
monitoring,
temperature
monitoring
O
O
O
O
O
O
O
O
O
O
-
-
-
RTC / TAMP
O
O
O
O
O
O
O
O
O
O
O
O
O
Number of RTC
Tamper pins
8
8
8
8
8
O
8
O
8
O
8
O
3
USB, UCPD
O(8)
O(8)
-
-
-
O
-
-
-
-
-
-
-
USARTx
(x=1,2,3,4,5)
O
O
O
O
O(6) O(6)
-
-
-
-
-
-
-
Low-power UART
(LPUART)
O
O
O
O
O(6) O(6) O(6) O(6)
-
-
-
-
-
I2Cx (x=1,2,4)
O
O
O
O
O(7) O(7)
Peripheral
Run
Sleep
Lowpower
run
Lowpower
sleep
-
(7)
Wakeup capability
-
Wakeup capability
Standby Shutdown
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
-
-
-
-
-
-
-
O(7)
O(7)
O(7)
-
-
-
-
-
I2C3
O
O
O
O
O
SPIx (x=1,2,3)
O
O
O
O
-
-
-
-
-
-
-
-
-
FDCAN1
O
O
O
O
-
-
-
-
-
-
-
-
-
SDMMC1
O
O
O
O
-
-
-
-
-
-
-
-
-
SAIx (x=1,2)
O
O
O
O
-
-
-
-
-
-
-
-
-
DFSDM1
O
O
O
O
-
-
-
-
-
-
-
-
-
ADCx (x=1,2)
O
O
O
O
-
-
-
-
-
-
-
-
-
DAC1
O
O
O
O
O
-
-
-
-
-
-
-
-
VREFBUF
O
O
O
O
O
-
-
-
-
-
-
-
-
OPAMPx (x=1,2)
O
O
O
O
O
-
-
-
-
-
-
-
-
COMPx (x=1,2)
O
O
O
O
O
O
O
O
-
-
-
-
-
Temperature sensor
O
O
O
O
-
-
-
-
-
-
-
-
-
Timers (TIMx)
O
O
O
O
-
-
-
-
-
-
-
-
-
Low-power timer 1,
3 (LPTIM1 and
LPTIM3)
O
O
O
O
O
O
O
O
-
-
-
-
-
Low-power timer 2
(LPTIM2)
O
O
O
O
O
O
-
-
-
-
-
-
-
Independent
watchdog (IWDG)
O
O
O
O
O
O
O
O
O
O
-
-
-
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DS12736 Rev 4
STM32L562xx
Functional overview
Table 11. Functionalities depending on the working mode(1) (continued)
-
-
Window watchdog
(WWDG)
O
O
O
O
-
-
-
-
-
-
-
-
-
SysTick timer
O
O
O
O
-
-
-
-
-
-
-
-
-
Touch sensing
controller (TSC)
O
O
O
O
-
-
-
-
-
-
-
-
-
Random number
generator (RNG)
O(8)
O(8)
-
-
-
-
-
-
-
-
-
-
-
AES hardware
accelerator
O
O
O
O
-
-
-
-
-
-
-
-
-
HASH hardware
accelerator
O
O
O
O
-
-
-
-
-
-
-
-
-
PKA
O
O
O
O
-
-
-
-
-
-
-
-
-
CRC calculation
unit
O
O
O
O
-
-
-
-
-
-
-
-
-
GPIOs
O
O
O
O
O
O
O
O
(9)
5
pins
(11)
5
pins
-
Peripheral
Run
Sleep
Lowpower
run
Lowpower
sleep
-
(10)
Wakeup capability
-
Wakeup capability
Standby Shutdown
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
(10)
1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.
3. The SRAM clock can be gated on or off.
4. 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling ranges 0 and 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.6
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
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80
Functional overview
3.9.7
STM32L562xx
VBAT operation
The VBAT pin allows the device VBAT domain to be powered from an external battery, an
external supercapacitor, or from VDD when there is no external battery and when an external
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note:
When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
3.9.8
PWR TrustZone security
When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security allows to secure the following configuration:
•
Low-power mode
•
Wake-up (WKUP) pins
•
Voltage detection and monitoring
•
VBAT mode
Other PWR configuration bits are secure when:
3.10
•
The system clock selection is secure in RCC, the voltage scaling (VOS) configuration is
secure
•
A GPIO is configured as secure, it's corresponding bit for Pull-up/Pull-down in standby
mode is secure
•
The RTC is secure, the backup domain write protection bit in PWR is secure.
Peripheral interconnect matrix
Several peripherals have direct connections between them, which allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep, Lowpower run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 12 for more details.
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DS12736 Rev 4
STM32L562xx
Functional overview
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
Table 12. STM32L562xx peripherals interconnect matrix
TIMx
Timers synchronization or chaining
Y
Y
Y
Y
-
-
ADC
DAC1
DFSDM1
Conversion triggers
Y
Y
Y
Y
-
-
DMA
Memory to memory transfer trigger
Y
Y
Y
Y
-
-
COMPx
Comparator output blanking
Y
Y
Y
Y
-
-
TIM1, 8
TIM2, 3
Timer input channel, trigger, break from
analog signals comparison
Y
Y
Y
Y
-
-
LPTIMERx
Low-power timer triggered by analog
signals comparison
Y
Y
Y
Y
Y
(1)
TIM1, 8
Timer triggered by analog watchdog
Y
Y
Y
Y
-
-
TIM16
Timer input channel from RTC events
Y
Y
Y
Y
-
-
LPTIMERx
Low-power timer triggered by RTC alarms
or tampers
Y
Y
Y
Y
Y
(1)
All clocks sources (internal TIM2
and external)
TIM15, 16, 17
Clock source used as input channel for
RC measurement and trimming
Y
Y
Y
Y
-
-
USB
Timer triggered by USB SOF
Y
Y
-
-
-
-
Timer break
Y
Y
Y
Y
-
-
TIMx
External trigger
Y
Y
Y
Y
-
-
LPTIMERx
External trigger
Y
Y
Y
Y
Y
(1)
ADC
DAC1
DFSDM1
Conversion external trigger
Y
Y
Y
Y
-
-
Interconnect source
TIMx
COMPx
ADCx
RTC
Interconnect
destination
TIM2
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
TIM1,8
COMPx
TIM15,16,17
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
GPIO
Interconnect action
Y
Y
Y
1. LPTIM1 and LPTIM3 only.
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80
Functional overview
3.11
STM32L562xx
Reset and clock controller (RCC)
The clock controller (see Figure 7) distributes the clocks coming from the different
oscillators to the core and to the peripherals. It also manages the clock gating for low-power
modes and ensures the clock robustness. It features:
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•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Clock security system: clock sources can be changed safely on the fly in Run mode
through a configuration register.
•
Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals or memory.
•
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
–
4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
–
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 110 MHz.
•
RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can
be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be
output on the MCO.
•
UCPD kernel clock: it is derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior to the UCPD kernel clock use.
•
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
–
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
–
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to
output a 250 Hz as source clock.
•
Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.
Three PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs.
•
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
DS12736 Rev 4
STM32L562xx
Functional overview
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
•
Clock-out capability:
–
MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application
–
LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 110 MHz.
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80
Functional overview
STM32L562xx
Figure 7. STM32L562xx clock tree
to IWDG
LSI RC 32 kHz
LSCO
to RTC
OSC32_OUT
LSE OSC
32.768 kHz
/32
OSC32_IN
MCO
to PWR
LSE
LSI
MSI
HSI16
HSE
SYSCLK
/ 1→16
to AHB bus, core, memory and DMA
AHB PRESC
/ 1,2,..512
HCLK
PLLCLK
HSI48
to Cortex system timer
/8
Clock
source
control
OSC_OUT
HSE OSC
4-48 MHz
OSC_IN
Clock
detector
FCLK Cortex free running clock
APB1 PRESC
/ 1,2,4,8,16
HSE
PCLK1
to APB1 peripherals
x1 or x2
MSI
SYSCLK
HSI16
LSE
HSI16
SYSCLK
to USARTx
X=2..5
to LPUART1
HSI RC
16 MHz
HSI16
SYSCLK
MSI RC
100 kHz – 48 MHz
PLL
MSI
HSI16
HSE
/M
/P
PLLSAI3CLK
/Q
PLL48M1CLK
/R
PLLCLK
OCTOSPI clock
CRS clock
PCLK2
APB2 PRESC
/ 1,2,4,8,16
MSI
HSI16
HSE
/M
/P
PLLSAI1CLK
/Q
PLL48M2CLK
/R
PLLADC1CLK
to TIMx
x=1,8,15,16,17
LSE
HSI16
SYSCLK
MSI
48 MHz clock to USB, RNG
/P
HSE
PLLSAI2CLK
To UCPD1
MSI
HSI16
DFSDM
audio clock
/Q
/R
to ADC
HSI16
FDCAN
/M
to
USART1
SDMMC clock
48
MHz
SYSCLK
MSI
HSI16
HSE
to APB2 peripherals
x1 or x2
HSI16
PLLSAI2
to LPTIMx
x=1,2
MSI
HSI16
PLLSAI1
to I2Cx
x=1,2,3,4
LSI
LSE
HSI16
RC 48 MHz
to TIMx
x=2..7
to SAI1
HSI16
SAI1_EXTCLK
to SAI2
SAI2_EXTCLK
MSv49302V2
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DS12736 Rev 4
STM32L562xx
Functional overview
TrustZone security
When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security allows to secure some RCC system configuration and
peripheral configuration clock from being read or modified by non-secure accesses:
•
•
RCC system security:
–
HSE, HSE-CSS, HSI, MSI, LSI, LSE, LSE-CSS, HSI48 configuration and status
bits
–
Main PLL, PLLSAI1, PLLSAI2, AHB prescaler configuration and status bits
–
System clock SYSCLK and HSI48 source clock selection and status bits
–
MCO clock output configuration and STOPWUCK bit
–
Reset flag RMVF configuration bit
RCC peripheral security:
–
•
3.12
When a peripheral is secure, the related peripheral clock, reset, clock source
selection and clock enable during low power modes control bits are secure.
A peripheral is in secure state when:
–
For securable peripherals, when it's corresponding SEC security bit is set in the
TZSC (TrustZone security controller)
–
For TrustZone-aware peripherals, a security feature of this peripheral is enabled
through its dedicated bits.
Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.13
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in Analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
GPIO TrustZone security
Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.
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Functional overview
3.14
STM32L562xx
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, SDMMC1) and
the slaves (Flash memory, RAM, FMC, OCTOSPI, AHB and APB peripherals). It also
ensures a seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Figure 8. Multi-AHB bus matrix
C-bus
CORTEX®-M33
with TrustZone and FPU
Legend
DMA2 SDMMC1
Bus multiplexer
Master Interface
S-bus
Slave Interface
MPCBBx: Memory protection controller block based
MPCWMx: Memory protection controller Watermark
Fast-bus
8 KB I-Cache
Slow-bus
DMA1
FLASH
512 KB
MPCBB1
SRAM1
MPCBB2
SRAM2
AHB1
peripherals
MPCWM1
MPCWM2
MPCWM3
OTFDEC
AHB2
peripherals
OctoSPI1
FSMC
BusMatrix-S
MSv49331V1
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DS12736 Rev 4
STM32L562xx
3.15
Functional overview
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 13: DMA1 and DMA2 implementation for the
features implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 16 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports 8 channels for each DMA1 and DMA2, independently configurable:
•
Each channel is associated either with a DMA request signal coming from a peripheral,
or with a software trigger in memory-to-memory transfers. This configuration is done by
software.
•
Priority between the requests is programmable by software (4 levels per channel: very
high, high, medium, low) or by hardware in case of equality (such as request 1 has
priority over request 2).
•
Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be aligned
on the data size.
•
Support of transfers from/to peripherals to/from memory with circular buffer
management.
•
Programmable number of data to be transferred: 0 to 218 - 1.
•
Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
•
TrustZone support:
•
–
Support for AHB secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source and destination sub-level
–
TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access
Privileged / unprivileged support:
–
Support for AHB privileged and unprivileged DMA transfers, independently at a
channel level
–
Privileged-aware AHB slave port.
Table 13. DMA1 and DMA2 implementation
Feature
DMA1
DMA2
Number of DMA channels
8
8
TrustZone
1 (supported)
1 (supported)
DS12736 Rev 4
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Functional overview
3.16
STM32L562xx
DMA request router (DMAMUX)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
DMAMUX main features
•
16-channel programmable DMA request line multiplexer output
•
4-channel DMA request generator
•
23 trigger inputs to DMA request generator
•
23 synchronization inputs
•
Per DMA request generator channel:
•
•
•
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–
DMA request trigger input selector
–
DMA request counter
–
Event overrun flag for selected DMA request trigger input
Per DMA request line multiplexer channel output:
–
90 input DMA request lines from peripherals
–
One DMA request line output
–
Synchronization input selector
–
DMA request counter
–
Event overrun flag for selected synchronization input
–
One event output, for DMA request chaining
TrustZone support:
–
Support for AHB secure and non-secure DMA transfers, independently at a
channel level.
–
TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access, with configurable interrupt
event.
–
Two secure and non-secure interrupt requests, resulting from any of the
respectively secure and non-secure channels. Each channel event being caused
from any of the two DMAMUX input events: trigger or synchronization overrun,
associated with a respectively secure and non-secure channels.
Privileged / Unprivileged support:
–
Support for AHB privileged and unprivileged DMA transfers, independently, at a
channel level.
–
Privileged-aware AHB slave port.
DS12736 Rev 4
STM32L562xx
Functional overview
3.17
Interrupts and events
3.17.1
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 8 priority
levels, and to handle up to 109 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M33.
The NVIC benefits are the following:
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
•
TrustZone support. The NVIC registers are banked across secure and non-secure
states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2
Extended interrupt/event controller (EXTI)
The Extended interrupts and event controller (EXTI) manages the individual CPU and
system wakeup through configurable and direct event inputs. It provides wakeup requests to
the power control, and generates an interrupt request to the CPU NVIC and events to the
CPU event input. For the CPU an additional Event Generation block (EVG) is needed to
generate the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in RUN modes. The
EXTI also includes the EXTI mux IOport selection.
The EXTI main features are the following:
The EXTI main features are the following:
•
43 input events supported
•
All event inputs allow to wake up the system.
•
Events which do not have an associated wakeup flag in the peripheral, have a flag in
the EXTI and generate an interrupt to the CPU from the EXTI.
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Functional overview
STM32L562xx
The asynchronous event inputs are classified in 2 groups:
•
Configurable events (signals from I/Os or peripherals able to generate a pulse)
–
•
Direct events (interrupt and wakeup sources from peripherals having an associated
flag which requiring to be cleared in the peripheral)
–
•
3.18
Direct events have the following features:
Fixed rising edge active trigger
No interrupt pending status register bit in the EXTI. (The interrupt pending status
flag is provided by the peripheral generating the event.)
Individual interrupt and event generation mask, used for conditioning the CPU
wakeup and event generation.
No SW trigger possibility
TrustZone secure events
–
•
Configurable events have the following features:
Selectable active trigger edge
Interrupt pending status register bit independent for the rising and falling edge.
Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation.
SW trigger possibility
The access to control and configuration bits of secure input events can be made
secure.
EXTI IO port selection
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.19
Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) includes two memory controllers:
•
The NOR/PSRAM memory controller
•
The NAND/memory controller
This memory controller is also named flexible memory controller (FMC).
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Functional overview
The main features of the FSMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (four memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
–
Ferroelectric RAM (FRAM)
•
8-,16- bit data bus width
•
Independent chip select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
TrustZone security
When the TrustZone security is enabled, the whole FSMC banks are secure after reset.
Non-secure area can be configured using the TZSC MPCWMx controller.
•
The FSMC NOR/PSRAM bank:
–
•
Up to two non-secure area can be configured thought the TZSC MPCWM2
controller with a granularity of 64 Kbytes.
The FSMC NAND bank:
–
Can be either configured as fully secure or fully non-secure using the TZSC
MPCWM3 controller.
The FSMC registers can be configured as secure through the TZSC controller.
3.20
Octo-SPI interface (OCTOSPI)
The OCTOSPI is a specialized communication interface targetting single, dual, quad or octal
SPI memories. It can operate in any of the three following modes:
•
Indirect mode: all the operations are performed using the OCTOSPI registers
•
Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation
The OCTOSPI supports two frame formats:
•
Classical frame format with command, address, alternate byte, dummy cycles and data
phase over 1, 2, 4 or 8 data pins
•
HyperBusTM frame format
The OCTOSPI offers the following features:
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•
Three functional modes: indirect, status-polling, and memory-mapped
•
Read and write support in memory-mapped mode
•
Supports for single, dual, quad and octal communication
•
Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel.
•
SDR and DTR support
•
Data strobe support
•
Fully programmable opcode for both indirect and memory mapped mode
•
Fully programmable frame format for both indirect and memory mapped mode
•
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
–
Instruction phase
–
Address phase
–
Alternate bytes phase
–
Dummy cycles phase
–
Data phase
•
HyperBusTM support
•
Integrated FIFO for reception and transmission
•
8, 16, and 32-bit data accesses are allowed
•
DMA channel for indirect mode operations
•
Timeout management
•
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
TrustZone security
When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a
granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.
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3.21
Functional overview
Analog-to-digital converter (ADC)
The device embeds two successive approximation analog-to-digital converters with the
following features:
•
12-bit native resolution, with built-in calibration
•
5.33 Msps maximum conversion rate with full resolution
Down to 18.75 ns sampling time
–
Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
•
Up to 16 external channels
•
5 internal channels: internal reference voltage, temperature sensor, VBAT/3 and DAC1
outputs
•
One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
•
Single-ended and differential mode inputs
•
Low-power design
•
3.21.1
–
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–
Results stored into a data register or in RAM with DMA controller support
–
Data pre-processing: left/right alignment and per channel offset compensation
–
Built-in oversampling unit for enhanced SNR
–
Channel-wise programmable sampling time
–
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channels which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Table 14. Temperature sensor calibration values
3.21.2
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x0BFA 05A8 - 0x0BFA 05A9
TS_CAL2
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x0BFA 05CA- 0x0BFA 05CB
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 15. Internal voltage reference calibration values
3.21.3
Calibration value name
Description
Memory address
VREFINT
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x0BFA 05AA - 0x0BFA 05AB
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the VBAT battery voltage using
the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than the VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third of the VBAT voltage.
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3.22
Functional overview
Digital to analog converter (DAC)
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
•
Up to two DAC output channels
•
8-bit or 12-bit output mode
•
Buffer offset calibration (factory and user trimming)
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
External triggers for conversion
•
Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.23
Voltage reference buffer (VREFBUF)
The devices embed a voltage reference buffer which can be used as voltage reference for
ADC, DACs and also as voltage reference for external components through the VREF+ pin.
The internal voltage reference buffer supports two voltages:
•
2.048 V
•
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 9. Voltage reference buffer
VREFBUF
VDDA
Bandgap
+
DAC, ADC
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
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STM32L562xx
Comparators (COMP)
The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low-power) and with selectable
output polarity.
The reference voltage can be one of the following:
•
External I/O
•
DAC output channels
•
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can also be combined into a window comparator.
3.25
Operational amplifier (OPAMP)
The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
3.26
•
Low input bias current
•
Low offset voltage
•
Low-power mode
•
Rail-to-rail input
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with four digital filters modules and eight external input
serial channels (transceivers) or alternately eight internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs).
The DFSDM can also interface the PDM (pulse density modulation) microphones and
perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional
parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into
DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators) and the DFSDM digital filter modules perform digital processing according to
the user’s selected filter parameters with up to 24-bit final ADC resolution.
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Functional overview
The DFSDM peripheral supports:
•
•
•
•
Up to 4 multiplexed input digital serial channels:
–
Configurable SPI interface to connect various Σ∆ modulators
–
Configurable Manchester coded 1 wire interface support
–
Clock output for Σ∆ modulator(s)
Alternative inputs from up to 4 internal digital parallel channels:
–
Inputs with up to 16 bit resolution
–
Internal sources: ADCs data or memory (CPU/DMA write) data streams
Adjustable digital signal processing:
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
Integrator: oversampling ratio (1..256)
Up to 24-bit output data resolution:
–
Right bit-shifter on final data (0..31 bits)
•
Signed output data format
•
Automatic data offset correction (offset stored in register by user)
•
Continuous or single conversion
•
Start-of-conversion synchronization with:
•
–
Software trigger
–
Internal timers
–
External events
–
Start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)
Analog watchdog feature:
–
•
Low value and high value data threshold registers
–
Own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
Input from output data register or from one or more input digital serial channels
–
Continuous monitoring independently from standard conversion
Short-circuit detector to detect saturated analog input values (bottom and top ranges):
–
Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream
–
Mnitoring continuously each channel (4 serial channel transceiver outputs)
•
Break generation on analog watchdog event or short-circuit detector event
•
Extremes detector:
–
Store minimum and maximum values of output data values
–
Refreshed by software
•
DMA may be used to read the conversion data
•
Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock
absence
•
“Regular” or “injected” conversions:
–
“Regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions.
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Functional overview
3.27
STM32L562xx
Touch sensing controller (TSC)
The touch sensing controller provides a simple solution to add capacitive sensing
functionality to any application. A capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (glass, plastic
or other). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
Note:
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•
Proven and robust surface charge transfer acquisition principle
•
Supports up to 22 capacitive sensing channels
•
Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
•
Spread spectrum feature to improve system robustness in noisy environments
•
Full hardware management of the charge transfer acquisition sequence
•
Programmable charge transfer frequency
•
Programmable sampling capacitor I/O pin
•
Programmable channel I/O pin
•
Programmable max count value to avoid long acquisition when a channel is faulty
•
Dedicated end of acquisition and max count error flags with interrupt capability
•
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
•
Designed to operate with STMTouch touch sensing firmware library
The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
DS12736 Rev 4
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3.28
Functional overview
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random number generator:
3.29
•
delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage,
•
can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG),
•
produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise),
•
embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management,
•
can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration),
•
has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored).
Advanced encryption standard hardware accelerator (AES)
The devices embed an AES hardware accelerator that can be used both to encipher and to
decipher data using an AES algorithm.
The AES peripheral supports:
•
Encryption/decryption using AES Rijndael block cipher algorithm
•
NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
•
128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x
32-bit registers)
•
Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois
Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher
Message Authentication Code mode (CMAC) supported
•
Key scheduler
•
Key derivation for decryption
•
128-bit data block processing
•
128-bit, 256-bit key length
•
1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer
•
Register access supporting 32-bit data width only
•
One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected, GCM mode or
CMAC mode
•
Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for out coming data
•
Suspend a message if another message with a higher priority needs to be processed.
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3.30
STM32L562xx
HASH hardware accelerator (HASH)
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the
HMAC (keyed-hash message authentication code) algorithm suitable for a variety of
applications.
It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256
algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for
messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating
messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,
SHA-224, SHA-256 or MD5 hash function twice.
3.31
Public key accelerator PKA
The public key accelerator (PKA) is intended for the computation of cryptographic public key
primitives, specifically those related to RSA, Diffie-Hellmann or ECC (elliptic curve
cryptography) over GF(p) (Galois fields). To achieve high performance at a reasonable cost,
these operations are executed in the Montgomery domain.
All needed computations are performed within the accelerator, so no further
hardware/software elaboration is needed to process the inputs or the outputs.
PKA main features:
•
Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications. More specifically:
–
3.32
RSA modular exponentiation, RSA Chinese remainder theorem (CRT)
exponentiation
–
ECC scalar multiplication, point on curve check
–
ECDSA signature generation and verification
•
Capability to handle operands up to 3136 bits for RSA/DH and 640 bits for ECC.
•
Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication.
•
Built-in Montgomery domain inward and outward transformations
•
AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise, for writes, an AHB bus error is generated, and write accesses are ignored)
On-the-fly decryption engine (OTFDEC)
The embedded OTFDEC decrypts in real-time the encrypted content stored in the external
Octo-SPI memories used in Memory-mapped mode.
The OTFDEC uses the AES-128 algorithm in counter mode (CTR).
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Functional overview
The OTFDEC main features are the following:
•
•
•
•
Zero latency 128-bit decryption during STM32 AHB OCTOSPI read operations (single
or multiple).
–
Minimum read granularity is 8-bit, maximum is 512-bit
–
AES-CTR algorithm
Up to four independent encrypted regions
–
Granularity of the region definition: 4096 bytes
–
Region configuration write locking mechanism
–
Option to condition data decryption on instruction fetches only.
128-bit data decryption specific to each protected region.
–
Each region has its firmware version (two bytes), its 128-bit key and a fixed 64-bit
nonce.
–
Keystream based on the data system address
Encryption keys confidentiality and integrity protection
–
•
Support for STM32 OCTOSPI pre-fetching mechanism.
–
•
3.33
Write only registers, with software locking mechanism
AES-CTR keystream FIFO (depth=2)
Possibility to select an enhanced encryption mode to add a proprietary layer of
protection on top of AES stream cipher.
Timers and watchdogs
The devices include two advanced control timers, up to nine general-purpose timers, two
basic timers, two low-power timers, two watchdog timers and a SysTick timer.
Table 16 compares the features of the advanced control, general-purpose and basic timers.
Table 16. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Advanced
control
TIM1, TIM8
16-bit
Up, down,
Up/down
Any integer
between 1
and 65536
Yes
4
3
Generalpurpose
TIM2, TIM5
32-bit
Up, down,
Up/down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM3, TIM4
16-bit
Up, down,
Up/down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
1
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Table 16. Timer feature comparison (continued)
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Generalpurpose
TIM16, TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
1
Basic
TIM6, TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
3.33.1
Advanced-control timer (TIM1, TIM8)
The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes) with full modulation capability (0100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.33.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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3.33.2
Functional overview
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32L562xx devices (see Table 16 for differences).
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time
base.
•
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
–
TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
–
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•
TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM15 has two channels and one complementary channel
–
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.33.3
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
3.33.4
Low-power timers (LPTIM1, LPTIM2 and LPTIM3)
The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
LPTIM1 and LPTIM3 are active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
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This low-power timer supports the following features:
3.33.5
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous/ one shot mode
•
Selectable software/hardware input trigger
•
Selectable clock source
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
–
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
Programmable digital glitch filter
•
Encoder mode (LPTIM1 only).
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.33.6
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.33.7
SysTick timer
The Cortex®-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
•
SysTick, Secure instance.
•
SysTick, Non-secure instance.
When TrustZone is disabled, only one SysTick timer is available.
This timer (secure or non-secure) is dedicated to real-time operating systems, but could
also be used as a standard down counter. It features:
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•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
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3.34
Functional overview
Real-time clock (RTC)
The RTC supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
•
TrustZone support:
–
RTC fully securable
–
Alarm A, alarm B, wakeup Timer and timestamp individual secure or non-secure
configuration
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.
3.35
Tamper and backup registers (TAMP)
32 32-bit backup registers are retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. 8 tamper pins and 7 internal tampers are available for anti-tamper
detection.
The external tamper pins can be configured for edge detection, or level detection with or
without filtering, or active tamper which increases the security level by auto checking that
the tamper pins are not externally opened or shorted.
DS12736 Rev 4
73/342
80
Functional overview
STM32L562xx
TAMP main features:
•
32 backup registers:
–
•
The backup registers (TAMP_BKPxR) are implemented in the RTC domain that
remains powered-on by VBAT when the VDD power is switched off
8 external tamper detection events
–
Each external event can be configured to be active or passive
–
External passive tampers with configurable filter and internal pull-up
•
5 internal tamper events
•
Any tamper detection can generate a RTC timestamp event
•
Any tamper detection can erase the backup registers
•
TrustZone support:
–
Tamper secure or non-secure configuration.
–
Backup registers configuration in 3 configurable-size areas:
1 read/write secure area
1 write secure/read non-secure area
1 read/write non-secure area
•
74/342
Monotonic counter.
DS12736 Rev 4
STM32L562xx
3.36
Functional overview
Inter-integrated circuit interface (I2C)
The device embeds four I2C. Refer to Table 17: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power system management protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 7: STM32L562xx clock tree
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Table 17. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
Fast-mode (up to 400 kbit/s)
X
X
X
X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
X
X
X
Programmable analog and digital noise filters
X
X
X
X
SMBus/PMBus hardware support
X
X
X
X
Independent clock
X
X
X
X
Wakeup from Stop 0, Stop 1 mode on address match
X
X
X
X
Wakeup from Stop 2 mode on address match
-
-
X
-
1. X: supported
DS12736 Rev 4
75/342
80
Functional overview
3.37
STM32L562xx
Universal synchronous/asynchronous receiver transmitter
(USART)
The devices have three embedded universal synchronous receiver transmitters (USART1,
USART2 and USART3) and two universal asynchronous receiver transmitters (UART4,
UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable. They are able to communicate at speeds of up to
10 Mbit/s.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The
wake up events from Stop mode are programmable and can be:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 18. USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3
UART4
UART5
LPUART1
Hardware flow control for modem
X
X
X
X
X
X
Continuous communication using DMA
X
X
X
X
X
X
Multiprocessor communication
X
X
X
X
X
X
Synchronous mode
X
X
X
-
-
-
Smartcard mode
X
X
X
-
-
-
Single-wire half-duplex communication
X
X
X
X
X
X
IrDA SIR ENDEC block
X
X
X
X
X
-
LIN mode
X
X
X
X
X
-
Dual clock domain
X
X
X
X
X
X
Wakeup from Stop 0 / Stop 1 modes
X
X
X
X
X
X
Wakeup from Stop 2 mode
-
-
-
-
-
X
Receiver timeout interrupt
X
X
X
X
X
-
Modbus communication
X
X
X
X
X
-
Auto baud rate detection
Driver enable
X (4 modes)
X
X
LPUART/USART data length
X
7, 8 and 9 bits
1. X = supported.
76/342
X
-
DS12736 Rev 4
X
X
STM32L562xx
3.38
Functional overview
Low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed one low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half-duplex single-wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.39
Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and
simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size
is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode
and hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.40
Serial audio interfaces (SAI)
The devices embed two SAI. Refer to Table 19: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
•
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•
8-word integrated FIFOs for each audio sub-block.
•
Synchronous or asynchronous mode between the audio sub-blocks.
•
Master or slave configuration independent for both audio sub-blocks.
•
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
•
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
DS12736 Rev 4
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80
Functional overview
STM32L562xx
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•
Number of bits by frame may be configurable.
•
Frame synchronization active level configurable (offset, bit length, level).
•
First active bit position in the slot is configurable.
•
LSB first or MSB first for data transfer.
•
Mute mode.
•
Stereo/Mono audio frame capability.
•
Communication clock strobing edge configurable (SCK).
•
Error flags with associated interrupts if enabled respectively.
•
•
–
Overrun and underrun detection.
–
Anticipated frame synchronization signal detection in slave mode.
–
Late frame synchronization signal detection in slave mode.
–
Codec not ready for the AC’97 mode in reception.
Interruption sources when enabled:
–
Errors.
–
FIFO requests.
DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
Table 19. SAI implementation
SAI features(1)
SAI1
SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
Mute mode
X
X
Stereo/Mono audio frame capability.
X
X
16 slots
X
X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X
X (8 Word)
X (8 Word)
SPDIF
X
X
PDM
X
-
FIFO size
1. X: supported
3.41
Secure digital input/output and MultiMediaCards Interface
(SDMMC)
The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.
78/342
DS12736 Rev 4
STM32L562xx
Functional overview
The SDMMC features include the following:
3.42
•
Full compliance with MultiMediaCard System Specification Version 4.51. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
•
Full compatibility with previous versions of MultiMediaCards (backward compatibility)
•
Full compliance with SD Memory Card Specifications Version 4.1. (SDR104
SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode
not supported)
•
Full compliance with SDIO Card Specification Version 4.0: card support for two different
databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to
maximum allowed IO speed, SPI mode and UHS-II mode not supported)
•
Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO
speed)
•
Data and command output enable signals to control external bidirectional drivers.
Controller area network (FDCAN)
The controller area network (CAN) subsystem consists of one CAN modules and message
RAM memory.
The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 1 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers.
3.43
Universal serial bus (USB FS)
The devices embed a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and battery charging detection according to Battery Charging Specification Revision
1.2.
The USB interface implements a full-speed (12 Mbit/s) function interface with added support
for USB 2.0 link power management. It has software-configurable endpoint setting with
packet memory up-to 1 Kbyte and suspend/resume support.
This interface requires a precise 48 MHz clock which can be generated from the internal
main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz
oscillator (HSI48) in automatic trimming mode. The synchronization for this oscillator can be
taken from the USB data stream itself (SOF signalization) which allows crystal less
operation.
3.44
USB Type-C™ / USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.
DS12736 Rev 4
79/342
80
Functional overview
STM32L562xx
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
•
“Dead battery” support
•
USB Power Delivery message transmission and reception
•
FRS (fast role swap) support
The digital controller handles notably:
•
USB Type-C level detection with debounce, generating interrupts
•
FRS detection, generating an interrupt
•
Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
•
USB Power Delivery timing dividers (including a clock pre-scaler)
•
CRC generation/checking
•
4b5b encode/decode
•
Ordered sets (with a programmable ordered set mask at receive)
•
Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.45
Development support
3.45.1
Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.45.2
Embedded Trace Macrocell™
The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the devices
through a small number of ETM pins to an external hardware trace port analyzer (TPA)
device. Real-time instruction and data flow activity be recorded and then formatted for
display on the host computer that runs the debugger software. TPA hardware is
commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
80/342
DS12736 Rev 4
STM32L562xx
Pinouts and pin description
PA14
PB5
41
PA15
PB6
42
37
PB7
43
38
PH3-BOOT0
44
PB4
PB8
45
PB3
PB9
46
39
VSS
47
40
VDD
48
Figure 10. STM32L562xx LQFP48 pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14_OSC32_IN
3
34
PA13
PC15_OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS
VDD
LQFP48
MSv49322V1
1. The above figure shows the package top view.
PB6
PB5
PB4
42
41
40
PA14
PB7
43
37
PH3-BOOT0
44
PB3
PB8
45
PA15
VDD12_2
46
38
VSS
47
39
VDD
48
Figure 11. STM32L562xxxxP LQFP48 external SMPS pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14-OSC_IN
3
34
PA13
PC15-OSC_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VDD12_1
VSS
VDD
LQFP48
PA3
4
Pinouts and pin description
MSv49311V1
1. The above figure shows the package top view.
DS12736 Rev 4
81/342
139
Pinouts and pin description
STM32L562xx
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 12. STM32L562xx UFQFPN48 pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS
VDD
UFQFPN48
MSv49321V2
1. The above figure shows the package top view.
VDD
VSS
VDD12_2
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 13. STM32L562xxxxP UFQFPN48 external SMPS pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14-OSC_IN
3
34
PA13
PC15-OSC_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VDD12_1
VSS
VDD
UFQFPN48
MSv49310V2
1. The above figure shows the package top view.
82/342
DS12736 Rev 4
STM32L562xx
Pinouts and pin description
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 14. STM32L562xx LQFP64 pinout
VBAT
1
48
VDDUSB
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
4
45
PA12
PH0-OSC_IN
5
44
PA11
PH1-OSC_OUT
6
43
PA10
NRST
7
42
PA9
PC0
8
41
PA8
PC1
9
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA/VREF-
12
37
PC6
VDDA/VREF+
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS
VDD
LQFP64
MSv49323V1
1. The above figure shows the package top view.
VDD
V15SMPS_2
VSS
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 15. STM32L562xxxxQ LQFP64 SMPS step down converter pinout
VBAT
1
48
VDDUSB
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
4
45
PA12
PH0-OSC_IN
5
44
PA11
PH1-OSC_OUT
6
43
PA10
NRST
7
42
PA9
PC0
8
41
PA8
PC1
9
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA/VREF-
12
37
PC6
VDDA/VREF+
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VDDSMPS
VLXSMPS
VSSSMPS
VSS
V15SMPS_1
LQFP64
MSv49316V1
1. The above figure shows the package top view.
DS12736 Rev 4
83/342
139
Pinouts and pin description
STM32L562xx
VDD
VSS
VDD12_2
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PC12
PC11
PC10
PA15
PA14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 16. STM32L562xxxxP LQFP64 external SMPS pinout
VBAT
1
48
VDDUSB
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
4
45
PA12
PH0-OSC_IN
5
44
PA11
PH1-OSC_OUT
6
43
PA10
NRST
7
42
PA9
PC0
8
41
PA8
PC1
9
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA/VREF-
12
37
PC6
VDDA/VREF+
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PB0
PB1
PB2
PB10
PB11
VDD12_1
VSS
VDD
LQFP64
MSv49312V2
1. The above figure shows the package top view.
Figure 17. STM32L562xxxxQ WLCSP81 SMPS step down converter ballout
1
2
3
4
5
6
7
8
9
A
VDD
PC10
PD2
PG13
VDDIO2
PB5
PB9
V15SMPS_2
VDD
B
VDDUSB
VSS
PC12
PG12
VSS
PB4
PC13
VSS
VBAT
C
PA11
PA12
PC11
PG10
PG15
PB6
PB8
PC15OSC32_OUT
PC14OSC32_IN
D
PA9
PA13
PA14
PG9
PG14
PB7
PH3-BOOT0
PH1OSC_OUT
PH0-OSC_IN
E
PC6
PC7
PA10
PA15
PG11
PB3
PC0
VSS
NRST
F
PB15
PB13
PC8
PA8
PA3
PA1
PC2
PC1
VDD
G
PB14
PB12
PC9
PC4
PA6
PA2
PC3
VREF+
VSSA/VREF-
H
VDD
VSS
VLXSMPS
PB11
PB1
PA5
PA4
PA0
VDDA
J
V15SMPS_1
VSSSMPS
VDDSMPS
PB10
PB2
PB0
PA7
VDD
VSS
MSv49317V1
1. The above figure shows the package top view.
84/342
DS12736 Rev 4
STM32L562xx
Pinouts and pin description
Figure 18. STM32L562xxxxP WLCSP81 external SMPS ballout
1
2
3
4
5
6
7
8
9
A
VDD
PC10
PD2
PG13
VDDIO2
PB5
PB9
VDD12_2
VDD
B
VDDUSB
VSS
PC12
PG12
VSS
PB4
PC13
VSS
VBAT
C
PA11
PA12
PC11
PG10
PG15
PB6
PB8
PC15OSC32_OUT
PC14OSC32_IN
D
PA9
PA13
PA14
PG9
PG14
PB7
PH3-BOOT0
PH1OSC_OUT
PH0-OSC_IN
E
PC6
PC7
PA10
PA15
PG11
PB3
PC0
VSS
NRST
F
PB15
PB13
PC8
PA8
PA3
PA1
PC2
PC1
VDD
G
PB14
PB12
PC9
PC4
PA6
PA2
PC3
VREF+
VSSA/VREF-
H
VDD
VSS
PE15
PE14
PB1
PA5
PA4
PA0
VDDA
J
VDD12_1
PB11
PB10
PE13
PB2
PB0
PA7
VDD
VSS
MSv49313V1
1. The above figure shows the package top view.
VDD
VSS
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 19. STM32L562xx LQFP100 pinout
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VDDUSB
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
VSSA
19
57
PD10
VREF-
20
56
PD9
VREF+
21
55
PD8
VDDA
22
54
PB15
PA0
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS
VDD
LQFP100
MSv49324V1
1. The above figure shows the package top view.
DS12736 Rev 4
85/342
139
Pinouts and pin description
STM32L562xx
V15SMPS_2
VSS
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD
100
99
Figure 20. STM32L562xxxxQ LQFP100 SMPS step down converter pinout
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VDDUSB
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
VSSA/VREF-
19
57
PD10
VREF+
20
56
PD9
VDDA
21
55
PD8
PA0
22
54
PB15
PA1
23
53
PB14
PA2
24
52
PB13
PA3
25
51
VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VDDSMPS
VLXSMPS
VSSSMPS
VSS
V15SMPS_1
LQFP100
MSv49318V1
1. The above figure shows the package top view.
86/342
DS12736 Rev 4
STM32L562xx
Pinouts and pin description
Figure 21. STM32L562xx UFBGA132 ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
PE5
PE3
PE1
PB9
PB6
PG12
PD6
PD5
PD2
PC11
PA15
VDDUSB
B
VBAT
PE4
PE2
PG15
PH3-BOOT0
PB4
PG9
PD4
PD1
PC12
PC10
PA12
C
PC14OSC32_IN
PE6
PC13
PE0
PB8
PB3
PG10
PD3
PD0
PA13
PA14
PA11
D
PC15OSC32_OUT
PF0
PF3
VDD
PB7
PB5
PD7
VDDIO2
VDD
PA9
PA10
PA8
E
PF2
PF1
PF4
VSS
VSS
PC7
PC9
PC8
F
PH0-OSC_IN
PF5
PC2
PC3
VSS
VDD
PG6
PG7
PC6
PG8
G
PH1OSC_OUT
NRST
PC1
PA1
VDD
VSS
PG4
PG2
PG3
PG5
VSS
VSS
PD14
PD13
PD15
H
VSSA/VREF-
PC0
OPAMP1_VI
NM
J
VREF+
PA0
PC5
VDD
PF14
PE8
PE10
PE12
VDD
PD9
PD11
PD12
K
VDDA
PA2
PA7
PB2
PF11
PG1
PE7
PE14
PB10
PB13
PB14
PB15
L
PA3
PA6
PA4
PB1
PF12
PF15
PE11
PE15
PB11
VSS
PB12
PD8
PA5
OPAMP2_VI
NM
PC4
PB0
PF13
PG0
PE9
PE13
PG14
PG13
PG11
PD10
M
MSv49325V1
1. The above figure shows the package top view.
Figure 22. STM32L562xxxxQ UFBGA132 SMPS step down converter ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
PE5
PE3
PE1
PB9
PB6
PG12
PD6
PD5
PD2
PC11
PA15
VDDUSB
B
VBAT
PE4
PE2
V15SMPS_2
PH3-BOOT0
PB4
PG9
PD4
PD1
PC12
PC10
PA12
C
PC14OSC32_IN
PE6
PC13
PE0
PB8
PB3
PG10
PD3
PD0
PA13
PA14
PA11
D
PC15OSC32_OUT
PF0
PF3
VDD
PB7
PB5
PD7
VDDIO2
VDD
PA9
PA10
PA8
E
PF2
PF1
PF4
VSS
VSS
PC7
PC9
PC8
F
PH0-OSC_IN
PF5
PC2
PC3
VSS
VDD
PG6
PG7
PC6
PG8
G
PH1OSC_OUT
NRST
PC1
PA1
VDD
VSS
PG4
PG2
PG3
PG5
H
VSSA/VREF-
PC0
OPAMP1_VI
NM
VSS
VSS
PD14
PD13
PD15
J
VREF+
PA0
PC5
VDD
PF14
PE8
PE10
PE12
VDD
PD9
PD11
PD12
K
VDDA
PA2
PA7
PB2
PF11
PG1
PE7
PE14
PB10
PB13
PB14
PB15
L
PA3
PA6
PA4
PB1
PF12
PF15
PE11
PE15
PB11
VSSSMPS
PB12
PD8
M
PA5
OPAMP2_VI
NM
PC4
PB0
PF13
PG0
PE9
PE13
VDDSMPS
VLXSMPS
V15SMPS_1
PD10
MSv49319V1
1. The above figure shows the package top view.
DS12736 Rev 4
87/342
139
Pinouts and pin description
STM32L562xx
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
VSS
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDDIO2
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 23. STM32L562xx LQFP144 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0
PA1
PA2
MSv49326V1
1. The above figure shows the package top view.
88/342
DS12736 Rev 4
STM32L562xx
Pinouts and pin description
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
V15SMPS_2
VSS
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDDIO2
VSS
PG14
PG13
PG12
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 24. STM32L562xxxxQ LQFP144 SMPS step down converter pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
VDD
VSS
VDD
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VDDSMPS
VLXSMPS
VSSSMPS
VSS
V15SMPS_1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA/VREFVREF+
VDDA
PA0
PA1
PA2
PA3
MSv49320V1
1. The above figure shows the package top view.
DS12736 Rev 4
89/342
139
Name
Pin name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
Pin type
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TT
3.6 V tolerant I/O
B
Dedicated BOOT0 pin
RST
Pinouts and pin description
90/342
Table 20. Legend/abbreviations used in the pinout table
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
DS12736 Rev 4
I/O structure
_f (1)
_u
_a
(2)
(3)(4)
_s (5)
Notes
I/O, Fm+ capable
I/O, with USB function supplied by VDDUSB
I/O, with Analog switch function supplied by VDDA
I/O supplied only by VDDIO2
_c
I/O, USB Type-C PD capable
_d
I/O, USB Type-C PD dead battery function
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional
Functions directly selected/enabled through peripheral registers
functions
2. The related I/O structures in Table 21 are: FT_u.
3. The related I/O structures in Table 21 are: FT_a, FT_fa, TT_a.
4. The analog switch for the TSC function is supplied by VDD.
5. The related I/O structures in Table 21 are: FT_s, FT_fs.
STM32L562xx
1. The related I/O structures in Table 21 are: FT_f, FT_fa.
STM32L562xx
Table 21. STM32L562xx pin definitions
DS12736 Rev 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
2
3
4
B3
A2
B2
A1
1
2
3
4
-
-
-
-
-
-
-
-
-
-
-
-
1
2
3
4
B3
A2
B2
A1
1
2
3
4
PE2
PE3
PE4
PE5
I/O
I/O
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xx
FT
FT
FT
FT
91/342
Alternate functions
Additional
functions
-
TRACECK, TIM3_ETR,
SAI1_CK1,
TSC_G7_IO1,
FMC_A23,
SAI1_MCLK_A,
EVENTOUT
-
-
TRACED0, TIM3_CH1,
OCTOSPI1_DQS,
TSC_G7_IO2,
FMC_A19,
SAI1_SD_B,
EVENTOUT
-
-
TRACED1, TIM3_CH2,
SAI1_D2,
DFSDM1_DATIN3,
TSC_G7_IO3,
FMC_A20, SAI1_FS_A,
EVENTOUT
-
-
TRACED2, TIM3_CH3,
SAI1_CK2,
DFSDM1_CKIN3,
TSC_G7_IO4,
FMC_A21,
SAI1_SCK_A,
EVENTOUT
-
Pinouts and pin description
-
-
STM32L562xxxxQ
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
DS12736 Rev 4
-
5
C2
5
-
-
-
5
C2
5
PE6
I/O
FT
-
1
1
1
B9
1
B9
6
B1
6
1
1
1
6
B1
6
VBAT
S
-
-
-
-
EVENTOUT
WKUP2,
RTC_TS/RTC_
OUT1,
TAMP_IN1/TAMP_
OUT2
EVENTOUT
OSC32_IN
(2)
EVENTOUT
OSC32_OUT
2
3
2
3
2
3
B7
C9
2
3
B7
C9
7
8
C3
C1
7
8
2
3
2
3
2
3
7
8
C3
C1
LQFP144
-
UFBGA132
-
LQFP100
-
LQFP64
-
LQFP48
-
TRACED3, TIM3_CH4,
SAI1_D1, FMC_A22,
SAI1_SD_A,
EVENTOUT
UFQFPN48
Alternate functions
LQFP64_SMPS
Notes
I/O structure
Pin type
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
STM32L562xxxxQ
WLCSP81_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
7
PC13
I/O
FT
8
PC14OSC3
I/O
2_IN
(PC14)
FT
PC15OSC3
I/O
2_OUT
(PC15)
FT
(1)
(2)
(1)
(2)
(1)
Additional
functions
WKUP3,
TAMP_IN3/TAMP_
OUT6
4
4
C8
4
C8
9
D1
9
4
4
4
9
D1
9
-
-
-
-
-
-
-
D2
10
-
-
-
-
D2
10
PF0
I/O
FT
_f
-
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
-
-
-
-
-
-
E2
11
-
-
-
-
E2
11
PF1
I/O
FT
_f
-
I2C2_SCL, FMC_A1,
EVENTOUT
-
STM32L562xx
4
Pinouts and pin description
92/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
Pin Number
LQFP64_SMPS
WLCSP81_SMPS
LQFP100_SMPS
UFBGA132_SMPS
LQFP144_SMPS
UFQFPN48
LQFP48
LQFP64
LQFP100
UFBGA132
LQFP144
Pin name
(function after reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
-
-
-
-
-
E1
12
-
-
-
-
E1
12
PF2
I/O
FT
-
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
-
-
-
D3
13
-
-
-
-
D3
13
PF3
I/O
FT
-
LPTIM3_IN1, FMC_A3,
EVENTOUT
-
-
-
-
-
-
-
-
E3
14
-
-
-
-
E3
14
PF4
I/O
FT
-
LPTIM3_ETR,
FMC_A4, EVENTOUT
-
-
-
-
-
-
-
-
F2
15
-
-
-
-
F2
15
PF5
I/O
FT
-
LPTIM3_OUT,
FMC_A5, EVENTOUT
-
-
-
-
-
-
-
10
F6
16
-
-
-
10
F6
16
VSS
S
-
-
-
-
-
-
-
-
-
-
11
F7
17
-
-
-
11
F7
17
VDD
S
-
-
-
-
-
TIM5_ETR, TIM5_CH1,
OCTOSPI1_IO3,
SAI1_SD_B,
EVENTOUT
-
-
TIM5_CH2,
OCTOSPI1_IO2,
SAI1_MCLK_B,
EVENTOUT
TAMP_IN6/TAMP_
OUT3
-
TIM5_CH3,
OCTOSPI1_IO0,
SAI1_SCK_B,
EVENTOUT
TAMP_IN7/TAMP_
OUT8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18
19
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18
19
20
PF6
PF7
PF8
I/O
I/O
I/O
FT
FT
FT
Additional
functions
93/342
Pinouts and pin description
WLCSP81_Ext-SMPS
DS12736 Rev 4
LQFP64_Ext-SMPS
STM32L562xx
LQFP48_Ext-SMPS
STM32L562xxxxQ
UFQFPN48_ExtSMPS
STM32L562xxxxP
DS12736 Rev 4
-
5
-
-
5
-
5
-
-
D9
-
-
5
-
-
D9
-
-
12
-
-
F1
21
22
23
-
-
5
-
-
5
-
-
5
-
-
12
-
-
F1
21
PF9
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xxxxQ
FT
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
TIM5_CH4,
OCTOSPI1_IO1,
SAI1_FS_B,
TIM15_CH1,
EVENTOUT
TAMP_IN8/TAMP_
OUT7
-
I/O
FT
-
OCTOSPI1_CLK,
DFSDM1_CKOUT,
SAI1_D3, TIM15_CH2,
EVENTOUT
23
PH0OSC_I
I/O
N
(PH0)
FT
-
EVENTOUT
OSC_IN
I/O
FT
-
EVENTOUT
OSC_OUT
I-O
RS
T
-
-
-
22
PF10
6
6
6
D8
6
D8
13
G1
24
6
6
6
13
G1
24
PH1OSC_
OUT
(PH1)
7
7
7
E9
7
E9
14
G2
25
7
7
7
14
G2
25
NRST
Pinouts and pin description
94/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
-
-
-
9
10
E7
F8
F7
8
9
10
E7
F8
F7
15
16
17
H2
G3
F3
26
27
28
-
-
-
-
-
-
8
9
10
15
16
17
H2
G3
F3
26
27
28
PC0
PC1
PC2
I/O
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
8
STM32L562xx
FT
_fa
FT
_fa
FT
_a
Alternate functions
Additional
functions
-
LPTIM1_IN1,
OCTOSPI1_IO7,
I2C3_SCL,
LPUART1_RX,
SDMMC1_D5,
SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
ADC12_IN1
-
TRACED0,
LPTIM1_OUT,
SPI2_MOSI,
I2C3_SDA,
LPUART1_TX,
OCTOSPI1_IO4,
SAI1_SD_A,
EVENTOUT
ADC12_IN2
-
LPTIM1_IN2,
SPI2_MISO,
DFSDM1_CKOUT,
OCTOSPI1_IO5,
EVENTOUT
ADC12_IN3
95/342
Pinouts and pin description
-
-
STM32L562xxxxQ
Notes
DS12736 Rev 4
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
DS12736 Rev 4
G7
18
F4
29
-
-
11
18
F4
29
PC3
I/O
FT
_a
-
-
-
-
-
-
-
-
-
-
-
-
-
19
-
30
VSSA
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
-
31
VREF-
S
-
-
-
-
8
8
12
G9
12
G9
19
H1
30
8
8
12
-
H1
-
VSSA/
VREF-
S
-
-
-
-
-
-
-
G8
-
G8
20
J1
31
-
-
-
21
J1
32
VREF
+
S
-
-
-
VREFBUF_OUT
-
-
-
H9
-
H9
21
K1
32
-
-
-
22
K1
33
VDDA
S
-
-
-
-
9
9
13
-
13
-
-
-
-
9
9
13
-
-
-
VDDA/
VREF
+
S
-
-
-
-
LQFP144
11
UFBGA132
G7
LQFP100
11
LQFP64
-
LQFP48
-
LPTIM1_ETR,
LPTIM3_OUT,
SAI1_D1, SPI2_MOSI,
OCTOSPI1_IO6,
SAI1_SD_A,
LPTIM2_ETR,
EVENTOUT
UFQFPN48
Alternate functions
LQFP64_SMPS
Notes
I/O structure
Pin type
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
STM32L562xxxxQ
WLCSP81_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Additional
functions
ADC12_IN4
Pinouts and pin description
96/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
DS12736 Rev 4
22
J2
33
10
10
14
23
J2
34
PA0
I/O
FT
_a
-
-
-
-
-
-
-
-
H3
-
-
-
-
-
H3
-
OPAM
P1_VI
NM
I
TT
-
-
-
-
TIM2_CH2, TIM5_CH2,
I2C1_SMBA,
SPI1_SCK,
USART2_RTS/USART
2_DE, UART4_RX,
OCTOSPI1_DQS,
TIM15_CH1N,
EVENTOUT
OPAMP1_VINM,
ADC12_IN6,
TAMP_IN5/TAMP_
OUT4
11
11
15
F6
15
F6
23
G4
34
11
11
15
24
G4
LQFP144
H8
UFBGA132
14
LQFP100
H8
LQFP64
14
LQFP48
10
UFQFPN48
10
TIM2_CH1, TIM5_CH1,
TIM8_ETR,
USART2_CTS/USART
2_NSS, UART4_TX,
SAI1_EXTCLK,
TIM2_ETR,
EVENTOUT
LQFP64_SMPS
Alternate functions
35
PA1
I/O
FT
_a
Additional
functions
OPAMP1_VINP,
ADC12_IN5,
WKUP1,
TAMP_IN2/TAMP_
OUT1
97/342
Pinouts and pin description
Notes
I/O structure
Pin type
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
STM32L562xxxxQ
WLCSP81_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
12
G6
16
G6
24
K2
35
12
12
16
25
K2
36
PA2
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
16
STM32L562xxxxQ
FT
_a
Notes
DS12736 Rev 4
12
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
TIM2_CH3, TIM5_CH3,
USART2_TX,
LPUART1_TX,
OCTOSPI1_NCS,
UCPD1_FRSTX1,
SAI2_EXTCLK,
TIM15_CH1,
EVENTOUT
ADC12_IN7,
WKUP4/LSCO,
COMP1_INP
OPAMP1_VOUT,
ADC12_IN8
13
17
F5
17
F5
25
L1
36
13
13
17
26
L1
37
PA3
I/O
TT
_a
-
-
-
18
H2
18
H2
26
G7
37
-
-
18
27
G7
38
VSS
S
-
-
-
-
-
-
19
-
19
-
27
G6
38
-
-
19
28
G6
39
VDD
S
-
-
-
-
-
OCTOSPI1_NCS,
SPI1_NSS, SPI3_NSS,
USART2_CK,
SAI1_FS_B,
LPTIM2_OUT,
EVENTOUT
ADC12_IN9,
DAC1_OUT1
14
14
20
H7
20
H7
28
L3
39
14
14
20
29
L3
40
PA4
I/O
TT
_a
STM32L562xx
13
TIM2_CH4, TIM5_CH4,
SAI1_CK1,
USART2_RX,
LPUART1_RX,
OCTOSPI1_CLK,
SAI1_MCLK_A,
TIM15_CH2,
EVENTOUT
Pinouts and pin description
98/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
15
H6
21
H6
29
M1
40
15
15
21
30
M1
41
PA5
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
21
STM32L562xxxxQ
TT
_a
DS12736 Rev 4
Alternate functions
Additional
functions
-
TIM2_CH1, TIM2_ETR,
TIM8_CH1N,
SPI1_SCK,
LPTIM2_ETR,
EVENTOUT
ADC12_IN10,
DAC1_OUT2
OPAMP2_VINP,
ADC12_IN11
-
16
16
22
G5
22
G5
30
L2
41
16
16
22
31
L2
42
PA6
I/O
FT
_a
-
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
USART3_CTS/USART
3_NSS,
LPUART1_CTS,
OCTOSPI1_IO3,
TIM16_CH1,
EVENTOUT
-
-
-
-
-
-
-
M2
-
-
-
-
-
M2
-
OPAM
P2_VI
NM
I
TT
-
-
99/342
Pinouts and pin description
Notes
15
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
DS12736 Rev 4
31
K3
42
17
17
23
32
K3
43
PA7
I/O
FT
_fa
-
-
-
24
G4
-
G4
-
M3
-
-
-
24
33
M3
44
PC4
I/O
FT
_a
-
USART3_TX,
OCTOSPI1_IO7,
EVENTOUT
COMP1_INM,
ADC12_IN13
-
SAI1_D3,
USART3_RX,
EVENTOUT
ADC12_IN14,
WKUP5,
TAMP_IN4/TAMP_
OUT5,
COMP1_INP
-
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
SPI1_NSS,
USART3_CK,
OCTOSPI1_IO1,
COMP1_OUT,
SAI1_EXTCLK,
EVENTOUT
OPAMP2_VOUT,
ADC12_IN15
-
18
-
18
-
25
-
J6
-
24
-
J6
-
32
J3
M4
-
43
-
18
-
18
25
26
34
35
J3
M4
LQFP144
J7
UFBGA132
23
LQFP100
J7
LQFP64
23
LQFP48
17
UFQFPN48
17
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
I2C3_SCL,
SPI1_MOSI,
OCTOSPI1_IO2,
TIM17_CH1,
EVENTOUT
LQFP64_SMPS
Alternate functions
45
46
PC5
PB0
I/O
I/O
FT
_a
TT
_a
Additional
functions
OPAMP2_VINM,
ADC12_IN12
STM32L562xx
Notes
I/O structure
Pin type
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
STM32L562xxxxQ
WLCSP81_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Pinouts and pin description
100/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
19
H5
25
H5
33
L4
44
19
19
27
36
L4
47
PB1
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
26
STM32L562xxxxQ
FT
_a
Notes
DS12736 Rev 4
19
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN0,
USART3_RTS/USART
3_DE,
LPUART1_RTS/LPUA
RT1_DE,
OCTOSPI1_IO0,
LPTIM2_IN1,
EVENTOUT
COMP1_INM,
ADC12_IN16
RTC_OUT2,
COMP1_INP
20
27
J5
26
J5
34
K4
45
20
20
28
37
K4
48
PB2
I/O
FT
_a
-
-
-
-
-
-
-
-
K5
46
-
-
-
-
K5
49
PF11
I/O
FT
-
OCTOSPI1_NCLK,
EVENTOUT
-
-
-
-
-
-
-
-
L5
47
-
-
-
-
L5
50
PF12
I/O
FT
-
FMC_A6, EVENTOUT
-
-
-
-
J9
-
J9
-
-
48
-
-
-
-
-
51
VSS
S
-
-
-
-
-
-
-
J8
-
J8
-
-
49
-
-
-
-
-
52
VDD
S
-
-
-
-
-
-
-
-
-
-
-
M5
50
-
-
-
-
M5
53
PF13
I/O
FT
-
I2C4_SMBA, FMC_A7,
EVENTOUT
-
Pinouts and pin description
101/342
20
LPTIM1_OUT,
I2C3_SMBA,
DFSDM1_CKIN0,
OCTOSPI1_DQS,
UCPD1_FRSTX1,
EVENTOUT
Pin Number
LQFP64_SMPS
WLCSP81_SMPS
LQFP100_SMPS
UFBGA132_SMPS
LQFP144_SMPS
UFQFPN48
LQFP48
LQFP64
LQFP100
UFBGA132
LQFP144
Pin name
(function after reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
-
-
-
-
-
J5
51
-
-
-
-
J5
54
PF14
I/O
FT
_f
-
I2C4_SCL,
TSC_G8_IO1,
FMC_A8, EVENTOUT
-
-
-
-
-
-
-
-
L6
52
-
-
-
-
L6
55
PF15
I/O
FT
_f
-
I2C4_SDA,
TSC_G8_IO2,
FMC_A9, EVENTOUT
-
-
-
-
-
-
-
-
M6
53
-
-
-
-
M6
56
PG0
I/O
FT
-
TSC_G8_IO3,
FMC_A10, EVENTOUT
-
-
-
-
-
-
-
-
K6
54
-
-
-
-
K6
57
PG1
I/O
FT
-
TSC_G8_IO4,
FMC_A11, EVENTOUT
-
-
TIM1_ETR,
DFSDM1_DATIN2,
FMC_D4, SAI1_SD_B,
EVENTOUT
-
-
TIM1_CH1N,
DFSDM1_CKIN2,
FMC_D5,
SAI1_SCK_B,
EVENTOUT
-
-
TIM1_CH1,
DFSDM1_CKOUT,
OCTOSPI1_NCLK,
FMC_D6, SAI1_FS_B,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35
36
37
K7
J6
M7
55
56
57
-
-
-
-
-
-
-
-
-
38
39
40
K7
J6
M7
58
59
60
PE7
PE8
PE9
I/O
I/O
I/O
FT
FT
FT
Additional
functions
STM32L562xx
WLCSP81_Ext-SMPS
DS12736 Rev 4
LQFP64_Ext-SMPS
STM32L562xx
LQFP48_Ext-SMPS
STM32L562xxxxQ
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pinouts and pin description
102/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
Pin Number
LQFP64_SMPS
WLCSP81_SMPS
LQFP100_SMPS
UFBGA132_SMPS
LQFP144_SMPS
UFQFPN48
LQFP48
LQFP64
LQFP100
UFBGA132
LQFP144
Pin name
(function after reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
-
-
-
-
-
-
58
-
-
-
-
L10
61
VSS
S
-
-
-
-
-
-
-
H1
-
H1
-
J4
59
-
-
-
-
J4
62
VDD
S
-
-
-
-
-
TIM1_CH2N,
TSC_G5_IO1,
OCTOSPI1_CLK,
FMC_D7,
SAI1_MCLK_B,
EVENTOUT
-
-
TIM1_CH2,
TSC_G5_IO2,
OCTOSPI1_NCS,
FMC_D8, EVENTOUT
-
-
TIM1_CH3N,
SPI1_NSS,
TSC_G5_IO3,
OCTOSPI1_IO0,
FMC_D9, EVENTOUT
-
-
TIM1_CH3, SPI1_SCK,
TSC_G5_IO4,
OCTOSPI1_IO1,
FMC_D10, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J4
-
-
-
-
-
-
-
-
38
39
40
41
J7
L7
J8
M8
60
61
62
63
-
-
-
-
-
-
-
-
-
-
-
-
41
42
43
44
J7
L7
J8
M8
63
64
65
66
PE10
PE11
PE12
PE13
I/O
I/O
I/O
I/O
FT
FT
FT
FT
Additional
functions
103/342
Pinouts and pin description
WLCSP81_Ext-SMPS
DS12736 Rev 4
LQFP64_Ext-SMPS
STM32L562xx
LQFP48_Ext-SMPS
STM32L562xxxxQ
UFQFPN48_ExtSMPS
STM32L562xxxxP
DS12736 Rev 4
-
21
-
-
21
-
28
H4
H3
J3
-
-
27
-
-
J4
42
43
44
K8
L8
K9
64
65
66
-
-
21
-
-
21
-
-
29
45
46
47
K8
L8
K9
67
68
69
PE14
PE15
PB10
I/O
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xxxxQ
FT
FT
FT
_f
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH4,
TIM1_BKIN2,
SPI1_MISO,
OCTOSPI1_IO2,
FMC_D11, EVENTOUT
-
-
TIM1_BKIN,
SPI1_MOSI,
OCTOSPI1_IO3,
FMC_D12, EVENTOUT
-
-
TIM2_CH3,
LPTIM3_OUT,
I2C4_SCL, I2C2_SCL,
SPI2_SCK,
USART3_TX,
LPUART1_RX,
TSC_SYNC,
OCTOSPI1_CLK,
COMP1_OUT,
SAI1_SCK_A,
EVENTOUT
-
Pinouts and pin description
104/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
DS12736 Rev 4
45
L9
67
22
22
30
48
L9
70
PB11
I/O
FT
_f
-
-
-
-
-
28
J3
46
M9
68
-
-
-
-
-
-
VDDS
MPS
S
-
-
-
-
-
-
-
-
29
H3
47
M1
0
69
-
-
-
-
-
-
VLXS
MPS
S
-
-
-
-
-
-
-
-
30
J2
48
L10
70
-
-
-
-
-
-
VSSS
MPS
S
-
-
-
-
22
22
30
J1
-
-
-
-
-
-
-
-
-
-
-
VDD12
_1
S
-
-
-
-
23
23
31
B2
31
B2
49
E9
71
23
23
31
49
E9
71
VSS
S
-
-
-
-
-
-
-
-
32
J1
50
M11
72
-
-
-
-
-
-
V15S
MPS_
1
S
-
-
-
-
24
24
32
A1
33
A1
51
D4
73
24
24
32
50
D4
72
VDD
S
-
-
-
-
LQFP144
H4
UFBGA132
-
LQFP100
J2
LQFP64
29
LQFP48
-
UFQFPN48
-
TIM2_CH4, I2C4_SDA,
I2C2_SDA,
USART3_RX,
LPUART1_TX,
OCTOSPI1_NCS,
COMP2_OUT,
EVENTOUT
LQFP64_SMPS
Alternate functions
Additional
functions
-
105/342
Pinouts and pin description
Notes
I/O structure
Pin type
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
STM32L562xxxxQ
WLCSP81_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
26
25
26
34
G2
F2
-
34
G2
F2
-
52
L11
K10
-
74
25
26
25
26
33
34
51
52
L11
K10
73
74
PB12
PB13
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
33
STM32L562xxxxQ
FT
FT
_f
Alternate functions
Additional
functions
-
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS,
DFSDM1_DATIN1,
USART3_CK,
LPUART1_RTS/LPUA
RT1_DE,
TSC_G1_IO1,
OCTOSPI1_NCLK,
SAI2_FS_A,
TIM15_BKIN,
EVENTOUT
-
-
TIM1_CH1N,
LPTIM3_IN1,
I2C2_SCL, SPI2_SCK,
DFSDM1_CKIN1,
USART3_CTS/USART
3_NSS,
LPUART1_CTS,
TSC_G1_IO2,
UCPD1_FRSTX2,
SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
-
STM32L562xx
Notes
DS12736 Rev 4
25
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Pinouts and pin description
106/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
27
G1
35
G1
53
K11
75
27
27
35
53
K11
75
PB14
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
35
STM32L562xxxxQ
FT
_fd
Alternate functions
Additional
functions
-
TIM1_CH2N,
LPTIM3_ETR,
TIM8_CH2N,
I2C2_SDA,
SPI2_MISO,
DFSDM1_DATIN2,
USART3_RTS/USART
3_DE, TSC_G1_IO3,
SAI2_MCLK_A,
TIM15_CH1,
EVENTOUT
UCPD1_DB2
UCPD1_CC2
107/342
28
28
36
F1
36
F1
54
K12
76
28
28
36
54
K12
76
PB15
I/O
FT
_c
-
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI,
DFSDM1_CKIN2,
SAI2_SD_A,
TIM15_CH2,
EVENTOUT
-
-
-
-
-
-
55
L12
77
-
-
-
55
L12
77
PD8
I/O
FT
-
USART3_TX,
FMC_D13, EVENTOUT
-
-
USART3_RX,
FMC_D14,
SAI2_MCLK_A,
EVENTOUT
-
-
-
-
-
-
-
56
J10
78
-
-
-
56
J10
78
PD9
I/O
FT
Pinouts and pin description
Notes
DS12736 Rev 4
27
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
DS12736 Rev 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
57
58
59
M1
2
J11
J12
79
80
81
-
-
-
-
-
-
-
-
-
57
58
59
M1
2
J11
J12
79
80
81
PD10
PD11
PD12
I/O
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xxxxQ
FT
FT
FT
_f
Alternate functions
Additional
functions
-
USART3_CK,
TSC_G6_IO1,
FMC_D15,
SAI2_SCK_A,
EVENTOUT
-
-
I2C4_SMBA,
USART3_CTS/USART
3_NSS, TSC_G6_IO2,
FMC_A16,
SAI2_SD_A,
LPTIM2_ETR,
EVENTOUT
-
-
TIM4_CH1, I2C4_SCL,
USART3_RTS/USART
3_DE, TSC_G6_IO3,
FMC_A17, SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
-
-
-
-
-
-
-
-
-
60
H11
82
-
-
-
60
H11
82
PD13
I/O
FT
_f
-
TIM4_CH2, I2C4_SDA,
TSC_G6_IO4,
FMC_A18,
LPTIM2_OUT,
EVENTOUT
-
-
-
-
-
-
-
-
83
-
-
-
-
-
83
VSS
S
-
-
-
STM32L562xx
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Pinouts and pin description
108/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
Pin Number
LQFP64_SMPS
WLCSP81_SMPS
LQFP100_SMPS
UFBGA132_SMPS
LQFP144_SMPS
UFQFPN48
LQFP48
LQFP64
LQFP100
UFBGA132
LQFP144
Pin name
(function after reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
-
-
-
-
-
-
84
-
-
-
-
-
84
VDD
S
-
-
-
-
-
-
-
-
-
-
61
H10
85
-
-
-
61
H10
85
PD14
I/O
FT
-
TIM4_CH3, FMC_D0,
EVENTOUT
-
-
-
-
-
-
-
62
H12
86
-
-
-
62
H12
86
PD15
I/O
FT
-
TIM4_CH4, FMC_D1,
EVENTOUT
-
-
-
-
-
-
-
-
G10
87
-
-
-
-
G10
87
PG2
I/O
FT
_s
-
SPI1_SCK, FMC_A12,
SAI2_SCK_B,
EVENTOUT
-
-
-
-
-
-
-
-
G11
88
-
-
-
-
G11
88
PG3
I/O
FT
_s
-
SPI1_MISO, FMC_A13,
SAI2_FS_B,
EVENTOUT
-
-
-
-
-
-
-
-
G9
89
-
-
-
-
G9
89
PG4
I/O
FT
_s
-
SPI1_MOSI, FMC_A14,
SAI2_MCLK_B,
EVENTOUT
-
-
SPI1_NSS,
LPUART1_CTS,
FMC_A15,
SAI2_SD_B,
EVENTOUT
-
-
-
-
-
-
-
-
G12
90
-
-
-
-
G12
90
PG5
I/O
FT
_s
Additional
functions
109/342
Pinouts and pin description
WLCSP81_Ext-SMPS
DS12736 Rev 4
LQFP64_Ext-SMPS
STM32L562xx
LQFP48_Ext-SMPS
STM32L562xxxxQ
UFQFPN48_ExtSMPS
STM32L562xxxxP
-
-
-
-
-
F9
91
-
-
-
-
F9
91
PG6
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xxxxQ
FT
_s
DS12736 Rev 4
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
OCTOSPI1_DQS,
I2C3_SMBA,
LPUART1_RTS/LPUA
RT1_DE,
UCPD1_FRSTX1,
EVENTOUT
-
-
-
-
-
-
-
-
-
F10
92
-
-
-
-
F10
92
PG7
I/O
FT
_fs
-
SAI1_CK1, I2C3_SCL,
DFSDM1_CKOUT,
LPUART1_TX,
UCPD1_FRSTX2,
FMC_INT,
SAI1_MCLK_A,
EVENTOUT
-
-
-
-
-
-
-
F12
93
-
-
-
-
F12
93
PG8
I/O
FT
_fs
-
I2C3_SDA,
LPUART1_RX,
EVENTOUT
-
-
-
-
-
-
-
-
-
94
-
-
-
-
-
94
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
95
-
-
-
-
-
95
VDDIO
2
S
-
-
-
-
Pinouts and pin description
110/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
-
E1
37
E1
63
F11
96
-
-
37
63
F11
96
PC6
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
37
STM32L562xxxxQ
FT
Additional
functions
-
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
SDMMC1_D0DIR,
TSC_G4_IO1,
SDMMC1_D6,
SAI2_MCLK_A,
EVENTOUT
-
-
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
SDMMC1_D123DIR,
TSC_G4_IO2,
SDMMC1_D7,
SAI2_MCLK_B,
EVENTOUT
-
-
-
-
38
39
E2
F3
38
39
E2
F3
64
65
E10
E12
97
98
-
-
-
-
38
39
64
65
E10
E12
97
98
PC7
PC8
I/O
I/O
FT
-
-
TIM3_CH3, TIM8_CH3,
TSC_G4_IO3,
SDMMC1_D0,
EVENTOUT
FT
-
111/342
Pinouts and pin description
Alternate functions
DS12736 Rev 4
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
29
30
29
30
31
41
42
43
G3
F4
D1
E3
40
41
42
43
G3
F4
D1
E3
66
67
68
69
E11
99
D12 100
D10 101
D11 102
-
29
30
31
-
29
30
31
40
41
42
43
66
67
68
69
E11
99
D12 100
D10 101
D11 102
PC9
PA8
PA9
PA10
I/O
I/O
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
40
STM32L562xx
FT
_f
FT
_f
FT
_fu
FT
_fu
Alternate functions
Additional
functions
-
TRACED0,
TIM8_BKIN2,
TIM3_CH4, TIM8_CH4,
TSC_G4_IO4,
USB_NOE,
SDMMC1_D1,
SAI2_EXTCLK,
EVENTOUT
-
-
MCO, TIM1_CH1,
SAI1_CK2,
USART1_CK,
SAI1_SCK_A,
LPTIM2_OUT,
EVENTOUT
-
-
TIM1_CH2, SPI2_SCK,
USART1_TX,
SAI1_FS_A,
TIM15_BKIN,
EVENTOUT
-
-
TIM1_CH3, SAI1_D1,
USART1_RX,
CRS_SYNC,
SAI1_SD_A,
TIM17_BKIN,
EVENTOUT
-
STM32L562xx
31
-
STM32L562xxxxQ
Notes
DS12736 Rev 4
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Pinouts and pin description
112/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
DS12736 Rev 4
33
32
33
45
C1
C2
44
45
C1
C2
70
71
C12 103
B12 104
34
46
D2
46
D2
72
C10 105
-
-
47
-
47
-
-
-
-
48
B1
48
B1
73
A12 106
35
35
-
B5
-
B5
74
H4
36
36
-
A9
-
A9
75
D9
-
32
33
33
44
45
70
C12 103
B12 104
PA13
(JTMS/
C10 105
I/O
SWDI
O)
34
46
72
-
-
47
-
-
-
48
73
A12 106
107
35
35
-
74
H4
108
36
36
-
75
D9
-
-
PA12
I/O
71
34
-
PA11
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
32
Alternate functions
Additional
functions
-
TIM1_CH4,
TIM1_BKIN2,
SPI1_MISO,
USART1_CTS/USART
1_NSS, FDCAN1_RX,
USB_DM, EVENTOUT
-
-
TIM1_ETR,
SPI1_MOSI,
USART1_RTS/USART
1_DE, FDCAN1_TX,
USB_DP, EVENTOUT
-
FT
(3)
JTMS/SWDIO,
IR_OUT, USB_NOE,
SAI1_SD_B,
EVENTOUT
-
FT
_u
FT
_u
VSS
S
-
-
-
-
VDDU
SB
S
-
-
-
-
107
VSS
S
-
-
-
-
108
VDD
S
-
-
-
-
113/342
Pinouts and pin description
34
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
44
STM32L562xxxxQ
Notes
32
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
49
76
C11 109
37
37
49
DS12736 Rev 4
38
-
38
-
50
51
E4
A2
50
51
E4
A2
77
78
A11 110
B11 111
38
-
38
-
50
51
77
78
A11 110
B11 111
PA15
(JTDI)
PC10
I/O
I/O
I/O structure
Pin type
76
LQFP144
LQFP64
LQFP48
UFQFPN48
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
D3
PA14
(JTCK/
C11 109
I/O
SWCL
K)
FT
FT
_c
FT
Alternate functions
Additional
functions
(3)
JTCK/SWCLK,
LPTIM1_OUT,
I2C1_SMBA,
I2C4_SMBA,
SAI1_FS_B,
EVENTOUT
-
(3)
JTDI, TIM2_CH1,
TIM2_ETR,
USART2_RX,
SPI1_NSS, SPI3_NSS,
USART3_RTS/USART
3_DE,
UART4_RTS/UART4_
DE, SAI2_FS_B,
EVENTOUT
UCPD1_CC1
-
TRACED1,
LPTIM3_ETR,
SPI3_SCK,
USART3_TX,
UART4_TX,
TSC_G3_IO2,
SDMMC1_D2,
SAI2_SCK_B,
EVENTOUT
-
STM32L562xx
Notes
D3
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
49
STM32L562xx
UFBGA132
37
STM32L562xxxxQ
LQFP100
37
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Pinouts and pin description
114/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
-
C3
52
C3
79
A10 112
-
-
52
79
A10 112
PC11
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
52
STM32L562xxxxQ
FT
Notes
DS12736 Rev 4
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
LPTIM3_IN1,
OCTOSPI1_NCS,
SPI3_MISO,
USART3_RX,
UART4_RX,
TSC_G3_IO3,
UCPD1_FRSTX2,
SDMMC1_D3,
SAI2_MCLK_B,
EVENTOUT
-
-
-
53
B3
53
B3
80
B10 113
-
-
53
80
B10 113
PC12
I/O
FT
-
-
-
-
-
-
-
81
C9
114
-
-
-
81
C9
114
PD0
I/O
FT
-
SPI2_NSS,
FDCAN1_RX,
FMC_D2, EVENTOUT
-
-
-
-
-
-
-
82
B9
115
-
-
-
82
B9
115
PD1
I/O
FT
-
SPI2_SCK,
FDCAN1_TX,
FMC_D3, EVENTOUT
-
Pinouts and pin description
115/342
-
TRACED3,
SPI3_MOSI,
USART3_CK,
UART5_TX,
TSC_G3_IO4,
SDMMC1_CK,
SAI2_SD_B,
EVENTOUT
DS12736 Rev 4
-
-
-
-
-
-
-
A3
-
-
54
-
-
A3
-
-
83
84
85
A9
C8
B8
116
117
118
-
-
-
-
-
-
54
-
-
83
84
85
A9
C8
B8
116
117
118
PD2
PD3
PD4
I/O
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xxxxQ
FT
FT
FT
Alternate functions
Additional
functions
-
TRACED2, TIM3_ETR,
USART3_RTS/USART
3_DE, UART5_RX,
TSC_SYNC,
SDMMC1_CMD,
EVENTOUT
-
-
SPI2_SCK,
SPI2_MISO,
DFSDM1_DATIN0,
USART2_CTS/USART
2_NSS, FMC_CLK,
EVENTOUT
-
-
SPI2_MOSI,
DFSDM1_CKIN0,
USART2_RTS/USART
2_DE, OCTOSPI1_IO4,
FMC_NOE,
EVENTOUT
-
-
-
-
-
-
-
-
86
A8
119
-
-
-
86
A8
119
PD5
I/O
FT
-
USART2_TX,
OCTOSPI1_IO5,
FMC_NWE,
EVENTOUT
-
-
-
-
-
-
-
-
120
-
-
-
-
-
120
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
121
-
-
-
-
-
121
VDD
S
-
-
-
-
STM32L562xx
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Pinouts and pin description
116/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
DS12736 Rev 4
-
-
-
-
-
-
-
-
-
-
D4
C4
-
-
-
-
-
-
D4
C4
87
88
-
-
A7
D7
B7
C7
122
123
124
125
-
-
-
-
-
-
-
-
-
-
-
-
87
88
-
-
A7
D7
B7
C7
122
123
124
125
PD6
PD7
PG9
PG10
I/O
I/O
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xx
FT
FT
FT
_s
FT
_s
117/342
Alternate functions
Additional
functions
-
SAI1_D1, SPI3_MOSI,
DFSDM1_DATIN1,
USART2_RX,
OCTOSPI1_IO6,
FMC_NWAIT,
SAI1_SD_A,
EVENTOUT
-
-
DFSDM1_CKIN1,
USART2_CK,
OCTOSPI1_IO7,
FMC_NCE/FMC_NE1,
EVENTOUT
-
-
SPI3_SCK,
USART1_TX,
FMC_NCE/FMC_NE2,
SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
-
-
LPTIM1_IN1,
SPI3_MISO,
USART1_RX,
FMC_NE3,
SAI2_FS_A,
TIM15_CH1,
EVENTOUT
-
Pinouts and pin description
-
-
STM32L562xxxxQ
Notes
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
-
E5
-
E5
-
-
-
-
-
-
-
M11 126
PG11
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
-
STM32L562xxxxQ
FT
_s
Notes
DS12736 Rev 4
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
LPTIM1_IN2,
OCTOSPI1_IO5,
SPI3_MOSI,
USART1_CTS/USART
1_NSS,
SAI2_MCLK_A,
TIM15_CH2,
EVENTOUT
-
-
-
-
B4
-
B4
-
A6
126
-
-
-
-
A6
127
PG12
I/O
FT
_s
-
-
-
-
A4
-
A4
-
-
127
-
-
-
-
M1
0
128
PG13
I/O
FT
_fs
-
I2C1_SDA,
USART1_CK,
FMC_A24, EVENTOUT
-
-
-
-
D5
-
D5
-
-
128
-
-
-
-
M9
129
PG14
I/O
FT
_fs
-
I2C1_SCL, FMC_A25,
EVENTOUT
-
-
-
-
B8
-
B8
-
H9
129
-
-
-
-
H9
130
VSS
S
-
-
-
-
-
-
-
A5
-
A5
-
D8
130
-
-
-
-
D8
131
VDDIO
2
S
-
-
-
-
STM32L562xx
-
LPTIM1_ETR,
SPI3_NSS,
USART1_RTS/USART
1_DE, FMC_NE4,
SAI2_SD_A,
EVENTOUT
Pinouts and pin description
118/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
Pin Number
LQFP64_Ext-SMPS
WLCSP81_Ext-SMPS
LQFP64_SMPS
WLCSP81_SMPS
LQFP100_SMPS
UFBGA132_SMPS
LQFP144_SMPS
UFQFPN48
LQFP48
LQFP64
LQFP100
UFBGA132
LQFP144
Pin name
(function after reset)
Pin type
I/O structure
Notes
STM32L562xx
LQFP48_Ext-SMPS
STM32L562xxxxQ
UFQFPN48_ExtSMPS
STM32L562xxxxP
Alternate functions
-
-
-
C5
-
C5
-
-
131
-
-
-
-
B4
132
PG15
I/O
FT
_s
-
LPTIM1_OUT,
I2C1_SMBA,
EVENTOUT
DS12736 Rev 4
39
40
54
55
E6
B6
55
56
E6
B6
89
90
C6
B6
132
133
39
40
39
40
55
56
89
90
C6
B6
PB4
134 (NJTR
ST)
I/O
FT
_a
FT
_fa
-
-
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK,
USART1_RTS/USART
1_DE, CRS_SYNC,
SAI1_SCK_B,
EVENTOUT
COMP2_INM
(3)
NJTRST, TIM3_CH1,
I2C3_SDA,
SPI1_MISO,
SPI3_MISO,
USART1_CTS/USART
1_NSS,
UART5_RTS/UART5_
DE, TSC_G2_IO1,
SAI1_MCLK_B,
TIM17_BKIN,
EVENTOUT
COMP2_INP
119/342
Pinouts and pin description
40
39
PB3
(JTDO/
133 TRAC I/O
ESWO
)
Additional
functions
42
41
42
57
A6
C6
57
58
A6
C6
91
92
D6
A5
134
135
41
42
41
42
57
58
91
92
D6
A5
135
136
PB5
PB6
I/O
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
56
STM32L562xxxxQ
FT
_d
FT
_fa
Alternate functions
Additional
functions
-
LPTIM1_IN1,
TIM3_CH2,
OCTOSPI1_NCLK,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI,
USART1_CK,
UART5_CTS/UART5_
NSS, TSC_G2_IO2,
COMP2_OUT,
SAI1_SD_B,
TIM16_BKIN,
EVENTOUT
UCPD1_DB1
-
LPTIM1_ETR,
TIM4_CH1,
TIM8_BKIN2,
I2C1_SCL, I2C4_SCL,
USART1_TX,
TSC_G2_IO3,
SAI1_FS_B,
TIM16_CH1N,
EVENTOUT
COMP2_INP
STM32L562xx
Notes
DS12736 Rev 4
41
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Pinouts and pin description
120/342
Table 21. STM32L562xx pin definitions (continued)
STM32L562xx
Table 21. STM32L562xx pin definitions (continued)
43
58
D6
59
D6
93
D5
136
43
43
59
93
D5
137
44
44
59
D7
60
D7
94
B5
137
44
44
60
94
B5
PH3138 BOOT
0
45
60
C7
61
C7
95
C5
138
45
45
61
95
C5
139
PB8
I/O structure
Alternate functions
I/O
FT
_fa
-
LPTIM1_IN2,
TIM4_CH2,
TIM8_BKIN,
I2C1_SDA, I2C4_SDA,
USART1_RX,
UART4_CTS,
TSC_G2_IO4,
FMC_NL,
TIM17_CH1N,
EVENTOUT
I/O
FT
-
EVENTOUT
-
-
TIM4_CH3, SAI1_CK1,
I2C1_SCL,
DFSDM1_CKOUT,
SDMMC1_CKIN,
FDCAN1_RX,
SDMMC1_D4,
SAI1_MCLK_A,
TIM16_CH1,
EVENTOUT
-
I/O
FT
_f
Additional
functions
COMP2_INM,
PVD_IN
121/342
Pinouts and pin description
45
PB7
Notes
DS12736 Rev 4
43
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
STM32L562xxxxQ
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
-
A7
-
A7
96
A4
139
46
46
62
96
A4
140
PB9
I/O
I/O structure
Pin type
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
STM32L562xx
LQFP144_SMPS
UFBGA132_SMPS
LQFP100_SMPS
WLCSP81_SMPS
LQFP64_SMPS
WLCSP81_Ext-SMPS
LQFP64_Ext-SMPS
61
STM32L562xxxxQ
FT
_f
Notes
DS12736 Rev 4
-
LQFP48_Ext-SMPS
UFQFPN48_ExtSMPS
STM32L562xxxxP
Pin name
(function after reset)
Pin Number
Alternate functions
Additional
functions
-
IR_OUT, TIM4_CH4,
SAI1_D2, I2C1_SDA,
SPI2_NSS,
SDMMC1_CDIR,
FDCAN1_TX,
SDMMC1_D5,
SAI1_FS_A,
TIM17_CH1,
EVENTOUT
-
-
-
-
-
-
-
97
C4
140
-
-
-
97
C4
141
PE0
I/O
FT
-
-
-
-
-
-
-
-
A3
141
-
-
-
98
A3
142
PE1
I/O
FT
-
FMC_NBL1,
TIM17_CH1,
EVENTOUT
-
46
46
62
A8
-
-
-
-
-
-
-
-
-
-
-
VDD12
_2
S
-
-
-
-
47
47
63
E8
62
E8
98
E4
142
47
47
63
99
E4
143
VSS
S
-
-
-
-
-
-
-
-
63
A8
99
B4
143
-
-
-
-
-
-
V15S
MPS_
2
S
-
-
-
-
48
48
64
F9
64
F9
100
J9
144
48
48
64
100
J9
144
VDD
S
-
-
-
-
STM32L562xx
-
TIM4_ETR,
FMC_NBL0,
TIM16_CH1,
EVENTOUT
Pinouts and pin description
122/342
Table 21. STM32L562xx pin definitions (continued)
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0438 reference manual.
3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated.
STM32L562xx
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output
mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
DS12736 Rev 4
Pinouts and pin description
123/342
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PA0
-
TIM2_CH1
TIM5_CH1
TIM8_ETR
-
-
-
USART2_CTS_
NSS
PA1
-
TIM2_CH2
TIM5_CH2
-
I2C1_SMBA
SPI1_SCK
-
USART2_RTS_
DE
PA2
-
TIM2_CH3
TIM5_CH3
-
-
-
-
USART2_TX
PA3
-
TIM2_CH4
TIM5_CH4
SAI1_CK1
-
-
-
USART2_RX
PA4
-
-
-
OCTOSPI1_NCS
-
SPI1_NSS
SPI3_NSS
USART2_CK
PA5
-
TIM2_CH1
TIM2_ETR
TIM8_CH1N
-
SPI1_SCK
-
-
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
-
SPI1_MISO
-
USART3_CTS_
NSS
PA7
-
TIM1_CH1N
TIM3_CH2
TIM8_CH1N
I2C3_SCL
SPI1_MOSI
-
-
PA8
MCO
TIM1_CH1
-
SAI1_CK2
-
-
-
USART1_CK
PA9
-
TIM1_CH2
-
SPI2_SCK
-
-
-
USART1_TX
PA10
-
TIM1_CH3
-
SAI1_D1
-
-
-
USART1_RX
PA11
-
TIM1_CH4
TIM1_BKIN2
-
-
SPI1_MISO
-
USART1_CTS_
NSS
PA12
-
TIM1_ETR
-
-
-
SPI1_MOSI
-
USART1_RTS_
DE
IR_OUT
-
-
-
-
-
-
-
-
I2C1_SMBA
I2C4_SMBA
-
-
TIM2_ETR
USART2_RX
-
SPI1_NSS
SPI3_NSS
USART3_RTS_
DE
Port
DS12736 Rev 4
Port
A
PA13 JTMS/SWDIO
PA14 JTCK/SWCLK LPTIM1_OUT
PA15
JTDI
TIM2_CH1
STM32L562xx
AF0
Pinouts and pin description
124/342
Table 22. Alternate function AF0 to AF7(1)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2N
-
SPI1_NSS
-
USART3_CK
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3N
-
-
DFSDM1_DATI USART3_RTS_
N0
DE
PB2
-
LPTIM1_OUT
-
-
I2C3_SMBA
-
DFSDM1_CKI
N0
-
PB3
JTDO/TRACE
SWO
TIM2_CH2
-
-
-
SPI1_SCK
SPI3_SCK
USART1_RTS_
DE
PB4
NJTRST
-
TIM3_CH1
-
I2C3_SDA
SPI1_MISO
SPI3_MISO
USART1_CTS_
NSS
PB5
-
LPTIM1_IN1
TIM3_CH2
OCTOSPI1_NCLK
I2C1_SMBA
SPI1_MOSI
SPI3_MOSI
USART1_CK
PB6
-
LPTIM1_ETR
TIM4_CH1
TIM8_BKIN2
I2C1_SCL
I2C4_SCL
-
USART1_TX
PB7
-
LPTIM1_IN2
TIM4_CH2
TIM8_BKIN
I2C1_SDA
I2C4_SDA
-
USART1_RX
PB8
-
-
TIM4_CH3
SAI1_CK1
I2C1_SCL
DFSDM1_CKOU
T
-
-
PB9
-
IR_OUT
TIM4_CH4
SAI1_D2
I2C1_SDA
SPI2_NSS
-
-
PB10
-
TIM2_CH3
LPTIM3_OUT
I2C4_SCL
I2C2_SCL
SPI2_SCK
-
USART3_TX
PB11
-
TIM2_CH4
-
I2C4_SDA
I2C2_SDA
-
-
USART3_RX
PB12
-
TIM1_BKIN
-
TIM1_BKIN
I2C2_SMBA
SPI2_NSS
DFSDM1_DATI
N1
USART3_CK
PB13
-
TIM1_CH1N
LPTIM3_IN1
-
I2C2_SCL
SPI2_SCK
DFSDM1_CKI
N1
USART3_CTS_
NSS
PB14
-
TIM1_CH2N
LPTIM3_ETR
TIM8_CH2N
I2C2_SDA
SPI2_MISO
DFSDM1_DATI USART3_RTS_
N2
DE
PB15
RTC_REFIN
TIM1_CH3N
-
TIM8_CH3N
-
SPI2_MOSI
DFSDM1_CKI
N2
Port
DS12736 Rev 4
Port
B
125/342
-
Pinouts and pin description
AF0
STM32L562xx
Table 22. Alternate function AF0 to AF7(1) (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PC0
-
LPTIM1_IN1
-
OCTOSPI1_IO7
I2C3_SCL
-
-
-
PC1
TRACED0
LPTIM1_OUT
-
SPI2_MOSI
I2C3_SDA
-
-
-
PC2
-
LPTIM1_IN2
-
-
-
SPI2_MISO
DFSDM1_CKO
UT
-
PC3
-
LPTIM1_ETR
LPTIM3_OUT
SAI1_D1
-
SPI2_MOSI
-
-
PC4
-
-
-
-
-
-
-
USART3_TX
PC5
-
-
-
SAI1_D3
-
-
-
USART3_RX
PC6
-
-
TIM3_CH1
TIM8_CH1
-
-
DFSDM1_CKI
N3
-
PC7
-
-
TIM3_CH2
TIM8_CH2
-
-
DFSDM1_DATI
N3
-
PC8
-
-
TIM3_CH3
TIM8_CH3
-
-
-
-
PC9
TRACED0
TIM8_BKIN2
TIM3_CH4
TIM8_CH4
-
-
-
-
PC10
TRACED1
-
LPTIM3_ETR
-
-
-
SPI3_SCK
USART3_TX
PC11
-
-
LPTIM3_IN1
-
-
OCTOSPI1_NCS
SPI3_MISO
USART3_RX
PC12
TRACED3
-
-
-
-
-
SPI3_MOSI
USART3_CK
PC13
-
-
-
-
-
-
-
-
PC14
-
-
-
-
-
-
-
-
PC15
-
-
-
-
-
-
-
-
Port
DS12736 Rev 4
Port
C
Pinouts and pin description
126/342
Table 22. Alternate function AF0 to AF7(1) (continued)
STM32L562xx
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PD0
-
-
-
-
-
SPI2_NSS
-
-
PD1
-
-
-
-
-
SPI2_SCK
-
-
PD2
TRACED2
-
TIM3_ETR
-
-
-
-
USART3_RTS_
DE
PD3
-
-
-
SPI2_SCK
-
SPI2_MISO
DFSDM1_DATI USART2_CTS_
N0
NSS
PD4
-
-
-
-
-
SPI2_MOSI
DFSDM1_CKI
N0
USART2_RTS_
DE
PD5
-
-
-
-
-
-
-
USART2_TX
PD6
-
-
-
SAI1_D1
-
SPI3_MOSI
DFSDM1_DATI
N1
USART2_RX
PD7
-
-
-
-
-
-
DFSDM1_CKI
N1
USART2_CK
PD8
-
-
-
-
-
-
-
USART3_TX
PD9
-
-
-
-
-
-
-
USART3_RX
PD10
-
-
-
-
-
-
-
USART3_CK
PD11
-
-
-
-
I2C4_SMBA
-
-
USART3_CTS_
NSS
PD12
-
-
TIM4_CH1
-
I2C4_SCL
-
-
USART3_RTS_
DE
PD13
-
-
TIM4_CH2
-
I2C4_SDA
-
-
-
PD14
-
-
TIM4_CH3
-
-
-
-
-
PD15
-
-
TIM4_CH4
-
-
-
-
-
Port
DS12736 Rev 4
Port
D
127/342
Pinouts and pin description
AF0
STM32L562xx
Table 22. Alternate function AF0 to AF7(1) (continued)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PE0
-
-
TIM4_ETR
-
-
-
-
-
PE1
-
-
-
-
-
-
-
-
PE2
TRACECK
-
TIM3_ETR
SAI1_CK1
-
-
-
-
PE3
TRACED0
-
TIM3_CH1
OCTOSPI1_DQS
-
-
-
-
PE4
TRACED1
-
TIM3_CH2
SAI1_D2
-
-
DFSDM1_DATI
N3
-
PE5
TRACED2
-
TIM3_CH3
SAI1_CK2
-
-
DFSDM1_CKI
N3
-
PE6
TRACED3
-
TIM3_CH4
SAI1_D1
-
-
-
-
PE7
-
TIM1_ETR
-
-
-
-
DFSDM1_DATI
N2
-
PE8
-
TIM1_CH1N
-
-
-
-
DFSDM1_CKI
N2
-
PE9
-
TIM1_CH1
-
-
-
-
DFSDM1_CKO
UT
-
PE10
-
TIM1_CH2N
-
-
-
-
-
-
PE11
-
TIM1_CH2
-
-
-
-
-
-
PE12
-
TIM1_CH3N
-
-
-
SPI1_NSS
-
-
PE13
-
TIM1_CH3
-
-
-
SPI1_SCK
-
-
PE14
-
TIM1_CH4
TIM1_BKIN2
TIM1_BKIN2
-
SPI1_MISO
-
-
PE15
-
TIM1_BKIN
-
TIM1_BKIN
-
SPI1_MOSI
-
-
Port
DS12736 Rev 4
Port
E
STM32L562xx
AF0
Pinouts and pin description
128/342
Table 22. Alternate function AF0 to AF7(1) (continued)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PF0
-
-
-
-
I2C2_SDA
-
-
-
PF1
-
-
-
-
I2C2_SCL
-
-
-
PF2
-
-
-
-
I2C2_SMBA
-
-
-
PF3
-
-
LPTIM3_IN1
-
-
-
-
-
PF4
-
-
LPTIM3_ETR
-
-
-
-
-
PF5
-
-
LPTIM3_OUT
-
-
-
-
-
PF6
-
TIM5_ETR
TIM5_CH1
-
-
-
-
-
PF7
-
-
TIM5_CH2
-
-
-
-
-
PF8
-
-
TIM5_CH3
-
-
-
-
-
PF9
-
-
TIM5_CH4
-
-
-
-
-
PF10
-
-
-
OCTOSPI1_CLK
-
-
DFSDM1_CKO
UT
-
PF11
-
-
-
OCTOSPI1_NCLK
-
-
-
-
PF12
-
-
-
-
-
-
-
-
PF13
-
-
-
-
I2C4_SMBA
-
-
-
PF14
-
-
-
-
I2C4_SCL
-
-
-
PF15
-
-
-
-
I2C4_SDA
-
-
-
Port
DS12736 Rev 4
Port
F
129/342
Pinouts and pin description
AF0
STM32L562xx
Table 22. Alternate function AF0 to AF7(1) (continued)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PG0
-
-
-
-
-
-
-
-
PG1
-
-
-
-
-
-
-
-
PG2
-
-
-
-
-
SPI1_SCK
-
-
PG3
-
-
-
-
-
SPI1_MISO
-
-
PG4
-
-
-
-
-
SPI1_MOSI
-
-
PG5
-
-
-
-
-
SPI1_NSS
-
-
PG6
-
-
-
OCTOSPI1_DQS
I2C3_SMBA
-
-
-
PG7
-
-
-
SAI1_CK1
I2C3_SCL
-
DFSDM1_CKO
UT
-
PG8
-
-
-
-
I2C3_SDA
-
-
-
PG9
-
-
-
-
-
-
SPI3_SCK
USART1_TX
PG1
0
-
LPTIM1_IN1
-
-
-
-
SPI3_MISO
USART1_RX
PG11
-
LPTIM1_IN2
-
OCTOSPI1_IO5
-
-
SPI3_MOSI
USART1_CTS_
NSS
PG1
2
-
LPTIM1_ETR
-
-
-
-
SPI3_NSS
USART1_RTS_
DE
PG1
3
-
-
-
-
I2C1_SDA
-
-
USART1_CK
PG1
4
-
-
-
-
I2C1_SCL
-
-
-
PG1
5
-
LPTIM1_OUT
-
-
I2C1_SMBA
-
-
-
Port
DS12736 Rev 4
Port
G
STM32L562xx
AF0
Pinouts and pin description
130/342
Table 22. Alternate function AF0 to AF7(1) (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS_AF
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
I2C1/2/3/4
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
SPI3/I2C3/DFS
DM1/COMP1/
USART1/2/3
PH0
-
-
-
-
-
-
-
-
PH1
-
-
-
-
-
-
-
-
PH3
-
-
-
-
-
-
-
-
Port
Port
H
-
STM32L562xx
Table 22. Alternate function AF0 to AF7(1) (continued)
1. Refer to Table 23 for AF8 to AF15.
DS12736 Rev 4
Pinouts and pin description
131/342
AF8
Port
DS12736 Rev 4
Port
A
AF9
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
PA0
UART4_TX
-
-
-
-
SAI1_EXTCLK
TIM2_ETR
EVENTOUT
PA1
UART4_RX
-
OCTOSPI1_DQS
-
-
-
TIM15_CH1N
EVENTOUT
PA2
LPUART1_TX
-
OCTOSPI1_NCS
UCPD1_FRSTX1
-
SAI2_EXTCLK
TIM15_CH1
EVENTOUT
PA3
LPUART1_RX
-
OCTOSPI1_CLK
-
-
SAI1_MCLK_A
TIM15_CH2
EVENTOUT
PA4
-
-
-
-
-
SAI1_FS_B
LPTIM2_OUT
EVENTOUT
PA5
-
-
-
-
-
-
LPTIM2_ETR
EVENTOUT
PA6
LPUART1_CTS
_NSS
-
OCTOSPI1_IO3
-
TIM1_BKIN
TIM8_BKIN
TIM16_CH1
EVENTOUT
PA7
-
-
OCTOSPI1_IO2
-
-
-
TIM17_CH1
EVENTOUT
PA8
-
-
-
-
-
SAI1_SCK_A
LPTIM2_OUT
EVENTOUT
PA9
-
-
-
-
-
SAI1_FS_A
TIM15_BKIN
EVENTOUT
PA10
-
-
CRS_SYNC
-
-
SAI1_SD_A
TIM17_BKIN
EVENTOUT
PA11
-
FDCAN1_
RX
USB_DM
-
TIM1_BKIN2
-
-
EVENTOUT
PA12
-
FDCAN1_
TX
USB_DP
-
-
-
-
EVENTOUT
PA13
-
-
USB_NOE
-
-
SAI1_SD_B
-
EVENTOUT
PA14
-
-
-
-
-
SAI1_FS_B
-
EVENTOUT
PA15
UART4_RTS_D
E
-
-
-
-
SAI2_FS_B
-
EVENTOUT
Pinouts and pin description
132/342
Table 23. Alternate function AF8 to AF15(1)
STM32L562xx
AF8
Port
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
PB0
-
-
OCTOSPI1_IO1
-
COMP1_OUT
SAI1_EXTCLK
-
EVENTOUT
PB1
LPUART1_RTS_
DE
-
OCTOSPI1_IO0
-
-
-
LPTIM2_IN1
EVENTOUT
PB2
-
-
OCTOSPI1_DQS
UCPD1_FRSTX1
-
-
-
EVENTOUT
PB3
-
-
CRS_SYNC
-
-
SAI1_SCK_B
-
EVENTOUT
DS12736 Rev 4
UART5_RTS_D TSC_G2_
E
IO1
-
-
-
SAI1_MCLK_B
TIM17_BKIN
EVENTOUT
PB5
UART5_CTS_N TSC_G2_
SS
IO2
-
-
COMP2_OUT
SAI1_SD_B
TIM16_BKIN
EVENTOUT
TSC_G2_
IO3
-
-
TIM8_BKIN2
SAI1_FS_B
TIM16_CH1N
EVENTOUT
PB7
UART4_CTS_N TSC_G2_
SS
IO4
-
-
FMC_NL
TIM8_BKIN
TIM17_CH1N
EVENTOUT
PB8
SDMMC1_CKIN
FDCAN1_
RX
-
-
SDMMC1_D4
SAI1_MCLK_A
TIM16_CH1
EVENTOUT
PB9
SDMMC1_CDIR
FDCAN1_
TX
-
-
SDMMC1_D5
SAI1_FS_A
TIM17_CH1
EVENTOUT
PB10
LPUART1_RX
TSC_SY
NC
OCTOSPI1_CLK
-
COMP1_OUT
SAI1_SCK_A
-
EVENTOUT
PB11
LPUART1_TX
-
OCTOSPI1_NCS
-
COMP2_OUT
-
-
EVENTOUT
PB12
LPUART1_RTS_ TSC_G1_
OCTOSPI1_NCLK
DE
IO1
-
-
SAI2_FS_A
TIM15_BKIN
EVENTOUT
PB13
LPUART1_CTS
_NSS
TSC_G1_
IO2
-
UCPD1_FRSTX2
-
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PB14
-
TSC_G1_
IO3
-
-
-
SAI2_MCLK_A
TIM15_CH1
EVENTOUT
PB15
-
-
-
-
-
SAI2_SD_A
TIM15_CH2
EVENTOUT
-
Pinouts and pin description
133/342
PB4
PB6
Port
B
AF9
STM32L562xx
Table 23. Alternate function AF8 to AF15(1) (continued)
AF8
Port
DS12736 Rev 4
Port
C
AF9
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
PC0
LPUART1_RX
-
-
-
SDMMC1_D5
SAI2_FS_A
LPTIM2_IN1
EVENTOUT
PC1
LPUART1_TX
-
OCTOSPI1_IO4
-
-
SAI1_SD_A
-
EVENTOUT
PC2
-
TSC_G3_
IO1
OCTOSPI1_IO5
-
-
-
-
EVENTOUT
PC3
-
TSC_G1_
IO4
OCTOSPI1_IO6
-
-
SAI1_SD_A
LPTIM2_ETR
EVENTOUT
PC4
-
-
OCTOSPI1_IO7
-
-
-
-
EVENTOUT
PC5
-
-
-
-
-
-
-
EVENTOUT
PC6
SDMMC1_D0DI TSC_G4_
R
IO1
-
-
SDMMC1_D6
SAI2_MCLK_A
-
EVENTOUT
PC7
SDMMC1_D123 TSC_G4_
DIR
IO2
-
-
SDMMC1_D7
SAI2_MCLK_B
-
EVENTOUT
-
TSC_G4_
IO3
-
-
SDMMC1_D0
-
-
EVENTOUT
PC9
-
TSC_G4_
IO4
USB_NOE
-
SDMMC1_D1
SAI2_EXTCLK
TIM8_BKIN2
EVENTOUT
PC10
UART4_TX
TSC_G3_
IO2
-
-
SDMMC1_D2
SAI2_SCK_B
-
EVENTOUT
PC11
UART4_RX
TSC_G3_
IO3
-
UCPD1_FRSTX2
SDMMC1_D3
SAI2_MCLK_B
-
EVENTOUT
PC12
UART5_TX
TSC_G3_
IO4
-
-
SDMMC1_CK
SAI2_SD_B
-
EVENTOUT
PC13
-
-
-
-
-
-
-
EVENTOUT
PC14
-
-
-
-
-
-
-
EVENTOUT
PC15
-
-
-
-
-
-
-
EVENTOUT
STM32L562xx
PC8
Pinouts and pin description
134/342
Table 23. Alternate function AF8 to AF15(1) (continued)
AF8
Port
DS12736 Rev 4
Port
D
AF9
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
-
FDCAN1_
RX
-
-
FMC_D2
-
-
EVENTOUT
PD1
-
FDCAN1_
TX
-
-
FMC_D3
-
-
EVENTOUT
PD2
UART5_RX
TSC_SY
NC
-
-
SDMMC1_CMD
-
-
EVENTOUT
PD3
-
-
-
-
FMC_CLK
-
-
EVENTOUT
PD4
-
-
OCTOSPI1_IO4
-
FMC_NOE
-
-
EVENTOUT
PD5
-
-
OCTOSPI1_IO5
-
FMC_NWE
-
-
EVENTOUT
PD6
-
-
OCTOSPI1_IO6
-
FMC_NWAIT
SAI1_SD_A
-
EVENTOUT
PD7
-
-
OCTOSPI1_IO7
-
FMC_NCE/FMC_
NE1
-
-
EVENTOUT
PD8
-
-
-
-
FMC_D13
-
-
EVENTOUT
PD9
-
-
-
-
FMC_D14
SAI2_MCLK_A
-
EVENTOUT
PD10
-
TSC_G6_
IO1
-
-
FMC_D15
SAI2_SCK_A
-
EVENTOUT
PD11
-
TSC_G6_
IO2
-
-
FMC_A16
SAI2_SD_A
LPTIM2_ETR
EVENTOUT
PD12
-
TSC_G6_
IO3
-
-
FMC_A17
SAI2_FS_A
LPTIM2_IN1
EVENTOUT
PD13
-
TSC_G6_
IO4
-
-
FMC_A18
-
LPTIM2_OUT
EVENTOUT
PD14
-
-
-
-
FMC_D0
-
-
EVENTOUT
PD15
-
-
-
-
FMC_D1
-
-
EVENTOUT
135/342
Pinouts and pin description
PD0
STM32L562xx
Table 23. Alternate function AF8 to AF15(1) (continued)
AF8
Port
DS12736 Rev 4
Port
E
AF9
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
-
-
-
-
FMC_NBL0
-
TIM16_CH1
EVENTOUT
PE1
-
-
-
-
FMC_NBL1
-
TIM17_CH1
EVENTOUT
PE2
-
TSC_G7_
IO1
-
-
FMC_A23
SAI1_MCLK_A
-
EVENTOUT
PE3
-
TSC_G7_
IO2
-
-
FMC_A19
SAI1_SD_B
-
EVENTOUT
PE4
-
TSC_G7_
IO3
-
-
FMC_A20
SAI1_FS_A
-
EVENTOUT
PE5
-
TSC_G7_
IO4
-
-
FMC_A21
SAI1_SCK_A
-
EVENTOUT
PE6
-
-
-
-
FMC_A22
SAI1_SD_A
-
EVENTOUT
PE7
-
-
-
-
FMC_D4
SAI1_SD_B
-
EVENTOUT
PE8
-
-
-
-
FMC_D5
SAI1_SCK_B
-
EVENTOUT
PE9
-
-
OCTOSPI1_NCLK
-
FMC_D6
SAI1_FS_B
-
EVENTOUT
PE10
-
TSC_G5_
IO1
OCTOSPI1_CLK
-
FMC_D7
SAI1_MCLK_B
-
EVENTOUT
PE11
-
TSC_G5_
IO2
OCTOSPI1_NCS
-
FMC_D8
-
-
EVENTOUT
PE12
-
TSC_G5_
IO3
OCTOSPI1_IO0
-
FMC_D9
-
-
EVENTOUT
PE13
-
TSC_G5_
IO4
OCTOSPI1_IO1
-
FMC_D10
-
-
EVENTOUT
PE14
-
-
OCTOSPI1_IO2
-
FMC_D11
-
-
EVENTOUT
PE15
-
-
OCTOSPI1_IO3
-
FMC_D12
-
-
EVENTOUT
STM32L562xx
PE0
Pinouts and pin description
136/342
Table 23. Alternate function AF8 to AF15(1) (continued)
AF8
Port
DS12736 Rev 4
Port
F
AF9
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
-
-
-
-
FMC_A0
-
-
EVENTOUT
PF1
-
-
-
-
FMC_A1
-
-
EVENTOUT
PF2
-
-
-
-
FMC_A2
-
-
EVENTOUT
PF3
-
-
-
-
FMC_A3
-
-
EVENTOUT
PF4
-
-
-
-
FMC_A4
-
-
EVENTOUT
PF5
-
-
-
-
FMC_A5
-
-
EVENTOUT
PF6
-
-
OCTOSPI1_IO3
-
-
SAI1_SD_B
-
EVENTOUT
PF7
-
-
OCTOSPI1_IO2
-
-
SAI1_MCLK_B
-
EVENTOUT
PF8
-
-
OCTOSPI1_IO0
-
-
SAI1_SCK_B
-
EVENTOUT
PF9
-
-
OCTOSPI1_IO1
-
-
SAI1_FS_B
TIM15_CH1
EVENTOUT
PF10
-
-
-
-
-
SAI1_D3
TIM15_CH2
EVENTOUT
PF11
-
-
-
-
-
-
-
EVENTOUT
PF12
-
-
-
-
FMC_A6
-
-
EVENTOUT
PF13
-
-
-
-
FMC_A7
-
-
EVENTOUT
PF14
-
TSC_G8_
IO1
-
-
FMC_A8
-
-
EVENTOUT
PF15
-
TSC_G8_
IO2
-
-
FMC_A9
-
-
EVENTOUT
137/342
Pinouts and pin description
PF0
STM32L562xx
Table 23. Alternate function AF8 to AF15(1) (continued)
AF8
Port
DS12736 Rev 4
Port
G
AF9
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
PG0
-
TSC_G8_
IO3
-
-
FMC_A10
-
-
EVENTOUT
PG1
-
TSC_G8_
IO4
-
-
FMC_A11
-
-
EVENTOUT
PG2
-
-
-
-
FMC_A12
SAI2_SCK_B
-
EVENTOUT
PG3
-
-
-
-
FMC_A13
SAI2_FS_B
-
EVENTOUT
PG4
-
-
-
-
FMC_A14
SAI2_MCLK_B
-
EVENTOUT
PG5
LPUART1_CTS
_NSS
-
-
-
FMC_A15
SAI2_SD_B
-
EVENTOUT
PG6
LPUART1_RTS_
DE
-
-
UCPD1_FRSTX1
-
-
-
EVENTOUT
PG7
LPUART1_TX
-
-
UCPD1_FRSTX2
FMC_INT
SAI1_MCLK_A
-
EVENTOUT
PG8
LPUART1_RX
-
-
-
-
-
-
EVENTOUT
PG9
-
-
-
-
FMC_NCE/FMC_
NE2
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PG10
-
-
-
-
FMC_NE3
SAI2_FS_A
TIM15_CH1
EVENTOUT
PG11
-
-
-
-
-
SAI2_MCLK_A
TIM15_CH2
EVENTOUT
PG12
-
-
-
-
FMC_NE4
SAI2_SD_A
-
EVENTOUT
PG13
-
-
-
-
FMC_A24
-
-
EVENTOUT
PG14
-
-
-
-
FMC_A25
-
-
EVENTOUT
PG15
-
-
-
-
-
-
-
EVENTOUT
Pinouts and pin description
138/342
Table 23. Alternate function AF8 to AF15(1) (continued)
STM32L562xx
AF8
Port
Port
H
AF9
UART4/5/LPUA FDCAN1/
RT1/SDMMC1
TSC
AF10
AF11
AF12
AF13
USB/OCTOSPI1
UCPD1
SDMMC1/COMP1
/2/TIM1/8/FMC
SAI1/2/TIM8
AF14
AF15
TIM2/8/15/16/17/
EVENTOUT
LPTIM2
PH0
-
-
-
-
-
-
-
EVENTOUT
PH1
-
-
-
-
-
-
-
EVENTOUT
PH3
-
-
-
-
-
-
-
EVENTOUT
STM32L562xx
Table 23. Alternate function AF8 to AF15(1) (continued)
1. Refer to Table 22 for AF0 to AF7.
DS12736 Rev 4
Pinouts and pin description
139/342
Electrical characteristics
STM32L562xx
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 25.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 26.
Figure 25. Pin loading conditions
Figure 26. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
140/342
DS12736 Rev 4
MS19211V1
STM32L562xx
Power supply scheme
Figure 27. STM32L552xx and STM32L562xx power supply overview
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
VDD
VCORE
n x VDD
Regulator
OUT
n x 100 nF
GPIOs
IN
+1 x 4.7 μF
Level shifter
VDDIO1
IO
logic
Level shifter
5.1.6
Electrical characteristics
IO
logic
Kernel logic
(CPU, Digital
& Memories)
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
10 nF
+1 μF
100 nF +1 μF
VREF+
VREF-
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VSSA
MSv62917V1
DS12736 Rev 4
141/342
309
Electrical characteristics
STM32L562xx
Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
2 x VDD12
1.05 – 1.32 V
VDD
VCORE
n x VDD
Regulator
n x 100 nF
GPIOs
IN
+1 x 4.7 μF
Level shifter
OUT
IO
logic
Level shifter
VDDIO1
IO
logic
Kernel logic
(CPU, Digital
& Memories)
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
10 nF
+1 μF
100 nF +1 μF
VREF+
VREF-
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VSSA
MSv62918V1
Note:
142/342
If the selected package has the external SMPS option but no external SMPS is used by the
application (the embedded LDO is used instead), the VDD12 pins are kept unconnected.
DS12736 Rev 4
STM32L562xx
Electrical characteristics
Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
VDD
VDDSMPS
SMPS
VLXSMPS
2 x V15SMPS
VSSSMPS
VDD
VCORE
n x VDD
Regulator
n x 100 nF
GPIOs
IN
+1 x 4.7 μF
Level shifter
OUT
IO
logic
Level shifter
VDDIO1
IO
logic
Kernel logic
(CPU, Digital
& Memories)
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
10 nF
+1 μF
100 nF +1 μF
VREF+
VREF-
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VSSA
MSv62919V1
1. Refer to Figure 3 for SMPS step down converter power supply scheme.
Note:
If the selected package has the SMPS step down converter option but the application does
not ever use the SMPS, it is recommended to set the SMPS power supply pins as follows:
VDDSMPS and VLXSMPS connected to VSS
V15SMPSconnected to VDD.
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DS12736 Rev 4
143/342
309
Electrical characteristics
5.1.7
STM32L562xx
Current consumption measurement
The IDD_ALL parameters given in Table 33 to Table 96 represent the total MCU consumption
including the current supplying VDD, VDDIO2, VDDA, VDDUSB, VBAT and VDDSMPS if the
device embeds the SMPS.
Figure 30. Current consumption measurement
IDD_VBAT
VBAT
IDD
VDD
VDDA
VDDUSB
VDDSMPS
VDDIO2
MSv62920V1
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 24: Voltage characteristics,
Table 25: Current characteristics and Table 26: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
Table 24. Voltage characteristics(1)
Symbol
Ratings
Min
Max
VDDX - VSS
External main supply voltage (including VDD,
VDDA, VDDIO2, VDDUSB, VBAT, VDDSMPS,
VREF+)
-0.3
4.0
VDD12 - VSS
External SMPS supply voltage
VIN
144/342
(2)
All ranges
0/1/2
-0.3
-0.3
1.4
Input voltage on FT_xxx pins except FT_c
pins
VSS-0.3
min (VDD, VDDA,
VDDIO2, VDDUSB,
VDDSMPS)
+ 4.0(3)(4)
Input voltage on FT_c pins
VSS-0.3
5.5
Input voltage on any other pins
VSS-0.3
4.0
DS12736 Rev 4
Unit
V
STM32L562xx
Electrical characteristics
Table 24. Voltage characteristics(1) (continued)
Symbol
Ratings
Min
Max
Unit
-
0.4
V
Variations between different VDDX power
pins of the same domain
-
50
Variations between all the different ground
pins(5)
-
VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA
|∆VDDx|
|VSSx-VSS|
mV
50
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 25: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 25. Current characteristics
Symbol
Ratings
Max
∑IVDD
Total current into sum of all VDD power lines (source)(1) (2)
160
∑IVSS
Total current out of sum of all VSS ground lines (sink)(1) (2)
160
IVDD(PIN)
Maximum current into each VDD power pin (source)(1)
100
IVSS(PIN)
(sink)(1)
100
IIO(PIN)
∑IIO(PIN)
IINJ(PIN)(4)
∑|IINJ(PIN)|
Maximum current out of each VSS ground pin
Output current sunk by any I/O and control pin except FT_f
20
Output current sunk by any FT_f pin
20
Output current sourced by any I/O and control pin
20
Total output current sunk by sum of all I/Os and control pins(3)
Unit
mA
100
(3)
Total output current sourced by sum of all I/Os and control pins
100
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(5)
Injected current on PA4, PA5
Total injected current (sum of all I/Os and control pins)
-5/0
(6)
+/-25
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the permitted range.
2. Valid also for VDD12 on SMPS package.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 24:
Voltage characteristics for the minimum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
DS12736 Rev 4
145/342
309
Electrical characteristics
STM32L562xx
Table 26. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
150
°C
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 27. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock
frequency
-
0
110
fPCLK1
Internal APB1 clock
frequency
-
0
110
fPCLK2
Internal APB2 clock
frequency
-
0
110
Standard operating voltage
-
VDD
VDDSMPS
VDD12
Supply voltage for the
internal SMPS step-down
converter
Standard operating voltage
VDDIO2
VDDA
Analog supply voltage
V
(1)
3.6
V
Up to 110 MHz
1.14
1.32
Up to 80 MHz
1.08
1.32
VDDSMPS = VDD
(1)
1.71
1.05
(2)
1.32
At least one I/O in
PG[15:2] used
1.08
3.6
PG[15:2] not used
0
3.6
ADC or COMP used
1.62
DAC or OPAMP used
1.8
VREFBUF used
2.4
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
146/342
MHz
3.6
Up to 26 MHz
PG[15:2] I/Os supply
voltage
1.71
Unit
DS12736 Rev 4
0
3.6
V
V
V
STM32L562xx
Electrical characteristics
Table 27. General operating conditions (continued)
Symbol
VBAT
Parameter
Conditions
Min
Max
Unit
-
1.55
3.6
V
3.0
3.6
Backup operating voltage
USB used
VDDUSB
USB supply voltage
V
USB not used
VIN
0
3.6
TT_xx I/O
-0.3
VDDIOx+0.3
FT_c I/O
-0.3
5
-0.3
MIN(MIN(VDD,
VDDA, VDDIO2,
VDDUSB)
+3.6 V,
5.5 V)(3)(4)
I/O input voltage
All I/O except FT_c and
TT_xx
LQFP48
UFQFPN48
LQFP64
PD
Power dissipation at
TA = 85 °C for suffix 6(5)
WLCSP81
LQFP100
UFBGA132
LQFP144
LQFP48
UFQFPN48
LQFP64
PD
Power dissipation at
TA = 125 °C for suffix 3(5)
WLCSP81
LQFP100
UFBGA132
LQFP144
DS12736 Rev 4
V
See Section 6.8:
Thermal
characteristics for
application appropriate
thermal resistance and
package. Power
dissipation is then
calculated according
ambient temperature
(TA) and maximum
junction temperature
(TJ) and selected
thermal resistance.
mW
See Section 6.8:
Thermal
characteristics for
application appropriate
thermal resistance and
package. Power
dissipation is then
calculated according
ambient temperature
(TA) and maximum
junction temperature
(TJ) and selected
thermal resistance.
mW
147/342
309
Electrical characteristics
STM32L562xx
Table 27. General operating conditions (continued)
Symbol
Parameter
Conditions
Ambient temperature for
the suffix 6 version
TA
Ambient temperature for
the suffix 3 version
TJ
Junction temperature range
Min
Max
Maximum power
dissipation
–40
85
Low-power dissipation(6)
–40
105
Maximum power
dissipation
–40
125
Low-power dissipation(6)
–40
130
Suffix 6 version
–40
105
Suffix 3 version
–40
130
Unit
°C
°C
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. For Flash erase and program operation, VDD12 min must be 1.08 V.
3. This formula has to be applied only on the power supplies related to the IO structure described by the pin
definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA, VDDIO2,
VDDUSB)+3.6 V and 5.5V.
4. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB) +0.3 V, the internal Pull-up and
Pull-Down resistors must be disabled.
5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal
characteristics).
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 7.7: Thermal characteristics).
5.3.2
SMPS step-down converter
The device embeds an SMPS step down converter which requires the external components
shown in below figure.
Figure 31. External components for SMPS step down converter
VDD
VDDSMPS
SMPS
Regulator
VCORE
VLXSMPS
L = 4.7 μH typ
C = 4.7 μF typ
2 x V15SMPS
VSSSMPS
MSv62972V2
The following table summarizes the SMPS behavior depending on the main regulator range,
VDD and consumption.
148/342
DS12736 Rev 4
STM32L562xx
Electrical characteristics
Table 28. SMPS modes summary
SMPS mode
Ranges
Max AHB clock VCORE
VDD ≤ 2.05 V
VDD > 2.05 V
Range 0
110 MHz
1.28 V
Automatic Bypass mode
V15SMPS = VDD
HP mode
Max current consumption = 120 mA
V15SMPS = 1.6 V
Range 1
80 MHz
1.2 V
Automatic Bypass mode
V15SMPS = VDD
HP mode
Max current consumption = 80 mA
V15SMPS = 1.5 V
Range 2
26 MHz
1.0 V
LP mode or HP mode
Software Bypass mode(1)
Max current consumption = 30 mA
V15SMPS = VDD
V15SMPS = 1.3 V
1. There is no automatic SMPS bypass in Range 2. The user application should use PVD0 to monitor VDD supply and request
the SMPS Bypass mode.
Table 29. SMPS characteristics(1)
Symbol
VDDSMPS
V15SMPS
SR
Parameter
Conditions
SMPS output slew
rate
Typ
1.71(2)
SMPS power supply
SMPS output voltage
Min
Max
Unit
3.6
V
Range 0
1.55
1.6
1.65
Range 1
1.45
1.5
1.55
Range 2
1.25
1.3
1.35
Fast startup disabled
SMPSFSTEN = 0
-
600
-
Fast startup enabled
SMPSFSTEN = 1
V
µs/V
-
120
-
1. Guaranteed by design.
2. When VDDSMPS is less than 2.05V, the SMPS bypass mode is forced by hardware in Range 0 and
Range 1. In Range 2, there is no automatic switch into SMPS bypass mode. It should be requested by
software. Refer to Table 28: SMPS modes summary.
DS12736 Rev 4
149/342
309
Electrical characteristics
5.3.3
STM32L562xx
Operating conditions at power-up / power-down
The parameters given in Table 30 are derived from tests performed under the ambient
temperature condition summarized in Table 27.
Table 30. Operating conditions at power-up / power-down(1)
Symbol
Parameter
VDD rise time rate
tVDD
VDDA rise time rate
VDDUSB rise time rate
5.3.4
0
∞
10
∞
0
∞
10
∞
0
∞
10
∞
0
∞
10
∞
-
VDDUSB fall time rate
VDDIO2 rise time rate
tVDDIO2
Max
-
VDDA fall time rate
tVDDUSB
Min
-
VDD fall time rate
tVDDA
1.
Conditions
-
VDDIO2 fall time rate
Unit
µs/V
At power-up, the VDD12 voltage should not be forced externally.
Embedded reset and power control block characteristics
The parameters given in Table 31 are derived from tests performed under the ambient
temperature conditions summarized in Table 27: General operating conditions.
Table 31. Embedded reset and power control block characteristics
Symbol
tRSTTEMPO(2)
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Parameter
Reset temporization after
BOR0 is detected
VBOR0(2)
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage
detector threshold 0
VPVD1
PVD threshold 1
Conditions(1)
Min
Typ
Max
Unit
-
250
400
μs
Rising edge
1.62
1.66
1.7
Falling edge
1.6
1.64
1.69
Rising edge
2.06
2.1
2.14
Falling edge
1.96
2
2.04
Rising edge
2.26
2.31
2.35
Falling edge
2.16
2.20
2.24
Rising edge
2.56
2.61
2.66
Falling edge
2.47
2.52
2.57
Rising edge
2.85
2.90
2.95
Falling edge
2.76
2.81
2.86
Rising edge
2.1
2.15
2.19
Falling edge
2
2.05
2.1
Rising edge
2.26
2.31
2.36
Falling edge
2.15
2.20
2.25
VDD rising
DS12736 Rev 4
V
V
V
V
V
V
V
STM32L562xx
Electrical characteristics
Table 31. Embedded reset and power control block characteristics (continued)
Conditions(1)
Min
Typ
Max
Rising edge
2.41
2.46
2.51
Falling edge
2.31
2.36
2.41
Rising edge
2.56
2.61
2.66
Falling edge
2.47
2.52
2.57
Rising edge
2.69
2.74
2.79
Falling edge
2.59
2.64
2.69
Rising edge
2.85
2.91
2.96
Falling edge
2.75
2.81
2.86
Rising edge
2.92
2.98
3.04
Falling edge
2.84
2.90
2.96
Hysteresis in
continuous
Hysteresis voltage of BORH0 mode
-
20
-
Hysteresis in
other mode
-
30
-
Symbol
Parameter
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst_BORH0
Unit
V
V
V
V
V
mV
Hysteresis voltage of BORH
(except BORH0) and PVD
-
-
100
-
mV
BOR(3) (except BOR0) and
IDD
(BOR_PVD)(2) PVD consumption from VDD
-
-
1.1
1.6
µA
Vhyst_BOR_PVD
VPVM3
VDDA peripheral voltage
monitoring
Rising edge
1.61
1.65
1.69
Falling edge
1.6
1.64
1.68
VPVM4
VDDA peripheral voltage
monitoring
Rising edge
1.78
1.82
1.86
Falling edge
1.77
1.81
1.85
V
V
Vhyst_PVM3
PVM3 hysteresis
-
-
10
-
mV
Vhyst_PVM4
PVM4 hysteresis
-
-
10
-
mV
IDD
PVM1 and PVM2
(PVM1/PVM2)
consumption from VDD
(2)
-
-
0.2
-
µA
IDD
PVM3 and PVM4
(PVM3/PVM4)
consumption from VDD
(2)
-
-
2
-
µA
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS12736 Rev 4
151/342
309
Electrical characteristics
5.3.5
STM32L562xx
Embedded voltage reference
The parameters given in Table 32 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 27: General operating
conditions.
Table 32. Embedded internal voltage reference
Symbol
VREFINT
Parameter
Internal reference
voltage
Conditions
–40 °C < TA < +130 °C
Min
Typ
1.182 1.212
Unit
1.232
V
ADC sampling time
when reading the
internal reference
voltage
-
4(2)
-
-
µs
Start time of reference
voltage buffer when
ADC is enable
-
-
8
12(2)
µs
VREFINT buffer
consumption from VDD
IDD(VREFINTBUF) when converted by
ADC
-
-
12.5
20(2)
µA
Internal reference
voltage spread over
VDD = 3 V
the temperature range
-
5
7.5(2)
mV
TCoeff
Average temperature
coefficient
–40°C < TA < +130°C
-
30
50(2)
ppm/°C
ACoeff
Long term stability
1000 hours, T = 25°C
-
300
1000(2)
ppm
Average voltage
coefficient
3.0 V < VDD < 3.6 V
-
250
1200(2)
ppm/V
24
25
26
49
50
51
74
75
76
tS_vrefint
(1)
tstart_vrefint
∆VREFINT
VDDCoeff
VREFINT_DIV1
1/4 reference voltage
VREFINT_DIV2
1/2 reference voltage
VREFINT_DIV3
3/4 reference voltage
-
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
152/342
Max
DS12736 Rev 4
%
VREFINT
STM32L562xx
Electrical characteristics
Figure 32. VREFINT versus temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40
-20
0
20
40
Mean
60
Min
80
100
120
°C
Max
MSv40169V2
DS12736 Rev 4
153/342
309
Electrical characteristics
5.3.6
STM32L562xx
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Section 5.1.7: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input mode
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0438 reference manual).
•
When the peripherals are enabled fPCLK = fHCLK
•
The voltage scaling range is adjusted to fHCLK frequency as follows:
–
Voltage Range 0 for 80 MHz < fHCLK