STM32MP151A/D
Arm® Cortex®-A7 800 MHz + Cortex®-M4 MPU,
TFT, 35 comm. interfaces, 25 timers, adv. analog
Datasheet - production data
Features
TFBGA
LFBGA
Includes ST state-of-the-art patented
technology
LFBGA448 (18 × 18mm)
LFBGA354 (16 × 16mm)
Pitch 0.8mm
Core
TFBGA361 (12 × 12 mm)
TFBGA257 (10 × 10 mm)
min Pitch 0.5mm
• Low-power modes: Sleep, Stop and Standby
• 32-bit Arm® Cortex®-A7
– L1 32-Kbyte I / 32-Kbyte D
– 256-Kbyte unified level 2 cache
– Arm® NEON™ and Arm® TrustZone®
• DDR memory retention in Standby mode
• Controls for PMIC companion chip
• 32-bit Arm® Cortex®-M4 with FPU/MPU
– Up to 209 MHz (Up to 703 CoreMark®)
Memories
Low-power consumption
• Total current consumption down to 2 µA
(Standby mode, no RTC, no LSE, no
BKPSRAM, no RETRAM)
• External DDR memory up to 1 Gbyte
– up to LPDDR2/LPDDR3-1066 16/32-bit
– up to DDR3/DDR3L-1066 16/32-bit
Clock management
• 708 Kbytes of internal SRAM: 256 Kbytes of
AXI SYSRAM + 384 Kbytes of AHB SRAM +
64 Kbytes of AHB SRAM in Backup domain
and 4 Kbytes of SRAM in Backup domain
• External oscillators: 8-48 MHz HSE oscillator,
32.768 kHz LSE oscillator
• Dual mode Quad-SPI memory interface
General-purpose input/outputs
• Flexible external memory controller with up to
16-bit data bus: parallel interface to connect
external ICs and SLC NAND memories with up
to 8-bit ECC
• Up to 176 I/O ports with interrupt capability
– Up to 8 secure I/Os
– Up to 6 Wakeup, 3 tampers, 1 active
tamper
Security/safety
• Cortex®-M4 resources isolation
Reset and power management
• 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
• POR, PDR, PVD and BOR
• On-chip LDOs (RETRAM, BKPSRAM, USB
1.8 V, 1.1 V)
• Internal temperature sensors
May 2021
This is information on a product in full production.
• 5 × PLLs with fractional mode
Interconnect matrix
• TrustZone® peripherals, active tamper
• Backup regulator (~0.9 V)
• Internal oscillators: 64 MHz HSI oscillator,
4 MHz CSI oscillator, 32 kHz LSI oscillator
• 2 bus matrices
– 64-bit Arm® AMBA® AXI interconnect, up to
266 MHz
– 32-bit Arm® AMBA® AHB interconnect, up
to 209 MHz
3 DMA controllers to unload the CPU
• 48 physical channels in total
• 1 × high-speed general-purpose master direct
memory access controller (MDMA)
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STM32MP151A/D
• 2 × dual-port DMAs with FIFO and request
router capabilities for optimal peripheral
management
Up to 35 communication peripherals
Up to 25 timers and 3 watchdogs
• 2 × 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
• 2 × 16-bit advanced motor control timers
• 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
• 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816
interface, LIN, IrDA, SPI slave)
• 6 × SPI (50 Mbit/s, including 3 with full duplex
I2S audio class accuracy via internal audio PLL
or external clock)
• 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
• SPDIF Rx with 4 inputs
• 10 × 16-bit general-purpose timers (including 2
basic timers without PWM)
• 5 × 16-bit low-power timers
• RTC with sub-second accuracy and hardware
calendar
• 4 Cortex®-A7 system timers (secure, nonsecure, virtual, hypervisor)
• 1 × SysTick M4 timer
• HDMI-CEC interface
• 3 × watchdogs (2 × independent and window)
• MDIO Slave interface
• 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
Hardware acceleration
• 2 × USB 2.0 high-speed Host
+ 1 × USB 2.0 full-speed OTG simultaneously
– or 1 × USB 2.0 high-speed Host
+ 1 × USB 2.0 high-speed OTG
simultaneously
• HASH (MD5, SHA-1, SHA224, SHA256),
HMAC
• 10/100M or Gigabit Ethernet GMAC
– IEEE 1588v2 hardware,
MII/RMII/GMII/RGMII
• 2 × true random number generator
(3 oscillators each)
• 2 × CRC calculation unit
Debug mode
• 8- to 14-bit camera interface up to 140 Mbyte/s
• Arm® CoreSight™ trace and debug: SWD and
JTAG interfaces
6 analog peripherals
• 8-Kbyte embedded trace buffer
• 2 × ADCs with 16-bit max. resolution (12 bits
up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up
to 3.6 Msps)
3072-bit fuses including 96-bit unique ID,
up to 1184-bit available for user
• 1 × temperature sensor
All packages are ECOPACK2 compliant
• 2 × 12-bit D/A converters (1 MHz)
• 1 × digital filters for sigma delta modulator
(DFSDM) with 8 channels/6 filters
• Internal or external ADC/DAC reference VREF+
Graphics
• LCD-TFT controller, up to 24-bit // RGB888
– up to WXGA (1366 × 768) @60 fps or up to
Full HD (1920 × 1080) @30 fps
– Pixel clock up to 90 MHz
– Two layers with programmable colour LUT
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Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Arm® Cortex®-A7 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2
Arm® Cortex®-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1
External SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . 24
3.5
TrustZone address space controller for DDR (TZC) . . . . . . . . . . . . . . . . 25
3.6
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.7.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.7.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9.1
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9.2
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10
Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11
Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . . . . . 31
3.11.1
IPCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.13
TrustZone protection controller (ETZPC) . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.14
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.15
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.16
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 35
3.17
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 35
3.18
Cyclic redundancy check calculation unit (CRC1, CRC2) . . . . . . . . . . . . 36
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3.19
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.20
Dual Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . 36
3.21
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.23
Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.24
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25
Digital-to-analog converters (DAC1, DAC2) . . . . . . . . . . . . . . . . . . . . . . . 38
3.26
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27
Digital filter for sigma delta modulators (DFSDM1) . . . . . . . . . . . . . . . . . 39
3.28
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.29
LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.30
True random number generator (RNG1, RNG2) . . . . . . . . . . . . . . . . . . . 41
3.31
Hash processors (HASH1, HASH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.32
Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . 42
3.33
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.33.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.33.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,
TIM14, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.33.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.33.4
Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . . 45
3.33.5
Independent watchdog (IWDG1, IWDG2) . . . . . . . . . . . . . . . . . . . . . . . 45
3.33.6
System window watchdog (WWDG1) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.33.7
SysTick timer (Cortex-M4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.33.8
Generic timers (Cortex-A7 CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34
System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.35
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.36
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.37
Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5, I2C6) . . . 49
3.38
Universal synchronous asynchronous receiver transmitter
(USART1, USART2, USART3, USART6 and UART4, UART5,
UART7, UART8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.39
Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5,
SPI6)– inter- integrated sound interfaces (I2S1, I2S2, I2S3) . . . . . . . . . . 50
3.40
Serial audio interfaces (SAI1, SAI2, SAI3, SAI4) . . . . . . . . . . . . . . . . . . . 51
3.41
SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Contents
3.42
Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.43
Secure digital input/output MultiMediaCard interface
(SDMMC1, SDMMC2, SDMMC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.44
Universal serial bus high-speed host (USBH) . . . . . . . . . . . . . . . . . . . . . 52
3.45
USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.46
Gigabit Ethernet MAC interface (ETH1) . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.47
High-definition multimedia interface (HDMI) – Consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.48
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4
Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 56
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 125
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . 127
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.5
Embedded regulators characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.7
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.8
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.9
External clock source security characteristics . . . . . . . . . . . . . . . . . . . 149
6.3.10
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.11
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.12
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 154
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6.3.13
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.14
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.15
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 159
6.3.16
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.3.17
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.3.18
NRST and NRST_CORE pin characteristics . . . . . . . . . . . . . . . . . . . . 169
6.3.19
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.20
QUADSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.3.21
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.3.22
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.3.23
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.24
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.25
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.26
DTS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.27
VBAT ADC monitoring characteristics and charging characteristics . . 204
6.3.28
Temperature and VBAT monitoring characteristics for
tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.3.29
VDDCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.3.30
Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.3.31
Compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.3.32
Digital filter for sigma-delta modulators (DFSDM) characteristics . . . . 205
6.3.33
Camera interface (DCMI) characteristics . . . . . . . . . . . . . . . . . . . . . . . 208
6.3.34
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 209
6.3.35
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.3.36
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.3.37
USART interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
6.3.38
USB High-Speed PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.3.39
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.1
TFBGA257 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.2
LFBGA354 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
7.3
TFBA361 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.4
LFBGA448 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.5.1
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Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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Contents
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
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List of tables
STM32MP151A/D
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
8/255
STM32MP151A/D features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
System versus domain power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
STM32MP151A/D pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 127
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Embedded reference voltage calibration value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
REG1V1 embedded regulator (USB_PHY) characteristics . . . . . . . . . . . . . . . . . . . . . . . 130
REG1V8 embedded regulator (USB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Current consumption (IDDCORE) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Current consumption (IDD) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Current consumption in LPLV-Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
High-speed external user clock characteristics
(digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
High-speed external user clock characteristics
(analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Low-speed external user clock characteristics
(analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Low-speed external user clock characteristics (digital bypass) . . . . . . . . . . . . . . . . . . . . 145
8-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
High-speed external user clock security system (HSE CSS) . . . . . . . . . . . . . . . . . . . . . . 149
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
PLL1_1600, PLL2_1600 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
PLL3_800, PLL4_800 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
USB_PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
OTP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DC specifications – DDR3 or DDR3L mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
DC specifications – LPDDR2 or LPDDR3 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DS12500 Rev 6
STM32MP151A/D
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
List of tables
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 163
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 164
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Output timing characteristics (HSLV ON, _h IO structure) . . . . . . . . . . . . . . . . . . . . . . . . 167
Output timing characteristics (HSLV ON, _vh IO structure) . . . . . . . . . . . . . . . . . . . . . . . 168
NRST and NRST_CORE pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 172
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 172
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 173
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 174
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 177
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 182
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 187
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Dynamics characteristics: Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Minimum sampling time versus RAIN with 47 pF PCB capacitor
up to 125 °C and VDDA = 1.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Minimum delay for interleaved conversion versus resolution . . . . . . . . . . . . . . . . . . . . . . 195
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DTS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
VBAT ADC monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Temperature and VBAT monitoring characteristics for temper detection . . . . . . . . . . . . . 204
VDDCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Compensation cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
DS12500 Rev 6
9/255
10
List of tables
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
10/255
STM32MP151A/D
I2C FM+ pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
MDIOS timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Dynamic characteristics: SD / MMC / e•MMC characteristics,
VDD = 2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Dynamic characteristics: SD / MMC / e•MMC characteristics
VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Dynamics characteristics: Ethernet MAC timings for MDIO/SMA. . . . . . . . . . . . . . . . . . . 225
Dynamics characteristics: Ethernet MAC timings for RMII . . . . . . . . . . . . . . . . . . . . . . . . 225
Dynamics characteristics: Ethernet MAC timings for MII . . . . . . . . . . . . . . . . . . . . . . . . . 226
Dynamics characteristics: Ethernet MAC signals for GMII . . . . . . . . . . . . . . . . . . . . . . . 227
Dynamics characteristics: Ethernet MAC signals for RGMII . . . . . . . . . . . . . . . . . . . . . . 228
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
USB High-Speed PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
TFBGA257 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
TFBGA257 - Recommended PCB design rules (0.5/0.65 mm pitch, BGA) . . . . . . . . . . . 236
LFBGA354 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
LFBGA354 - Recommended PCB design rules (0.8 mm pitch, BGA) . . . . . . . . . . . . . . . 240
TFBGA361 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
TFBGA361 - Recommended PCB design rules (0.5/0.65 mm pitch BGA) . . . . . . . . . . . . 243
LFBGA448 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
LFBGA448 - Recommended PCB design rules (0.8 mm pitch, BGA) . . . . . . . . . . . . . . . 246
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
STM32MP151A/D ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
DS12500 Rev 6
STM32MP151A/D
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM32MP151A/D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32MP151A/D bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32MP151A/DADxx TFBGA257 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STM32MP151A/DABxx LFBGA354 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
STM32MP151A/DACxx TFBGA361 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STM32MP151A/DAAxx LFBGA448 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
VDDCORE rise time from reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
VDDCORE rise time from LPLV-Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
High-speed external clock source AC timing diagram (digital bypass) . . . . . . . . . . . . . . . 143
High-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . 144
Low-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . 145
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Typical application with a 24 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
VIL/VIH for FT I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Recommended NRST and NRST_CORE pin protection . . . . . . . . . . . . . . . . . . . . . . . . . 170
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 171
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 173
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 174
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 176
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 182
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 186
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 186
QUADSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
QUADSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
DS12500 Rev 6
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12
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
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STM32MP151A/D
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
MDIOS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Ethernet MDIO/SMA timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Ethernet GMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Ethernet RGMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
USART timing diagram in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
USART timing diagram in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
SWD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
TFBGA257 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
TFBGA257 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
TFBGA257 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
LFBGA354 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
LFBGA354 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
LFBGA354 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
TFBGA361 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
TFBGA361 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
TFBGA361 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
LFBGA448 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
LFBGA448 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
LFBGA448 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
DS12500 Rev 6
STM32MP151A/D
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32MP151A/D microprocessors.
This document should be read in conjunction with the STM32MP151 reference manual
(RM0441), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-A7 and Cortex®-M4 cores, refer to the Cortex®-A7
and Cortex®-M4 Technical Reference Manuals.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32MP151A/D errata sheet (ES0438), available on the STMicroelectronics
website www.st.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Description
2
STM32MP151A/D
Description
The STM32MP151A/D devices are based on the high-performance Arm® Cortex®-A7 32-bit
RISC core operating at up to 800 MHz. The Cortex-A7 processor includes a 32-Kbyte L1
instruction cache, a 32-Kbyte L1 data cache and a 256-Kbyte level2 cache. The Cortex-A7
processor is a very energy-efficient application processor designed to provide rich
performance in high-end wearables, and other low-power embedded and consumer
applications. It provides up to 20% more single thread performance than the Cortex-A5 and
provides similar performance than the Cortex-A9.
The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and CortexA17 processors, including virtualization support in hardware, NEON™, and 128-bit AMBA®4
AXI bus interface.
The STM32MP151A/D devices also embed a Cortex® -M4 32-bit RISC core operating at up
to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision
which supports Arm® single-precision data-processing instructions and data types. The
Cortex® -M4 supports a full set of DSP instructions and a memory protection unit (MPU)
which enhances application security.
The STM32MP151A/D devices provide an external SDRAM interface supporting external
memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L
up to 533 MHz.
The STM32MP151A/D devices incorporate high-speed embedded memories with
708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes
each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in
backup domain), as well as an extensive range of enhanced I/Os and peripherals connected
to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI
interconnect supporting internal and external memories access.
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STM32MP151A/D
Description
All the devices offer two ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit
timers, two PWM timers for motor control, five low-power timers, a true random number
generator (RNG). The devices support six digital filters for external sigma delta modulators
(DFSDM). They also feature standard and advanced communication interfaces.
•
Standard peripherals
–
•
Six I2Cs
–
Four USARTs and four UARTs
–
Six SPIs, three I2Ss full-duplex master/slave. To achieve audio class accuracy, the
I2S peripherals can be clocked via a dedicated internal audio PLL or via an
external clock to allow synchronization.
–
Four SAI serial audio interfaces
–
One SPDIF Rx interface
–
Management data input/output slave (MDIOS)
–
Three SDMMC interfaces
–
An USB high-speed Host with two ports two high-speed PHYs and a USB OTG
high-speed with full-speed PHY or high-speed PHY shared with second port of
USB Host.
–
A Gigabit Ethernet interface
–
HDMI-CEC
Advanced peripherals including
–
A flexible memory control (FMC) interface
–
A Quad-SPI Flash memory interface
–
A camera interface for CMOS sensors
–
An LCD-TFT display controller
Refer to Table 1: STM32MP151A/D features and peripheral counts for the list of peripherals
available on each part number.
A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32MP151A/D devices are proposed in 4 packages ranging from 257 to 448 balls
with pitch 0.5 mm to 0.8 mm. The set of included peripherals changes with the device
chosen.
These features make the STM32MP151A/D suitable for a wide range of consumer,
industrial, white goods and medical applications.
shows the general block diagram of the device family.
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55
Description
STM32MP151A/D
STM32MP151AABxx
STM32MP151DABxx
STM32MP151AACxx
STM32MP151DACxx
STM32MP151AAAxx
STM32MP151DAAxx
TFBGA257
LFBGA354
TFBGA361
LFBGA448
Body size (mm)
10x10
16x16
12x12
18x18
Pitch (mm)
0.5(1)
0.8
0.5(1)
0.8
Ball size (mm)
0.30
0.40
0.30
0.40
Thickness (mm)