STM32U585xx
Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,
240 DMIPS, up to 2 MB Flash memory, 786 KB SRAM, crypto
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
Ultra-low-power with FlexPowerControl
• 1.71 V to 3.6 V power supply
LQFP48 (7 x 7 mm) UFQFPN48
LQFP64 (10 x 10 mm) (7 x 7 mm)
LQFP100 (14 x 14 mm)
LQFP144 (20 x 20 mm)
WLCSP90
(4.2 x 3.95 mm)
UFBGA132
(7 x 7 mm)
UFBGA169
(7 x 7 mm)
• –40 °C to +85/125 °C temperature range
• 651 CoreMark® (4.07 CoreMark®/MHz)
• Low-power background autonomous mode
(LPBAM): autonomous peripherals with DMA,
functional down to Stop 2 mode
• 535 ULPMark™-CP
• VBAT mode: supply for RTC, 32 x 32-bit backup
registers and 2-Kbyte backup SRAM
• 149 ULPMark™-PP
• 58.2 ULPMark™-CM
• 133000 SecureMark™-TLS
• 160 nA Shutdown mode (24 wakeup pins)
Memories
• 210 nA Standby mode (24 wakeup pins)
• 2-Mbyte Flash memory with ECC, 2 banks
read-while-write, including 512 Kbytes with
100 kcycles
• 440 nA Standby mode with RTC
• 1.9 μA Stop 3 mode with 16-Kbyte SRAM
• 786-Kbyte SRAM with ECC OFF or 722-Kbyte
SRAM including up to 322-Kbyte SRAM with
ECC ON
• 4.3 µA Stop 3 mode with full SRAM
• 4.0 µA Stop 2 mode with 16-Kbyte SRAM
• 8.95 µA Stop 2 mode with full SRAM
• External memory interface supporting SRAM,
PSRAM, NOR, NAND and FRAM memories
• 19.5 μA/MHz Run mode @ 3.3 V
• 2 Octo-SPI memory interfaces
Core
• Arm® 32-bit Cortex®-M33 CPU with
TrustZone®, MPU, DSP, and FPU
Security and cryptography
ART Accelerator
• Arm® TrustZone® and securable I/Os,
memories and peripherals
• PSA level 3 and SESIP level 3 certified
• 8-Kbyte instruction cache allowing 0-wait-state
execution from Flash and external memories:
up to 160 MHz, 240 DMIPS
• Flexible life cycle scheme with RDP and
password protected debug
• 4-Kbyte data cache for external memories
• Root of trust thanks to unique boot entry and
secure hide protection area (HDP)
Power management
• Secure firmware installation (SFI) thanks to
embedded root secure services (RSS)
• Embedded regulator (LDO) and SMPS
step-down converter supporting switch
on-the-fly and voltage scaling
Benchmarks
• Secure data storage with hardware unique key
(HUK)
• Secure firmware upgrade support with TF-M
• 1.5 DMIPS/MHz (Drystone 2.1)
June 2022
This is information on a product in full production.
DS13086 Rev 6
1/334
www.st.com
STM32U585xx
• 2 AES coprocessors including one with
DPA resistance
• 3 SPIs (5x SPIs with the dual OCTOSPI)
• Public key accelerator, DPA resistant
• 2 SDMMC interfaces
• 1 CAN FD controller
• On-the-fly decryption of Octo-SPI external
memories
• HASH hardware accelerator
• 1 multi-function digital filter (6 filters)+ 1 audio
digital filter with sound-activity detection
• Parallel synchronous slave interface
• True random number generator, NIST
SP800-90B compliant
16- and 4-channel DMA controllers,
functional in Stop mode
• 96-bit unique ID
• 512-byte OTP (one-time programmable)
Graphic features
• Active tampers
• Chrom-ART Accelerator (DMA2D) for
enhanced graphic content creation
Clock management
• 1 digital camera interface
• 4 to 50 MHz crystal oscillator
Mathematical co-processor
• 32 kHz crystal oscillator for RTC (LSE)
• Internal 16 MHz factory-trimmed RC (±1%)
• Internal low-power 32 kHz RC (±5%)
• 2 internal multispeed 100 kHz to 48 MHz
oscillators, including one auto-trimmed by LSE
(better than ±0.25% accuracy)
• Internal 48 MHz with clock recovery
• 3 PLLs for system clock, USB, audio, ADC
General-purpose input/outputs
• Up to 136 fast I/Os with interrupt capability
most 5V-tolerant and up to 14 I/Os with
independent supply down to 1.08 V
Up to 17 timers and 2 watchdogs
• 2 16-bit advanced motor-control, 4 32-bit,
5 16-bit, 4 low-power 16-bit (available in Stop
mode), 2 SysTick timers and 2 watchdogs
• CORDIC for trigonometric functions
acceleration
• Filter mathematical accelerator (FMAC)
Up to 22 capacitive sensing channels
• Support touch key, linear and rotary touch
sensors
Rich analog peripherals (independent
supply)
• 14-bit ADC 2.5-Msps with hardware
oversampling
• 12-bit ADC 2.5-Msps, with hardware
oversampling, autonomous in Stop 2 mode
• 2 12-bit DAC, low-power sample and hold
• 2 operational amplifiers with built-in PGA
• 2 ultra-low-power comparators
• RTC with hardware calendar and calibration
CRC calculation unit
Up to 22 communication peripherals
Debug
• 1 USB Type-C®/USB power delivery controller
• 1 USB OTG 2.0 full-speed controller
• 2 SAIs (serial-audio interface)
• 4 I2C FM+(1 Mbit/s), SMBus/PMBus®
• Development support: serial-wire debug
(SWD), JTAG, Embedded Trace Macrocell™
(ETM)
ECOPACK2 compliant packages
• 6 USARTs (ISO 7816, LIN, IrDA, modem)
Table 1. Device summary
Reference
STM32U585xx
2/334
Part numbers
STM32U585AI, STM32U585CI, STM32U585OI, STM32U585QI, STM32U585RI,
STM32U585VI, STM32U585ZI
DS13086 Rev 6
STM32U585xx
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 22
3.2
ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1
Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.2
Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5
3.6
3.4.1
Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.2
Additional Flash memory protections when TrustZone activated . . . . . 27
3.4.3
FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.1
SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.2
SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6.1
TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6.2
Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8
Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.9.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.3
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.9.4
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.9.5
PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.10
Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.11
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.11.1
RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.13
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 50
DS13086 Rev 6
3/334
8
Contents
STM32U585xx
3.13.1
3.14
Low-power general-purpose inputs/outputs (LPGPIO) . . . . . . . . . . . . . . 50
3.14.1
LPGPIO TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.15
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.16
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . 51
3.17
General purpose direct memory access controller (GPDMA) . . . . . . . . . 51
3.18
Low-power direct memory access controller (LPDMA) . . . . . . . . . . . . . . 53
3.19
Chrom-ART Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . . . . . 55
3.20
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.20.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 56
3.20.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 56
3.21
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 57
3.22
CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.23
Filter math accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.24
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.25
3.24.1
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.24.2
FSMC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.25.1
OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.26
OCTOSPI I/O manager (OCTOSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.27
Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.28
Analog-to-digital converter (ADC1 and ADC4) . . . . . . . . . . . . . . . . . . . . . 60
3.28.1
Analog-to-digital converter 1 (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.28.2
Analog-to-digital converter 4 (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.28.3
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.28.4
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.28.5
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.29
Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.30
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.31
Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.32
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.33
Multi-function digital filter (MDF) and audio digital filter (ADF) . . . . . . . . . 67
3.34
4/334
GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.33.1
Multi-function digital filter (MDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.33.2
Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DS13086 Rev 6
STM32U585xx
Contents
3.35
Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 71
3.36
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.37
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.38
Secure advanced encryption standard hardware accelerator (SAES)
and encryption standard hardware accelerator (AES) . . . . . . . . . . . . . . . 73
3.39
HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.40
On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.41
Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.42
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.43
3.42.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,
TIM16,TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.3
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.42.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4) . . . . . . . . . . . . 79
3.42.5
Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.42.6
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.42.7
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.42.8
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 80
3.43.1
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.43.2
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.44
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.45
Universal synchronous/asynchronous receiver transmitter (USART/UART)
and low-power universal asynchronous receiver transmitter (LPUART) . 84
3.45.1
Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.45.2
Low-power universal asynchronous receiver transmitter (LPUART) . . . 86
3.46
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.47
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.48
Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 89
3.49
Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.50
USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.51
USB Type-C /USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . . 93
3.52
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.52.1
Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.52.2
Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DS13086 Rev 6
5/334
8
Contents
4
5
STM32U585xx
Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . . 94
4.1
Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1
6/334
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.2
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . 155
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . 155
5.3.4
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.3.7
External clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.8
Internal clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.10
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
5.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
5.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.3.16
Extended interrupt and event controller input (EXTI) characteristics . . 234
5.3.17
Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.3.18
14-bit analog-to-digital converter (ADC1) characteristics . . . . . . . . . . 235
5.3.19
12-bit analog-to-digital converter (ADC4) characteristics . . . . . . . . . . 241
5.3.20
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
DS13086 Rev 6
STM32U585xx
6
7
Contents
5.3.21
VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
5.3.22
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
5.3.23
Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 247
5.3.24
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 251
5.3.25
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
5.3.26
Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 255
5.3.27
Temperature and Backup domain supply thresholds monitoring . . . . . 258
5.3.28
ADF/MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.3.29
DCMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.3.30
PSSI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.3.31
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.3.32
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.3.33
OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
5.3.34
SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics . . . . 286
5.3.35
Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
5.3.36
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
5.3.37
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
5.3.38
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
5.3.39
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
5.3.40
OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
5.3.41
UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
5.3.42
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.1
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.2
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
6.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
6.4
WLSCP90 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
6.5
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
6.6
UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
6.7
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6.8
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
6.9
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
DS13086 Rev 6
7/334
8
Contents
STM32U585xx
8
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
8/334
DS13086 Rev 6
STM32U585xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32U585xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Access status versus protection level and execution modes when TZEN = 0 . . . . . . . . . . 25
Access status versus protection level and execution modes when TZEN = 1 . . . . . . . . . . 26
Example of memory map security attribution versus SAU configuration regions . . . . . . . . 29
Boot modes when TrustZone is disabled (TZEN = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Boot modes when TrustZone is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32U585xx mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
GPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GPDMA1 autonomous mode and wakeup in low-power modes. . . . . . . . . . . . . . . . . . . . . 53
LPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LPDMA1 autonomous mode and wakeup in low-power modes . . . . . . . . . . . . . . . . . . . . . 55
ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MDF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
STM32U585xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 155
Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Current consumption in Run mode on LDO, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 160
Current consumption in Run mode on SMPS, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 161
Current consumption in Run mode on SMPS, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON, VDD = 3.0 V . . . . . . . . 162
Typical current consumption in Run mode on LDO, with different codes
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . 163
Typical current consumption in Run mode on LDO, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 163
Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . 165
DS13086 Rev 6
9/334
12
List of tables
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
10/334
STM32U585xx
Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 165
Current consumption in Sleep mode on LDO, Flash memory in power down . . . . . . . . . 167
Current consumption in Sleep mode on SMPS, Flash memory in power down . . . . . . . . 168
Current consumption in Sleep mode on SMPS,
Flash memory in power down, VDD = 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS . . . . . . . 170
Static power consumption of Flash banks, when supplied by LDO/SMPS . . . . . . . . . . . . 171
Current consumption in Stop 0 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Current consumption in Stop 0 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Current consumption in Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Current consumption during wakeup from Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . . 175
Current consumption in Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Current consumption during wakeup from Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . 177
Current consumption in Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SRAM static power consumption in Stop 2 when supplied by LDO . . . . . . . . . . . . . . . . . 179
Current consumption during wakeup from Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . . 180
Current consumption in Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SRAM static power consumption in Stop 2 when supplied by SMPS. . . . . . . . . . . . . . . . 182
Current consumption during wakeup from Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . 183
Current consumption in Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
SRAM static power consumption in Stop 3 when supplied by LDO . . . . . . . . . . . . . . . . . 185
Current consumption during wakeup from Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . . 186
Current consumption in Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
SRAM static power consumption in Stop 3 when supplied by SMPS. . . . . . . . . . . . . . . . 188
Current consumption during wakeup from Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . 189
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Current consumption during wakeup from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 193
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Current consumption during wakeup from Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . 194
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Typical dynamic current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Low-power mode wakeup timings on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Low-power mode wakeup timings on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SHSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz. . . . . . . . . . . . . . . . . . . . . . . 222
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
DS13086 Rev 6
STM32U585xx
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
List of tables
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Output voltage characteristics for FT_t I/Os in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 228
Output AC characteristics, HSLV OFF (all I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . 228
Output AC characteristics, HSLV ON (all I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . 231
Output AC characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Output AC characteristics for FT_t I/Os in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
14-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Maximum RAIN for 14-bit ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14-bit ADC1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
12-bit ADC4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Maximum RAIN for 12-bit ADC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12-bit ADC4 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
WWDG min/max timeout value at 160 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 268
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 268
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 269
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 270
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 271
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 273
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 277
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 280
OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
OCTOSPI characteristics in DTR mode (with DQS)/HyperBus . . . . . . . . . . . . . . . . . . . . 283
SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
DS13086 Rev 6
11/334
12
List of tables
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
12/334
STM32U585xx
e•MMC characteristics (VDD = 1.71 V to 1.9 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
WLCSP90 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
WLCSP90 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
UFBGA132 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 319
LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 326
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
DS13086 Rev 6
STM32U585xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
STM32U585xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32U585xQ power supply overview (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32U585xx power supply overview (without SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power-up /down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LQFP48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
UFQFPN48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP64_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
WLCSP90-SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP100_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UFBGA132 _SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LQFP144 _SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UFBGA169_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
STM32U585xx power supply scheme (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 149
STM32U585xQ power supply scheme (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
AC timing diagram for high-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . 208
AC timing diagram for low-speed external square clock source . . . . . . . . . . . . . . . . . . . . 208
AC timing diagram for low-speed external sinusoidal clock source . . . . . . . . . . . . . . . . . 209
Typical application with a 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
I/O input characteristics (all I/Os except BOOT0 and FT_c). . . . . . . . . . . . . . . . . . . . . . . 226
Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Typical connection diagram when using the ADC
with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
VREFBUF_OUT versus temperature (VRS = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
VREFBUF_OUT versus temperature (VRS = 001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
VREFBUF_OUT versus temperature (VRS = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
VREFBUF_OUT versus temperature (VRS = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ . . . . . . . . . . . . . . . . . . . . 258
OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ . . . . . . . . . . . . . . . . . . 258
ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
DS13086 Rev 6
13/334
15
List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
14/334
STM32U585xx
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 267
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 269
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 270
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 272
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 276
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 279
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 280
OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
USART timing diagram in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
USART timing diagram in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
SAI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SAI slave timing digram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
LQFP48 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
LQFP48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
WLCSP90 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
WLCSP90 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
WLCSP90 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
UFBGA132 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
UFBGA132 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
UFBGA132 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
DS13086 Rev 6
STM32U585xx
Figure 100.
Figure 101.
Figure 102.
Figure 103.
Figure 104.
List of figures
LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
DS13086 Rev 6
15/334
15
Introduction
1
STM32U585xx
Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32U585xx microcontrollers.
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33
Technical Reference Manual, available from the www.arm.com website.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32U575xx and STM32U585xx errata sheet (ES0499)
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
16/334
DS13086 Rev 6
STM32U585xx
2
Description
Description
The STM32U585xx devices belong to an ultra-low-power microcontrollers family
(STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core.
They operate at a frequency of up to 160 MHz.
The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all
the Arm® single-precision data-processing instructions and all the data types.
The Cortex®-M33 core also implements a full set of DSP (digital signal processing)
instructions and a MPU (memory protection unit) that enhances the application security.
The devices embed high-speed memories (2 Mbytes of Flash memory and 786 Kbytes of
SRAM), a FSMC (flexible external memory controller) for static memories (for devices with
packages of 90 pins and more), two Octo-SPI Flash memory interfaces (at least one
Quad-SPI available on all packages) and an extensive range of enhanced I/Os and
peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus
matrix.
The devices offer security foundation compliant with the TBSA (trusted-based security
architecture) requirements from Arm®. It embeds the necessary security features to
implement a secure boot, secure data storage and secure firmware update. Besides these
capabilities, the devices incorporate a secure firmware installation feature, that allows the
customer to secure the provisioning of the code during its production. A flexible lifecycle is
managed thanks to multiple levels of readout protection and debug unlock with password.
Firmware hardware isolation is supported thanks to securable peripherals, memories and
I/Os, and privilege configuration of peripherals and memories.
The devices feature several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection, secure and hide protection areas.
The devices embed several peripherals reinforcing security: a fast AES coprocessor,
a secure AES coprocessor with DPA resistance and hardware unique key that can be
shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance,
an on-the-fly decryption engine for Octo-SPI external memories, a HASH hardware
accelerator, and a true random number generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring generating secret
data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications.
The devices offer one fast 14-bit ADC (2.5 Msps), one 12-bit ADC (2.5 Msps), two
comparators, two operational amplifiers, two DAC channels, an internal voltage reference
buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers
dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and
four 16-bit low-power timers.
The devices support a MDF (multi-function digital filter) with six filters dedicated to the
connection of external sigma-delta modulators. Another low-power digital filter dedicated to
audio signals is embedded (ADF), with one filter supporting sound-activity detection. The
devices embed also a Chrom-ART Accelerator dedicated to graphic applications, and
mathematical accelerators (a trigonometric functions accelerator plus a filter mathematical
accelerator). In addition, up to 22 capacitive sensing channels are available.
DS13086 Rev 6
17/334
21
Description
STM32U585xx
The devices also feature standard and advanced communication interfaces such as:
four I2Cs, three SPIs, three USARTs, two UARTs, one low-power UART, two SAIs, one
digital camera interface (DCMI), two SDMMCs, one FDCAN, one USB OTG full-speed,
one USB Type-C /USB Power Delivery controller, and one generic synchronous 8-/16-bit
PSSI (parallel data input/output slave interface).
The devices operate in the –40 to +85 °C (+105 °C junction) and –40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power applications.
Many peripherals (including communication, analog, timers and audio peripherals) can be
functional and autonomous down to Stop mode with direct memory access, thanks to
LPBAM support (low-power background autonomous mode).
Some independent power supplies are supported like an analog independent supply input
for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and
up to 14 I/Os, that can be supplied independently down to 1.08 V. A VBAT input is available
for connecting a backup battery in order to preserve the RTC functionality and to backup 32
32-bit registers and 2-Kbyte SRAM.
The devices offer eight packages from 48 to 169 pins.
Flash memory (Mbytes)
SRAM
18/334
2048 backup SRAM + 128 backup registers
Yes(1)
No
Yes(2)
2(3)
2
Advanced control
2 (16 bits)
General purpose
4 (32 bits) and 3 (16 bits)
Basic
2 (16 bits)
Low power
4 (16 bits)
SysTick timer
2
Watchdog timers
(independent,
window)
2
DS13086 Rev 6
STM32U585AI
STM32U585ZI
STM32U585QI
784 (192+64+512+16)
Backup (bytes)
OCTOSPI
Timers
2
System (Kbytes)
External memory controller for
static memories (FSMC)
STM32U585VI
STM32U585OI
STM32U585RI
Peripherals
STM32U585CI
Table 2. STM32U585xx features and peripheral counts
STM32U585xx
Description
STM32U585ZI
STM32U585AI
4/3
-/8
8/7
8/8
8/7
8/8
2/2
3/2
-/7
7/6
7/7
7/6
7/7
STM32U585VI
3/3
SPI
3
I2C
4
USART
3
UART
1
2
LPUART
1
Communication SAI
interfaces
FDCAN
1
2
1
OTG FS
Yes
UCPD
Yes
SDMMC
Camera interface
PSSI
MDF (multi-function digital filter)
2(4)
0
No
Yes/No(5)
Yes
No
Yes/No(5)
Yes
Yes
(2 filters)
Yes
(6 filters)
ADF (audio digital filter)
Yes
CORDIC co-processor
Yes
FMAC (filter mathematical
accelerator)
Yes
RTC (real-time clock)
Yes
Tamper pins (without SMPS /
with SMPS)
Active tampers (without SMPS /
with SMPS)(6)
True random number generator
Yes
SAES, AES
Yes
PKA (public key accelerator)
Yes
HASH (SHA-256)
Yes
On-the-fly decryption for OCTOSPI
Yes
GPIOs (without SMPS /
with SMPS)
Wakeup pins (without SMPS /
with SMPS)
Number of I/Os down to 1.08 V
(without SMPS / with SMPS)
STM32U585QI
STM32U585OI
STM32U585RI
Peripherals
STM32U585CI
Table 2. STM32U585xx features and peripheral counts (continued)
37 / 33
51 / 47
69
82 / 79
17 / 15
18 / 17
23
23 / 22
24 / 24
24 / 23
24 / 24
0/0
0/0
6
0/0
13 / 10
14 / 13
14 / 11
DS13086 Rev 6
110 / 106 114 / 111 136 / 133
19/334
21
Description
STM32U585xx
11
ADC
DAC
STM32U585AI
10 / 9
STM32U585ZI
STM32U585OI
5/4
STM32U585QI
STM32U585RI
Capacitive sensing
Number of channels (without SMPS
/ with SMPS)
STM32U585VI
Peripherals
STM32U585CI
Table 2. STM32U585xx features and peripheral counts (continued)
19 / 18
22 / 22
22 / 21
22 / 22
24 / 24
24 / 22
24 / 24
12-bit ADC
1
14-bit ADC
1
Nbr of channels
(without SMPS /
with SMPS)
11 / 10
17 / 15
16
20 / 18
Number of 12-bit
D-to-A converters
Internal voltage reference buffer
2
No
Yes
Analog comparator
2
Operational amplifiers
2
Maximum CPU frequency
160 MHz
Operating voltage
Operating temperature
Package
1.71 to 3.6 V
Ambient operating temperature: –40 to +85 °C / –40 to +125 °C
Junction temperature: –40 to +105 °C / –40 to +130 °C
LQFP48,
UFQFPN
48
LQFP64
WLCSP
90
LQFP
100
UFBGA
132
LQFP144
UFBGA
169
1. For the WLCSP90 package, FSMC can only support 8-bit LCD interface.
2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 chip select.
3. Two OCTOSPIs are available only in Muxed mode.
4. When both are used simultaneously, one supports only SDIO interface.
5. Available on packages without SMPS, not available on packages with SMPS.
6. Active tampers in output sharing mode (one output shared by all inputs).
20/334
DS13086 Rev 6
STM32U585xx
Description
Figure 1. STM32U585xx block diagram
Arm Cortex-M33
160 MHz
C-BUS
TrustZone FPU
FIFO
S-BUS
SDMMC1
FIFO
D[7:0], D[3:1]dir
CMD, CMDdir,CK, CKin
D0dir, D2dir
SDMMC2
IO[7:0], CLK, NCLK, NCS.
DQS as AF
OTFDEC1 and Octo-SPI1 memory interface
IO[7:0], CLK, NCLK, NCS.
DQS as AF
OTFDEC2 and Octo-SPI2 memory interface
Flash memory
(up to 2 Mbytes)
RNG
AES
HASH
SAES
SRAM1 (192 Kbytes)
@VDDUSB
PKA
SRAM2 (64 Kbytes)
SRAM3 (512 Kbytes)
PHY
NVIC
FIFO
ETM
CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE, INT as AF
Flexible static memory controller (FSMC):
SRAM, PSRAM, NOR Flash,FRAM, NAND Flash
AHB bus-matrix
MPU
ICACHE
(8 Kbytes)
TRACECLK,
TRACED[3:0]
JTAG/ SW
DCACHE1
(4 Kbytes)
NJTRST, JTDI, JTCK/SWCLK,
JTMS/SWDIO, JTDO
USB FS
DCMI/PSSI
DP
DM
D[15:0], CK, CMD as AF
AHB2 160 MHz
DMA2D
@VDD
VDD
SHSI
GPDMA1
HSI48
8 groups of 4 channels max
as AF
SDIN[5:0], CKIN[5:0], CCK0,
CCK1 as AF
GPIO port C
GPIO port D
GPIO port E
PF[15:0]
GPIO port F
PG[15:2]
PG[1:0]
GPIO port G
PH[15:0]
GPIO port H
PI[7:0]
GPIO port I
136 AF
EXT IT. WKP
@VDD
GTZC1
AHB/APB2
16b
CRS
AHB/APB1
16b
TIM15
16b
1 channel,
1 compl. channel, BKIN as AF
TIM16
16b
1 channel,
1 compl. channel, BKIN as AF
TIM17
16b
MOSI, MISO, SCK, NSS as
AF
MCLK_A, SD_A, FS_A,
SCK_A, MCLK_B, SD_B,
FS_B, SCK_B as AF
smcard
USART1
irDA
WWDG
AUDIOCLK as AF
RTC_OUT[8:1], RTC_IN[8:1]
VREF+
INP, INN, OUT
INP, INN, OUT
INP, INN, OUT
INP, INN, OUT
@VSW
XTAL 32k
TIM6 16b
32b
4 channels, ETR as AF
TIM3
32b
4 channels, ETR as AF
TIM4
32b
4 channels, ETR as AF
TIM5
32b
4 channels, ETR as AF
smcard
USART2 irDA
RX, TX, CK, CTS, RTS as AF
smcard
USART3 irDA
RX, TX, CK, CTS, RTS as AF
UART4
RX, TX, CTS, RTS as AF
UART5
RX, TX, CTS, RTS as AF
I2C1/SMBUS
SCL, SDA, SMBA as AF
I2C2/SMBUS
SCL, SDA, SMBA as AF
I2C4/SMBUS
SCL, SDA, SMBA as AF
@VDDA
OpAmp2
IN1, IN2, CH1, CH2,
ETR as AF
LPTIM1
IN1, IN2, CH1, CH2,
ETR as AF
LPTIM3
IN1, OUT, ETR as AF
LPTIM4
SCL, SDA, SMBA as AF
I2C3/SMBUS
MOSI, MISO, SCK, NSS as
AF
RX, TX, CTS, RTS_DE as
AF
SPI3
LPUART1
UCPD1
CC1, DBCC1, CC2, DBCC2,
FRSCC1, FRSCC2 as AF
IN1, IN2, CH1, CH2,
ETR as AF
D/A converter 1
DAC1_OUT1
D/A converter 2
DAC1_OUT2
AHB/APB3
VREF buffer
@VDDA
OpAmp1
TX, RX as AF
@VDDA
ITF
TAMP
COMP2
FDCAN1
LPTIM2
RTC
@VDDA
COMP1
MOSI, MISO, SCK, NSS as
AF
SPI2
TIM7 16b
@VDDA
AHB3 160 MHz
RTC_OUT1, RTC_OUT2,
RTC_REFIN, RTC_TS
SAI2
Temperature
monitoring
APB3 160 MHz
MCLK_A, SD_A, FS_A,
SCK_A, MCLK_B, SD_B,
FS_B, SCK_B as AF
SRAM4
(16 Kbytes)
LPDMA1
SAI1
WKUPx (x=1 to 8)
TIM2
SPI1
AHB bus-matrix
RX, TX, CK,CTS, RTS as AF
APB2 160 MHz
SYSCFG
2 channels,
1 compl. channel, BKIN as AF
OSC_IN
OSC_OUT
Standby
interface
ITF
TIM1/PWM
TIM8/PWM
IWDG
APB1 160 MHz (max)
3 compl. channels
(TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
LSI
FMAC
ADC1
3 compl. channels
(TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
XTAL OSC
4- 50 MHz
Reset and clock control
CORDIC
17xIN
@VSW
CRC
@VDDA
VDDIO, VDDUSB, VDDA,
VSSA, VDD, VSS, NRST
PVD, PVM
FIFO
PE[15:0]
GPIO port B
BOR
Int
PLL 1, 2, 3
PHY
PD[15:0]
@VSW
BKPSRAM
(2 Kbytes)
VDD = 1.71 to 3.6 V
VSS
@VDD
Supply supervision
PCLKx
PC[12:0]
GPIO port A
HCLKx
PC[15:13]
Reset
FCLK
PB[15:0]
MSI
HSI16
AHB1 160 MHz
PA[15:0]
TSC
MDF1
@VDD
Power management
Voltage regulator LDO
and SMPS 3.3 to 1.2 V
ITF
ADC4
LPGPIO
ADF1
19xIN
IO[15:0] as AF
SDIN0, CKIN0, CCK0,
CCK1 as AF
GTZC2
VDD power
domain
VDDUSB power
domain
VSW power
domain
VDDIO2 power
domain
VDDA power
domain
Note: VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0.
MSv60471V6
DS13086 Rev 6
21/334
21
Functional overview
STM32U585xx
3
Functional overview
3.1
Arm Cortex-M33 core with TrustZone and FPU
The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
•
Arm TrustZone technology, using the Armv8-M main extension supporting secure and
non-secure states
•
MPUs (memory protection units), supporting up to 16 regions for secure and
non-secure applications
•
Configurable SAU (secure attribute unit) supporting up to eight memory regions as
secure or non-secure
•
Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
•
System AHB bus:
The S-AHB (system AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
•
Code AHB bus:
The C-AHB (code AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32U585xx devices.
3.2
ART Accelerator (ICACHE and DCACHE)
3.2.1
Instruction cache (ICACHE)
The ICACHE is introduced on C-AHB code bus of Cortex-M33 processor to improve
performance when fetching instruction (or data) from both internal and external memories.
ICACHE offers the following features:
•
22/334
Multi-bus interface:
–
Slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
–
Master1 port performing refill requests to internal memories (Flash memory and
SRAMs)
–
Master2 port performing refill requests to external memories (external Flash
memory and RAMs through Octo-SPI and FMC interfaces)
–
Second slave port dedicated to ICACHE registers access
DS13086 Rev 6
STM32U585xx
•
3.2.2
Functional overview
Close to zero wait-states instructions/data access performance:
–
0 wait-state on cache hit
–
Hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
–
Critical-word-first refill policy, minimizing processor stalls on cache miss
–
Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
–
Dual master ports allowing to decouple internal and external memory traffics, on
fast and slow buses, respectively; also minimizing impact on interrupt latency
–
Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
–
Performance monitoring by means of a hit counter and a miss counter
•
Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
•
Power consumption reduced intrinsically (more accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default two-ways set-associative mode)
•
TrustZone security support
•
Maintenance operation for software management of cache coherency
•
Error management: detection of unexpected cacheable write access, with optional
interrupt raising
Data cache (DCACHE)
The DCACHE is introduced on S-AHB system bus of Cortex-M33 processor to improve the
performance of data traffic to/from external memories.
DCACHE offers the following features:
•
•
Multi-bus interface:
–
Slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
–
Master port performing refill requests to external memories (external Flash
memory and RAMs through Octo-SPI and FMC interfaces)
–
Second slave port dedicated to DCACHE registers access
Close to zero wait-states external data access performance:
–
Zero wait-states on cache hit
–
Hit-under-miss capability, allowing to serve new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
–
Critical-word-first refill policy for read transactions, minimizing processor stalls on
cache miss
–
Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
–
Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
–
Performance monitoring by means of two hit counters (for read and write) and two
miss counters (for read and write)
DS13086 Rev 6
23/334
93
Functional overview
•
Supported cache accesses:
–
Both write-back and write-through policies supported (selectable with AHB
bufferable attribute)
–
Read and write-back always allocated
–
Write-through always non-allocated (write-around)
–
Byte, half-word and word writes supported
•
TrustZone security support
•
Maintenance operations for software management of cache coherency:
•
3.3
STM32U585xx
–
Full cache invalidation (non interruptible)
–
Address range clean and/or invalidate operations (background task, interruptible)
Error management: detection of error for master port request initiated by DCACHE (line
eviction or clean operation), with optional interrupt raising
Memory protection unit
The MPU (memory protection unit) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 16 protected areas.
The MPU regions and registers are banked across secure and non-secure states.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by a RTOS
(real-time operating system).
If a program accesses a memory location that is prohibited by the MPU, the RTOS can
detect it and take action. In a RTOS environment, the kernel can dynamically update the
MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.4
Embedded Flash memory
The devices feature 2 Mbytes of embedded Flash memory that is available for storing
programs and data. The Flash memory supports 10 000 cycles and up to 100 000 cycles
on 512 Kbytes.
A 128-bit instruction prefetch is implemented and can optionally be enabled.
The Flash memory interface features:
•
Dual-bank operating modes
•
Read-while-write (RWW)
This allows a read operation to be performed from one bank while an erase or program
operation is performed to the other bank. The dual-bank boot is also supported. Each bank
contains 128 pages of 8 Kbytes. The Flash memory also embeds 512-byte OTP (one-time
programmable) for user data.
The whole non-volatile memory embeds the ECC (error correction code) feature supporting:
24/334
•
single-error detection and correction
•
double-error detection
•
ECC fail address report
DS13086 Rev 6
STM32U585xx
3.4.1
Functional overview
Flash memory protection
The option bytes allow the configuration of flexible protections:
•
write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
•
RDP (readout protection) to protect the whole memory, has four levels of protection
available (see Table 3 and Table 4):
–
Level 0: no readout protection
–
Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-secure Flash
memory are possible. The debug access to secure area is prohibited.
Debug access to non-secure area remains possible.
–
Level 1: memory readout protection
The Flash memory cannot be read from or written to if either the debug features
are connected or the boot in RAM or bootloader are selected. If TrustZone is
enabled, the non-secure debug is possible and the boot in SRAM is not possible.
Regressions from Level 1 to lower levels can be protected by password
authentication.
–
Level 2: chip readout protection
The debug features, the boot in RAM and the bootloader selection are disabled.
A secure secret key can be configured in the secure options to allow the
regression capability from Level 2 to Level 1. By default (key not configured), this
Level 2 selection is irreversible and JTAG/SWD interfaces are disabled. If the
secret key was previously configured in lower RDP levels, the device enables the
RDP regression from Level 2 to Level 1 after password authentication through
JTAG/SWD interface.
Note:
In order to reach the best protection level, it is recommended to activate TrustZone and to
set the RDP Level 2 with password authentication regression enabled.
Table 3. Access status versus protection level and execution modes when TZEN = 0
Area
RDP
level
User execution
(boot from Flash memory)
Debug/boot from RAM/ bootloader(1)
Read
Write
Erase
Read
Write
Erase
1
Yes
Yes
Yes
No
No
No(4)
2
Yes
Yes
Yes
N/A
N/A
N/A
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
1
Yes
Yes(4)
N/A
Yes
Yes(4)
N/A
2
Yes
No(5)
N/A
N/A
N/A
N/A
1
Yes
Yes(6)
N/A
Yes
Yes(6)
N/A
2
Yes
Yes(6)
N/A
N/A
N/A
N/A
Flash main memory
System memory (2)
Option bytes(3)
OTP
DS13086 Rev 6
25/334
93
Functional overview
STM32U585xx
Table 3. Access status versus protection level and execution modes when TZEN = 0 (continued)
Area
RDP
level
User execution
(boot from Flash memory)
Debug/boot from RAM/ bootloader(1)
Read
Write
Erase
Read
Write
Erase
1
Yes
Yes
N/A
No
No
N/A(7)
2
Yes
Yes
N/A
N/A
N/A
N/A
1
Yes
Yes
N/A
No
No
N/A(8)
2
Yes
Yes
N/A
N/A
N/A
N/A
1
Yes
Yes
Yes
No(9)
Yes
Yes
2
Yes
Yes
Yes
N/A
N/A
N/A
Backup registers
SRAM2/backup
RAM
OTFDEC regions
(Octo-SPI)
1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. Option bytes are only accessible through the Flash memory registers and OPSTRT bit.
4. The Flash main memory is erased when the RDP option byte changes from level 1 to level 0.
5. SWAP_BANK option bit can be modified.
6. OTP can only be written once.
7. The backup registers are erased when RDP changes from level 1 to level 0.
8. All SRAMs are erased when RDP changes from level 1 to level 0.
9. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.
Table 4. Access status versus protection level and execution modes when TZEN = 1
Area
Flash main memory
System memory (3)
Option bytes(4)
26/334
RDP
level
User execution
(boot from Flash memory)
Debug/ bootloader(1)
Read
Write
Erase
Read
Write
Erase
0.5
Yes
Yes
Yes
Yes(2)
Yes(2)
Yes(2)
1
Yes
Yes
Yes
No
No
No(5)
2
Yes
Yes
Yes
N/A
N/A
N/A
0.5
Yes
No
No
Yes
No
No
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
0.5
Yes
Yes(5)
N/A
Yes
Yes (5)
N/A
1
Yes
Yes(5)
N/A
Yes
Yes(5)
N/A
2
Yes
No(6)
N/A
N/A
N/A
N/A
DS13086 Rev 6
STM32U585xx
Functional overview
Table 4. Access status versus protection level and execution modes when TZEN = 1 (continued)
RDP
level
Area
OTP
Backup registers
SRAM2/backup
RAM
OTFDEC regions
(Octo-SPI)
User execution
(boot from Flash memory)
Debug/ bootloader(1)
Read
Write
Erase
Read
Write
Erase
0.5
Yes
Yes(7)
N/A
Yes
Yes(7)
N/A
1
Yes
Yes(7)
N/A
Yes
Yes(7)
N/A
2
Yes
Yes(7)
N/A
N/A
N/A
N/A
0.5
Yes
Yes
N/A
Yes(2)
Yes(2)
N/A(8)
1
Yes
Yes
N/A
No
No
N/A(8)
2
Yes
Yes
N/A
N/A
N/A
N/A
0.5
Yes
Yes
N/A
Yes(2)
Yes(2)
N/A(9)
1
Yes
Yes
N/A
No
No
N/A(9)
2
Yes
Yes
N/A
N/A
N/A
N/A
0.5
Yes
Yes
Yes
No(10)
Yes
Yes
1
Yes
Yes
Yes
No(10)
Yes
Yes
2
Yes
Yes
Yes
N/A
N/A
N/A
1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. Depends on TrustZone security access rights.
3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are only accessible through the Flash memory registers and OPSTRT bit.
5. The Flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
6. SWAP_BANK option bit can be modified.
7. OTP can only be written once.
8. The backup registers are erased when RDP changes from level 1 to level 0.
9. All SRAMs are erased when RDP changes from level 1 to level 0.
10. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.
3.4.2
Additional Flash memory protections when TrustZone activated
When the TrustZone security is enabled through option bytes, the whole Flash memory is
secure after reset and the following protections are available:
•
non-volatile watermark-based secure Flash memory area
The secure area can be accessed only in Secure mode. One area per bank can be
selected with a page granularity.
•
secure HDP (hide protection area)
It is part of the Flash memory secure area and can be protected to deny an access to
this area by any data read, write and instruction fetch. For example, a software code in
the secure Flash memory hide protection area can be executed only once and deny
DS13086 Rev 6
27/334
93
Functional overview
STM32U585xx
any further access to this area until next system reset. One area per bank can be
selected at the beginning of the secure area.
•
volatile block-based secure Flash memory area
Each page can be programmed on-the-fly as secure or non-secure.
3.4.3
FLASH privilege protection
Each Flash memory page can be programmed on-the-fly as privileged or unprivileged.
3.5
Embedded SRAMs
Five SRAMs are embedded in the STM32U585xx devices, each with specific features.
SRAM1, SRAM2, and SRAM3 are the main SRAMs. SRAM4 is in the SRAM used for
peripherals LPBAM (low-power background autonomous mode) in Stop 2 mode.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
3.5.1
•
SRAM1: three 64-Kbyte blocks (total 192 Kbytes)
•
SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In addition
SRAM2 blocks can be retained in Standby mode.
•
SRAM3: eight 64-Kbyte blocks (total 512 Kbytes) with optional ECC. When ECC is
enabled, 256 Kbytes support ECC and 192 Kbytes of SRAM3 can be accessed
without ECC.
•
SRAM4: 16 Kbytes
•
BKPSRAM (backup SRAM): 2 Kbytes with optional ECC. The BKPSRAM can be
retained in all low-power modes and when VDD is off in VBAT mode, but not in
Shutdown mode.
SRAMs TrustZone security
When the TrustZone security is enabled, all SRAMs are secure after reset.
The SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as secure or non-secure by
blocks, using the MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or non-secure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).
3.5.2
SRAMs privilege protection
The SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as privileged or unprivileged
by blocks, using the MPCBB. The granularity of SRAM privilege block based is a page
of 512 bytes. Backup SRAM regions can be programmed as privileged or unprivileged
with watermark, using the TZSC (TrustZone security controller) in the GTZC (global
TrustZone controller).
28/334
DS13086 Rev 6
STM32U585xx
3.6
Functional overview
TrustZone security architecture
The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and non-secure state.
•
SAU: up to eight SAU configurable regions are available for security attribution.
•
IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and
the higher security state is selected.
Based on IDAU security attribution, the Flash memory, system SRAM and peripheral
memory space is aliased twice for secure and non-secure states. However, the external
memory space is not aliased.
The table below shows an example of typical SAU region configuration based on IDAU
regions. The user can split and choose the secure, non-secure or NSC regions for external
memories as needed.
Table 5. Example of memory map security attribution versus SAU configuration regions
Region
description
Address range
IDAU security
attribution
SAU security
attribution typical
configuration
Final security
attribution
Code - external memories
0x0000 0000
0x07FF FFFF
Non-secure
Secure or
non-secure or NSC(1)
Secure or
non-secure or NSC
0x0800 0000
0x0BFF FFFF
Non-secure
Non-secure
Non-secure
0x0C00 0000
0x0FFF FFFF
NSC
Secure or NSC
Secure or NSC
Code - Flash and SRAM
Code - external memories
SRAM
Peripherals
External memories
0x1000 0000
0x17FF FFFF
0x1800 0000
0x1FFF FFFF
Non-secure
Non-secure
0x2000 0000
0x2FFF FFFF
Non-secure
0x3000 0000
0x3FFF FFFF
NSC
Secure or NSC
Secure or NSC
0x4000 0000
0x4FFF FFFF
Non-secure
Non-secure
Non-secure
0x5000 0000
0x5FFF FFFF
NSC
Secure or NSC
Secure or NSC
0x6000 0000
0xDFFF FFFF
Non-secure
Secure or
non-secure or NSC
Secure or
non-secure or NSC
1. NSC = non-secure callable.
DS13086 Rev 6
29/334
93
Functional overview
3.6.1
STM32U585xx
TrustZone peripheral classification
When the TrustZone security is active, a peripheral can be either securable or
TrustZone-aware type as follows:
3.6.2
•
securable: peripheral protected by an AHB/APB firewall gate that is controlled from
TZSC to define security properties
•
TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure
Default TrustZone security state
The default system security state is detailed below:
•
CPU:
–
•
Memory map:
–
•
•
–
Flash memory security area is defined by watermark user options.
–
Flash memory block based area is non-secure after reset.
SRAMs:
FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) is secure.
Peripherals
–
Securable peripherals are non-secure after reset.
–
TrustZone-aware peripherals are non-secure after reset. Their secure
configuration registers are secure.
•
All GPIOs are secure after reset.
•
Interrupts:
–
•
3.7
All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
External memories:
–
•
SAU is fully secure after reset. Consequently, all memory map is fully secure.
Up to eight SAU configurable regions are available for security attribution.
Flash memory:
–
•
Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
NVIC: All interrupts are secure after reset. NVIC is banked for secure and nonsecure state.
TZIC: All illegal access interrupts are disabled after reset.
Boot modes
At startup, a BOOT0 pin, nBOOT0, NSBOOTADDx[24:0] (x = 0, 1) and
SECBOOTADD0[24:0] option bytes are used to select the boot memory address that
includes:
30/334
•
Boot from any address in user Flash memory.
•
Boot from system memory bootloader.
•
Boot from any address in embedded SRAM.
•
Boot from RSS (root security services).
DS13086 Rev 6
STM32U585xx
Functional overview
The BOOT0 value comes from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
The bootloader is located in the system memory, programmed by ST during production.
The bootloader is used to reprogram the Flash memory by using USART, I2C, SPI, FDCAN
or USB FS in device mode through the DFU (device firmware upgrade).
The bootloader is available on all devices. Refer to the application note
STM32 microcontroller system memory boot mode (AN2606) for more details.
The RSS are embedded in a Flash memory area named secure information block,
programmed during ST production.
For example, the RSS enable the SFI (secure firmware installation), thanks to the RSSe SFI
(RSS extension firmware).
This feature allows customer to produce the confidentiality of the firmware to be provisioned
into the STM32, when production is sub-contracted to untrusted third party.
The RSS are available on all devices, after enabling the TrustZone through the TZEN option
bit. Refer to the application note Overview secure firmware install (SFI) (AN4992)
for more details.
Refer to Table 6 and Table 7 for boot modes when TrustZone is disabled and
enabled respectively.
Table 6. Boot modes when TrustZone is disabled (TZEN = 0)
nBOOT0
FLASH_
OPTR[27]
BOOT0
pin PH3
nSWBOOT0
FLASH_
OPTR[26]
Boot address
option-byte
selection
Boot area
ST programmed
default value
-
0
1
NSBOOTADD0[24:0]
Boot address defined by
user option bytes
NSBOOTADD0[24:0]
Flash: 0x0800 0000
-
1
1
NSBOOTADD1[24:0]
Boot address defined by
user option bytes
NSBOOTADD1[24:0]
Bootloader:
0x0BF9 0000
1
-
0
NSBOOTADD0[24:0]
Boot address defined by
user option bytes
NSBOOTADD0[24:0]
Flash: 0x0800 0000
0
-
0
NSBOOTADD1[24:0]
Boot address defined by
user option bytes
NSBOOTADD1[24:0]
Bootloader:
0x0BF9 0000
When TrustZone is enabled by setting the TZEN option bit, the boot space must be in the
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.
DS13086 Rev 6
31/334
93
Functional overview
STM32U585xx
Table 7. Boot modes when TrustZone is enabled (TZEN = 1)
BOOT_
LOCK
nBOOT0 BOOT0 nSWBOOT0 RSS
FLASH_
pin
FLASH_
comOPTR[27]
PH3
OPTR[26] mand
-
0
1
0
SECBOOTADD0
[24:0]
-
1
1
0
N/A
0
1
Boot address
option-bytes
selection
Boot area
ST programmed
default value
Secure boot address
defined by user
Flash:
option bytes
0x0C00 0000
SECBOOTADD0[24:0]
RSS
RSS:
0x0FF8 0000
Secure boot address
defined by user
Flash:
option bytes
0x0C00 0000
SECBOOTADD0[24:0]
1
-
0
0
SECBOOTADD0
[24:0]
0
-
0
0
N/A
RSS
RSS:
0x0FF8 0000
-
-
-
≠0
N/A
RSS
RSS:
0x0FF8 0000
-
SECBOOTADD0
[24:0]
-
-
-
Secure boot address
defined by user
Flash:
option bytes
0x0C00 0000
SECBOOTADD0[24:0]
The boot address option bytes allow any boot memory address to be programmed.
However, the allowed address space depends on the Flash memory RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot address is forced either in secure Flash memory
or non-secure Flash memory, depending on TrustZone security option as described in the
table below.
Table 8. Boot space versus RDP protection
RDP
TZEN = 1
TZEN = 0
0
Any boot address
Any boot address
0.5
1
2
32/334
N/A
Boot address only in RSS or secure Flash memory:
0x0C00 0000 - 0x0C1F FFFF
Otherwise, forced boot address is 0x0FF8 0000.
Any boot address
Boot address only in Flash memory
0x0800 0000 - 0x081F FFFF
Otherwise, forced boot address is 0x0800 0000.
DS13086 Rev 6
STM32U585xx
3.8
Functional overview
Global TrustZone controller (GTZC)
GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes three different sub-blocks:
•
TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
•
TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates
a secure interrupt towards NVIC.
•
MPCBB: MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone
system product having segmented SRAM with programmable-security and privileged
attributes.
The GTZC main features are:
3.9
•
Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
•
Secure and non-secure access supported for privileged/unprivileged part of TZSC
•
Set of registers to define product security settings:
–
Secure/privilege regions for external memories
–
Secure/privilege access mode for securable peripherals
–
Secure/privilege access mode for securable legacy masters
Power supply management
The PWR (power controller) main features are:
•
•
•
Power supplies and supply domains
–
Core domain (VCORE)
–
VDD domain
–
Backup domain (VBAT)
–
Analog domain (VDDA)
–
SMPS power stage (VDDSMPS, available only on SMPS packages)
–
VDDIO2 domain
–
VDDUSB for USB transceiver
System supply voltage regulation
–
SMPS step down converter
–
Voltage regulator (LDO)
Power supply supervision
–
BOR monitor
–
PVD monitor
–
PVM monitor (VDDA, VDDUSB, VDDIO2)
DS13086 Rev 6
33/334
93
Functional overview
•
3.9.1
STM32U585xx
Power management
–
Operating modes
–
Voltage scaling control
–
Low-power modes
•
VBAT battery charging
•
TrustZone security and privileged protection
Power supply schemes
The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
•
VDD = 1.71 V to 3.6 V (functionality guaranteed down to VBORx min value)
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
VDDA = 1.58 V (COMPs) / 1.6 V (DACs, OPAMPs) / 1.62 V (ADCs) /
1.8 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs, voltage reference buffer,
operational amplifiers and comparators. The VDDA voltage level is independent from
the VDD voltage and must be connected to VDD or VSS pin (preferably to VDD) when
these peripherals are not used.
•
VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is provided
externally through VDDSMPS supply pin and must be connected to the same supply
than VDD.
•
Note:
VLXSMPS is the switched SMPS step down converter output.
The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
•
VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. VDDUSB
voltage level is independent from the VDD voltage and must be connected to VDD or
VSS pin (preferably to VDD) when the USB is not used.
•
VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level
is independent from the VDD voltage and must be connected to VDD or VSS pin
(preferably to VDD) when PG[15:2] are not used.
•
VBAT = 1.65 V to 3.6 V (functionality guaranteed down to VBOR_VBAT min value)
VBAT is the power supply for RTC, TAMP, external and internal clocks 32 kHz
oscillators, and backup registers (through power switch) when VDD is not present.
•
VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports four outputs:
34/334
–
VREF+ around 1.5 V. This requires VDDA ≥ 1.8 V.
–
VREF+ around 1.8 V. This requires VDDA ≥ 2.1 V.
DS13086 Rev 6
STM32U585xx
Functional overview
–
VREF+ around 2.048 V. This requires VDDA ≥ 2.4 V.
–
VREF+ around 2.5 V. This requires VDDA ≥ 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled.
VREF- must always be equal to VSSA.
The STM32U585xx devices embed two regulators: one LDO and one SMPS in parallel to
provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3 and SRAM4 and
embedded Flash memory. The SMPS generates this voltage on VDD11 (two pins), with
a total external capacitor of 4.7 μF typical. SMPS requires an external coil of 2.2 μH typical.
The LDO generates this voltage on VCAP pin connected to an external capacitor of 4.7 μF
typical.
Both regulators can provide four different voltages (voltage scaling) and can operate in
Stop modes.
It is possible to switch from SMPS to LDO and from LDO to SMPS on-the-fly.
Figure 2. STM32U585xQ power supply overview (with SMPS)
VDDA domain
VDDA
VSSA
VDDUSB
VSS
VDDIO2
VSS
A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer
USB transceiver
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain
VDDIO1 I/O ring
Reset block
Temperature sensor
3 x PLL
Internal RC oscillators
VCORE domain
Core
VSS
Standby circuitry
(Wakeup logic, IWDG)
SRAM1
SRAM2
SRAM3
SRAM4
VDD
Voltage regulator
LDO regulator
2x VDD11
VLXSMPS
VDDSMPS
VSSSMPS
VCORE
SMPS regulator
Digital
peripherals
Flash memory
Low-voltage detector
Backup domain
VBAT
LSE crystal 32 kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM
MSv63604V3
DS13086 Rev 6
35/334
93
Functional overview
STM32U585xx
Figure 3. STM32U585xx power supply overview (without SMPS)
VDDA domain
VDDA
VSSA
A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer
VDDUSB
VSS
VDDIO2
VSS
USB transceiver
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain
VDDIO1
VSS
VDD
I/O ring
VCORE domain
Reset block
Temperature sensor
3 x PLL
Internal RC oscillators
Core
SRAM1
SRAM2
SRAM3
SRAM4
Standby circuitry
(Wakeup logic, IWDG)
VCORE
VCAP
LDO regulator
Digital
peripherals
Flash memory
Low-voltage detector
Backup domain
VBAT
LSE crystal 32kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM
MSv64350V4
During power-up and power-down phases, the following power sequence requirements
must be respected:
36/334
•
When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain
below VDD + 300 mV.
•
When VDD is above 1 V, all power supplies are independent.
•
During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the
power-down transient phase.
DS13086 Rev 6
STM32U585xx
Functional overview
Figure 4. Power-up /down sequence
V
3.6
VDDX(1)
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.
3.9.2
Power supply supervisor
The devices have an integrated ultra-low-power BOR (Brownout reset) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after power
on and during power down. The device remains in reset mode when the monitored supply
voltage VDD is below a specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded PVD (programmable voltage
detector) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below and/or rises above the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the independent
supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional
supply range.
The devices support dynamic voltage scaling to optimize its power consumption in Run
mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
•
Range 1 (VCORE = 1.2 V) with CPU and peripherals running at up to 160 MHz
•
Range 2 (VCORE = 1.1 V) with CPU and peripherals running at up to 110 MHz
•
Range 3 (VCORE = 1.0 V) with CPU and peripherals running at up to 55 MHz
•
Range 4 (VCORE = 0.9 V) with CPU and peripherals running at up to 25 MHz
DS13086 Rev 6
37/334
93
Functional overview
STM32U585xx
Low-power modes
The ultra-low-power STM32U585xx devices support seven low-power modes to achieve the
best compromise between low-power consumption, short startup time, available peripherals
and available wakeup sources.
The table below details the related low-power modes.
Table 9. STM32U585xx mode overview
Mode
Regulator
(1)
CPU Flash
SRAM
Clocks
ON
Any
DMA and peripherals(2)
Wakeup source
Range 1
Run
Range 2
Range 3
Yes
ON(3)
Range 4
All
N/A
All except OTG_FS and UCPD
Range 1
Sleep
Stop 0
Range 2
Range 3
No
ON
ON(4)
Any
Range 4
All except OTG_FS, and UCPD
Range 1
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP (temp. sensor),
VREFBUF,
ADC4(7),
DAC1 (2 channels)(8),
COMPx (x = 1, 2),
OPAMPx (x = 1, 2),
USARTx (x = 1...5)(9),
LPUART1,
SPIx (x = 1...3)(10),
I2Cx (x = 1...4)(11),
LPTIMx (x = 1...4)(12),
MDF1(13), ADF1,
GPIO, LPGPIO,
GPDMA1(14), LPDMA1
Range 2
Range 3
Range 4
No
OFF
ON(5)
LSE
LSI
(6)
Stop 1
All
LPR
All other peripherals are frozen.
38/334
DS13086 Rev 6
Any interrupt or
event
Reset pin, all I/Os,
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP,
ADC4,
DAC1 (2 channels),
COMPx (x = 1, 2),
USARTx (x = 1...5),
LPUART1,
SPIx (x = 1...3),
I2Cx (x = 1...4),
LPTIMx (x = 1...4),
MDF1, ADF1,
GPDMA1,
LPDMA1,
OTG_FS, UCPD
STM32U585xx
Functional overview
Table 9. STM32U585xx mode overview (continued)
Mode
Stop 2
Regulator(1)
LPR
CPU Flash
No
OFF
SRAM
Clocks
LSE
LSI
ON(5)
DMA and peripherals(2)
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP, VREFBUF,
ADC4,
DAC1 (2 channels),
COMPx (x = 1, 2),
OPAMPx (x = 1, 2),
LPUART1,
SPI3,
I2C3,
LPTIMx (x = 1, 3, 4),
ADF1,
LPGPIO,
LPDMA1
Wakeup source
Reset pin, all I/Os,
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP,
ADC4,
COMPx (x = 1, 2),
LPUART1,
SPI3,
I2C3,
LPTIMx (x = 1,3,4),
ADF1,
LPDMA1
All other peripherals are frozen.
Stop 3
LPR
No
OFF
LSE
LSI
ON(5)
BOR,
RTC, TAMP, IWDG,
DAC1 (2 static channels),
OPAMPx (x = 1, 2)
Reset pin,
24 I/Os (WKUPx),
BOR, RTC, TAMP,
IWDG
All other peripherals are frozen.
OFF
64-, 56- or 8-Kbyte SRAM2
2-Kbyte BKPSRAM(5)
all other SRAMs powered off
Standby
BOR, RTC, TAMP, IWDG
All other peripherals are
powered off.
LSE
LSI
OFF
I/O configuration can be floating,
pull-up or pull-down.
OFF
Powered
off
OFF
Powered off
RTC, TAMP
Shutdown
Reset pin,
24 I/Os (WKUPx),
BOR, RTC, TAMP,
IWDG
Powered
off
LPR
Powered off
I/O configuration can be floating,
pull-up or pull-down.
LSE
All other peripherals are
powered off.
Reset pin,
24 I/Os (WKUPx),
RTC, TAMP
I/O configuration can be floating,
pull-up or pull-down(15).
DS13086 Rev 6
39/334
93
Functional overview
STM32U585xx
1. LPR means that the main regulator is OFF and the low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. One bank can
also be put in power-down mode.
4. The SRAM1, SRAM2, SRAM3, SRAM4 and BKPSRAM clocks can be gated on or off independently.
5. The SRAM can be individually powered off to save power consumption.
6. MSI and HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wakeup from
Stop event detections.
7. The ADC4 conversion is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt on
conversion events.
8. DAC1 is the digital-to-analog (D/A) converter controller instance name. This instance controls two D/A converters also
called "two channels". The DAC conversions are functional and autonomous with DMA in Stop mode.
9. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop mode, and can
generate a wakeup interrupt on transfer events.
10. SPI transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt
on transfer events.
11. I2C transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt
on transfer events.
12. LPTIM is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt on all events.
13. MDF and ADF are functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt on events.
14. GPDMA and LPDMA are functional and autonomous in Stop mode, and can generate a wakeup interrupt on events.
15. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop 0, Stop 1, Stop 2 and Stop 3 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI,
the HSI16, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is
still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals are autonomous and can operate in Stop mode by requesting their
kernel clock and their bus (APB or AHB) when needed, in order to transfer data with
DMA (GPDMA1 in Stop 0 and Stop 1 modes, LPDMA1 in Stop 0, Stop 1 and Stop 2
modes). Refer to Low-power background autonomous mode (LPBAM) for more details.
LPBAM is not supported in Stop 3 mode.
In Stop 2 and Stop 3 modes, most of the VCORE domain is put in a lower leakage mode.
Stop 0 and Stop 1 modes offer the largest number of active peripherals and wakeup
sources, a smaller wakeup time but a higher consumption than Stop 2 mode.
In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but
with much higher consumption.
Stop 3 is the lowest power mode with full retention, but the functional peripherals and
sources of wakeup are reduced to the same ones than in Standby mode.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 mode can be either MSI
up to 24 MHz or HSI16, depending on software configuration.
40/334
DS13086 Rev 6
STM32U585xx
•
Functional overview
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI, the HSI16, the HSI48 and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except for registers
and backup SRAM in the Backup domain and Standby circuitry. Optionally, the full
SRAM2 or 8 Kbytes or 56 Kbytes can be retained in Standby mode, supplied by the
low-power regulator (Standby with SRAM2 retention mode).
The BOR can be configured in ultra-low-power mode to further reduce power
consumption during Standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm,
periodic wakeup, timestamp), or a tamper detection. The tamper detection can be
raised either due to external pins or due to an internal failure detection.
The system clock after wakeup is MSI up to 4 MHz.
•
Shutdown mode
The lowest power consumption is achieved in Shutdown mode. The internal regulator
is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the HSI48, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported (VBAT).
SRAMs and register contents are lost except for registers in the Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp), or a tamper detection.
The system clock after wakeup is MSI at 4 MHz.
Low-power background autonomous mode (LPBAM)
The ultra-low-power STM32U585xx devices support LPBAM (low-power background
autonomous mode) that allows peripherals to be functional and autonomous in Stop mode
(Stop 0, Stop 1 and Stop 2 modes), so without any software running.
In Stop 0 and Stop 1 modes, the autonomous peripherals are the following: ADC4, DAC1,
LPTIMx (x = 1 to 4), USARTx (x = 1 to 5), LPUART1, SPIx (x = 1 to 3), I2Cx (x = 1 to 4),
MDF1, ADF1, GPDMA1 and LPDMA1. In these modes, SRAM1, SRAM2, SRAM3 and
SRAM4 can be accessed by the GPDMA1, and SRAM4 can be accessed by the LPDMA1.
In Stop 2 mode, the autonomous peripherals are the following: ADC4, DAC1, LPTIM1,
LPTIM3, LPTIM4, LPUART1, SPI3, I2C3, ADF1 and LPDMA1. In this mode, the SRAM4
can be accessed by the LPDMA1.
DS13086 Rev 6
41/334
93
Functional overview
STM32U585xx
Those peripherals support the features detailed below:
•
Functionality in Stop mode thanks to its own independent clock (named kernel clock)
request capability: the peripheral kernel clock is automatically switched on when
requested by a peripheral, and automatically switched off when no peripheral
requests it.
•
DMA transfers supported in Stop mode thanks to system clock request capability: the
system clock (MSI or HSI16) automatically switched on when requested by
a peripheral, and automatically switched off when no peripheral requests it. When the
system clock is requested by an autonomous peripheral, the system clock is woken up
and distributed to all peripherals enabled in the RCC. This allows the DMA to access
the enabled SRAM, and any enabled peripheral register (for instance GPIO or LPGPIO
registers).
•
Automatic start of the peripheral thanks to hardware synchronous or asynchronous
triggers (such as I/Os edge detection and low-power timer event).
•
Wakeup from Stop mode with peripheral interrupt.
The GPDMA and LPDMA are fully functional and the linked-list is updated in Stop mode,
allowing the different DMA transfers to be linked without any CPU wakeup. This can be
used to chain different peripherals transfers, or to write peripherals registers in order to
change their configuration while remaining in Stop mode.
The DMA transfers from memory to memory can be started by hardware synchronous or
asynchronous triggers, and the DMA transfers between peripherals and memories can also
be gated by those triggers.
Here below some use-cases that can be done while remaining in Stop mode:
•
•
A/D or D/A conversion triggered by a low-power timer (or any other trigger)
–
wakeup from Stop mode on analog watchdog if the A/D conversion result is out of
programmed thresholds
–
wakeup from Stop mode on DMA buffer event
Audio digital filter data transfer into SRAM
–
•
–
•
•
42/334
wakeup at the end of peripheral transfer or on DMA buffer event
2
I C master transfer, SPI transmission, UART/LPUART transmission, triggered by
a low-power timer (or any other trigger):
–
example: sensor periodic read
–
wakeup at the end of peripheral transfer or on DMA buffer event
Bridges between peripherals
–
•
wakeup from Stop on sound-activity detection
I2C slave reception or transmission, SPI reception, UART/LPUART reception
example: ADC converted data transferred by communication peripherals
Data transfer from/to GPIO/LPGPIO to/from SRAM for:
–
controlling external components
–
implementing data transmission and reception protocols
DS13086 Rev 6
STM32U585xx
Functional overview
Table 10. Functionalities depending on the working mode(1)
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
O(2)
O(2)
-
-
-
-
-
-
-
-
-
-
-
SRAM1 (192 Kbytes)
Y(3)(4)
Y(3)(4)
O(7)
-
O(7)
-
O(7)
-
-
-
-
-
-
SRAM2 (64 Kbytes)
Y(3)(4)
Y(3)(4)
O(7)
O(5)
O(7)
-
O(7)
-
O(6)
-
-
-
-
SRAM3 (512 Kbytes)
(3)(4)
Y
Y(3)(4)
O(7)
O(5)
O(7)
-
O(7)
-
-
-
-
-
-
SRAM4 (16 Kbytes)
Y(3)(4)
Y(3)(4)
O(7)
-
O(7)
-
O(7)
-
-
-
-
-
-
O(4)
O
O(5)
O
Peripheral
Run
CPU
Flash memory
(2 Mbytes)
BKPSRAM
O
(4)
Sleep
-
O
O
Wakeup
capability
Shutdown
Wakeup
capability
Standby
Wakeup
capability
Stop 3
Wakeup
capability
Stop 2
Wakeup
capability
Stop 0/1
-
VBAT
O
FSMC
O
O
-
-
-
-
-
-
-
-
-
-
-
OCTOSPIx (x = 1,2)
O
O
-
-
-
-
-
-
-
-
-
-
-
Backup registers
Y
Y
Y
-
Y
-
Y
-
Y
-
Y
-
Y
BOR (Brownout reset)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
PVD (programmable
voltage detector)
O
O
O
O
O
O
-
-
-
-
-
-
-
Peripheral voltage
monitor
O
O
O
O
O
O
-
-
-
-
-
-
-
GPDMA1
O
O
O
O(8)
-
-
-
-
-
-
-
-
-
O
O(9)
O
O(9)
-
-
-
-
-
-
-
LPDMA1
O
O
DMA2D
O
O
HSI16 (high-speed
internal)
O
O
(10)
-
(10)
-
-
-
-
-
-
-
-
HSI48 oscillator
O
O
-
-
-
-
-
-
-
-
-
-
-
HSE (high-speed
external)
O
O
-
-
-
-
-
-
-
-
-
-
-
LSI (low-speed
internal)
O
O
O
-
O
-
O
-
O
-
-
-
O
LSE (low-speed
external)
O
O
O
-
O
-
O
-
O
-
O
-
O
MSIS and MSIK
(multi-speed internal)
O
O
(10)
-
(10)
-
-
-
-
-
-
-
-
CSS (clock security
system)
O
O
-
-
-
-
-
-
-
-
-
-
-
Clock security system
on LSE
O
O
O
O
O
O
O
O
O
O
O
O
O
DS13086 Rev 6
43/334
93
Functional overview
STM32U585xx
Table 10. Functionalities depending on the working mode(1) (continued)
-
-
-
-
Backup domain
voltage and
temperature
monitoring
O
O
O
O
O
O
O
O
O
O
O
O
O
RTC/TAMP
O
O
O
O
O
O
O
O
O
O
O
O
O
Number of RTC
tamper pins
8
8
8
O
8
O
8
O
8
O
8
O
8
OTG_FS, UCPD
O(11)
O(11)
-
O
-
-
-
-
-
-
-
-
-
USARTx
(x = 1,2,3,4,5)
O
O
O(12) O(12)
-
-
-
-
-
-
-
-
-
Low-power UART
(LPUART1)
O
O
O(12) O(12) O(12) O(12)
-
-
-
-
-
-
-
I2Cx (x = 1,2,4)
O
O
O(13) O(13)
O
O(13)
O(13)
O
(14)
O(14)
(14)
O(14)
Peripheral
I2C3
SPIx (x = 1,2)
Run
O
O
Sleep
-
O
VBAT
-
-
-
-
-
-
-
-
-
O(13)
O(13)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O(14)
O(14)
SPI3
O
O
FDCAN1
O
O
-
-
-
-
-
-
-
-
-
-
-
SDMMCx (x = 1,2)
O
O
-
-
-
-
-
-
-
-
-
-
-
SAIx (x = 1,2)
O
O
-
-
-
-
-
-
-
-
-
-
-
ADC1
O
O
-
-
-
-
-
-
-
-
-
-
-
ADC4
O
O
-
-
-
-
-
-
-
DAC1 (2 converters)
O
O
O
-
O
-
-
-
-
-
-
-
-
VREFBUF
O
O
O
-
O
-
-
-
-
-
-
-
-
OPAMPx (x = 1,2)
O
O
O
-
O
-
-
-
-
-
-
-
-
COMPx (x = 1,2)
O
O
O
O
O
O
-
-
-
-
-
-
-
Temperature sensor
O
O
O
-
O
-
-
-
-
-
-
-
-
Timers (TIMx)
O
O
-
-
-
-
-
-
-
-
-
-
-
LPTIMx (x = 1,3,4)
O
O
O(16) O(16) O(16) O(16)
-
-
-
-
-
-
-
LPTIM2
O
O
O(16) O(16)
-
-
-
-
-
IWDG (independent
watchdog)
O
O
O
WWDG (window
watchdog)
O
O
-
44/334
O
Wakeup
capability
Shutdown
Wakeup
capability
Standby
Wakeup
capability
Stop 3
Wakeup
capability
Stop 2
Wakeup
capability
Stop 0/1
O(15) O(15) O(15) O(15)
-
-
-
-
O
O
O
O
(17)
O
(17)
-
-
-
-
-
-
-
-
-
-
-
-
-
DS13086 Rev 6
O
O
STM32U585xx
Functional overview
Table 10. Functionalities depending on the working mode(1) (continued)
-
-
-
-
-
-
-
-
-
Wakeup
capability
-
-
-
-
-
-
-
Shutdown
Wakeup
capability
Sleep
Standby
Wakeup
capability
Run
Stop 3
Wakeup
capability
Peripheral
Stop 2
Wakeup
capability
Stop 0/1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VBAT
SysTick timer
O
O
MDF1 (multi-function
digital filter)
O
O
O(18) O(18)
ADF1 (audio digital
filter)
O
O
O(18) O(18) O(18) O(18)
DCMI (digital camera
interface)
O
O
-
-
-
-
-
-
-
-
-
-
-
PSSI (paral. synch.
slave interface)
O
O
-
-
-
-
-
-
-
-
-
-
-
CORDIC coprocessor
O
O
-
-
-
-
-
-
-
-
-
-
-
FMAC (filter
mathematical
accelerator)
O
O
-
-
-
-
-
-
-
-
-
-
-
TSC (touch sensing
controller)
O
O
-
-
-
-
-
-
-
-
-
-
-
RNG (true random
number generator)
O
O
-
-
-
-
-
-
-
-
-
-
-
AES and secure AES
O
O
-
-
-
-
-
-
-
-
-
-
-
PKA (public key
accelerator)
O
O
-
-
-
-
-
-
-
-
-
-
-
OTFDEC (on-the-fly
decryption)
O
O
-
-
-
-
-
-
-
-
-
-
-
HASH accelerator
O
O
-
-
-
-
-
-
-
-
-
-
-
CRC calculation unit
O
O
-
-
-
-
-
-
-
-
-
-
-
GPIOs
O
O
O
O
O
O
-
24
pins
-
(19)
(19)
24
pins
(20)
-
24
pins
-
1. Y = yes (enabled). O = optional (disabled by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash memory can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAMs can be powered on or off independently.
4. The SRAM clock can be gated on or off independently.
5. ECC error interrupt or NMI wakeup from Stop mode.
6. 8-Kbyte, 56-Kbyte or full SRAM2 content can be preserved.
7. Sub-blocks or full SRAM1 and SRAM3, full SRAM2 and SRAM4 can be powered-off to save power consumption. SRAM1,
SRAM2, SRAM3 and SRAM4 can be accessed by GPDMA1 in Stop 0 and Stop 1 modes. SRAM4 can be accessed by
LPDMA1 in Stop 0, Stop 1 and Stop 2 modes.
8. GPDMA transfers are functional and autonomous in Stop mode, and generates a wakeup interrupt on transfer events.
9. LPDMA transfers are functional and autonomous in Stop mode, and generates a wakeup interrupt on transfer events.
DS13086 Rev 6
45/334
93
Functional overview
STM32U585xx
10. Some peripherals with autonomous mode and wakeup from Stop capability can request HSI16, MSIS or MSIK to be
enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.
11. OTG_FS is functional in voltage scaling range 1, 2 and 3.
12. USART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and
in SPI master modes, and generate a wakeup interrupt on transfer events.
13. I2C reception and transmission are functional and autonomous in Stop mode, and generate a wakeup interrupt
on transfer events.
14. SPI reception and transmission are functional and autonomous in Stop mode, and generate a wakeup interrupt
on transfer events.
15. A/D conversion is functional and autonomous in Stop mode, and generates a wakeup interrupt on conversion events.
16. LPTIM is functional and autonomous in Stop mode, and generates a wakeup interrupt on events.
17. Only IWDG reset can exit the device from Stop 3 and Standby modes. Wakeup with IWDG interrupt is not supported.
18. MDF and ADF are functional and autonomous in Stop mode, and generate a wakeup interrupt on events.
19. I/Os can be configured with internal pull-up, pull-down or floating in Stop 3 and Standby modes.
20. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.3
Reset mode
In order to improve the consumption under reset, the I/O state under and after reset is
“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.4
VBAT operation
The VBAT pin allows the device VBAT domain to be powered from an external battery or
an external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers
and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal
VBAT battery charging circuit is embedded and can be activated when VDD is present.
Note:
When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
3.9.5
PWR TrustZone security
When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
•
low-power mode
•
WKUP (wakeup) pins
•
voltage detection and monitoring
•
VBAT mode
Some of the PWR configuration bits security is defined by the security of other peripherals:
46/334
•
The VOS (voltage scaling) configuration is secure when the system clock selection is
secure in RCC.
•
The I/O pull-up/pull-down in Standby mode configuration is secure when the
corresponding GPIO is secure.
DS13086 Rev 6
STM32U585xx
3.10
Functional overview
Peripheral interconnect matrix
Several peripherals have direct connections between them, that allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep,
Low-power Run and Sleep, Stop 0, Stop 1 and Stop 2 modes.
3.11
Reset and clock controller (RCC)
The RCC (reset and clock control) manages the different reset types, and generates all
clocks for the bus and peripherals.
The RCC distributes the clocks coming from the different oscillators to the core and to
the peripherals. It also manages the clock gating for low-power modes and ensures the
clock robustness. It features:
•
Clock prescaler: in order to get the best trade-off between speed and current
consumption, the clock frequency to the CPU and peripherals can be adjusted by
a programmable prescaler.
•
Clock security system: clock sources can be changed safely on-the-fly in Run mode
through a configuration register.
•
Clock management: in order to reduce the power consumption, the clock controller
can stop the clock to the core, individual peripherals or memory.
•
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
–
HSE (4 to 50 MHz high-speed external crystal or ceramic resonator) that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
–
HSI16 (16 MHz high-speed internal RC oscillator) trimmable by software, that can
supply a PLL.
–
MSI (multispeed internal RC oscillator) trimmable by software, that can generate
16 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
–
System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 160 MHz.
•
HSI48 (RC48 with clock recovery system) internal 48 MHz clock source that can be
used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output
on the MCO.
•
UCPD kernel clock, derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior to the UCPD kernel clock use.
DS13086 Rev 6
47/334
93
Functional overview
•
STM32U585xx
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
–
LSE (32.768 kHz low-speed external crystal), supporting three drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
–
LSI (32 kHz low-speed internal RC), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to
output a 250 Hz as source clock.
•
Peripheral clock sources: several peripherals have their own independent clock
whatever the system clock. Three PLLs, each having three independent outputs
allowing the highest flexibility, can generate independent clocks for the ADC, USB,
SDMMC, RNG, MDF, ADF, FDCAN1, OCTOSPIs and SAIs.
•
Startup clock: after reset, the microcontroller restarts by default with MSI. The prescaler
ratio and clock source can be changed by the application program as soon as the code
execution starts.
•
CSS (clock security system): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock automatically switches to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and generates
an interrupt.
•
Clock-out capability:
–
MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application.
–
LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT mode).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 160 MHz.
48/334
DS13086 Rev 6
STM32U585xx
Functional overview
Figure 5. Clock tree
LSI RC
32 kHz or 250 Hz
LSCO
OSC32_OUT
LSI
To IWDG
HSI16
LSE OSC
32.768 kHz
Clock
detector
OSC32_IN
MCO
/ 1→16
OSC_OUT
HSE OSC
4-50 MHz
OSC_IN
/32
LSE
LSI
MSIS
HSI16
HSE
SYSCLK
pll1_r_ck
HSI48
MSIK
MSIS
MSIK 100 kHz – 48 MHz
MSIK
/Q
/R
VCO
/Q
/N
/R
/R
HSI16
SYSCLK
MSIK
MSIS
HSI16
HSE
PCLK1
To APB1 peripherals
To TIMx
(x = 2 to 7)
x4
To USARTx
(x = 2 to 5)
To SPI2
x3
To LPTIM2
HSE
pll1_q_ck
pll2_p_ck
MSIS
HSI16
HSE
pll2_p_ck
To I2Cx
(X = 1,2,4)
LSI
LSE
HSI16
pll1_r_ck
To FDCAN1
CRS clock
SYSCLK
MSIK
pll1_q_ck
pll2_q_ck
pll2_q_ck
To OCTOSPIx
(X = 1,2)
PCLK2
pll2_r_ck
APB2
PRESC
/ 1,2,4,8,16
pll3_p_ck
To SAES
To APB2 peripherals
x1 or x2
MSIS
HSI16
HSE
/M
/P
/Q
/N
HSI48
pll1_q_ck
PLL3
VCO
APB1
PRESC
/ 1,2,4,8,16
MSIK
HSI16
SYSCLK
/M
/P
To Cortex system timer
/8
LSE
HSI16
SYSCLK
pll1_p_ck
PLL2
FCLK Cortex free running clock
LSE
LSI
Clock
source
control
/M
/P
HCLK
x1 or x2
MSI RC
MSIS 100 kHz – 48 MHz
/N
AHB
PRESC
/ 1,2,..512
SYSCLK
HSI16
VCO
To LPTIM1, LPTIM3, LPTIM4
HSE
HSI RC 16 MHz
PLL1
x2
To AHB bus, core, memory and DMA
Clock
detector
HSI48 RC 48 MHz
To UCPD1
To RTC
LSI
LSE
MSIK
HSI16
To TIMx
(x = 1,8,15,16,17)
pll3_q_ck
pll3_r_ck
SHSI RC
/2
pll1_p_ck
pll3_q_ck
MSIK
LSE
HSI16
SYSCLK
To USART1
MSIK
HSI16
SYSCLK
To SPI1
x2
To ADF1 and MDF1
AUDIOCLK
pll1_p_ck
MSIK
HSI48
pll1_q_ck
pll2_q_ck
pll1_p_ck
pll2_p_ck
pll3_p_ck
HSI16
x2
To SDMMCx
(X = 1,2)
ICLK
48 MHz clock to OTG_FS
HSI16
/2
To RNG
APB3
PRESC
/ 1,2,4,8,16
pll2_r_ck
HSE
HSI16
MSIK
To SAIx
(X = 1,2)
PCLK3
To APB3 peripherals
MSIK
HSI16
To I2C3
MSIK
HSI16
To SPI3
MSIK
HSI16
LSE
To LPUART1
To ADC1, ADC4 and DAC1
LSI
LSE
DAC1 sample and hold clock
MSv63634V6
DS13086 Rev 6
49/334
93
Functional overview
3.11.1
STM32U585xx
RCC TrustZone security
When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and peripheral
configuration clock from being read or modified by non-secure accesses: when a peripheral
is secure, the related peripheral clock, reset, clock source selection and clock enable during
low-power modes control bits are secure.
A peripheral is in secure state:
3.12
•
when its corresponding SEC security bit is set in the TZSC (TrustZone security
controller), for securable peripherals.
•
when a security feature of this peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.
Clock recovery system (CRS)
The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, that is either derived
from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin
or generated by user software. For faster lock-in during startup, automatic trimming and
manual trimming action can be combined.
3.13
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain),
as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13.1
GPIOs TrustZone security
Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.
3.14
Low-power general-purpose inputs/outputs (LPGPIO)
The LPGPIO allows dynamic I/O control in Stop 2 mode thanks to LPDMA1. Up to 16 I/Os
can be configured and controlled as input or output (open-drain or push-pull depending on
GPIO configuration).
50/334
DS13086 Rev 6
STM32U585xx
3.14.1
Functional overview
LPGPIO TrustZone security
Each I/O pin registers bit of the LPGPIO is configured as secure if the corresponding I/O is
configured as secure in the GPIO.
3.15
Multi-AHB bus matrix
A 32-bit multi-AHB bus matrix interconnects all master (CPU, DMA2D, GPDMA1, SDMMC1,
SDMMC2) and slave (Flash memory, RAM, FMC, OCTOSPIs, SRAMs, AHB and APB)
peripherals. It also ensures a seamless and efficient operation even when several highspeed peripherals work simultaneously.
Another multi-AHB bus matrix interconnects two masters (previous AHB bus matrix slave
port and LPDMA1) and all slaves that are functional in Stop 2 modes (SRAM4 and
AHB/APB peripherals functional in Stop 2 mode).
3.16
System configuration controller (SYSCFG)
The STM32U585xx devices feature a set of configuration registers. The main purposes of
the system configuration controller are the following:
3.17
•
Managing robustness feature
•
Configuring FPU interrupts
•
Enabling/disabling the FMP high-drive mode of some I/Os and voltage booster for I/Os
analog switches
•
Managing the I/O compensation cell
•
Configuring register security access
General purpose direct memory access controller (GPDMA)
The general purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
•
Dual bidirectional AHB master
•
Memory-mapped data transfers from a source to a destination:
–
Peripheral-to-memory
–
Memory-to-peripheral
–
Memory-to-memory
–
Peripheral-to-peripheral
•
Autonomous data transfers during Sleep and Stop modes
•
Transfers arbitration based on a four-grade programmed priority at a channel level:
–
One high-priority traffic class, for time-sensitive channels (queue 3)
–
Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
DS13086 Rev 6
51/334
93
Functional overview
•
Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
•
Per channel interrupt generation, with separately programmed interrupt enable
per event
•
16 concurrent DMA channels:
•
•
•
•
52/334
STM32U585xx
–
Per channel FIFO for queuing source and destination transfers
–
Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
–
Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
Per linked-list item within a channel:
–
Separately programmed source and destination transfers
–
Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
–
Programmable number of data bytes to be transferred from the source, defining
the block level
–
12 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
–
Four channels with 2D source and destination addressing: programmable signed
address offsets between successive burst transfers (non-contiguous addressing
within a block, combined with programmable signed address offsets between
successive blocks, at a second 2D/repeated block level)
–
Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
–
Programmable DMA request and trigger selection
–
Programmable DMA half-transfer and transfer complete events generation
–
Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
Debug:
–
Channel suspend and resume support
–
Channel status reporting including FIFO level and event flags
TrustZone support:
–
Support for secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source/destination and link sub-levels
–
Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
–
TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a non-secure access
Privileged/unprivileged support:
–
Support for privileged and unprivileged DMA transfers, independently at
channel level
–
Privileged-aware AHB slave port
DS13086 Rev 6
STM32U585xx
Functional overview
Table 11. GPDMA1 channels implementation and usage
Hardware parameters
Channel
x
Features
dma_fifo_
dma_
size[x]
addressing[x]
x = 0 to 11
2
x = 12 to
15
4
0
Channel x (x = 0 to 11) is implemented with:
– a FIFO of 8 bytes, 2 words
– fixed/contiguously incremented addressing
These channels may be also used for GPDMA transfers, between an APB
or AHB peripheral and SRAM.
1
Channel x (x = 12 to 15) is implemented with:
– a FIFO of 32 bytes, 8 words
– 2D addressing
These channels may be also used for GPDMA transfers, between
a demanding AHB peripheral and SRAM, or for transfers from/to external
memories.
Table 12. GPDMA1 autonomous mode and wakeup in low-power modes
Feature
Low-power modes
Autonomous mode and wakeup
3.18
GPDMA1 in Sleep, Stop 0 and Stop 1 modes
Low-power direct memory access controller (LPDMA)
The LPDMA controller is a bus master and system peripheral. The LPDMA is used to
perform programmable data transfers between memory-mapped peripherals and/or
memories via linked-lists, upon the control of an off-loaded CPU.
The LPDMA main features are:
•
Single bidirectional AHB master
•
Memory-mapped data transfers from a source to a destination:
–
Peripheral-to-memory
–
Memory-to-peripheral
–
Memory-to-memory
–
Peripheral-to-peripheral
•
Autonomous data transfers during Sleep and Stop modes
•
Transfers arbitration based on a 4-grade programmed priority at channel level:
–
One high-priority traffic class, for time-sensitive channels (queue 3)
–
Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
•
Per channel event generation, on any of the following events: transfer complete, or
half-transfer complete, or data transfer error, or user setting error, and/or update
linked-list item error, or completed suspension
•
Per channel interrupt generation, with separately programmed interrupt enable
per event
DS13086 Rev 6
53/334
93
Functional overview
•
STM32U585xx
Four concurrent DMA channels:
•
–
Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
–
Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
Per linked-list item within a channel:
•
–
Separately programmed source and destination transfers
–
Programmable data handling between source and destination: byte-based
padding or truncation, sign extension and left/right realignment
–
Programmable number of data bytes to be transferred from the source, defining
the block level
–
Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at a block level, between successive
single transfers
–
Programmable DMA request and trigger selection
–
Programmable DMA half-transfer and transfer complete events generation
–
Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
Debug:
•
–
Channel suspend and resume support
–
Channel status reporting and event flags
TrustZone support
•
–
Support for secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source/destination and link sub-levels
–
Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
–
TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a non-secure access
Privileged/unprivileged support:
–
Support for privileged and unprivileged DMA transfers, independently at
channel level
–
Privileged-aware AHB slave port
Table 13. LPDMA1 channels implementation and usage
Hardware parameters
Channel
x
x = 0 to 3
54/334
dma_fifo_
size[x]
0
Features
dma_
addressing[x]
0
Channel x (x = 0 to 3) is implemented with:
– no FIFO. Only a single source transfer cell is internally registered.
– fixed/contiguously incremented addressing
DS13086 Rev 6
STM32U585xx
Functional overview
Table 14. LPDMA1 autonomous mode and wakeup in low-power modes
Feature
Low-power modes
Autonomous mode and wakeup
3.19
LPDMA1 in Sleep, Stop 0, Stop 1 and Stop 2 modes
Chrom-ART Accelerator controller (DMA2D)
The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image
manipulation. It can perform the following operations:
•
Filling a part or the whole of a destination image with a specific color
•
Copying a part or the whole of a source image into a part or the whole of a destination
image
•
Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
•
Blending a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format.
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with
indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color
look-up tables).
The main DMA2D features are:
•
Single AHB master bus architecture
•
AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT
accesses that are 32-bit)
•
User programmable working area size
•
User programmable offset for sources and destination areas expressed in pixels or
bytes expressed in pixels or bytes
•
User programmable sources and destination addresses on the whole memory space
•
Up to two sources with blending operation
•
Alpha value can be modified (source value, fixed value or modulated value)
•
User programmable source and destination color format
•
Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct
color coding
•
Two internal memories for CLUT storage in indirect color mode
•
Automatic CLUT loading or CLUT programming via the CPU
•
User programmable CLUT size
•
Internal timer to control AHB bandwidth
•
Six operating modes: register-to-memory, memory-to-memory, memory-to-memory
with pixel format conversion, memory-to-memory with pixel format conversion and
blending, memory-to memory with pixel format conversion, blending and fixed color
foreground, and memory-to memory with pixel format conversion, blending and fixed
color background
•
Area filling with a fixed color
•
Copy from an area to another
•
Copy with pixel format conversion between source and destination images
•
Copy from two sources with independent color format and blending
DS13086 Rev 6
55/334
93
Functional overview
STM32U585xx
•
Output buffer byte swapping to support refresh of displays through parallel interface
•
Abort and suspend of DMA2D operations
•
Watermark interrupt on a user programmable destination line
•
Interrupt generation on bus error or access conflict
•
Interrupt generation on process completion
3.20
Interrupts and events
3.20.1
Nested vectored interrupt controller (NVIC)
The devices embed a NVIC that is able to manage 16 priority levels and to handle up to 125
maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33.
The NVIC benefits are the following:
•
closely coupled NVIC giving low-latency interrupt processing
•
interrupt entry vector table address passed directly to the core
•
early processing of interrupts
•
processing of late arriving higher priority interrupts
•
support for tail chaining
•
processor state automatically saved
•
interrupt entry restored on interrupt exit with no instruction overhead
•
TrustZone support: NVIC registers banked across secure and non-secure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.20.2
Extended interrupt/event controller (EXTI)
The EXTI manages the individual CPU and system wakeup through configurable event
inputs. It provides wakeup requests to the power control, and generates an interrupt request
to the CPU NVIC and events to the CPU event input. For the CPU an additional event
generation block (EVG) is needed to generate the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes.
The EXTI also includes the EXTI multiplexer I/O port selection.
The EXTI main features are the following:
56/334
•
All event inputs allowed to wake up the system
•
Configurable events (signals from I/Os or peripherals able to generate a pulse)
–
Selectable active trigger edge
–
Interrupt pending status register bit independent for the rising and falling edge
–
Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation
–
Software trigger possibility
DS13086 Rev 6
STM32U585xx
•
Functional overview
TrustZone secure events
–
•
3.21
The access to control and configuration bits of secure input events can be made
secure
EXTI I/O port selection
Cyclic redundancy check calculation unit (CRC)
The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, that
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.
3.22
CORDIC co-processor (CORDIC)
The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
The CORDIC main features are:
3.23
•
24-bit CORDIC rotation engine
•
Circular and hyperbolic modes
•
Rotation and vectoring modes
•
Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root,
natural logarithm
•
Programmable precision
•
Low-latency AHB slave interface
•
Results can be read as soon as ready without polling or interrupt
•
DMA read and write channels
•
Multiple register read/write by DMA
Filter math accelerator (FMAC)
The FMAC performs arithmetic operations on vectors. It comprises a MAC
(multiplier/accumulator) unit, together with address generation logic that allows it to index
vector elements held in local memory.
The unit includes support for circular buffers on input and output, that allows digital filters to
be implemented. Both finite and infinite impulse response filters can be done.
DS13086 Rev 6
57/334
93
Functional overview
STM32U585xx
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
The FMAC main features are:
3.24
•
16 x 16-bit multiplier
•
24 + 2-bit accumulator with addition and subtraction
•
16-bit input and output data
•
256 x 16-bit local memory
•
Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•
Input and output buffers can be circular
•
Filter functions: FIR, IIR (direct form 1)
•
Vector functions: dot product, convolution, correlation
•
AHB slave interface
•
DMA read and write data channels
Flexible static memory controller (FSMC)
The FSMC includes two memory controllers:
•
NOR/PSRAM memory controller
•
NAND/memory controller
The FSMC is also named flexible memory controller (FMC).
The main features of the FSMC are the following:
•
3.24.1
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (four memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
–
Ferroelectric RAM (FRAM)
•
8-,16-bit data bus width
•
Independent chip select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces.
This LCD parallel interface capability makes it easy to build cost effective graphic
applications using LCD modules with embedded controllers or high-performance solutions
using external controllers with dedicated acceleration.
58/334
DS13086 Rev 6
STM32U585xx
3.24.2
Functional overview
FSMC TrustZone security
When the TrustZone security is enabled, the whole FSMC banks are secure after reset.
Non-secure area can be configured using the TZSC MPCWMx controller:
•
FSMC NOR/PSRAM bank:
–
•
Up to two non-secure area can be configured thought the TZSC MPCWM2
controller with a 64-Kbyte granularity
FSMC NAND bank:
–
Can be either configured as fully secure or fully non-secure using the TZSC
MPCWM3 controller
The FSMC registers can be configured as secure through the TZSC controller.
3.25
Octo-SPI interface (OCTOSPI)
The devices embed two OCTOSPIs. The OCTOSPI supports most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAMs™ and
HyperFlash™ memories, with the following functional modes:
•
Indirect mode: all the operations are performed using the OCTOSPI registers.
•
Status-polling mode: the external memory status register is periodically read and
an interrupt can be generated in case of flag setting.
•
Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
The OCTOSPI supports the following protocols with associated frame formats:
•
the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
•
the HyperBus™ frame format
The OCTOSPI offers the following features:
•
Three functional modes: Indirect, Status-polling, and Memory-mapped
•
Read and write support in Memory-mapped mode
•
Supports for single, dual, quad and octal communication
•
Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad memories in parallel.
•
SDR (single-data rate) and DTR (double-transfer rate) support
•
Data strobe support
•
Fully programmable opcode
•
Fully programmable frame format
•
HyperBus support
•
Integrated FIFO for reception and transmission
•
8-, 16-, and 32-bit data accesses allowed
•
DMA channel for Indirect mode operations
•
Interrupt generation on FIFO threshold, timeout, operation complete, and access error
DS13086 Rev 6
59/334
93
Functional overview
3.25.1
STM32U585xx
OCTOSPI TrustZone security
When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 and MPCWM5
controllers with a granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.
3.26
OCTOSPI I/O manager (OCTOSPIM)
The OCTOSPI I/O manager is a low-level interface enabling:
•
efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map)
•
multiplex of Single-, Dual-, Quad-, Octal-SPI interfaces over the same bus and hence
support memories embedded in a multichip package
The OCTOSPIM main features are:
3.27
•
Supports up to two Single-, Dual-, Quad-, Octal-SPI interfaces
•
Supports up to two ports for pin assignment
•
Fully programmable I/O matrix for pin assignment by function (data/control/clock)
Delay block (DLYB)
The delay block (DLYB) is used to generate an output clock that is dephased from the input
clock. The phase of the output clock must be programmed by the user application. The
output clock is then used to clock the data received by another peripheral such as
a SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may
require the application to re-configure and recenter the output clock phase with the received
data.
The delay block main features are:
3.28
•
Input clock frequency ranging from 25 to 160 MHz
•
Up to 12 oversampling phases
Analog-to-digital converter (ADC1 and ADC4)
The devices embed two successive approximation analog-to-digital converters.
Table 15. ADC features
ADC modes/features(1)
ADC1
ADC4
14 bits
12 bits
2.5 Msps
2.5 Msps
Hardware offset calibration
X
X
Hardware linearity calibration
X
-
Single-ended inputs
X
X
Differential inputs
X
-
Resolution
Maximum sampling speed for 14-bit resolution
60/334
DS13086 Rev 6
STM32U585xx
Functional overview
Table 15. ADC features (continued)
ADC modes/features(1)
ADC1
ADC4
X
-
Oversampling
up to x1024
up to x256
Data register
32 bits
16 bits
DMA support
X
X
Parallel data output to MDF
X
-
Autonomous mode
-
X
Offset compensation
X
-
Gain compensation
X
-
Number of analog watchdogs
3
3
Wakeup from Stop mode
-
X(2)
Injected channel conversion
1. X = supported.
2. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.
3.28.1
Analog-to-digital converter 1 (ADC1)
The ADC1 is a 14-bit ADC successive approximation analog-to-digital converter.
This ADC has up to 20 multiplexed channels. A/D conversion of the various channels can
be performed in Single, Continuous, Scan or Discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 32-bit data register.
This ADC is mapped on the AHB bus to allow fast data handling. The analog watchdog
features allow the application to detect if the input voltage goes outside the user-defined
high or low thresholds.
A built-in hardware over sampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
The ADC1 main features are:
•
High-performance features
–
14-, 12-, 10- or 8-bit configurable resolution
–
A/D conversion time independent from the AHB bus clock frequency
–
Faster conversion time by lowering resolution
–
Management of single-ended or differential inputs (programmable per channels)
–
Fast data handling thanks to the AHB slave bus interface
–
Self-calibration (both offset and linearity)
–
Channel-wise programmable sampling time
–
Flexible sampling time control
–
Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
–
Fast context switching thanks to the hardware assistant that prepares the context
of the injected channels
DS13086 Rev 6
61/334
93
Functional overview
•
•
•
•
–
Data alignment with in-built data coherency
–
Data can be managed by GPDMA for regular channel conversions with FIFO
–
Data can be routed to MDF for post processing
–
Four dedicated data registers for the injected channels
Oversampler
–
32-bit data register
–
Oversampling ratio adjustable from 2 to 1024
–
Programmable data right and left shift
Data preconditioning
–
Gain compensation
–
Offset compensation
Low-power features
–
Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
–
Slow bus frequency application while keeping optimum ADC performance
–
Automatic control to avoid ADC overrun in low AHB bus clock frequency
application (auto-delayed mode)
ADC features an external analog input channel:
–
•
•
Up to 17 channels from dedicated GPIO pads
Three additional internal dedicated channels:
–
•
STM32U585xx
One channel for internal reference voltage (VREFINT)
–
One channel for internal temperature sensor (VSENSE)
–
One channel for VBAT monitoring channel (VBAT/4)
Start-of-conversion can be initiated:
–
by software for both regular and injected conversions
–
by hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions
Conversion modes
–
Single mode: the ADC converts a single channel. The conversion is triggered by
a special event.
–
Scan mode: the ADC scans and converts a sequence of channels.
–
Continuous mode: the ADC converts continuously selected inputs.
–
Discontinuous mode: the ADC converts a subset of the conversion sequence.
•
Interrupt generation when the ADC is ready, at end of sampling, end of conversion
(regular or injected), end of sequence conversion (regular or injected), analog
watchdog 1, 2 or 3 or when an overrun event occurs
•
Three analog watchdogs
–
•
Filtering to ignore out-of-range data
ADC input range: VSSA < VIN < VREF+
Note:
The ADC1 analog block clock frequency must be between 5 MHz and 55 MHz.
62/334
DS13086 Rev 6
STM32U585xx
3.28.2
Functional overview
Analog-to-digital converter 4 (ADC4)
The 12-bit ADC4 is a successive approximation analog-to-digital converter. It has up to
25 multiplexed channels allowing it to measure signals from 19 external and six internal
sources. A/D conversion of the various channels can be performed in Single, Continuous,
Scan or Discontinuous mode. The result of the ADC is stored in a left-aligned or
right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency. The ADC4 is autonomous in low-power modes down to Stop 2 mode.
A built-in hardware oversampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
The ADC4 main features are:
•
•
•
High performance
–
12-, 10-, 8- or 6-bit configurable resolution
–
A/D conversion time: 0.4 µs for 12-bit resolution (2.5 MHz), faster conversion
times obtained by lowering resolution
–
Self-calibration
–
Programmable sampling time
–
Data alignment with built-in data coherency
–
DMA support
Low-power
–
HCLK frequency reduced for low-power operation while still keeping optimum
ADC performance
–
Wait mode: ADC overrun prevented in applications with low frequency HCLK
–
Auto-off mode: ADC automatically powered off except during the active
conversion phase, dramatically reducing the ADC power consumption
–
Autonomous mode: In low-power modes down to Stop 2 mode, the ADC4 is
automatically switched on when a trigger occurs to start conversion, and it is
automatically switched off after conversion. Data are transfered in SRAM
with DMA.
–
ADC4 interrupts wake up the device from Stop 0, Stop 1 and Stop 2 modes.
Analog input channels
–
•
Up to 19 external analog inputs
–
One channel for the internal temperature sensor (VSENSE)
–
One channel for the internal reference voltage (VREFINT)
–
One channel for the internal digital core voltage (VCORE)
–
One channel for monitoring the external VBAT power supply pin
–
Connection to two DAC internal channels
Start-of-conversion can be initiated:
–
By software
–
By hardware triggers with configurable polarity (timer events or GPIO input
events)
DS13086 Rev 6
63/334
93
Functional overview
•
STM32U585xx
Conversion modes
–
Conversion of a single channel or scan of a sequence of channels
–
Selected inputs converted once per trigger in Single mode
–
Selected inputs converted continuously in Continuous mode
–
Discontinuous mode
•
Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events, with wakeup from Stop
capability
•
Analog watchdog
•
Oversampler
–
16-bit data register
–
Oversampling ratio adjustable from 2 to 256
–
Programmable data shift up to 8 bits
•
ADC supply requirements: 1.62 to 3.6 V
•
ADC input range: VSSA < VIN < VREF+
Note:
The ADC4 analog block clock frequency must be between 140 kHz and 55 MHz.
3.28.3
Temperature sensor
The temperature sensor generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to ADC1 and ADC4 input channel that is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by STMicroelectronics in the system memory area, accessible in read-only mode.
Table 16. Temperature sensor calibration values
Calibration
value name
Description
Memory address
TS_CAL1
Temperature sensor 14-bit raw data acquired by ADC1
at 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)
0x0BFA 0710 - 0x0BFA 0711
TS_CAL2
Temperature sensor 14-bit raw data acquired by ADC1
at 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)
0x0BFA 0742 - 0x0BFA 0743
64/334
DS13086 Rev 6
STM32U585xx
3.28.4
Functional overview
Internal voltage reference (VREFINT)
The VREFINT provides a stable (bandgap) voltage output for the ADC and the comparators.
The VREFINT is internally connected to ADC1 and ADC4 input channels.
The precise voltage of VREFINT is individually measured for each part by
STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.
Table 17. Internal voltage reference calibration values
Calibration value name
VREFINT_CAL
3.28.5
Description
14-bit raw data acquired by ADC1
at 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)
Memory address
0x0BFA 07A5 - 0x0BFA 07A6
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the VBAT battery voltage using
ADC1 or ADC4 input channel. As the VBAT voltage may be higher than the VDDA, and thus
outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
four. As a consequence, the converted digital value is a quarter of the VBAT voltage.
3.29
Digital to analog converter (DAC)
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller.
In 12-bit mode, the data may be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations. An input reference pin, VREF+
(shared with others analog peripherals) is available for better resolution. An internal
reference can also be set on the same input.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low-power mode, the sample and hold mode.
The digital interface supports the following features:
•
One DAC interface, maximum two output channels
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave and triangular-wave generation
•
Sawtooth wave generation
•
Dual DAC channel for independent or simultaneous conversions
•
DMA capability for each channel including DMA underrun error detection
•
Double data DMA capability to reduce the bus activity
•
External triggers for conversion
•
DAC output channel buffered/unbuffered modes
DS13086 Rev 6
65/334
93
Functional overview
3.30
STM32U585xx
•
Buffer offset calibration
•
Each DAC output can be disconnected from the DAC_OUTx output pin
•
DAC output connection to on chip peripherals
•
Sample and hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
•
Autonomous mode to reduce the power consumption for the system
•
Voltage reference input
Voltage reference buffer (VREFBUF)
The devices embed a voltage reference buffer that can be used as voltage reference for
ADCs, DACs and also as voltage reference for external components through the
VREF+ pin.
Figure 6. VREFBUF block diagram
VREFINT
+
VREF+
-
VSSA
MSv64430V2
The internal voltage reference buffer supports four voltages: 1.5 V, 1.8 V, 2.048 V and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
3.31
Comparators (COMP)
The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low power) and with selectable
output polarity.
The reference voltage can be one of the following:
66/334
•
External I/O
•
DAC output channels
•
Internal reference voltage or submultiple (1/4, 1/2, 3/4)
DS13086 Rev 6
STM32U585xx
Functional overview
All comparators can wake up from Stop 0, Stop 1 and Stop 2 modes, generate interrupts and
breaks for the timers and can also be combined into a window comparator.
3.32
Operational amplifiers (OPAMP)
The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
3.33
•
Low-input bias current
•
Low-offset voltage
•
Low-power mode
•
Rail-to-rail input
Multi-function digital filter (MDF) and audio digital filter (ADF)
The table below lists the set of features implemented into the MDF and the ADF.
Table 18. MDF features
MDF modes/features(1)
ADF1
MDF1
1
6
ADF_CKI0 / MDF_CKIy connected to pins
-
X
Sound activity detection (SAD)
X
-
RXFIFO depth (number of 24-bit words)
4
4
ADC connected to ADCITF1
-
ADC1
ADC connected to ADCITF2
-
-
Motor dedicated features (SCD, OLD, OEC, INT, snapshot, break)
-
X
Main path with CIC4, CIC5
X
X
Main path with CIC1,2, 3 or FastSinc
-
X
Number of filters (DFLTx) and serial interfaces (SITFx)
RSFLT, HPF, SAT, SCALE, DLY, Discard functions
Autonomous in Stop mode
X
X
X(2)
X(3)
1. X = supported.
2. Stop 0, Stop 1 and Stop 2 modes only.
3. Stop 0 and Stop 1 modes only.
3.33.1
Multi-function digital filter (MDF)
The MDF is a high-performance module dedicated to the connection of external sigma-delta
(Σ∆) modulators. It is mainly targeted for the following applications:
•
audio capture signals
•
motor control
•
metering
The MDF features six digital serial interfaces (SITFx) and digital filters (DFLTx) with flexible
digital processing options to offer up to 24-bit final resolution.
The DFLTx of the MDF also include the filters of the ADF (audio digital filter).
DS13086 Rev 6
67/334
93
Functional overview
STM32U585xx
The MDF can receive, via its serial interfaces, streams coming from various digital sensors.
The MDF supports the following standards allowing the connection of various ΣΔ modulator
sensors:
•
SPI interface
•
Manchester coded 1-wire interface
•
PDM interface
A flexible BSMX (bitstream matrix) allows the connection of any incoming bitstream to any
filter.
The MDF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks.In addition it is
possible to insert a high-pass filter or DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio, integrator length. The
maximum output data resolution is up to 24 bits. There are two conversion modes: single
conversion and continuous modes. The data can be automatically stored in a system RAM
buffer through DMA, thus reducing the software overhead.
A flexible trigger interface can be used to control the conversion start. This timing control
can trigger simultaneous conversions or insert a programmable delay between conversions.
The MDF features an OLD (out-off limit detectors) function. There is one OLD for each
digital filter chain. Independent programmable thresholds are available for each OLD,
making it very suitable for over-current detection.
A SCD (short circuit detector) is also available for every selected bitstream. The SCD is able
to detect a short-circuit condition with a very short latency. Independent programmable
thresholds are offered in order to define the short circuit condition.
All the digital processing is performed using only the kernel clock. The MDF requests the
bus interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The MDF main features are:
•
AHB interface
•
Six serial digital inputs:
–
configurable SPI interface to connect various digital sensors
–
configurable Manchester coded interface support
–
compatible with PDM interface to support digital microphones
•
Two common clock input/output for Σ∆ modulators
•
Flexible BSMX for connection between filters and digital inputs
•
Two inputs to connect the internal ADCs
•
Six flexible digital filter paths, including:
–
A configurable CIC filter:
- Can be split into two CIC filters: high-resolution filter and out-off limit detector
- Can be configured in Sinc4 filter
- Can be configured in Sinc5 filter
- Adjustable decimation ratio
–
68/334
A reshape filter to improve the out-off band rejection and in-band ripple
DS13086 Rev 6
STM32U585xx
3.33.2
Functional overview
–
A high-pass filter to cancel the DC offset
–
An offset error cancellation
–
Gain control
–
Saturation blocks
–
An out-off limit detector
•
Short-circuit detector
•
Clock absence detector
•
16- or 24-bit signed output data resolution
•
Continuous or single conversion
•
Possibility to delay independently each bitstream
•
Various trigger possibilities
•
Break generation on out-of limit or short-circuit detector events
•
Autonomous functionality in Stop modes
•
DMA can be used to read the conversion data
•
Interrupts services
Audio digital filter (ADF)
The ADF is a high-performance module dedicated to the connection of external Σ∆
modulators. It is mainly targeted for the following applications:
•
audio capture signals
•
metering
The ADF features one digital serial interface (SITF0) and one digital filter (DFLT0) with
flexible digital processing options to offer up to 24-bit final resolution.
The DLFT0 of the ADF is a subset of the digital filters included into the MDF.
The ADF serial interface supports several standards allowing the connection of various Σ∆
modulator sensors:
•
SPI interface
•
Manchester coded 1-wire interface
•
PDM interface
A flexible BSMX allows the connection of any incoming bitstream to any filter.
The ADF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks. In addition it is
possible to insert a high-pass filter or a DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio. The maximum output data
resolution is up to 24 bits. There are two conversion modes: single conversion and
continuous modes. The data can be automatically stored in a system RAM buffer through
DMA, thus reducing the software overhead.
A SAD (sound activity detector) is available for the detection of “speech-like” signals. The
SAD is connected at the output of DFLT0. Several parameters can be programmed to adjust
properly the SAD to the sound environment. The SAD can strongly reduce the power
consumption by preventing the storage of samples into the system memory as long as the
observed signal does not match the programmed criteria.
DS13086 Rev 6
69/334
93
Functional overview
STM32U585xx
A flexible trigger interface can be used to control the start of conversion of the ADF.
All the digital processing is performed using only the kernel clock. The ADF requests the bus
interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The ADF main features are:
•
AHB interface
•
One serial digital input:
–
Configurable SPI interface to connect various digital sensors
–
Configurable Manchester coded interface support
–
Compatible with PDM interface to support digital microphones
•
Two common clocks input/output for Σ∆ modulators
•
Flexible BSMX for connection between filters and digital inputs
•
One flexible digital filter path, including:
–
A configurable CIC filter:
- Can be configured in Sinc4 filter
- Can be configured in Sinc5 filter
- Adjustable decimation ratio
70/334
–
A reshape filter to improve the out-off band rejection and in-band ripple
–
A high-pass filter to cancel the DC offset
–
Gain control
–
Saturation blocks
•
Clock absence detector
•
Sound activity detector
•
16- or 24-bit signed output data resolution
•
Continuous or single conversion
•
Possibility to delay independently each bitstream
•
Various trigger possibilities
•
Autonomous mode in Stop 0, Stop 1 and Stop 2 modes
•
Wakeup from Stop with all interrupts
•
DMA can be used to read the conversion data
•
Interrupts services
DS13086 Rev 6
STM32U585xx
3.34
Functional overview
Digital camera interface (DCMI)
The DCMI is a synchronous parallel interface able to receive a high-speed data flow from
an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats:
YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black and white cameras, X24 and X5 cameras, and it is
assumed that all preprocessing such as resizing is performed in the camera module.
The DCMI features are:
3.35
•
8-, 10-, 12- or 14-bit parallel interface
•
Embedded/external line and frame synchronization
•
Continuous or snapshot mode
•
Crop feature
•
Supports the following data formats:
–
8/10/12/14-bit progressive video: either monochrome or raw Bayer
–
YCbCr 4:2:2 progressive video
–
RGB 565 progressive video
–
Compressed data: JPEG
Parallel synchronous slave interface (PSSI)
The PSSI and the DCMI use the same circuitry. As a result, these two peripherals cannot be
used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and
vice versa. In addition, the PSSI and the DCMI share the same alternate functions and the
same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.
The PSSI peripheral main features are the following:
•
Slave mode operation
•
8-bit or 16-bit parallel data input or output
•
4-word (16-byte) FIFO
•
Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate
function output
When selected, these inputs can either enable the transmitter to indicate when the data is
valid, or allow the receiver to indicate when it is ready to sample the data, or both.
3.36
Touch sensing controller (TSC)
The TSC provides a simple solution to add capacitive sensing functionality to any
application. A capacitive sensing technology is able to detect finger presence near
an electrode that is protected from direct touch by a dielectric (such as glass or plastic). The
capacitive variation introduced by the finger (or any conductive object) is measured using
a proven implementation based on a surface charge transfer acquisition principle.
DS13086 Rev 6
71/334
93
Functional overview
STM32U585xx
The TSC is fully supported by the STMTouch touch sensing firmware library that is free to
use and allows touch sensing functionality to be implemented reliably in the end application.
The TSC main features are the following:
•
Proven and robust surface charge transfer acquisition principle
•
Supports up to 22 capacitive sensing channels
•
Up to eight capacitive sensing channels can be acquired in parallel offering a very good
response time
•
Spread spectrum feature to improve system robustness in noisy environments
•
Full hardware management of the charge transfer acquisition sequence
•
Programmable charge transfer frequency
•
Programmable sampling capacitor I/O pin
•
Programmable channel I/O pin
•
Programmable max count value to avoid long acquisition when a channel is faulty
•
Dedicated end of acquisition and max count error flags with interrupt capability
•
One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
•
Designed to operate with STMTouch touch sensing firmware library
Note:
The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.37
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and
an internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct
a non-deterministic random bit generator (NDRBG).
The true random generator:
72/334
•
delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
•
can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
•
produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
•
embeds startup and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
•
can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
•
has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)
DS13086 Rev 6
STM32U585xx
3.38
Functional overview
Secure advanced encryption standard hardware accelerator
(SAES)
and encryption standard hardware accelerator (AES)
The devices embed two AES accelerators: SAES and AES. The SAES with hardware
unique key embeds protection against differential power analysis (DPA) and related side
channel attacks. The SAES can share its current key register information with the faster
AES using a dedicated hardware bus.
The SAES and the AES can be used to both encrypt and decrypt data using the AES
algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)
as defined by Federal Information Processing Standards Publication (FIPS PUB 197,
Nov 2001).
Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB and CBC
chaining is supported by both SAES and AES, while CTR, CCM, GCM and GMAC chaining
is only supported by the AES.
SAES and AES support DMA single transfers for incoming and outgoing data (two DMA
channels required).
The SAES supports the selection of all the following key sources, while the AES support
only the first:
•
256-bit software key, written by the application in the key registers (write only)
•
256-bit derived hardware unique key (DHUK), computed inside the SAES engine from
a non-volatile OTP based root hardware unique key (RHUK)
•
256-bit boot hardware key (BHK), stored in tamper-resistant secure backup registers,
written by a secure code during boot. Once written, this key cannot be read or write by
any application until the next product reset.
•
XOR of DHUK (provisioned chip secret) and BHK (software secret)
DHUK, BHK and their XOR are not visible by any software (even secure).
Note:
128-bit key size can also be selected.
BHK key is cleared in case of tamper or RDP regression.
When the SAES is secure (respectively non-secure), DHUK secure (respectively nonsecure) is used.
The SAES peripheral is connected by hardware to the true random number generator RNG
(for side-channel resistance).
The SAES and AES peripherals support:
•
Compliant implementation of standard NIST Special Publication 197, Advanced
Encryption Standard (AES) and Special Publication 800-38A, Recommendation for
Block Cipher Modes of Operation
•
128-bit data block processing
•
Support for cipher keys length of 128-bit and 256-bit
•
Encryption and decryption with multiple chaining modes:
–
Electronic codebook (ECB) mode
–
Cipher block chaining (CBC) mode
DS13086 Rev 6
73/334
93
Functional overview
•
STM32U585xx
Additional chaining modes supported by AES only:
–
Counter (CTR) mode
–
Galois counter mode (GCM)
–
Galois message authentication code (GMAC) mode
–
Counter with CBC-MAC (CCM) mode
•
528 or 743 clock cycle latency in ECB encryption mode for SAES processing one
128-bit block of data with, respectively, 128-bit or 256-bit key
•
51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit
block of data with, respectively, 128-bit or 256-bit key
•
Integrated round key scheduler to compute the last round key for AES ECB/CBC
decryption
•
256-bit register for storing the cryptographic key (four 32-bit registers), with key
atomicity enforcement
•
128-bit registers for storing initialization vectors (four 32-bit registers)
•
One 32-bit input buffer and one 32-bit output buffer
•
Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
•
Data swapping logic to support 1-, 8-, 16- or 32-bit data
•
Possibility for software to suspend a message if the SAES/AES needs to process
another message with a higher priority (suspend/resume operation)
•
SAES additional features:
–
Security context enforcement for keys
–
Hardware secret key encryption/ decryption (wrapped key mode) and sharing with
faster AES peripheral (Shared key mode)
–
Protection against differential power analysis (DPA) and related side-channel
attacks
–
Optional hardware loading of two hardware secret keys (BHK, DHUK) that can be
XORed together
On top of standard AES encryption and decryption with a key loaded by software, SAES
peripheral allows the following advanced use cases:
Note:
74/334
•
Allow or deny the sharing of a key between a secure and a non-secure application,
enforced by hardware
•
Encrypt once a key using side-channel resistant AES, then share it to a faster AES
engine by decrypting it (Shared key mode)
•
On-chip encrypted storage using chip-unique secret DHUK
•
Transport key generation by encrypting the device public unique ID with the application
secret BHK
•
Binding of device secure storage keys, using the silicon unique secret key (DHUK)
XORed with the boot secret key (BHK). If BHK is lost, the whole device secure storage
is lost.
Encrypted storage or derived keys that are using DHUK or BHK, cannot be used anymore
when a security breach is detected.
DS13086 Rev 6
STM32U585xx
Functional overview
Table 19. AES/SAES features
AES/SAES modes/features(1)
AES
SAES
ECB, CBC chaining
X
X
CTR, CCM, GCM chaining
X
-
AES 128-bit ECB encryption in cycles
51
528
DHUK and BHK key selection
-
X
Side-channel attacks resistance
-
X
Shared key between SAES and AES
X
1. X = supported.
3.39
HASH hardware accelerator (HASH)
The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for
applications requiring message authentication.
The HASH computes FIPS (Federal information processing standards) approved digests of
length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes 128 bits
digests for the MD5 algorithm.
The HASH main features are:
•
•
•
•
Suitable for data authentication applications, compliant with:
–
Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
–
Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
–
Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5
Message-Digest Algorithm
–
Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
Fast computation of SHA-1, SHA-224, SHA-256, and MD5
–
82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
–
66 clock cycles for processing one 512-bit block of data using MD5 algorithm
Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message:
–
Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
–
Word swapping supported: bits, bytes, half-words and 32-bit words
Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
DS13086 Rev 6
75/334
93
Functional overview
3.40
STM32U585xx
•
Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
•
AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
•
8 × 32-bit words (H0 to H7) for output message digest
•
Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
•
Interruptible message digest computation, on a per-32-bit word basis
–
Re-loadable digest registers
–
Hashing computation suspend/resume mechanism, including using DMA
On-the-fly decryption engine (OTFDEC)
The OTFDEC allows the decryption of the on-the-fly AHB traffic based on the read request
address information, for example execute-in-place of a code stored encrypted. Four
independent and non-overlapping encrypted regions can be defined in OTFDEC.
OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency.
As consequence, each time the content of one encrypted region is changed the entire
region must be re-encrypted with a different cryptographic context (key or initialization
vector). This constraint makes OTFDEC suitable to decrypt read-only data or code, stored in
external NOR Flash.
Note:
When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to access the Flash
memory using the Memory-mapped mode of the Flash memory controller.
When security is enabled in the product, OTFDEC can be programmed only by
a secure host.
The OTFDEC main features are the following:
•
•
•
76/334
On-the-fly 128-bit decryption during OCTOSPI memory-mapped read operations
(single or multiple)
–
Use of AES in counter (CTR) mode, with two 128-bit keystream buffers
–
Support for any read size
–
Physical address of the reads is used for the encryption/decryption
Up to 4 independent encrypted regions
–
Granularity of the region definition: 4096 bytes
–
Region configuration write locking mechanism
–
Each region has its own 128-bit key, two bytes firmware version, and eight bytes
application-defined nonce. At least one of those must be changed each time
an encryption is performed by the application.
Encryption keys confidentiality and integrity protection
–
Write-only registers, with software locking mechanism
–
Availability of 8-bit CRC as public key information
•
Support for OCTOSPI prefetching mechanism
•
Possibility to select an enhanced encryption mode to add a proprietary layer of
protection on top of AES stream cipher (execute only)
DS13086 Rev 6
STM32U585xx
3.41
Functional overview
•
AMBA® AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)
•
Secure only programming if TrustZone security is enabled
•
Encryption mode
Public key accelerator (PKA)
The PKA is intended for the computation of cryptographic public key primitives, specifically
those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p)
(Galois fields). To achieve high performance at a reasonable cost, these operations are
executed in the Montgomery domain.
All needed computations are performed within the accelerator, so no further
hardware/software elaboration is needed to process the inputs or the outputs.
The PKA main features are:
•
3.42
Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications. More specifically:
–
RSA modular exponentiation, RSA Chinese remainder theorem (CRT)
exponentiation
–
ECC scalar multiplication, point on curve check, complete addition, double base
ladder, projective to affine
–
ECDSA signature generation and verification
•
Capability to handle operands up to 4160 bits for RSA/DH and 640 bits for ECC
•
Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication
•
Built-in Montgomery domain inward and outward transformations
•
Protection against differential power analysis (DPA) and related side-channel attacks.
Timers and watchdogs
The devices include two advanced control timers, up to seven general-purpose timers, two
basic timers, four low-power timers, two watchdog timers and two SysTick timers.
The table below compares the features of the advanced control, general-purpose and basic
timers.
Table 20. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Advanced
control
TIM1, TIM8
16 bits
Up, down,
Up/down
Any integer
between 1 and
65536
Yes
4
3
Generalpurpose
TIM2, TIM3,
TIM4, TIM5
32 bits
Up, down,
Up/down
Any integer
between 1 and
65536
Yes
4
No
DS13086 Rev 6
Capture/
Complementary
compare
outputs
channels
77/334
93
Functional overview
STM32U585xx
Table 20. Timer feature comparison (continued)
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Generalpurpose
TIM15
16 bits
Up
Any integer
between 1 and
65536
Yes
2
1
Generalpurpose
TIM16,
TIM17
16 bits
Up
Any integer
between 1 and
65536
Yes
1
1
Basic
TIM6, TIM7
16 bits
Up
Any integer
between 1 and
65536
Yes
0
No
3.42.1
Capture/
Complementary
compare
outputs
channels
Advanced-control timers (TIM1, TIM8)
The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100%)
•
One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.
3.42.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,
TIM16,TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32U585xx devices (see Table 20 for differences). Each general-purpose timer can be
used to generate PWM outputs, or act as a simple time base.
•
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers with 32-bit auto-reload up/downcounter
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other
general-purpose timers via the Timer Link feature for synchronization or event
chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.
78/334
DS13086 Rev 6
STM32U585xx
•
Functional overview
TIM15, 16 and 17
They are general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM15 has two channels and one complementary channel
–
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.
3.42.3
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebase.
3.42.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4)
The devices embed four low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by HSI16, MSI, LSE, LSI or an external clock. They
are able to wake up the system from Stop mode.
LPTIM1, LPTIM3, and LPTIM4 are active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
The low-power timer supports the following features:
•
16-bit up counter with 16-bit autoreload register
•
3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
•
Selectable clock
–
Internal clock sources: LSE, LSI, HSI16, MSIK (LPTIM1, LPTIM3, LPTIM4 only) or
APB clock (LPTIM2 only)
–
External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
•
16-bit ARR autoreload register
•
16-bit capture/compare register
•
Continuous/One-shot mode
•
Selectable software/hardware input trigger
•
Programmable digital glitch filter
•
Configurable output: pulse, PWM
•
Configurable I/O polarity
•
Encoder mode
•
Repetition counter
•
Up to 2 independent channels for:
•
–
Input capture
–
PWM generation (edge-aligned mode)
–
One-pulse mode output
Interrupt generation on 10 events
DS13086 Rev 6
79/334
93
Functional overview
•
3.42.5
STM32U585xx
DMA request generation on the following events:
–
Update event
–
Input capture
Infrared interface (IRTIM)
An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions. It uses internal connections with
TIM16 and TIM17.
3.42.6
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as
a watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in Debug mode.
3.42.7
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen
in Debug mode.
3.42.8
SysTick timer
The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
•
SysTick, secure instance
•
SysTick, non-secure instance
When TrustZone is disabled, only one SysTick timer is available. This timer (secure or
non-secure) is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
3.43
Real-time clock (RTC), tamper and backup registers
3.43.1
Real-time clock (RTC)
The RTC supports the following features:
80/334
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
•
Binary mode with 32-bit free-running counter
DS13086 Rev 6
STM32U585xx
Functional overview
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
•
Two programmable alarms
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
•
Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
•
TrustZone support:
–
RTC fully securable
–
Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure
configuration
–
Alarm A, alarm B, wakeup timer and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
•
32.768 kHz external crystal (LSE)
•
external resonator or oscillator (LSE)
•
internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•
high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (alarm, wakeup timer, timestamp) can generate an interrupt and wakeup the
device from the low-power modes.
3.43.2
Tamper and backup registers (TAMP)
The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32
32-bit backup registers are retained in all low-power modes and also in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with eight tamper pins and eleven internal tampers. The external tamper
pins can be configured for edge detection, or level detection with or without filtering, or
active tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
•
A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches
and cryptographic peripherals.
•
32 32-bit backup registers:
–
The backup registers (TAMP_BKPxR) are implemented in the Backup domain that
remains powered-on by VBAT when the VDD power is switched off.
DS13086 Rev 6
81/334
93
Functional overview
•
•
•
STM32U585xx
Up to 8 tamper pins for 8 external tamper detection events:
–
Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
–
Flexible active tamper I/O management: from 4 meshes (each input associated to
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper
inputs)
–
Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
–
Configurable digital filter
11 internal tamper events to protect against transient or environmental perturbation
attacks:
–
Backup domain voltage monitoring
–
Temperature monitoring
–
LSE monitoring
–
RTC calendar overflow
–
JTAG/SWD access if RDP different from 0
–
Monotonic counter overflow
–
Cryptographic peripherals fault (RNG, SAES, AES, PKA)
–
Independent watchdog reset when tamper flag is already set
–
3 ADC4 watchdogs
Each tamper can be configured in two modes:
–
Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
–
Software mode: erase of secrets following a tamper detection launched by
software
•
Any tamper detection can generate a RTC time stamp event.
•
TrustZone support:
–
Tamper secure or non-secure configuration
–
Backup registers configuration in 3 configurable-size areas:
- 1 read/write secure area
- 1 write secure/read non-secure area
- 1 read/write non-secure area
–
82/334
Boot secret key (BHK) only usable by secure AES peripheral, stored in backup
registers, protected against read and write access
•
Tamper configuration and backup registers privilege protection
•
Monotonic counter
DS13086 Rev 6
STM32U585xx
3.44
Functional overview
Inter-integrated circuit interface (I2C)
The device embeds four I2C. Refer to Table 21 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and Master modes, multimaster capability
–
Standard-mode (Sm), with a bit rate up to 100 Kbit/s
–
Fast-mode (Fm), with a bit rate up to 400 Kbit/s
–
Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System management bus (SMBus) specification rev 3.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with
ACK control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power system management protocol (PMBus) specification rev 1.3 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
•
Autonomous functionality in Stop modes with wakeup from Stop capability
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Table 21. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 Kbit/s)
X
X
X
X
Fast-mode (up to 400 Kbit/s)
X
X
X
X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
X
X
X
Programmable analog and digital noise filters
X
X
X
X
SMBus/PMBus hardware support
X
X
X
X
Independent clock
X
X
X
X
Autonomous in Stop 0, Stop 1 mode with wakeup capability
X
X
X
X
Autonomous in Stop 2 mode with wakeup capability
-
-
X
-
1. X: supported
DS13086 Rev 6
83/334
93
Functional overview
3.45
STM32U585xx
Universal synchronous/asynchronous receiver transmitter
(USART/UART)
and low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed three universal synchronous receiver transmitters (USART1, USART2
and USART3), two universal asynchronous receiver transmitters (UART4, UART5) and one
low-power universal asynchronous receiver transmitter (LPUART1).
Table 22. USART, UART and LPUART features
USART modes/features(1)
USART1/2/3
UART4/5
LPUART1
Hardware flow control for modem
X
X
X
Continuous communication using DMA
X
X
X
Multiprocessor communication
X
X
X
Synchronous mode (master/slave)
X
-
-
Smartcard mode
X
-
-
Single-wire half-duplex communication
X
X
X
IrDA SIR ENDEC block
X
X
-
LIN mode
X
X
-
Dual-clock domain and wakeup from Stop mode
(2)
X(2)
X(3)
X
Receiver timeout interrupt
X
X
-
Modbus communication
X
X
-
Auto-baud rate detection
X
X
-
Driver enable
X
X
X
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
Tx/Rx FIFO size
X
X
8 bytes
Autonomous mode
X
X
X
1. X = supported.
2. Wakeup supported from Stop 0 and Stop 1 modes.
3. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.
3.45.1
Universal synchronous/asynchronous receiver transmitter
(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
84/334
DS13086 Rev 6
STM32U585xx
Functional overview
High-speed data communications up to 20 Mbauds are possible by using the DMA (direct
memory access) for multibuffer configuration.
The USART main features are:
•
Full-duplex asynchronous communication
•
NRZ standard format (mark/space)
•
Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
•
Baud rate generator systems
•
Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
•
A common programmable transmit and receive baud rate
•
Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
•
Auto baud rate detection
•
Programmable data word length (7, 8 or 9 bits)
•
Programmable data order with MSB-first or LSB-first shifting
•
Configurable stop bits (1 or 2 stop bits)
•
Synchronous Master/Slave mode and clock output/input for synchronous
communications
•
SPI slave transmission underrun error flag
•
Single-wire half-duplex communications
•
Continuous communications using DMA
•
Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
•
Separate enable bits for transmitter and receiver
•
Separate signal polarity control for transmission and reception
•
Swappable Tx/Rx pin configuration
•
Hardware flow control for modem and RS-485 transceiver
•
Communication control/error detection flags
•
Parity control:
–
Transmits parity bit
–
Checks parity of received data byte
•
Interrupt sources with flags
•
Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
•
Autonomous functionality in Stop mode with wakeup from stop capability
•
LIN master synchronous break send capability and LIN slave break detection capability
–
13-bit break generation and 10/11-bit break detection when USART is hardware
configured for LIN
•
IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode
•
Smartcard mode
–
Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
–
0.5 and 1.5 stop bits for Smartcard operation
DS13086 Rev 6
85/334
93
Functional overview
•
3.45.2
STM32U585xx
Support for Modbus communication
–
Timeout feature
–
CR/LF character recognition
Low-power universal asynchronous receiver transmitter (LPUART)
The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
The LPUART main features are:
•
Full-duplex asynchronous communications
•
NRZ standard format (mark/space)
•
Programmable baud rate
•
From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
•
Higher baud rates can be achieved by using a higher frequency clock source
•
Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for
FIFO states.
•
Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
•
Programmable data word length (7 or 8 or 9 bits)
•
Programmable data order with MSB-first or LSB-first shifting
•
Configurable stop bits (1 or 2 stop bits)
•
Single-wire half-duplex communications
•
Continuous communications using DMA
•
Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
•
Separate enable bits for transmitter and receiver
•
Separate signal polarity control for transmission and reception
•
Swappable Tx/Rx pin configuration
•
Hardware flow control for modem and RS-485 transceiver
•
Transfer detection flags:
•
86/334
–
Receive buffer full
–
Transmit buffer empty
–
Busy and end of transmission flags
Parity control:
–
Transmits parity bit
–
Checks parity of received data byte
DS13086 Rev 6
STM32U585xx
•
3.46
Functional overview
Four error detection flags:
–
Overrun error
–
Noise detection
–
Frame error
–
Parity error
•
Interrupt sources with flags
•
Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
•
Autonomous functionality in Stop mode with wakeup from Stop capability
Serial peripheral interface (SPI)
The devices embed three serial peripheral interfaces (SPI) that can be used to
communicate with external devices while using the specific synchronous protocol. The SPI
protocol supports half-duplex, full-duplex and simplex synchronous, serial communication
with external devices.
The interface can be configured as master or slave and can operate in multi-slave or
multi-master configurations. The device configured as master provides communication
clock (SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be
applied optionally just to setup communication with concrete slave and to assure it handles
the data flow properly. The Motorola® data format is used by default, but some other specific
modes are supported as well.
The SPI main features are:
•
Full-duplex synchronous transfers on three lines
•
Half-duplex synchronous transfer on two lines (with bidirectional data line)
•
Simplex synchronous transfers on two lines (with unidirectional data line)
•
4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
•
Multi master or multi slave mode capability
•
Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
•
Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
•
Protection of configuration and setting
•
Hardware or software management of SS for both master and slave
•
Adjustable minimum delays between data and between SS and data flow
•
Configurable SS signal polarity and timing, MISO x MOSI swap capability
•
Programmable clock polarity and phase
•
Programmable data order with MSB-first or LSB-first shifting
•
Programmable number of data within a transaction to control SS and CRC
•
Dedicated transmission and reception flags with interrupt capability
•
SPI Motorola® and Texas Instruments® formats support
•
Hardware CRC feature can secure communication at the end of transaction by:
–
Adding CRC value in Tx mode
–
Automatic CRC error checking for Rx mode
DS13086 Rev 6
87/334
93
Functional overview
STM32U585xx
•
Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
•
Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
•
Programmable number of data in transaction
•
Configurable FIFO thresholds (data packing)
•
Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
•
Autonomous functionality in Stop modes (handling of the transaction flow and required
clock distribution) with wakeup from stop capability
•
Optional status pin RDY signalizing the slave device ready to handle the data flow.
Table 23. SPI features
SPI1, SPI2
(full feature set instances)
SPI3
(limited feature set instance)
Data size
Configurable from 4 to 32-bit
8/16-bit
CRC computation
CRC polynomial length
configurable from 5 to 33-bit
CRC polynomial length
configurable from 9 to 17-bit
16x 8-bit
8x 8-bit
Unlimited, expandable
Up to 1024, no data counter
Autonomous in Stop 0, Stop 1 mode
with wakeup capability
Yes
Yes
Autonomous in Stop 2 mode with
wakeup capability
No
Yes
SPI feature
Size of FIFOs
Number of transfered data
3.47
Serial audio interfaces (SAI)
The devices embed two SAIs. Refer to Table 24: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
88/334
•
Two independent audio sub-blocks that can be transmitters or receivers with their
respective FIFO
•
8-word integrated FIFOs for each audio sub-block
•
Synchronous or Asynchronous mode between the audio sub-blocks
•
Master or slave configuration independent for both audio sub-blocks
•
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
•
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and
SPDIF out
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
•
Number of bits by frame may be configurable
DS13086 Rev 6
STM32U585xx
Functional overview
•
Frame synchronization active level configurable (offset, bit length, level)
•
First active bit position in the slot is configurable
•
LSB first or MSB first for data transfer
•
Mute mode
•
Stereo/mono audio frame capability
•
Communication clock strobing edge configurable (SCK)
•
Error flags with associated interrupts if enabled respectively
•
•
–
Overrun and underrun detection
–
Anticipated frame synchronization signal detection in Slave mode
–
Late frame synchronization signal detection in Slave mode
–
Codec not ready for the AC’97 mode in reception
Interruption sources when enabled:
–
Errors
–
FIFO requests
DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
Table 24. SAI implementation
SAI features(1)
SAI1
SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
Mute mode
X
X
Stereo/mono audio frame capability.
X
X
16 slots
X
X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X
X (8 words)
X (8 words)
SPDIF
X
X
PDM
X
-
FIFO size
1. X: supported
3.48
Secure digital input/output and MultiMediaCards interface
(SDMMC)
The SDMMC (SD/SDIO embedded MultiMediaCard e•MMC™ host interface) provides
an interface between the AHB bus and SD memory cards, SDIO cards and e•MMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
Association website at www.sdcard.org.
DS13086 Rev 6
89/334
93
Functional overview
STM32U585xx
The SDMMC features include the following:
•
Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
(HS200 SDMMC_CK speed limited to maximum allowed I/O speed) (HS400 is not
supported).
•
Full compatibility with previous versions of MultiMediaCards (backward compatibility).
•
Full compliance with SD memory card specifications version 6.0
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
•
Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
•
Data transfer up to 208 Mbyte/s for the 8-bit mode
(Depending maximum allowed I/O speed).
•
Data and command output enable signals to control external bidirectional drivers
•
IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/e•MMC card at any one
time and a stack of e•MMC.
Table 25. SDMMC features
SDMMC modes/features(1)
SDMMC1
SDMMC2
Variable delay (SDR104, HS200)
X
X
SDMMC_CKIN
X
-
SDMMC_CDIR, SDMMC_D0DIR
X
-
SDMMC_D123DIR
X
-
1. X = supported.
When SDMMC peripherals are used simultaneously:
90/334
•
Only one can be used in e•MMC with 8-bit bus width.
•
The SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2 interfacing
e•MMC with 8-bit bus width, as follows:
–
If SDMMC1 has to support SDIO UHS-I modes (SDR12, SDR25, SDR50,
SDR104 or DDR50), SDMMC2 cannot support e•MMC with 8-bit bus width.
–
if SDMMC2 has to support e•MMC with 8-bit bus width, SDMMC1 supports only
SDIO default mode and high-speed mode.
DS13086 Rev 6
STM32U585xx
3.49
Functional overview
Controller area network (FDCAN)
The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
3.50
•
Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
•
CAN FD with maximum 64 data bytes supported
•
CAN error logging
•
AUTOSAR and J1939 support
•
Improved acceptance filtering
•
2 receive FIFOs of three payloads each (up to 64 bytes per payload)
•
Separate signaling on reception of high priority messages
•
Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
•
Configurable transmit Event FIFO
•
Programmable loop-back test mode
•
Maskable module interrupts
•
Two clock domains: APB bus interface and CAN core kernel clock
•
Power-down support
USB on-the-go full-speed (OTG_FS)
The devices embed a USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG_FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume.
This interface requires a precise 48 MHz clock that can be generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator
(HSI48) in Automatic-trimming mode. The synchronization for this oscillator can be taken
from the USB data stream itself (SOF signalization) that allows crystal less operation.
The OTG_FS features are:
•
USB-IF certified to the Universal Serial Bus Specification Rev 2.0
•
On-chip full-speed PHY
•
Full support (PHY) for the optional OTG (on-the-go) protocol detailed in the OTG
Supplement Rev 2.0 specification
–
Integrated support for A-B device identification (ID line)
–
Integrated support for host negotiation protocol (HNP) and session request
protocol (SRP)
–
Allows host to turn VBUS off to conserve battery power in OTG applications
–
Supports OTG monitoring of VBUS levels with internal comparators
–
Supports dynamic host-peripheral switch of role
DS13086 Rev 6
91/334
93
Functional overview
•
•
STM32U585xx
Software-configurable to operate as:
–
SRP capable USB FS peripheral (B-device)
–
SRP capable USB FS/LS host (A-device)
–
USB On-The-Go Full-Speed dual role device
Supports FS SOF and LS keep-alives with
–
SOF pulse PAD connectivity
–
SOF pulse internal connection to timer (TIMx)
–
Configurable framing period
–
Configurable end of frame interrupt
•
USB 2.0 link power management (LPM) support
•
Includes power saving features such as system stop during USB suspend, switch-off
of clock domains internal to the digital core, PHY and DFIFO power management.
•
Dedicated RAM of 1.25 Kbytes with advanced FIFO control:
–
Configurable partitioning of RAM space into different FIFOs for flexible and
efficient use of RAM
–
Each FIFO able to hold multiple packets
–
Dynamic memory allocation
–
Configurable FIFO sizes that are not powers of two to allow the use of contiguous
memory locations
•
Max guaranteed USB bandwidth for up to one frame (1 ms) without system intervention
•
Support of charging port detection as described in Battery Charging Specification
revision 1.2 on the FS PHY transceiver only.
Host-mode features:
•
External charge pump for VBUS voltage generation.
•
Up to 12 host channels (pipes): each channel is dynamically reconfigurable to allocate
any type of USB transfer.
•
Built-in hardware scheduler holding:
•
–
Up to 12 interrupt plus isochronous transfer requests in the periodic hardware
queue
–
Up to 12 control plus bulk transfer requests in the non-periodic hardware queue
Management of a shared Rx FIFO, a periodic Tx FIFO and a non-periodic Tx FIFO for
efficient usage of the USB data RAM
Peripheral-mode features:
92/334
•
1 bidirectional control endpoint0
•
5 IN endpoints (EPs) configurable to support bulk, interrupt or isochronous transfers
•
5 OUT endpoints configurable to support bulk, interrupt or isochronous transfers
•
Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB
data RAM
•
Management of up to 6 dedicated Tx-IN FIFOs (one for each active IN EP) to put less
load on the application
•
Support for the soft disconnect feature
DS13086 Rev 6
STM32U585xx
3.51
Functional overview
USB Type-C /USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Cable and
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB power delivery
requirements, featuring:
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
•
“Dead battery” support
•
USB power delivery message transmission and reception
•
FRS (fast role swap) support
The digital controller handles notably:
•
USB Type-C level detection with debounce, generating interrupts
•
FRS detection, generating an interrupt
•
Byte-level interface for USB power delivery payload, generating interrupts
(DMA compatible)
•
USB power delivery timing dividers (including a clock prescaler)
•
CRC generation/checking
•
4b5b encode/decode
•
Ordered sets (with a programmable ordered set mask at receive)
•
Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB power delivery messages and FRS signaling.
3.52
Development support
3.52.1
Serial-wire/JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.52.2
Embedded Trace Macrocell
The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.
DS13086 Rev 6
93/334
93
Pinout, pin description and alternate functions
STM32U585xx
4
Pinout, pin description and alternate functions
4.1
Pinout/ballout schematics
VDD
VSS
VDD11
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 7. LQFP48_SMPS pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA
8
29
PA8
VDDA
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
VDD
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
VLXSMPS
VDDSMPS
VSSSMPS
VDD11
VSS
LQFP48
MSv62928V1
1. The above figure shows the package top view.
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 8. LQFP48 pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA
8
29
PA8
VDDA
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
LQFP48
MSv62922V1
1. The above figure shows the package top view.
94/334
DS13086 Rev 6
STM32U585xx
Pinout, pin description and alternate functions
VDD
VSS
VDD11
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 9. UFQFPN48_SMPS pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA
8
29
PA8
VDDA
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
VDD
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
VLXSMPS
VDDSMPS
VSSSMPS
VDD11
VSS
UFQFPN48
MSv63695V3
1. The above figure shows the package top view.
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 10. UFQFPN48 pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA
8
29
PA8
VDDA
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
UFQFPN48
MSv63696V2
1. The above figure shows the package top view.
DS13086 Rev 6
95/334
147
Pinout, pin description and alternate functions
STM32U585xx
VDD
VSS
VDD11
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 11. LQFP64_SMPS pinout
VBAT
1
48
VDDUSB
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
4
45
PA12
PH0-OSC_IN
5
44
PA11
PH1-OSC_OUT
6
43
PA10
NRST
7
42
PA9
PC0
8
41
PA8
PC1
9
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA
12
37
PC6
VDDA
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VLXSMPS
VDDSMPS
VSSSMPS
VDD11
VSS
LQFP64
MSv62929V1
1. The above figure shows the package top view.
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 12. LQFP64 pinout
VBAT
1
48
VDDUSB
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
4
45
PA12
PH0-OSC_IN
5
44
PA11
PH1-OSC_OUT
6
43
PA10
NRST
7
42
PA9
PC0
8
41
PA8
PC1
9
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA
12
37
PC6
VDDA
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
LQFP64
MSv62923V1
1. The above figure shows the package top view.
96/334
DS13086 Rev 6
STM32U585xx
Pinout, pin description and alternate functions
Figure 13. WLCSP90-SMPS ballout
1
3
2
A
VDD
PC11
B
C
VSS
VDDUSB
D
E
G
PD14
J
K
PD15
VDD
VDD11
PC6
PB10
VSS
SMPS
VDD
SMPS
PE10
VLX
SMPS
PA6
PE7
PE8
PB2
PH1-OSC_
OUT
PA4
PH0-OSC_IN
NRST
VREF+
PA2
PA7
PC14-OSC32
_IN
PC15OSC32_OUT
PC1
PA1
PB0
VBAT
PC13
PC3
PB1
VDD
PE6
PC0
PA5
VDD11
PE3
PE5
PA0
18
VSS
PE4
PC2
PA3
PE9
PH3-BOOT0
PA9
PC5
PB8
PB5
17
16
PB9
PB7
PB3
PA8
15
14
PB6
PB4
PG11
PC9
PB14
VSS
PD4
13
12
VDDIO2
PG13
PC10
PB15
VSS
PG12
PG9
PA15
11
10
PG14
PD1
PC7
PB13
PG10
PD0
PA11
9
8
PD5
PA13
PC8
H
PD2
PA14
PA10
7
6
PC12
PA12
F
5
4
VSSA
VDDA
VDD
VSS
MSv62645V2
1. The above figure shows the package top view.
DS13086 Rev 6
97/334
147
Pinout, pin description and alternate functions
STM32U585xx
VDD
VSS
VDD11
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 14. LQFP100_SMPS pinout
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VDDUSB
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
VSSA
19
57
PD10
VREF+
20
56
PD9
VDDA
21
55
PD8
PA0
22
54
PB15
PA1
23
53
PB14
PA2
24
52
PB13
PA3
25
51
VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VLXSMPS
VDDSMPS
VSSSMPS
VDD11
VSS
LQFP100
1. The above figure shows the package top view.
98/334
DS13086 Rev 6
MSv62930V1
STM32U585xx
Pinout, pin description and alternate functions
VDD
VSS
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 15. LQFP100 pinout
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VDDUSB
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
VSSA
19
57
PD10
VREF-
20
56
PD9
VREF+
21
55
PD8
VDDA
22
54
PB15
PA0
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDD
LQFP100
MSv62924V1
1. The above figure shows the package top view.
DS13086 Rev 6
99/334
147
Pinout, pin description and alternate functions
STM32U585xx
Figure 16. UFBGA132 _SMPS ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
PE5
PE3
PE1
PB9
PB6
PG12
PD6
PD5
PD2
PC11
PA15
VDDUSB
B
VBAT
PE4
PE2
VDD11
PH3BOOT0
PB4
PG9
PD4
PD1
PC12
PC10
PA12
C
PC14OSC32
_IN
PE6
PC13
PE0
PB8
PB3
PG10
PD3
PD0
PA13
PA14
PA11
D
PC15OSC32_
OUT
PF0
PF3
VDD
PB7
PB5
PD7
VDDIO2
VDD
PA9
PA10
PA8
E
PF2
PF1
PF4
VSS
VSS
PC7
PC9
PC8
F
PH0OSC_IN
PF5
PC2
PC3
VSS
VDD
PG6
PG7
PC6
PG8
G
PH1-OSC
_OUT
NRST
PC1
PA1
VDD
VSS
PG4
PG2
PG3
PG5
H
VSSA
PC0
OPAMP1
_VINM
VSS
VSS
PD14
PD13
PD15
J
VREF+
PA0
PC5
VDD
PF14
PE8
PE10
PE12
VDD
PD9
PD11
PD12
K
VDDA
PA2
PA7
PB2
PF11
PG1
PE7
PE14
PB10
PB13
PB14
PB15
L
PA3
PA6
PA4
PB1
PF12
PF15
PE11
PE15
PB11
VSS
SMPS
PB12
PD8
M
PA5
OPAMP2
_VINM
PC4
PB0
PF13
PG0
PE9
PE13
VDD
SMPS
VLX
SMPS
VDD11
PD10
MSv62931V2
1. The above figure shows the package top view.
100/334
DS13086 Rev 6
STM32U585xx
Pinout, pin description and alternate functions
Figure 17. UFBGA132 ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
PE5
PE3
PE1
PB9
PB6
PG12
PD6
PD5
PD2
PC11
PA15
VDDUSB
B
VBAT
PE4
PE2
PG15
PH3BOOT0
PB4
PG9
PD4
PD1
PC12
PC10
PA12
C
PC14OSC32
_IN
PE6
PC13
PE0
PB8
PB3
PG10
PD3
PD0
PA13
PA14
PA11
D
PC15OSC32_
OUT
PF0
PF3
VDD
PB7
PB5
PD7
VDDIO2
VDD
PA9
PA10
PA8
E
PF2
PF1
PF4
VSS
VSS
PC7
PC9
PC8
F
PH0OSC_IN
PF5
PC2
PC3
VSS
VDD
PG6
PG7
PC6
PG8
G
PH1OSC_
OUT
NRST
PC1
PA1
VDD
VSS
PG4
PG2
PG3
PG5
H
VSSA
PC0
OPAMP1
_VINM
VSS
VSS
PD14
PD13
PD15
J
VREF+
PA0
PC5
VDD
PF14
PE8
PE10
PE12
VDD
PD9
PD11
PD12
K
VDDA
PA2
PA7
PB2
PF11
PG1
PE7
PE14
PB10
PB13
PB14
PB15
L
PA3
PA6
PA4
PB1
PF12
PF15
PE11
PE15
PB11
VCAP
PB12
PD8
M
PA5
OPAMP2
_VINM
PC4
PB0
PF13
PG0
PE9
PE13
PG14
PG13
PG11
PD10
MSv62925V2
1. The above figure shows the package top view.
DS13086 Rev 6
101/334
147
Pinout, pin description and alternate functions
STM32U585xx
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
VSS
VDD11
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDDIO2
VSS
PG14
PG13
PG12
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 18. LQFP144 _SMPS pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
VDD
VSS
VDD
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VLXSMPS
VDDSMPS
VSSSMPS
VDD11
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF+
VDDA
PA0
PA1
PA2
PA3
1. The above figure shows the package top view.
102/334
DS13086 Rev 6
MSv62932V1
STM32U585xx
Pinout, pin description and alternate functions
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
VSS
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDDIO2
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 19. LQFP144 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0
PA1
PA2
MSv62926V1
1. The above figure shows the package top view.
DS13086 Rev 6
103/334
147
Pinout, pin description and alternate functions
STM32U585xx
Figure 20. UFBGA169_SMPS ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PE2
PI6
VDD
VDD11
PG15
VDDIO2
PG9
VDD
PC11
PA15
VDD
PI1
PH15
B
VDD
VSS
PI5
VSS
PB6
PB4
PD6
VSS
PD0
PI4
VSS
PI0
PH12
C
VBAT
PE4
PI7
PE1
PH3BOOT0
PB5
PG10
PD4
PC10
PA14
PH14
PH13
PH10
D
PC14OSC32
_IN
PE5
PE3
PE0
PB9
PB3
PD7
PD3
PH11
PI3
PI2
PH8
VDD
E
PC15OSC32_
OUT
PF0
PC13
PE6
PB8
PG12
PD5
PC12
PH9
PH4
PH6
VSS
VDDUSB
F
PF8
VSS
PF1
PF2
PB7
PD1
PD2
PH7
PH5
PH2
PA10
PA13
PA12
G
VDD
PF7
PF9
PF5
PF3
PF4
PA8
PG7
PC9
PC8
PA9
PC7
PA11
H
PH0OSC_IN
VSS
NRST
PF10
OPAMP2
_VINM
PF6
PG1
PE10
PG8
PG6
PG4
VDDIO2
PC6
J
PH1OSC_
OUT
PC0
PC1
PC2
PA7
PG0
PE9
PG3
PG5
PD14
PD15
VSS
VDD
K
PC3
VSSA
PA0
PA5
PB0
PF12
PE8
PE14
PB10
PD12
PD10
PD13
PG2
L
VREF+
VDDA
PA1
PC4
PB2
PF14
PE7
PE13
PB11
PB12
PB15
PD8
PD9
M
OPAMP1
_VINM
PA2
VSS
PC5
PF11
PF13
VSS
PE11
PE15
VSS
SMPS
VSS
PB14
PD11
N
PA4
PA3
VDD
PA6
PB1
PF15
VDD
PE12
VLX
SMPS
VDD
SMPS
VDD11
VDD
PB13
MSv62933V3
1. The above figure shows the package top view.
104/334
DS13086 Rev 6
STM32U585xx
Pinout, pin description and alternate functions
Figure 21. UFBGA169 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PE2
PI6
VDD
VCAP
PG15
VDDIO2
PG9
VDD
PC11
PA15
VDD
PI1
PH15
B
VDD
VSS
PI5
VSS
PB6
PB4
PD6
VSS
PD0
PI4
VSS
PI0
PH12
C
VBAT
PE4
PI7
PE1
PH3BOOT0
PB5
PG10
PD4
PC10
PA14
PH14
PH13
PH10
D
PC14OSC32_
IN
PE5
PE3
PE0
PB9
PB3
PD7
PD3
PH11
PI3
PI2
PH8
VDD
E
PC15OSC32_
OUT
PF0
PC13
PE6
PB8
PG12
PD5
PC12
PH9
PH4
PH6
VSS
VDDUSB
F
PF8
VSS
PF1
PF2
PB7
PD1
PD2
PH7
PH5
PH2
PA10
PA13
PA12
G
VDD
PF7
PF9
PF5
PF3
PF4
PA8
PG7
PC9
PC8
PA9
PC7
PA11
H
PH0OSC_IN
VSS
NRST
PF10
OPAMP2
_VINM
PF6
PG1
PE10
PG8
PG6
PG4
VDDIO2
PC6
J
PH1OSC_
OUT
PC0
PC1
PC2
PA7
PG0
PE9
PG3
PG5
PD14
PD15
VSS
VDD
K
PC3
VSSA
PA0
PA5
PB0
PF12
PE8
PE14
PB10
PD12
PD10
PD13
PG2
L
VREF+
VDDA
PA1
PC4
PB2
PF14
PE7
PE13
PB11
PB12
PB15
PD8
PD9
M
OPAMP1
_VINM
PA2
VSS
PC5
PF11
PF13
VSS
PE11
PE15
PG11
VSS
PB14
PD11
N
PA4
PA3
VDD
PA6
PB1
PF15
VDD
PE12
PG14
PG13
VCAP
VDD
PB13
MSv62927V3
1. The above figure shows the package top view.
DS13086 Rev 6
105/334
147
Pinout, pin description and alternate functions
4.2
STM32U585xx
Pin description
Table 26. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input/output pin
FT
5V-tolerant I/O
TT
3.6V-tolerant I/O
RST
Bidirectional reset pin with embedded weak pull-up
resistor
Option for TT or FT I/Os(1)
I/O structure
Notes
Pin
functions
_a
I/O, with analog switch function supplied by VDDA
_c
I/O with USB Type-C power delivery function
_d
I/O with USB Type-C power delivery dead battery function
_f
I/O, Fm+ capable
_h
I/O with high-speed low-voltage mode
_s
I/O supplied only by VDDIO2
_t
I/O with a function supported in VBAT mode
_u
I/O, with USB function supplied by VDDUSB
_v
I/O very high-speed capable
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.
106/334
DS13086 Rev 6
-
-
-
-
-
C15
D14
E13
1
2
3
4
B3
A2
B2
A1
1
2
3
4
A1
D3
C2
D2
-
-
-
-
-
-
-
-
1
2
3
4
B3
A2
B2
A1
1
2
3
4
A1
D3
C2
D2
PE2
PE3
PE4
PE5
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
-
I/O FT_ha
I/O
FT_
hat
I/O
FT_
hat
I/O
FT_
hat
Alternate functions
Additional
functions
-
TRACECLK, TIM3_ETR,
SAI1_CK1, TSC_G7_IO1,
LPGPIO1_P14, FMC_A23,
SAI1_MCLK_A, EVENTOUT
-
-
TRACED0, TIM3_CH1,
OCTOSPIM_P1_DQS,
TSC_G7_IO2, LPGPIO1_P15,
FMC_A19, SAI1_SD_B,
EVENTOUT
TAMP_IN6/
TAMP_
OUT3
-
TRACED1, TIM3_CH2, SAI1_D2,
MDF1_SDI3, TSC_G7_IO3,
DCMI_D4/PSSI_D4, FMC_A20,
SAI1_FS_A, EVENTOUT
WKUP1,
TAMP_IN7/
TAMP_
OUT8
-
TRACED2, TIM3_CH3, SAI1_CK2,
MDF1_CKI3, TSC_G7_IO4,
DCMI_D6/PSSI_D6, FMC_A21,
SAI1_SCK_A, EVENTOUT
WKUP2,
TAMP_IN8/
TAMP_
OUT7
WKUP3,
TAMP_IN3/
TAMP_
OUT6
-
-
D16
5
C2
5
E4
-
-
5
C2
5
E4
PE6
I/O
FT_ht
-
TRACED3, TIM3_CH4, SAI1_D1,
DCMI_D7/PSSI_D7, FMC_A22,
SAI1_SD_A, EVENTOUT
1
1
C17
6
B1
6
C1
1
1
6
B1
6
C1
VBAT
S
-
-
-
-
-
-
-
-
-
-
F2
-
-
-
-
-
F2
VSS
S
-
-
-
-
107/334
Pinout, pin description and alternate functions
DS13086 Rev 6
-
-
Pin name
(function after
reset)
Notes
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1)
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
DS13086 Rev 6
Alternate functions
Additional
functions
EVENTOUT
WKUP2,
RTC_TS/
RTC_OUT1,
TAMP_IN1/
TAMP_
OUT2
EVENTOUT
OSC32_IN
(3)
EVENTOUT
OSC32_
OUT
(2)
2
E15
7
C3
7
E3
2
2
7
C3
7
E3
PC13
I/O
FT
3
3
D18
8
C1
8
D1
3
3
8
C1
8
D1
PC14OSC32_IN
(PC14)
I/O
FT
4
4
E17
9
D1
9
E1
4
4
9
D1
9
E1
PC15OSC32_OUT
(PC15)
I/O
FT
-
-
-
-
D2
10
E2
-
-
-
D2
10
E2
PF0
I/O
FT_fh
-
I2C2_SDA, OCTOSPIM_P2_IO0,
FMC_A0, EVENTOUT
-
-
-
-
-
E2
11
F3
-
-
-
E2
11
F3
PF1
I/O
FT_fh
-
I2C2_SCL, OCTOSPIM_P2_IO1,
FMC_A1, EVENTOUT
-
-
-
-
-
E1
12
F4
-
-
-
E1
12
F4
PF2
I/O
FT_h
-
LPTIM3_CH2, I2C2_SMBA,
OCTOSPIM_P2_IO2, FMC_A2,
EVENTOUT
WKUP8
-
-
-
-
D3
13
G5
-
-
-
D3
13
G5
PF3
I/O
FT_h
-
LPTIM3_IN1, OCTOSPIM_P2_IO3,
FMC_A3, EVENTOUT
-
-
-
-
-
E3
14
G6
-
-
-
E3
14
G6
PF4
I/O FT_hv
-
LPTIM3_ETR,
OCTOSPIM_P2_CLK, FMC_A4,
EVENTOUT
-
-
-
-
-
F2
15
G4
-
-
-
F2
15
G4
PF5
I/O FT_hv
-
LPTIM3_CH1,
OCTOSPIM_P2_NCLK, FMC_A5,
EVENTOUT
-
(3)
(2)
(3)
(2)
STM32U585xx
2
Pinout, pin description and alternate functions
108/334
Table 27. STM32U585xx pin definitions(1) (continued)
LQFP48 SMPS
UFQFPN48 SMPS
LQFP64 SMPS
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin number
Alternate functions
-
-
-
10
F6
16
H2
-
-
10
F6
16
H2
VSS
S
-
-
-
-
-
-
-
11
F7
17
G1
-
-
11
F7
17
G1
VDD
S
-
-
-
-
-
Additional
functions
109/334
-
-
-
-
18
H6
-
-
-
-
18
H6
PF6
I/O
FT_h
-
-
-
-
-
-
19
G2
-
-
-
-
19
G2
PF7
I/O
FT_h
-
TIM5_CH2, FDCAN1_RX,
OCTOSPIM_P1_IO2,
SAI1_MCLK_B, EVENTOUT
-
-
-
-
-
-
20
F1
-
-
-
-
20
F1
PF8
I/O
FT_h
-
TIM5_CH3, PSSI_D14,
FDCAN1_TX, OCTOSPIM_P1_IO0,
SAI1_SCK_B, EVENTOUT
-
-
-
-
-
-
21
G3
-
-
-
-
21
G3
PF9
I/O
FT_h
-
TIM5_CH4, PSSI_D15,
OCTOSPIM_P1_IO1, SAI1_FS_B,
TIM15_CH1, EVENTOUT
-
I/O FT_hv
-
OCTOSPIM_P1_CLK, PSSI_D15,
MDF1_CCK1,
DCMI_D11/PSSI_D11, SAI1_D3,
TIM15_CH2, EVENTOUT
-
I/O
FT
-
EVENTOUT
OSC_IN
PH1-OSC_OUT
I/O
(PH1)
FT
-
EVENTOUT
OSC_OUT
RST
-
-
-
-
-
-
-
-
22
H4
-
-
-
-
22
H4
PF10
5
5
F18
12
F1
23
H1
5
5
12
F1
23
H1
PH0-OSC_IN
(PH0)
6
6
F16
13
G1
24
J1
6
6
13
G1
24
J1
7
7
G17
14
G2
25
H3
7
7
14
G2
25
H3
NRST
I/O
Pinout, pin description and alternate functions
DS13086 Rev 6
-
TIM5_ETR, TIM5_CH1,
DCMI_D12/PSSI_D12,
OCTOSPIM_P2_NCS,
OCTOSPIM_P1_IO3, SAI1_SD_B,
EVENTOUT
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
8
15
H2
26
J2
-
8
15
H2
26
J2
PC0
I/O
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
F14
Pin name
(function after
reset)
FT_
fha
DS13086 Rev 6
FT_
fhav
-
9
G15
16
G3
27
J3
-
9
16
G3
27
J3
PC1
I/O
-
10
F12
17
F3
28
J4
-
10
17
F3
28
J4
PC2
I/O FT_ha
I/O FT_ha
Notes
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Alternate functions
Additional
functions
-
LPTIM1_IN1, OCTOSPIM_P1_IO7,
I2C3_SCL(boot), SPI2_RDY,
MDF1_SDI4, LPUART1_RX,
SDMMC1_D5, SAI2_FS_A,
LPTIM2_IN1, EVENTOUT
ADC1_IN1,
ADC4_IN1
-
TRACED0, LPTIM1_CH1,
SPI2_MOSI, I2C3_SDA(boot),
MDF1_CKI4, LPUART1_TX,
OCTOSPIM_P1_IO4,
SDMMC2_CK, SAI1_SD_A,
EVENTOUT
ADC1_IN2,
ADC4_IN2
-
LPTIM1_IN2, SPI2_MISO,
MDF1_CCK1, OCTOSPIM_P1_IO5,
LPGPIO1_P5, EVENTOUT
ADC1_IN3,
ADC4_IN3
-
LPTIM1_ETR, LPTIM3_CH1,
SAI1_D1, SPI2_MOSI,
OCTOSPIM_P1_IO6, SAI1_SD_A,
LPTIM2_ETR, EVENTOUT
ADC1_IN4,
ADC4_IN4
11
G13
18
F4
29
K1
-
11
18
F4
29
K1
PC3
8
12
H18
19
H1
30
K2
8
12
19
H1
30
K2
VSSA
S
-
-
-
-
-
-
-
-
-
-
-
-
-
20
-
31
-
VREF-
S
-
-
-
-
-
-
H16
20
J1
31
L1
-
-
21
J1
32
L1
VREF+
S
-
-
-
VREFBUF_
OUT
9
13
J17
21
K1
32
L2
9
13
22
K1
33
L2
VDDA
S
-
-
-
-
STM32U585xx
-
Pinout, pin description and alternate functions
110/334
Table 27. STM32U585xx pin definitions(1) (continued)
G11
22
J2
33
K3
10
14
23
J2
34
K3
PA0
I/O
FT_
hat
-
-
-
-
-
H3
-
M1
-
-
-
H3
-
M1
OPAMP1_
VINM
I
TT
-
-
-
-
LPTIM1_CH2, TIM2_CH2,
TIM5_CH2, I2C1_SMBA,
SPI1_SCK, USART2_RTS_DE,
UART4_RX, OCTOSPIM_P1_DQS,
LPGPIO1_P0, TIM15_CH1N,
EVENTOUT
OPAMP1_
VINM,
ADC1_IN6,
WKUP3,
TAMP_IN5/
TAMP_
OUT4
-
TIM2_CH3, TIM5_CH3, SPI1_RDY,
USART2_TX(boot), LPUART1_TX,
OCTOSPIM_P1_NCS,
UCPD1_FRSTX1, TIM15_CH1,
EVENTOUT
COMP1_
INP3,
ADC1_IN7,
WKUP4/
LSCO
-
TIM2_CH4, TIM5_CH4, SAI1_CK1,
USART2_RX(boot), LPUART1_RX,
OCTOSPIM_P1_CLK,
LPGPIO1_P1, SAI1_MCLK_A,
TIM15_CH2, EVENTOUT
OPAMP1_
VOUT,
ADC1_IN8,
WKUP5
11
12
15
16
J13
J15
23
24
G4
K2
34
35
L3
M2
11
12
15
16
24
25
G4
K2
LQFP144
14
LQFP100
10
TIM2_CH1, TIM5_CH1, TIM8_ETR,
SPI3_RDY, USART2_CTS,
UART4_TX, OCTOSPIM_P2_NCS,
SDMMC2_CMD, AUDIOCLK,
TIM2_ETR, EVENTOUT
LQFP64
Alternate functions
35
36
L3
M2
PA1
PA2
I/O
FT_
hat
I/O FT_ha
Additional
functions
OPAMP1_
VINP,
ADC1_IN5,
WKUP1,
TAMP_IN2/
TAMP_
OUT1
111/334
13
17
H10
25
L1
36
N2
13
17
26
L1
37
N2
PA3
I/O
TT_
hav
-
18
K18
26
G7
37
M3
-
18
27
G7
38
M3
VSS
S
-
-
-
-
-
19
K16
27
G6
38
N3
-
19
28
G6
39
N3
VDD
S
-
-
-
-
Pinout, pin description and alternate functions
DS13086 Rev 6
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA169
UFBGA132
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
DS13086 Rev 6
15
20
21
H12
28
29
L3
M1
39
40
N1
K4
14
15
20
21
29
30
L3
M1
40
41
N1
K4
PA4
PA5
16
22
F10
30
L2
41
N4
16
22
31
L2
42
N4
PA6
-
-
-
-
M2
-
H5
-
-
-
M2
-
H5
OPAMP2_VINM
17
23
K14
31
K3
42
J5
17
23
32
K3
43
J5
PA7
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
H14
Pin name
(function after
reset)
I/O TT_ha
I/O
TT_a
I/O FT_ha
I
I/O
TT
Alternate functions
Additional
functions
-
OCTOSPIM_P1_NCS,
SPI1_NSS(boot), SPI3_NSS,
USART2_CK,
DCMI_HSYNC/PSSI_DE,
SAI1_FS_B, LPTIM2_CH1,
EVENTOUT
ADC1_IN9,
ADC4_IN9,
DAC1_
OUT1,
WKUP2
-
CSLEEP, TIM2_CH1, TIM2_ETR,
TIM8_CH1N, PSSI_D14,
SPI1_SCK(boot), USART3_RX,
LPTIM2_ETR, EVENTOUT
ADC1_IN10,
ADC4_IN10,
DAC1_
OUT2,
WKUP6
-
CDSTOP, TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
DCMI_PIXCLK/PSSI_PDCK,
SPI1_MISO(boot), USART3_CTS,
LPUART1_CTS,
OCTOSPIM_P1_IO3,
LPGPIO1_P2, TIM16_CH1,
EVENTOUT
OPAMP2_
VINP,
ADC1_IN11,
ADC4_IN11,
WKUP7
-
-
-
-
SRDSTOP, TIM1_CH1N,
OPAMP2_
TIM3_CH2, TIM8_CH1N,
VINM,
I2C3_SCL, SPI1_MOSI(boot),
ADC1_IN12,
USART3_TX, OCTOSPIM_P1_IO2,
ADC4_IN20,
LPTIM2_CH2, TIM17_CH1,
WKUP8
EVENTOUT
STM32U585xx
FT_
fha
Notes
14
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Pinout, pin description and alternate functions
112/334
Table 27. STM32U585xx pin definitions(1) (continued)
-
18
19
-
-
24
25
G9
K12
J11
-
-
32
33
M3
J3
M4
L4
-
-
43
44
L4
M4
K5
N5
-
-
18
19
24
25
26
27
33
34
35
36
M3
J3
M4
L4
44
45
46
47
L4
M4
K5
N5
PC4
PC5
PB0
PB1
I/O FT_ha
I/O
FT_at
I/O TT_ha
I/O FT_ha
Notes
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
-
Pin name
(function after
reset)
Alternate functions
Additional
functions
-
COMP1_
INM2,
USART3_TX, OCTOSPIM_P1_IO7,
ADC1_IN13,
EVENTOUT
ADC4_IN22
-
COMP1_
INP1,
ADC1_IN14,
TIM1_CH4N, SAI1_D3, PSSI_D15, ADC4_IN23,
WKUP5,
USART3_RX, EVENTOUT
TAMP_IN4/
TAMP_
OUT5
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LPTIM3_CH1,
SPI1_NSS, USART3_CK,
OCTOSPIM_P1_IO1,
LPGPIO1_P9, COMP1_OUT,
AUDIOCLK, EVENTOUT
OPAMP2_
VOUT,
ADC1_IN15,
ADC4_IN18
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LPTIM3_CH2,
MDF1_SDI0, USART3_RTS_DE,
LPUART1_RTS_DE,
OCTOSPIM_P1_IO0,
LPGPIO1_P3, LPTIM2_IN1,
EVENTOUT
COMP1_
INM1,
ADC1_IN16,
ADC4_IN19,
WKUP4
113/334
Pinout, pin description and alternate functions
DS13086 Rev 6
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
FT_
hat
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Alternate functions
Additional
functions
-
LPTIM1_CH1, TIM8_CH4N,
I2C3_SMBA, SPI1_RDY,
MDF1_CKI0,
OCTOSPIM_P1_DQS,
UCPD1_FRSTX1, EVENTOUT
COMP1_
INP2,
ADC1_IN17,
WKUP1,
RTC_OUT2
DS13086 Rev 6
26
K10
34
K4
45
L5
20
28
37
K4
48
L5
PB2
I/O
-
-
-
-
K5
46
M5
-
-
-
K5
49
M5
PF11
I/O FT_hv
-
OCTOSPIM_P1_NCLK,
DCMI_D12/PSSI_D12,
LPTIM4_IN1, EVENTOUT
-
-
-
-
-
L5
47
K6
-
-
-
L5
50
K6
PF12
I/O
FT_h
-
OCTOSPIM_P2_DQS, FMC_A6,
LPTIM4_ETR, EVENTOUT
-
-
-
-
-
-
48
M7
-
-
-
-
51
M7
VSS
S
-
-
-
-
-
-
-
-
-
49
N7
-
-
-
-
52
N7
VDD
S
-
-
-
-
-
-
-
-
M5
50
M6
-
-
-
M5
53
M6
PF13
I/O
FT_h
-
I2C4_SMBA, UCPD1_FRSTX2,
FMC_A7, LPTIM4_OUT,
EVENTOUT
-
-
-
-
-
J5
51
L6
-
-
-
J5
54
L6
PF14
I/O
FT_
fha
-
I2C4_SCL, TSC_G8_IO1, FMC_A8,
EVENTOUT
ADC4_IN5
-
-
-
-
L6
52
N6
-
-
-
L6
55
N6
PF15
I/O
FT_
fha
-
I2C4_SDA, TSC_G8_IO2,
FMC_A9, EVENTOUT
ADC4_IN6
-
-
-
-
M6
53
J6
-
-
-
M6
56
J6
PG0
I/O FT_ha
-
OCTOSPIM_P2_IO4,
TSC_G8_IO3, FMC_A10,
EVENTOUT
ADC4_IN7
-
-
-
-
K6
54
H7
-
-
-
K6
57
H7
PG1
I/O FT_ha
-
OCTOSPIM_P2_IO5,
TSC_G8_IO4, FMC_A11,
EVENTOUT
ADC4_IN8
STM32U585xx
-
Pinout, pin description and alternate functions
114/334
Table 27. STM32U585xx pin definitions(1) (continued)
LQFP64 SMPS
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
H8
35
K7
55
L7
-
-
38
K7
58
L7
PE7
I/O
FT_h
-
TIM1_ETR, MDF1_SDI2, FMC_D4,
SAI1_SD_B, EVENTOUT
WKUP6
-
-
J9
36
J6
56
K7
-
-
39
J6
59
K7
PE8
I/O
FT_h
-
TIM1_CH1N, MDF1_CKI2,
FMC_D5, SAI1_SCK_B,
EVENTOUT
WKUP7
-
TIM1_CH1, ADF1_CCK0,
MDF1_CCK0,
OCTOSPIM_P1_NCLK, FMC_D6,
SAI1_FS_B, EVENTOUT
-
I/O FT_hv
Additional
functions
115/334
-
-
K8
37
M7
57
J7
-
-
40
M7
60
J7
PE9
-
-
-
-
-
58
-
-
-
-
-
61
-
VSS
S
-
-
-
-
-
-
-
-
J4
59
-
-
-
-
J4
62
-
VDD
S
-
-
-
-
-
-
J7
38
J7
60
H8
-
-
41
J7
63
H8
PE10
I/O
FT_
hav
-
TIM1_CH2N, ADF1_SDI0,
MDF1_SDI4, TSC_G5_IO1,
OCTOSPIM_P1_CLK, FMC_D7,
SAI1_MCLK_B, EVENTOUT
-
-
-
-
39
L7
61
M8
-
-
42
L7
64
M8
PE11
I/O FT_ha
-
TIM1_CH2, SPI1_RDY,
MDF1_CKI4, TSC_G5_IO2,
OCTOSPIM_P1_NCS, FMC_D8,
EVENTOUT
-
-
-
-
40
J8
62
N8
-
-
43
J8
65
N8
PE12
I/O FT_ha
-
TIM1_CH3N, SPI1_NSS,
MDF1_SDI5, TSC_G5_IO3,
OCTOSPIM_P1_IO0, FMC_D9,
EVENTOUT
-
-
-
-
41
M8
63
L8
-
-
44
M8
66
L8
PE13
I/O FT_ha
-
TIM1_CH3, SPI1_SCK,
MDF1_CKI5, TSC_G5_IO4,
OCTOSPIM_P1_IO1, FMC_D10,
EVENTOUT
-
Pinout, pin description and alternate functions
DS13086 Rev 6
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
LQFP64 SMPS
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Pin name
(function after
reset)
Pin type
I/O structure
Notes
DS13086 Rev 6
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Alternate functions
-
-
-
42
K8
64
K8
-
-
45
K8
67
K8
PE14
I/O
FT_h
-
TIM1_CH4, TIM1_BKIN2,
SPI1_MISO, OCTOSPIM_P1_IO2,
FMC_D11, EVENTOUT
-
-
-
-
43
L8
65
M9
-
-
46
L8
68
M9
PE15
I/O
FT_h
-
TIM1_BKIN, TIM1_CH4N,
SPI1_MOSI, OCTOSPIM_P1_IO3,
FMC_D12, EVENTOUT
-
-
TIM2_CH3, LPTIM3_CH1,
I2C4_SCL, I2C2_SCL(boot),
SPI2_SCK, USART3_TX,
LPUART1_RX, TSC_SYNC,
OCTOSPIM_P1_CLK,
LPGPIO1_P4, COMP1_OUT,
SAI1_SCK_A, EVENTOUT
WKUP8
-
-
27
H6
44
K9
66
K9
21
29
47
K9
69
K9
PB10
I/O
FT_
fhv
Additional
functions
-
-
45
L9
67
L9
-
-
-
L9
-
L9
PB11
I/O
FT_fh
-
20
28
K6
46
M10
68
N9
-
-
-
-
-
-
VLXSMPS
S
-
-
-
-
21
29
K4
47
M9
69
N10
-
-
-
-
-
-
VDDSMPS
S
-
-
-
-
22
30
J5
48
L10
70
M10
-
-
-
-
-
-
VSSSMPS
S
-
-
-
-
-
-
-
-
-
-
-
22
30
48
L10
70
N11
VCAP
S
-
-
-
-
23
31
K2
49
M11
71
N11
-
-
-
-
-
-
VDD11
S
-
-
-
-
24
32
J3
50
E9
72
M11
23
31
49
E9
71
M11
VSS
S
-
-
-
-
25
33
J1
51
D4
73
N12
24
32
50
D4
72
N12
VDD
S
-
-
-
-
STM32U585xx
-
TIM2_CH4, I2C4_SDA,
I2C2_SDA(boot), SPI2_RDY,
USART3_RX, LPUART1_TX,
OCTOSPIM_P1_NCS,
COMP2_OUT, EVENTOUT
Pinout, pin description and alternate functions
116/334
Table 27. STM32U585xx pin definitions(1) (continued)
27
34
35
H2
H4
-
52
53
L11
K10
K11
-
74
75
L10
N13
M12
25
26
27
33
34
35
51
52
53
L11
K10
K11
73
74
75
L10
N13
M12
PB12
PB13
PB14
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
-
FT_
hav
FT_f
FT_fd
Alternate functions
Additional
functions
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS(boot), MDF1_SDI1,
USART3_CK, LPUART1_RTS_DE,
TSC_G1_IO1,
OCTOSPIM_P1_NCLK,
SAI2_FS_A, TIM15_BKIN,
EVENTOUT
-
-
TIM1_CH1N, LPTIM3_IN1,
I2C2_SCL, SPI2_SCK(boot),
MDF1_CKI1, USART3_CTS,
LPUART1_CTS, TSC_G1_IO2,
SAI2_SCK_A, TIM15_CH1N,
EVENTOUT
-
-
TIM1_CH2N, LPTIM3_ETR,
TIM8_CH2N, I2C2_SDA,
SPI2_MISO(boot), MDF1_SDI2,
USART3_RTS_DE, TSC_G1_IO3,
SDMMC2_D0, SAI2_MCLK_A,
TIM15_CH1, EVENTOUT
UCPD1_
DBCC2
UCPD1_
CC2,
WKUP7
-
117/334
28
36
G5
54
K12
76
L11
28
36
54
K12
76
L11
PB15
I/O
FT_c
(4)
RTC_REFIN, TIM1_CH3N,
LPTIM2_IN2, TIM8_CH3N,
SPI2_MOSI(boot), MDF1_CKI2,
FMC_NBL1, SDMMC2_D1,
SAI2_SD_A, TIM15_CH2,
EVENTOUT
-
-
-
55
L12
77
L12
-
-
55
L12
77
L12
PD8
I/O
FT_h
-
USART3_TX,
DCMI_HSYNC/PSSI_DE,
FMC_D13, EVENTOUT
Pinout, pin description and alternate functions
DS13086 Rev 6
26
-
Pin name
(function after
reset)
Notes
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
-
DS13086 Rev 6
-
-
-
-
-
-
-
-
-
56
57
58
59
J10
M12
J11
J12
78
79
80
81
L13
K11
M13
K10
-
-
-
-
-
-
-
-
56
57
58
59
J10
M12
J11
J12
78
79
80
81
L13
K11
M13
K10
PD9
PD10
PD11
PD12
I/O
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
-
Pin name
(function after
reset)
FT_h
I/O FT_ha
I/O FT_ha
Notes
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Alternate functions
Additional
functions
-
LPTIM2_IN2, USART3_RX,
DCMI_PIXCLK/PSSI_PDCK,
FMC_D14, SAI2_MCLK_A,
LPTIM3_IN1, EVENTOUT
-
-
LPTIM2_CH2, USART3_CK,
TSC_G6_IO1, FMC_D15,
SAI2_SCK_A, LPTIM3_ETR,
EVENTOUT
-
-
I2C4_SMBA, USART3_CTS,
TSC_G6_IO2,
FMC_CLE/FMC_A16, SAI2_SD_A,
LPTIM2_ETR, EVENTOUT
ADC4_IN15
-
TIM4_CH1, I2C4_SCL,
USART3_RTS_DE, TSC_G6_IO3,
FMC_ALE/FMC_A17, SAI2_FS_A,
LPTIM2_IN1, EVENTOUT
ADC4_IN16
ADC4_IN17
I/O
FT_
fha
-
TIM4_CH2, I2C4_SDA,
TSC_G6_IO4, LPGPIO1_P6,
FMC_A18, LPTIM4_IN1,
LPTIM2_CH1, EVENTOUT
-
-
60
H11
82
K12
-
-
60
H11
82
K12
PD13
I/O
-
-
-
-
-
83
J12
-
-
-
-
83
J12
VSS
S
-
-
-
-
-
-
-
-
-
84
J13
-
-
-
-
84
J13
VDD
S
-
-
-
-
-
-
G1
61
H10
85
J10
-
-
61
H10
85
J10
PD14
I/O
FT_h
-
TIM4_CH3, FMC_D0,
LPTIM3_CH1, EVENTOUT
-
-
-
G3
62
H12
86
J11
-
-
62
H12
86
J11
PD15
I/O
FT_h
-
TIM4_CH4, FMC_D1,
LPTIM3_CH2, EVENTOUT
-
STM32U585xx
-
FT_
fha
Pinout, pin description and alternate functions
118/334
Table 27. STM32U585xx pin definitions(1) (continued)
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Notes
Alternate functions
-
-
-
-
G10
87
K13
-
-
-
G10
87
K13
PG2
I/O FT_hs
-
SPI1_SCK, FMC_A12,
SAI2_SCK_B, EVENTOUT
-
-
-
-
-
G11
88
J8
-
-
-
G11
88
J8
PG3
I/O FT_hs
-
SPI1_MISO, FMC_A13,
SAI2_FS_B, EVENTOUT
-
-
-
-
-
G9
89
H11
-
-
-
G9
89
H11
PG4
I/O FT_hs
-
SPI1_MOSI, FMC_A14,
SAI2_MCLK_B, EVENTOUT
-
-
-
-
-
G12
90
J9
-
-
-
G12
90
J9
PG5
I/O FT_hs
-
SPI1_NSS, LPUART1_CTS,
FMC_A15, SAI2_SD_B,
EVENTOUT
-
-
OCTOSPIM_P1_DQS,
I2C3_SMBA, SPI1_RDY,
LPUART1_RTS_DE,
UCPD1_FRSTX1, EVENTOUT
-
-
-
-
-
-
F9
91
H10
-
-
-
F9
91
H10
PG6
Pin type
LQFP64 SMPS
Pin name
(function after
reset)
I/O FT_hs
Additional
functions
119/334
-
-
-
-
F10
92
G8
-
-
-
F10
92
G8
PG7
I/O FT_fhs
-
SAI1_CK1, I2C3_SCL,
OCTOSPIM_P2_DQS,
MDF1_CCK0, LPUART1_TX,
UCPD1_FRSTX2, FMC_INT,
SAI1_MCLK_A, EVENTOUT
-
-
-
-
F12
93
H9
-
-
-
F12
93
H9
PG8
I/O
FT_fs
-
I2C3_SDA, LPUART1_RX,
EVENTOUT
-
-
-
-
-
-
94
-
-
-
-
-
94
-
VSS
S
-
-
-
-
-
-
-
-
-
95
H12
-
-
-
-
95
H12
VDDIO2
S
-
-
-
-
-
CSLEEP, TIM3_CH1, TIM8_CH1,
MDF1_CKI3, SDMMC1_D0DIR,
TSC_G4_IO1, DCMI_D0/PSSI_D0,
SDMMC2_D6, SDMMC1_D6,
SAI2_MCLK_A, EVENTOUT
-
-
37
G7
63
F11
96
H13
-
37
63
F11
96
H13
PC6
I/O
FT_a
Pinout, pin description and alternate functions
DS13086 Rev 6
LQFP48 SMPS
UFQFPN48 SMPS
I/O structure
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
DS13086 Rev 6
-
-
29
30
38
39
40
41
42
F2
F6
F8
E11
64
65
66
67
68
E10
E12
E11
97
98
99
D12 100
G12
G10
G9
G7
D10 101 G11
-
-
-
29
30
38
39
40
41
42
64
65
66
67
68
E10
E12
E11
97
98
99
D12 100
G12
G10
G9
G7
D10 101 G11
PC7
PC8
PC9
PA8
PA9
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
F4
Pin name
(function after
reset)
FT_a
FT_a
FT_a
I/O FT_hv
I/O
FT_u
Alternate functions
Additional
functions
-
CDSTOP, TIM3_CH2, TIM8_CH2,
MDF1_SDI3, SDMMC1_D123DIR,
TSC_G4_IO2, DCMI_D1/PSSI_D1,
SDMMC2_D7, SDMMC1_D7,
SAI2_MCLK_B, LPTIM2_CH2,
EVENTOUT
-
-
SRDSTOP, TIM3_CH3, TIM8_CH3,
TSC_G4_IO3, DCMI_D2/PSSI_D2,
SDMMC1_D0, LPTIM3_CH1,
EVENTOUT
-
-
TRACED0, TIM8_BKIN2,
TIM3_CH4, TIM8_CH4,
DCMI_D3/PSSI_D3, TSC_G4_IO4,
OTG_FS_NOE, SDMMC1_D1,
LPTIM3_CH2, EVENTOUT
-
-
MCO, TIM1_CH1, SAI1_CK2,
SPI1_RDY, USART1_CK,
OTG_FS_SOF, TRACECLK,
SAI1_SCK_A, LPTIM2_CH1,
EVENTOUT
-
-
TIM1_CH2, SPI2_SCK,
DCMI_D0/PSSI_D0,
USART1_TX(boot), SAI1_FS_A,
TIM15_BKIN, EVENTOUT
OTG_FS_
VBUS
STM32U585xx
Notes
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Pinout, pin description and alternate functions
120/334
Table 27. STM32U585xx pin definitions(1) (continued)
44
E3
69
70
D11 102 F11
C12 103 G13
31
32
43
44
69
70
D11 102 F11
C12 103 G13
PA10
PA11
I/O
I/O
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
E1
FT_u
FT_u
Alternate functions
Additional
functions
-
CRS_SYNC, TIM1_CH3,
LPTIM2_IN2, SAI1_D1,
DCMI_D1/PSSI_D1,
USART1_RX(boot), OTG_FS_ID,
SAI1_SD_A, TIM17_BKIN,
EVENTOUT
-
-
TIM1_CH4, TIM1_BKIN2,
SPI1_MISO, USART1_CTS,
FDCAN1_RX, OTG_FS_DM(boot),
EVENTOUT
-
-
33
45
D2
71
B12 104 F13
33
45
71
B12 104 F13
PA12
I/O
FT_u
-
TIM1_ETR, SPI1_MOSI,
OCTOSPIM_P2_NCS,
USART1_RTS_DE, FDCAN1_TX,
OTG_FS_DP(boot), EVENTOUT
34
46
D4
72
C10 105 F12
34
46
72
C10 105 F12
PA13 (JTMS/
SWDIO)
I/O
FT
(5)
JTMS/SWDIO, IR_OUT,
OTG_FS_NOE, SAI1_SD_B,
EVENTOUT
-
-
47
-
-
-
47
-
VSS
S
-
-
-
-
-
48
C1
73
A12 106 E13
-
48
73
A12 106 E13
VDDUSB
S
-
-
-
-
35
-
B2
74
H4
107 E12
35
-
74
H4
107 E12
VSS
S
-
-
-
-
36
-
A1
75
D9
108 D13
36
-
75
D9
108 D13
VDD
S
-
-
-
-
FT
(5)
JTCK/SWCLK, LPTIM1_CH1,
I2C1_SMBA, I2C4_SMBA,
OTG_FS_SOF, SAI1_FS_B,
EVENTOUT
-
37
49
C3
76
-
-
-
C11 109 C10
37
49
76
-
-
-
C11 109 C10
PA14 (JTCK/
SWCLK)
I/O
121/334
Pinout, pin description and alternate functions
DS13086 Rev 6
32
43
Pin name
(function after
reset)
Notes
31
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
38
DS13086 Rev 6
-
-
50
51
52
E5
E7
A3
77
78
79
A11
B11
110 A10
111
A10 112
C9
A9
38
-
-
50
51
52
77
78
79
A11
B11
110 A10
111
A10 112
C9
A9
PA15 (JTDI)
PC10
PC11
I/O
I/O
FT_c
FT_a
I/O FT_ha
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Alternate functions
Additional
functions
(5)
JTDI, TIM2_CH1, TIM2_ETR,
USART2_RX, SPI1_NSS,
SPI3_NSS, USART3_RTS_DE,
UART4_RTS_DE, SAI2_FS_B,
EVENTOUT
UCPD1_
CC1
-
TRACED1, LPTIM3_ETR,
ADF1_CCK1, SPI3_SCK,
USART3_TX(boot), UART4_TX,
TSC_G3_IO2, DCMI_D8/PSSI_D8,
LPGPIO1_P8, SDMMC1_D2,
SAI2_SCK_B, EVENTOUT
-
-
LPTIM3_IN1, ADF1_SDI0,
DCMI_D2/PSSI_D2,
OCTOSPIM_P1_NCS, SPI3_MISO,
USART3_RX(boot), UART4_RX,
TSC_G3_IO3, DCMI_D4/PSSI_D4,
UCPD1_FRSTX2, SDMMC1_D3,
SAI2_MCLK_B, EVENTOUT
-
-
(4)
53
B4
80
B10 113
E8
-
53
80
B10 113
E8
PC12
I/O
FT_
hav
-
-
-
C5
81
C9
114
B9
-
-
81
C9
114
B9
PD0
I/O
FT_h
-
TIM8_CH4N, SPI2_NSS,
FDCAN1_RX, FMC_D2,
EVENTOUT
-
-
-
D6
82
B9
115
F6
-
-
82
B9
115
F6
PD1
I/O
FT_h
-
SPI2_SCK, FDCAN1_TX, FMC_D3,
EVENTOUT
-
STM32U585xx
-
TRACED3, SPI3_MOSI,
USART3_CK, UART5_TX,
TSC_G3_IO4, DCMI_D9/PSSI_D9,
LPGPIO1_P10, SDMMC1_CK,
SAI2_SD_B, EVENTOUT
Pinout, pin description and alternate functions
122/334
Table 27. STM32U585xx pin definitions(1) (continued)
-
-
83
84
A9
C8
116
117
F7
D8
-
-
54
-
83
84
A9
C8
116
117
F7
D8
PD2
PD3
I/O
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
A5
FT
I/O FT_hv
Alternate functions
Additional
functions
-
TRACED2, TIM3_ETR,
USART3_RTS_DE, UART5_RX,
TSC_SYNC, DCMI_D11/PSSI_D11,
LPGPIO1_P7, SDMMC1_CMD,
LPTIM4_ETR, EVENTOUT
-
-
SPI2_SCK, DCMI_D5/PSSI_D5,
SPI2_MISO, MDF1_SDI0,
USART2_CTS,
OCTOSPIM_P2_NCS, FMC_CLK,
EVENTOUT
-
-
-
-
D8
85
B8
118
C8
-
-
85
B8
118
C8
PD4
I/O
FT_h
-
SPI2_MOSI, MDF1_CKI0,
USART2_RTS_DE,
OCTOSPIM_P1_IO4, FMC_NOE,
EVENTOUT
-
-
B6
86
A8
119
E7
-
-
86
A8
119
E7
PD5
I/O
FT_h
-
SPI2_RDY, USART2_TX,
OCTOSPIM_P1_IO5, FMC_NWE,
EVENTOUT
-
-
-
-
-
-
120
B8
-
-
-
-
120
B8
VSS
S
-
-
-
-
-
-
-
-
-
121
A8
-
-
-
-
121
A8
VDD
S
-
-
-
-
-
SAI1_D1, DCMI_D10/PSSI_D10,
SPI3_MOSI, MDF1_SDI1,
USART2_RX, OCTOSPIM_P1_IO6,
SDMMC2_CK, FMC_NWAIT,
SAI1_SD_A, EVENTOUT
-
-
-
-
87
A7
122
B7
-
-
87
A7
122
B7
PD6
I/O FT_hv
123/334
Pinout, pin description and alternate functions
DS13086 Rev 6
-
54
Pin name
(function after
reset)
Notes
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
DS13086 Rev 6
-
-
-
-
-
-
-
C7
A7
E9
88
-
-
-
D7
B7
C7
-
123
124
125
-
D7
A7
C7
-
-
-
-
-
-
-
-
-
88
-
-
-
-
B8
-
A6
126
E6
-
-
-
-
-
C9
-
-
127
-
-
-
-
-
-
A9
-
-
128
-
-
-
-
D7
B7
C7
124
125
D7
A7
C7
M11 126 M10
PD7
PG9
PG10
PG11
I/O
I/O structure
Pin type
UFBGA169
LQFP144
123
FT_h
I/O FT_hs
I/O FT_hs
I/O FT_hs
Alternate functions
Additional
functions
-
MDF1_CKI1, USART2_CK,
OCTOSPIM_P1_IO7,
SDMMC2_CMD,
FMC_NCE/FMC_NE1,
LPTIM4_OUT, EVENTOUT
-
-
OCTOSPIM_P2_IO6,
SPI3_SCK(boot), USART1_TX,
FMC_NCE/FMC_NE2,
SAI2_SCK_A, TIM15_CH1N,
EVENTOUT
-
-
LPTIM1_IN1, OCTOSPIM_P2_IO7,
SPI3_MISO(boot), USART1_RX,
FMC_NE3, SAI2_FS_A,
TIM15_CH1, EVENTOUT
-
-
LPTIM1_IN2, OCTOSPIM_P1_IO5,
SPI3_MOSI, USART1_CTS,
SAI2_MCLK_A, TIM15_CH2,
EVENTOUT
-
-
PG12
I/O FT_hs
-
LPTIM1_ETR,
OCTOSPIM_P2_NCS,
SPI3_NSS(boot),
USART1_RTS_DE, FMC_NE4,
SAI2_SD_A, EVENTOUT
M10 128 N10
PG13
I/O FT_fhs
-
I2C1_SDA, SPI3_RDY,
USART1_CK, FMC_A24,
EVENTOUT
-
M9
PG14
I/O FT_fhs
-
LPTIM1_CH2, I2C1_SCL,
FMC_A25, EVENTOUT
-
A6
127
129
E6
N9
STM32U585xx
-
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
-
Pin name
(function after
reset)
Notes
-
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Pinout, pin description and alternate functions
124/334
Table 27. STM32U585xx pin definitions(1) (continued)
LQFP64 SMPS
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
B10
-
H9
129
-
-
-
-
H9
130
-
VSS
S
-
-
-
-
-
-
A11
-
D8
130
A6
-
-
-
D8
131
A6
VDDIO2
S
-
-
-
-
-
-
-
-
-
131
A5
-
-
-
B4
132
A5
PG15
-
LPTIM1_CH1, I2C1_SMBA,
OCTOSPIM_P2_DQS,
DCMI_D13/PSSI_D13, EVENTOUT
-
-
JTDO/TRACESWO, TIM2_CH2,
LPTIM1_CH1, ADF1_CCK0,
I2C1_SDA, SPI1_SCK, SPI3_SCK,
USART1_RTS_DE, CRS_SYNC,
LPGPIO1_P11, SDMMC2_D2,
SAI1_SCK_B, EVENTOUT
COMP2_
INM2
NJTRST, LPTIM1_CH2, TIM3_CH1,
ADF1_SDI0, I2C3_SDA,
SPI1_MISO, SPI3_MISO,
USART1_CTS, UART5_RTS_DE,
(5)
TSC_G2_IO1,
DCMI_D12/PSSI_D12,
LPGPIO1_P12, SDMMC2_D3,
SAI1_MCLK_B, TIM17_BKIN,
EVENTOUT
COMP2_
INP1
39
40
41
55
56
57
D10
C11
D12
89
90
91
C6
B6
D6
132
133
134
D6
B6
C6
39
40
41
55
56
57
89
90
91
C6
B6
D6
133
134
135
D6
B6
C6
I/O FT_hs
PB3
(JTDO/TRACES I/O
WO)
PB4 (NJTRST)
PB5
I/O
I/O
FT_fa
FT_fa
FT_
havd
-
125/334
LPTIM1_IN1, TIM3_CH2,
OCTOSPIM_P1_NCLK,
I2C1_SMBA, SPI1_MOSI,
SPI3_MOSI(boot), USART1_CK,
UART5_CTS, TSC_G2_IO2,
DCMI_D10/PSSI_D10,
COMP2_OUT, SAI1_SD_B,
TIM16_BKIN, EVENTOUT
Additional
functions
UCPD1_
DBCC1,
WKUP6
Pinout, pin description and alternate functions
DS13086 Rev 6
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
58
92
A5
135
B5
42
58
92
A5
136
B5
PB6
I/O
I/O structure
Pin type
UFBGA169
LQFP144
UFBGA132
LQFP100
LQFP64
LQFP48
UFQFPN48
UFBGA169 SMPS
LQFP144 SMPS
UFBGA132 SMPS
LQFP100 SMPS
WLCSP90 SMPS
A13
Pin name
(function after
reset)
FT_fa
DS13086 Rev 6
43
59
B12
93
D5
136
F5
43
59
93
D5
137
F5
PB7
I/O
FT_
fhav
44
60
C13
94
B5
137
C5
44
60
94
B5
138
C5
PH3-BOOT0
I/O
FT
45
-
B14
A15
95
96
C5
A4
138
139
E5
D5
45
46
61
62
95
96
C5
A4
139
140
E5
D5
PB8
PB9
I/O
I/O
FT_f
FT_f
Alternate functions
Additional
functions
-
LPTIM1_ETR, TIM4_CH1,
TIM8_BKIN2, I2C1_SCL(boot),
I2C4_SCL, MDF1_SDI5,
USART1_TX, TSC_G2_IO3,
DCMI_D5/PSSI_D5, SAI1_FS_B,
TIM16_CH1N, EVENTOUT
COMP2_
INP2,
WKUP3
-
LPTIM1_IN2, TIM4_CH2,
TIM8_BKIN, I2C1_SDA(boot),
I2C4_SDA, MDF1_CKI5,
USART1_RX, UART4_CTS,
TSC_G2_IO4,
DCMI_VSYNC/PSSI_RDY,
FMC_NL, TIM17_CH1N,
EVENTOUT
COMP2_
INM1,
PVD_IN,
WKUP4
-
EVENTOUT
-
-
TIM4_CH3, SAI1_CK1, I2C1_SCL,
MDF1_CCK0, SPI3_RDY,
SDMMC1_CKIN,
FDCAN1_RX(boot),
DCMI_D6/PSSI_D6, SDMMC2_D4,
SDMMC1_D4, SAI1_MCLK_A,
TIM16_CH1, EVENTOUT
WKUP5
-
IR_OUT, TIM4_CH4, SAI1_D2,
I2C1_SDA, SPI2_NSS,
SDMMC1_CDIR,
FDCAN1_TX(boot),
DCMI_D7/PSSI_D7, SDMMC2_D5,
SDMMC1_D5, SAI1_FS_A,
TIM17_CH1, EVENTOUT
-
STM32U585xx
-
61
Notes
42
LQFP64 SMPS
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Pinout, pin description and alternate functions
126/334
Table 27. STM32U585xx pin definitions(1) (continued)
LQFP64 SMPS
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Pin type
I/O structure
Notes
127/334
Pin name
(function after
reset)
Alternate functions
-
-
-
97
C4
140
D4
-
-
97
C4
141
D4
PE0
I/O
FT_h
-
TIM4_ETR, DCMI_D2/PSSI_D2,
LPGPIO1_P13, FMC_NBL0,
TIM16_CH1, EVENTOUT
-
-
-
-
-
A3
141
C4
-
-
98
A3
142
C4
PE1
I/O
FT_h
-
DCMI_D3/PSSI_D3, FMC_NBL1,
TIM17_CH1, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
A4
VCAP
S
-
-
-
-
46
62
A17
98
B4
142
A4
-
-
-
-
-
-
VDD11
S
-
-
-
-
47
63
B16
99
E4
143
B4
47
63
99
E4
143
B4
VSS
S
-
-
-
-
48
64
B18 100
J9
144
A3
48
64
100
J9
144
A3
VDD
S
-
-
-
-
-
-
-
-
-
-
B11
-
-
-
-
-
B11
VSS
S
-
-
-
-
-
-
-
-
-
-
F10
-
-
-
-
-
F10
PH2
I/O
FT_h
-
OCTOSPIM_P1_IO4, EVENTOUT
-
-
-
-
-
-
-
E10
-
-
-
-
-
E10
PH4
I/O
FT_fh
-
I2C2_SCL, OCTOSPIM_P2_DQS,
PSSI_D14, EVENTOUT
-
-
-
-
-
-
-
F9
-
-
-
-
-
F9
PH5
I/O
FT_f
-
I2C2_SDA,
DCMI_PIXCLK/PSSI_PDCK,
EVENTOUT
-
-
-
-
-
-
-
E11
-
-
-
-
-
E11
PH6
I/O FT_hv
-
I2C2_SMBA, OCTOSPIM_P2_CLK,
DCMI_D8/PSSI_D8, EVENTOUT
-
-
-
-
-
-
-
F8
-
-
-
-
-
F8
PH7
I/O
FT_
fhv
-
I2C3_SCL, OCTOSPIM_P2_NCLK,
DCMI_D9/PSSI_D9, EVENTOUT
-
-
-
-
-
-
-
D12
-
-
-
-
-
D12
PH8
I/O
FT_fh
-
I2C3_SDA, OCTOSPIM_P2_IO3,
DCMI_HSYNC/PSSI_DE,
EVENTOUT
-
Additional
functions
Pinout, pin description and alternate functions
DS13086 Rev 6
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
-
-
-
-
E9
-
-
-
-
-
E9
PH9
I/O
FT_h
-
I2C3_SMBA, OCTOSPIM_P2_IO4,
DCMI_D0/PSSI_D0, EVENTOUT
-
-
-
-
-
-
-
C13
-
-
-
-
-
C13
PH10
I/O
FT_h
-
TIM5_CH1, OCTOSPIM_P2_IO5,
DCMI_D1/PSSI_D1, EVENTOUT
-
-
-
-
-
-
-
D9
-
-
-
-
-
D9
PH11
I/O
FT_h
-
TIM5_CH2, OCTOSPIM_P2_IO6,
DCMI_D2/PSSI_D2, EVENTOUT
-
-
-
-
-
-
-
B13
-
-
-
-
-
B13
PH12
I/O
FT_h
-
TIM5_CH3, TIM8_CH4N,
OCTOSPIM_P2_IO7,
DCMI_D3/PSSI_D3, EVENTOUT
-
-
-
-
-
-
-
C12
-
-
-
-
-
C12
PH13
I/O
FT
-
TIM8_CH1N, FDCAN1_TX,
EVENTOUT
-
-
-
-
-
-
-
C11
-
-
-
-
-
C11
PH14
I/O
FT
-
TIM8_CH2N, FDCAN1_RX,
DCMI_D4/PSSI_D4, EVENTOUT
-
-
-
-
-
-
-
A13
-
-
-
-
-
A13
PH15
I/O
FT_h
-
TIM8_CH3N, OCTOSPIM_P2_IO6,
DCMI_D11/PSSI_D11, EVENTOUT
-
-
-
-
-
-
-
A11
-
-
-
-
-
A11
VDD
S
-
-
-
-
-
-
-
-
-
-
B12
-
-
-
-
-
B12
PI0
I/O
FT_h
-
TIM5_CH4, OCTOSPIM_P1_IO5,
SPI2_NSS, DCMI_D13/PSSI_D13,
EVENTOUT
-
-
-
-
-
-
-
A12
-
-
-
-
-
A12
PI1
I/O
FT_h
-
SPI2_SCK, OCTOSPIM_P2_IO2,
DCMI_D8/PSSI_D8, EVENTOUT
-
-
-
-
-
-
-
D11
-
-
-
-
-
D11
PI2
I/O FT_hv
-
TIM8_CH4, SPI2_MISO,
OCTOSPIM_P2_IO1,
DCMI_D9/PSSI_D9, EVENTOUT
-
Additional
functions
STM32U585xx
LQFP64 SMPS
DS13086 Rev 6
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
Pinout, pin description and alternate functions
128/334
Table 27. STM32U585xx pin definitions(1) (continued)
LQFP64 SMPS
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions
-
-
-
-
-
-
D10
-
-
-
-
-
D10
PI3
I/O
FT_h
-
TIM8_ETR, SPI2_MOSI,
OCTOSPIM_P2_IO0,
DCMI_D10/PSSI_D10, EVENTOUT
-
-
-
-
-
-
-
B2
-
-
-
-
-
B2
VSS
S
-
-
-
-
-
-
-
-
-
-
B1
-
-
-
-
-
B1
VDD
S
-
-
-
-
-
-
-
-
-
-
B10
-
-
-
-
-
B10
PI4
I/O
FT
-
TIM8_BKIN, SPI2_RDY,
DCMI_D5/PSSI_D5, EVENTOUT
-
-
-
-
-
-
-
B3
-
-
-
-
-
B3
PI5
I/O
FT_h
-
TIM8_CH1, OCTOSPIM_P2_NCS,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT
-
-
-
-
-
-
-
A2
-
-
-
-
-
A2
PI6
I/O FT_hv
-
TIM8_CH2, OCTOSPIM_P2_CLK,
DCMI_D6/PSSI_D6, EVENTOUT
-
-
-
-
-
-
-
C3
-
-
-
-
-
C3
PI7
I/O FT_hv
-
TIM8_CH3, OCTOSPIM_P2_NCLK,
DCMI_D7/PSSI_D7, EVENTOUT
-
Additional
functions
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs
in output mode is limited:
- The speed must not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (for example to drive a LED).
3. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the product reference manual.
4. After reset, a pull-down resistor (Rd = 5.1 kΩ from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15
(UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2).
This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register.
5. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.
129/334
Pinout, pin description and alternate functions
DS13086 Rev 6
LQFP48 SMPS
UFQFPN48 SMPS
Pin number
STM32U585xx
Table 27. STM32U585xx pin definitions(1) (continued)
Alternate functions
Table 28. Alternate function AF0 to AF7(1)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
PA0
-
TIM2_CH1
TIM5_CH1
TIM8_ETR
-
-
SPI3_RDY
USART2_CTS
PA1
LPTIM1_CH2
TIM2_CH2
TIM5_CH2
-
I2C1_SMBA
SPI1_SCK
-
USART2_
RTS_DE
PA2
-
TIM2_CH3
TIM5_CH3
-
-
SPI1_RDY
-
USART2_TX
PA3
-
TIM2_CH4
TIM5_CH4
SAI1_CK1
-
-
-
USART2_RX
PA4
-
-
-
OCTOSPIM_P1
_NCS
-
SPI1_NSS
SPI3_NSS
USART2_CK
PA5
CSLEEP
TIM2_CH1
TIM2_ETR
TIM8_CH1N
PSSI_D14
SPI1_SCK
-
USART3_RX
PA6
CDSTOP
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
DCMI_PIXCL
K/PSSI_
PDCK
SPI1_MISO
-
USART3_CTS
PA7
SRDSTOP
TIM1_CH1N
TIM3_CH2
TIM8_CH1N
I2C3_SCL
SPI1_MOSI
-
USART3_TX
PA8
MCO
TIM1_CH1
-
SAI1_CK2
-
SPI1_RDY
-
USART1_CK
PA9
-
TIM1_CH2
-
SPI2_SCK
-
DCMI_D0/PSSI_D0
-
USART1_TX
PA10
CRS_SYNC
TIM1_CH3
LPTIM2_IN2
SAI1_D1
-
DCMI_D1/PSSI_D1
-
USART1_RX
PA11
-
TIM1_CH4
TIM1_BKIN2
-
-
SPI1_MISO
-
USART1_CTS
PA12
-
TIM1_ETR
-
-
-
SPI1_MOSI
OCTOSPIM_
P2_NCS
USART1_
RTS_DE
PA13
JTMS/SWDIO
IR_OUT
-
-
-
-
-
-
PA14
JTCK/SWCLK
LPTIM1_CH1
-
-
I2C1_SMBA
I2C4_SMBA
-
-
PA15
JTDI
TIM2_CH1
TIM2_ETR
USART2_RX
-
SPI1_NSS
SPI3_NSS
USART3_
RTS_DE
DS13086 Rev 6
STM32U585xx
CRS/LPTIM1/
SYS_AF
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
Port
Port A
AF1
Pinout, pin description and alternate functions
130/334
4.3
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2N
LPTIM3_CH1
SPI1_NSS
-
USART3_CK
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3N
LPTIM3_CH2
-
MDF1_SDI0
USART3_
RTS_DE
PB2
-
LPTIM1_CH1
-
TIM8_CH4N
I2C3_SMBA
SPI1_RDY
MDF1_CKI0
-
PB3
JTDO/
TRACESWO
TIM2_CH2
LPTIM1_CH1
ADF1_CCK0
I2C1_SDA
SPI1_SCK
SPI3_SCK
USART1_
RTS_DE
PB4
NJTRST
LPTIM1_CH2
TIM3_CH1
ADF1_SDI0
I2C3_SDA
SPI1_MISO
SPI3_MISO
USART1_CTS
PB5
-
LPTIM1_IN1
TIM3_CH2
OCTOSPIM_
P1_NCLK
I2C1_SMBA
SPI1_MOSI
SPI3_MOSI
USART1_CK
PB6
-
LPTIM1_ETR
TIM4_CH1
TIM8_BKIN2
I2C1_SCL
I2C4_SCL
MDF1_SDI5
USART1_TX
PB7
-
LPTIM1_IN2
TIM4_CH2
TIM8_BKIN
I2C1_SDA
I2C4_SDA
MDF1_CKI5
USART1_RX
PB8
-
-
TIM4_CH3
SAI1_CK1
I2C1_SCL
MDF1_CCK0
SPI3_RDY
-
PB9
-
IR_OUT
TIM4_CH4
SAI1_D2
I2C1_SDA
SPI2_NSS
-
-
PB10
-
TIM2_CH3
LPTIM3_CH1
I2C4_SCL
I2C2_SCL
SPI2_SCK
-
USART3_TX
PB11
-
TIM2_CH4
-
I2C4_SDA
I2C2_SDA
SPI2_RDY
-
USART3_RX
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
SPI2_NSS
MDF1_SDI1
USART3_CK
PB13
-
TIM1_CH1N
LPTIM3_IN1
-
I2C2_SCL
SPI2_SCK
MDF1_CKI1
USART3_CTS
PB14
-
TIM1_CH2N
LPTIM3_ETR
TIM8_CH2N
I2C2_SDA
SPI2_MISO
MDF1_SDI2
USART3_
RTS_DE
PB15
RTC_REFIN
TIM1_CH3N
LPTIM2_IN2
TIM8_CH3N
-
SPI2_MOSI
MDF1_CKI2
-
DS13086 Rev 6
131/334
Pinout, pin description and alternate functions
CRS/LPTIM1/
SYS_AF
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
Port
Port B
AF1
STM32U585xx
Table 28. Alternate function AF0 to AF7(1) (continued)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
PC0
-
LPTIM1_IN1
-
OCTOSPIM_
P1_IO7
I2C3_SCL
SPI2_RDY
MDF1_SDI4
-
PC1
TRACED0
LPTIM1_CH1
-
SPI2_MOSI
I2C3_SDA
-
MDF1_CKI4
-
PC2
-
LPTIM1_IN2
-
-
-
SPI2_MISO
MDF1_CCK1
-
PC3
-
LPTIM1_ETR
LPTIM3_CH1
SAI1_D1
-
SPI2_MOSI
-
-
PC4
-
-
-
-
-
-
-
USART3_TX
PC5
-
TIM1_CH4N
-
SAI1_D3
PSSI_D15
-
-
USART3_RX
PC6
CSLEEP
-
TIM3_CH1
TIM8_CH1
-
-
MDF1_CKI3
-
PC7
CDSTOP
-
TIM3_CH2
TIM8_CH2
-
-
MDF1_SDI3
-
PC8
SRDSTOP
-
TIM3_CH3
TIM8_CH3
-
-
-
-
PC9
TRACED0
TIM8_BKIN2
TIM3_CH4
TIM8_CH4
DCMI_D3/
PSSI_D3
-
-
-
PC10
TRACED1
-
LPTIM3_ETR
ADF1_CCK1
-
-
SPI3_SCK
USART3_TX
PC11
-
-
LPTIM3_IN1
ADF1_SDI0
DCMI_D2/
PSSI_D2
OCTOSPIM_
P1_NCS
SPI3_MISO
USART3_RX
PC12
TRACED3
-
-
-
-
-
SPI3_MOSI
USART3_CK
PC13
-
-
-
-
-
-
-
-
PC14
-
-
-
-
-
-
-
-
PC15
-
-
-
-
-
-
-
-
DS13086 Rev 6
STM32U585xx
CRS/LPTIM1/
SYS_AF
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
Port
Port C
AF1
Pinout, pin description and alternate functions
132/334
Table 28. Alternate function AF0 to AF7(1) (continued)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
PD0
-
-
-
TIM8_CH4N
-
SPI2_NSS
-
-
PD1
-
-
-
-
-
SPI2_SCK
-
-
PD2
TRACED2
-
TIM3_ETR
-
-
-
-
USART3_
RTS_DE
PD3
-
-
-
SPI2_SCK
DCMI_D5/
PSSI_D5
SPI2_MISO
MDF1_SDI0
USART2_CTS
PD4
-
-
-
-
-
SPI2_MOSI
MDF1_CKI0
USART2_
RTS_DE
PD5
-
-
-
-
-
SPI2_RDY
-
USART2_TX
PD6
-
-
-
SAI1_D1
DCMI_D10/
PSSI_D10
SPI3_MOSI
MDF1_SDI1
USART2_RX
PD7
-
-
-
-
-
-
MDF1_CKI1
USART2_CK
PD8
-
-
-
-
-
-
-
USART3_TX
PD9
-
-
LPTIM2_IN2
-
-
-
-
USART3_RX
PD10
-
-
LPTIM2_CH2
-
-
-
-
USART3_CK
PD11
-
-
-
-
I2C4_SMBA
-
-
USART3_CTS
PD12
-
-
TIM4_CH1
-
I2C4_SCL
-
-
USART3_
RTS_DE
PD13
-
-
TIM4_CH2
-
I2C4_SDA
-
-
-
PD14
-
-
TIM4_CH3
-
-
-
-
-
PD15
-
-
TIM4_CH4
-
-
-
-
-
DS13086 Rev 6
133/334
Pinout, pin description and alternate functions
CRS/LPTIM1/
SYS_AF
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
Port
Port D
AF1
STM32U585xx
Table 28. Alternate function AF0 to AF7(1) (continued)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
CRS/LPTIM1/
SYS_AF
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
PE0
-
-
TIM4_ETR
-
-
-
-
-
PE1
-
-
-
-
-
-
-
-
PE2
TRACECLK
-
TIM3_ETR
SAI1_CK1
-
-
-
-
PE3
TRACED0
-
TIM3_CH1
OCTOSPIM_
P1_DQS
-
-
-
-
PE4
TRACED1
-
TIM3_CH2
SAI1_D2
-
-
MDF1_SDI3
-
PE5
TRACED2
-
TIM3_CH3
SAI1_CK2
-
-
MDF1_CKI3
-
PE6
TRACED3
-
TIM3_CH4
SAI1_D1
-
-
-
-
PE7
-
TIM1_ETR
-
-
-
-
MDF1_SDI2
-
PE8
-
TIM1_CH1N
-
-
-
-
MDF1_CKI2
-
PE9
-
TIM1_CH1
-
ADF1_CCK0
-
-
MDF1_CCK0
-
PE10
-
TIM1_CH2N
-
ADF1_SDI0
-
-
MDF1_SDI4
-
PE11
-
TIM1_CH2
-
-
-
SPI1_RDY
MDF1_CKI4
-
PE12
-
TIM1_CH3N
-
-
-
SPI1_NSS
MDF1_SDI5
-
PE13
-
TIM1_CH3
-
-
-
SPI1_SCK
MDF1_CKI5
-
PE14
-
TIM1_CH4
TIM1_BKIN2
-
-
SPI1_MISO
-
-
PE15
-
TIM1_BKIN
-
TIM1_CH4N
-
SPI1_MOSI
-
-
Port
DS13086 Rev 6
Port E
AF1
Pinout, pin description and alternate functions
134/334
Table 28. Alternate function AF0 to AF7(1) (continued)
STM32U585xx
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
PF0
-
-
-
-
I2C2_SDA
OCTOSPIM_P2_IO0
-
-
PF1
-
-
-
-
I2C2_SCL
OCTOSPIM_P2_IO1
-
-
PF2
-
-
LPTIM3_CH2
-
I2C2_SMBA
OCTOSPIM_P2_IO2
-
-
PF3
-
-
LPTIM3_IN1
-
-
OCTOSPIM_P2_IO3
-
-
PF4
-
-
LPTIM3_ETR
-
-
OCTOSPIM_
P2_CLK
-
-
PF5
-
-
LPTIM3_CH1
-
-
OCTOSPIM_
P2_NCLK
-
-
PF6
-
TIM5_ETR
TIM5_CH1
-
DCMI_D12/P
SSI_D12
OCTOSPIM_
P2_NCS
-
-
PF7
-
-
TIM5_CH2
-
-
-
-
-
PF8
-
-
TIM5_CH3
-
PSSI_D14
-
-
-
PF9
-
-
TIM5_CH4
-
PSSI_D15
-
-
-
PF10
-
-
-
OCTOSPIM_
P1_CLK
PSSI_D15
-
MDF1_CCK1
-
PF11
-
-
-
OCTOSPIM_
P1_NCLK
-
-
-
-
PF12
-
-
-
-
-
OCTOSPIM_
P2_DQS
-
-
PF13
-
-
-
-
I2C4_SMBA
-
-
-
PF14
-
-
-
-
I2C4_SCL
-
-
-
PF15
-
-
-
-
I2C4_SDA
-
-
-
DS13086 Rev 6
135/334
Pinout, pin description and alternate functions
CRS/LPTIM1/
SYS_AF
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
Port
Port F
AF1
STM32U585xx
Table 28. Alternate function AF0 to AF7(1) (continued)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
PG0
-
-
-
-
-
OCTOSPIM_P2_IO4
-
-
PG1
-
-
-
-
-
OCTOSPIM_P2_IO5
-
-
PG2
-
-
-
-
-
SPI1_SCK
-
-
PG3
-
-
-
-
-
SPI1_MISO
-
-
PG4
-
-
-
-
-
SPI1_MOSI
-
-
PG5
-
-
-
-
-
SPI1_NSS
-
-
PG6
-
-
-
OCTOSPIM_
P1_DQS
I2C3_SMBA
SPI1_RDY
-
-
PG7
-
-
-
SAI1_CK1
I2C3_SCL
OCTOSPIM_
P2_DQS
MDF1_CCK0
-
PG8
-
-
-
-
I2C3_SDA
-
-
-
PG9
-
-
-
-
-
OCTOSPIM_P2_IO6
SPI3_SCK
USART1_TX
PG10
-
LPTIM1_IN1
-
-
-
OCTOSPIM_P2_IO7
SPI3_MISO
USART1_RX
PG11
-
LPTIM1_IN2
-
OCTOSPIM_
P1_IO5
-
-
SPI3_MOSI
USART1_CTS
PG12
-
LPTIM1_ETR
-
-
-
OCTOSPIM_
P2_NCS
SPI3_NSS
USART1_
RTS_DE
PG13
-
-
-
-
I2C1_SDA
-
SPI3_RDY
USART1_CK
PG14
-
LPTIM1_CH2
-
-
I2C1_SCL
-
-
-
PG15
-
LPTIM1_CH1
-
-
I2C1_SMBA
OCTOSPIM_
P2_DQS
-
-
DS13086 Rev 6
STM32U585xx
CRS/LPTIM1/
SYS_AF
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
Port
Port G
AF1
Pinout, pin description and alternate functions
136/334
Table 28. Alternate function AF0 to AF7(1) (continued)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
PH0
-
-
-
-
-
-
-
-
PH1
-
-
-
-
-
-
-
-
PH2
-
-
-
OCTOSPIM_
P1_IO4
-
-
-
-
PH3
-
-
-
-
-
-
-
-
PH4
-
-
-
-
I2C2_SCL
OCTOSPIM_
P2_DQS
-
-
PH5
-
-
-
-
I2C2_SDA
-
-
-
PH6
-
-
-
-
I2C2_SMBA
OCTOSPIM_
P2_CLK
-
-
PH7
-
-
-
-
I2C3_SCL
OCTOSPIM_
P2_NCLK
-
-
PH8
-
-
-
-
I2C3_SDA
OCTOSPIM_P2_IO3
-
-
PH9
-
-
-
-
I2C3_SMBA
OCTOSPIM_P2_IO4
-
-
PH10
-
-
TIM5_CH1
-
-
OCTOSPIM_P2_IO5
-
-
PH11
-
-
TIM5_CH2
-
-
OCTOSPIM_P2_IO6
-
-
PH12
-
-
TIM5_CH3
TIM8_CH4N
-
OCTOSPIM_P2_IO7
-
-
PH13
-
-
-
TIM8_CH1N
-
-
-
-
PH14
-
-
-
TIM8_CH2N
-
-
-
-
PH15
-
-
-
TIM8_CH3N
-
OCTOSPIM_P2_IO6
-
-
DS13086 Rev 6
137/334
Pinout, pin description and alternate functions
CRS/LPTIM1/
SYS_AF
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
Port
Port H
AF1
STM32U585xx
Table 28. Alternate function AF0 to AF7(1) (continued)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
DCMI/
I2C1/2/3/4/
LPTIM3
DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/
SPI1/2/3
I2C3/MDF1/
OCTOSPIM_P2/
SPI3
USART1/2/3
CRS/LPTIM1/
SYS_AF
LPTIM1/
TIM1/2/5/8
LPTIM1/2/3/
TIM1/2/3/4/5
ADF1/I2C4/
OCTOSPIM_P1/
OTG_FS/SAI1/
SPI2/TIM1/8/
USART2
PI0
-
-
TIM5_CH4
OCTOSPIM_
P1_IO5
-
SPI2_NSS
-
-
PI1
-
-
-
-
-
SPI2_SCK
OCTOSPIM_
P2_IO2
-
PI2
-
-
-
TIM8_CH4
-
SPI2_MISO
OCTOSPIM_
P2_IO1
-
PI3
-
-
-
TIM8_ETR
-
SPI2_MOSI
OCTOSPIM_
P2_IO0
-
PI4
-
-
-
TIM8_BKIN
-
SPI2_RDY
-
-
PI5
-
-
-
TIM8_CH1
-
OCTOSPIM_
P2_NCS
-
-
PI6
-
-
-
TIM8_CH2
-
OCTOSPIM_
P2_CLK
-
-
PI7
-
-
-
TIM8_CH3
-
OCTOSPIM_
P2_NCLK
-
-
Port
DS13086 Rev 6
Port I
AF1
Pinout, pin description and alternate functions
138/334
Table 28. Alternate function AF0 to AF7(1) (continued)
1. Refer to the next table for AF8 to AF15.
STM32U585xx
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PA0
UART4_TX
-
OCTOSPIM_
P2_NCS
-
SDMMC2_CMD
AUDIOCLK
TIM2_ETR
EVENTOUT
PA1
UART4_RX
-
OCTOSPIM_
P1_DQS
LPGPIO1_P0
-
-
TIM15_CH1N
EVENTOUT
PA2
LPUART1_TX
-
OCTOSPIM_
P1_NCS
UCPD1_
FRSTX1
-
-
TIM15_CH1
EVENTOUT
PA3
LPUART1_RX
-
OCTOSPIM_P1_CLK
LPGPIO1_P1
-
SAI1_MCLK_A
TIM15_CH2
EVENTOUT
PA4
-
-
DCMI_HSYNC/
PSSI_DE
-
-
SAI1_FS_B
LPTIM2_CH1
EVENTOUT
PA5
-
-
-
-
-
-
LPTIM2_ETR
EVENTOUT
PA6
LPUART1_CTS
-
OCTOSPIM_P1_IO3
LPGPIO1_P2
-
-
TIM16_CH1
EVENTOUT
PA7
-
-
OCTOSPIM_P1_IO2
-
-
LPTIM2_CH2
TIM17_CH1
EVENTOUT
PA8
-
-
OTG_FS_SOF
-
TRACECLK
SAI1_SCK_A
LPTIM2_CH1
EVENTOUT
PA9
-
-
-
-
-
SAI1_FS_A
TIM15_BKIN
EVENTOUT
PA10
-
-
OTG_FS_ID
-
-
SAI1_SD_A
TIM17_BKIN
EVENTOUT
PA11
-
FDCAN1_RX
OTG_FS_DM
-
-
-
-
EVENTOUT
PA12
-
FDCAN1_TX
OTG_FS_DP
-
-
-
-
EVENTOUT
PA13
-
-
OTG_FS_NOE
-
-
SAI1_SD_B
-
EVENTOUT
PA14
-
-
OTG_FS_SOF
-
-
SAI1_FS_B
-
EVENTOUT
-
-
-
-
SAI2_FS_B
-
EVENTOUT
DS13086 Rev 6
Port A
Port
PA15 UART4_RTS_DE
139/334
Pinout, pin description and alternate functions
AF8
STM32U585xx
Table 29. Alternate function AF8 to AF15(1)
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PB0
-
-
OCTOSPIM_P1_IO1
LPGPIO1_P9
COMP1_OUT
AUDIOCLK
-
EVENTOUT
PB1
LPUART1_
RTS_DE
-
OCTOSPIM_P1_IO0
LPGPIO1_P3
-
-
LPTIM2_IN1
EVENTOUT
PB2
-
-
OCTOSPIM_
P1_DQS
UCPD1_
FRSTX1
-
-
-
EVENTOUT
PB3
-
-
CRS_SYNC
LPGPIO1_P11
SDMMC2_D2
SAI1_SCK_B
-
EVENTOUT
PB4
UART5_RTS_DE
TSC_G2_IO1
DCMI_D12/
PSSI_D12
LPGPIO1_P12
SDMMC2_D3
SAI1_MCLK_B
TIM17_BKIN
EVENTOUT
PB5
UART5_CTS
TSC_G2_IO2
DCMI_D10/
PSSI_D10
-
COMP2_OUT
SAI1_SD_B
TIM16_BKIN
EVENTOUT
PB6
-
TSC_G2_IO3
DCMI_D5/PSSI_D5
-
-
SAI1_FS_B
TIM16_CH1N
EVENTOUT
PB7
UART4_CTS
TSC_G2_IO4
DCMI_VSYNC/
PSSI_RDY
-
FMC_NL
-
TIM17_CH1N
EVENTOUT
PB8
SDMMC1_CKIN
FDCAN1_RX
DCMI_D6/PSSI_D6
SDMMC2_D4
SDMMC1_D4
SAI1_MCLK_A
TIM16_CH1
EVENTOUT
PB9
SDMMC1_CDIR
FDCAN1_TX
DCMI_D7/PSSI_D7
SDMMC2_D5
SDMMC1_D5
SAI1_FS_A
TIM17_CH1
EVENTOUT
PB10
LPUART1_RX
TSC_SYNC
OCTOSPIM_P1_CLK
LPGPIO1_P4
COMP1_OUT
SAI1_SCK_A
-
EVENTOUT
PB11
LPUART1_TX
-
OCTOSPIM_
P1_NCS
-
COMP2_OUT
-
-
EVENTOUT
PB12
LPUART1_RTS_
DE
TSC_G1_IO1
OCTOSPIM_
P1_NCLK
-
-
SAI2_FS_A
TIM15_BKIN
EVENTOUT
PB13
LPUART1_CTS
TSC_G1_IO2
-
-
-
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PB14
-
TSC_G1_IO3
-
-
SDMMC2_D0
SAI2_MCLK_A
TIM15_CH1
EVENTOUT
PB15
-
-
-
FMC_NBL1
SDMMC2_D1
SAI2_SD_A
TIM15_CH2
EVENTOUT
DS13086 Rev 6
Port B
Port
STM32U585xx
AF8
Pinout, pin description and alternate functions
140/334
Table 29. Alternate function AF8 to AF15(1) (continued)
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PC0
LPUART1_RX
-
-
-
SDMMC1_D5
SAI2_FS_A
LPTIM2_IN1
EVENTOUT
PC1
LPUART1_TX
-
OCTOSPIM_P1_IO4
-
SDMMC2_CK
SAI1_SD_A
-
EVENTOUT
PC2
-
-
OCTOSPIM_P1_IO5
LPGPIO1_P5
-
-
-
EVENTOUT
PC3
-
-
OCTOSPIM_P1_IO6
-
-
SAI1_SD_A
LPTIM2_ETR
EVENTOUT
PC4
-
-
OCTOSPIM_P1_IO7
-
-
-
-
EVENTOUT
PC5
-
-
-
-
-
-
-
EVENTOUT
PC6
SDMMC1_
D0DIR
TSC_G4_IO1
DCMI_D0/PSSI_D0
SDMMC2_D6
SDMMC1_D6
SAI2_MCLK_A
-
EVENTOUT
PC7
SDMMC1_
D123DIR
TSC_G4_IO2
DCMI_D1/PSSI_D1
SDMMC2_D7
SDMMC1_D7
SAI2_MCLK_B
LPTIM2_CH2
EVENTOUT
PC8
-
TSC_G4_IO3
DCMI_D2/PSSI_D2
-
SDMMC1_D0
-
LPTIM3_CH1
EVENTOUT
PC9
-
TSC_G4_IO4
OTG_FS_NOE
-
SDMMC1_D1
-
LPTIM3_CH2
EVENTOUT
PC10
UART4_TX
TSC_G3_IO2
DCMI_D8/PSSI_D8
LPGPIO1_P8
SDMMC1_D2
SAI2_SCK_B
-
EVENTOUT
PC11
UART4_RX
TSC_G3_IO3
DCMI_D4/PSSI_D4
UCPD1_
FRSTX2
SDMMC1_D3
SAI2_MCLK_B
-
EVENTOUT
PC12
UART5_TX
TSC_G3_IO4
DCMI_D9/PSSI_D9
LPGPIO1_P10
SDMMC1_CK
SAI2_SD_B
-
EVENTOUT
PC13
-
-
-
-
-
-
-
EVENTOUT
PC14
-
-
-
-
-
-
-
EVENTOUT
PC15
-
-
-
-
-
-
-
EVENTOUT
DS13086 Rev 6
Port C
Port
141/334
Pinout, pin description and alternate functions
AF8
STM32U585xx
Table 29. Alternate function AF8 to AF15(1) (continued)
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PD0
-
FDCAN1_RX
-
-
FMC_D2
-
-
EVENTOUT
PD1
-
FDCAN1_TX
-
-
FMC_D3
-
-
EVENTOUT
PD2
UART5_RX
TSC_SYNC
DCMI_D11/
PSSI_D11
LPGPIO1_P7
SDMMC1_CMD
LPTIM4_ETR
-
EVENTOUT
PD3
-
-
OCTOSPIM_
P2_NCS
-
FMC_CLK
-
-
EVENTOUT
PD4
-
-
OCTOSPIM_P1_IO4
-
FMC_NOE
-
-
EVENTOUT
PD5
-
-
OCTOSPIM_P1_IO5
-
FMC_NWE
-
-
EVENTOUT
PD6
-
-
OCTOSPIM_P1_IO6
SDMMC2_CK
FMC_NWAIT
SAI1_SD_A
-
EVENTOUT
PD7
-
-
OCTOSPIM_P1_IO7
SDMMC2_CMD
FMC_NCE/
FMC_NE1
LPTIM4_OUT
-
EVENTOUT
PD8
-
-
DCMI_HSYNC/
PSSI_DE
-
FMC_D13
-
-
EVENTOUT
PD9
-
-
DCMI_PIXCLK/
PSSI_PDCK
-
FMC_D14
SAI2_MCLK_A
LPTIM3_IN1
EVENTOUT
PD10
-
TSC_G6_IO1
-
-
FMC_D15
SAI2_SCK_A
LPTIM3_ETR
EVENTOUT
PD11
-
TSC_G6_IO2
-
-
FMC_CLE/
FMC_A16
SAI2_SD_A
LPTIM2_ETR
EVENTOUT
PD12
-
TSC_G6_IO3
-
-
FMC_ALE/
FMC_A17
SAI2_FS_A
LPTIM2_IN1
EVENTOUT
PD13
-
TSC_G6_IO4
-
LPGPIO1_P6
FMC_A18
LPTIM4_IN1
LPTIM2_CH1
EVENTOUT
PD14
-
-
-
-
FMC_D0
-
LPTIM3_CH1
EVENTOUT
PD15
-
-
-
-
FMC_D1
-
LPTIM3_CH2
EVENTOUT
DS13086 Rev 6
Port D
Port
STM32U585xx
AF8
Pinout, pin description and alternate functions
142/334
Table 29. Alternate function AF8 to AF15(1) (continued)
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PE0
-
-
DCMI_D2/PSSI_D2
LPGPIO1_P13
FMC_NBL0
-
TIM16_CH1
EVENTOUT
PE1
-
-
DCMI_D3/PSSI_D3
-
FMC_NBL1
-
TIM17_CH1
EVENTOUT
PE2
-
TSC_G7_IO1
-
LPGPIO1_P14
FMC_A23
SAI1_MCLK_A
-
EVENTOUT
PE3
-
TSC_G7_IO2
-
LPGPIO1_P15
FMC_A19
SAI1_SD_B
-
EVENTOUT
PE4
-
TSC_G7_IO3
DCMI_D4/PSSI_D4
-
FMC_A20
SAI1_FS_A
-
EVENTOUT
PE5
-
TSC_G7_IO4
DCMI_D6/PSSI_D6
-
FMC_A21
SAI1_SCK_A
-
EVENTOUT
PE6
-
-
DCMI_D7/PSSI_D7
-
FMC_A22
SAI1_SD_A
-
EVENTOUT
PE7
-
-
-
-
FMC_D4
SAI1_SD_B
-
EVENTOUT
PE8
-
-
-
-
FMC_D5
SAI1_SCK_B
-
EVENTOUT
PE9
-
-
OCTOSPIM_P1_NC
LK
-
FMC_D6
SAI1_FS_B
-
EVENTOUT
PE10
-
TSC_G5_IO1
OCTOSPIM_P1_CLK
-
FMC_D7
SAI1_MCLK_B
-
EVENTOUT
PE11
-
TSC_G5_IO2
OCTOSPIM_
P1_NCS
-
FMC_D8
-
-
EVENTOUT
PE12
-
TSC_G5_IO3
OCTOSPIM_P1_IO0
-
FMC_D9
-
-
EVENTOUT
PE13
-
TSC_G5_IO4
OCTOSPIM_P1_IO1
-
FMC_D10
-
-
EVENTOUT
PE14
-
-
OCTOSPIM_P1_IO2
-
FMC_D11
-
-
EVENTOUT
PE15
-
-
OCTOSPIM_P1_IO3
-
FMC_D12
-
-
EVENTOUT
DS13086 Rev 6
Port E
Port
143/334
Pinout, pin description and alternate functions
AF8
STM32U585xx
Table 29. Alternate function AF8 to AF15(1) (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PF0
-
-
-
-
FMC_A0
-
-
EVENTOUT
PF1
-
-
-
-
FMC_A1
-
-
EVENTOUT
PF2
-
-
-
-
FMC_A2
-
-
EVENTOUT
PF3
-
-
-
-
FMC_A3
-
-
EVENTOUT
PF4
-
-
-
-
FMC_A4
-
-
EVENTOUT
PF5
-
-
-
-
FMC_A5
-
-
EVENTOUT
PF6
-
-
OCTOSPIM_P1_IO3
-
-
SAI1_SD_B
-
EVENTOUT
PF7
-
FDCAN1_RX
OCTOSPIM_P1_IO2
-
-
SAI1_MCLK_B
-
EVENTOUT
PF8
-
FDCAN1_TX
OCTOSPIM_P1_IO0
-
-
SAI1_SCK_B
-
EVENTOUT
PF9
-
-
OCTOSPIM_P1_IO1
-
-
SAI1_FS_B
TIM15_CH1
EVENTOUT
PF10
-
-
DCMI_D11/
PSSI_D11
-
-
SAI1_D3
TIM15_CH2
EVENTOUT
PF11
-
-
DCMI_D12/
PSSI_D12
-
-
LPTIM4_IN1
-
EVENTOUT
PF12
-
-
-
-
FMC_A6
LPTIM4_ETR
-
EVENTOUT
PF13
-
-
-
UCPD1_
FRSTX2
FMC_A7
LPTIM4_OUT
-
EVENTOUT
PF14
-
TSC_G8_IO1
-
-
FMC_A8
-
-
EVENTOUT
PF15
-
TSC_G8_IO2
-
-
FMC_A9
-
-
EVENTOUT
DS13086 Rev 6
Port F
Port
Pinout, pin description and alternate functions
144/334
Table 29. Alternate function AF8 to AF15(1) (continued)
STM32U585xx
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PG0
-
TSC_G8_IO3
-
-
FMC_A10
-
-
EVENTOUT
PG1
-
TSC_G8_IO4
-
-
FMC_A11
-
-
EVENTOUT
PG2
-
-
-
-
FMC_A12
SAI2_SCK_B
-
EVENTOUT
PG3
-
-
-
-
FMC_A13
SAI2_FS_B
-
EVENTOUT
PG4
-
-
-
-
FMC_A14
SAI2_MCLK_B
-
EVENTOUT
PG5
LPUART1_CTS
-
-
-
FMC_A15
SAI2_SD_B
-
EVENTOUT
PG6
LPUART1_
RTS_DE
-
-
UCPD1_
FRSTX1
-
-
-
EVENTOUT
PG7
LPUART1_TX
-
-
UCPD1_
FRSTX2
FMC_INT
SAI1_MCLK_A
-
EVENTOUT
PG8
LPUART1_RX
-
-
-
-
-
-
EVENTOUT
PG9
-
-
-
-
FMC_NCE/
FMC_NE2
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PG10
-
-
-
-
FMC_NE3
SAI2_FS_A
TIM15_CH1
EVENTOUT
PG11
-
-
-
-
-
SAI2_MCLK_A
TIM15_CH2
EVENTOUT
PG12
-
-
-
-
FMC_NE4
SAI2_SD_A
-
EVENTOUT
PG13
-
-
-
-
FMC_A24
-
-
EVENTOUT
PG14
-
-
-
-
FMC_A25
-
-
EVENTOUT
PG15
-
-
DCMI_D13/
PSSI_D13
-
-
-
-
EVENTOUT
DS13086 Rev 6
Port G
Port
145/334
Pinout, pin description and alternate functions
AF8
STM32U585xx
Table 29. Alternate function AF8 to AF15(1) (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PH0
-
-
-
-
-
-
-
EVENTOUT
PH1
-
-
-
-
-
-
-
EVENTOUT
PH2
-
-
-
-
-
-
-
EVENTOUT
PH3
-
-
-
-
-
-
-
EVENTOUT
PH4
-
-
PSSI_D14
-
-
-
-
EVENTOUT
PH5
-
-
DCMI_PIXCLK/
PSSI_PDCK
-
-
-
-
EVENTOUT
PH6
-
-
DCMI_D8/PSSI_D8
-
-
-
-
EVENTOUT
PH7
-
-
DCMI_D9/PSSI_D9
-
-
-
-
EVENTOUT
PH8
-
-
DCMI_HSYNC/
PSSI_DE
-
-
-
-
EVENTOUT
PH9
-
-
DCMI_D0/PSSI_D0
-
-
-
-
EVENTOUT
PH10
-
-
DCMI_D1/PSSI_D1
-
-
-
-
EVENTOUT
PH11
-
-
DCMI_D2/PSSI_D2
-
-
-
-
EVENTOUT
PH12
-
-
DCMI_D3/PSSI_D3
-
-
-
-
EVENTOUT
PH13
-
FDCAN1_TX
-
-
-
-
-
EVENTOUT
PH14
-
FDCAN1_RX
DCMI_D4/PSSI_D4
-
-
-
-
EVENTOUT
PH15
-
-
DCMI_D11/
PSSI_D11
-
-
-
-
EVENTOUT
DS13086 Rev 6
Port H
Port
Pinout, pin description and alternate functions
146/334
Table 29. Alternate function AF8 to AF15(1) (continued)
STM32U585xx
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
LPUART1/
SDMMC1/
UART4/5
CAN1/TSC
CRS/DCMI/
OCTOSPIM_P1/2/
OTG_FS
LPGPIO1/
SDMMC2/
UCPD1/FMC
COMP1/2/FMC/
SDMMC1/2
LPTIM2/4/
SAI1/2
LPTIM2/3/
TIM2/15/16/17
EVENOUT
PI0
-
-
DCMI_D13/
PSSI_D13
-
-
-
-
EVENTOUT
PI1
-
-
DCMI_D8/PSSI_D8
-
-
-
-
EVENTOUT
PI2
-
-
DCMI_D9/PSSI_D9
-
-
-
-
EVENTOUT
PI3
-
-
DCMI_D10/
PSSI_D10
-
-
-
-
EVENTOUT
PI4
-
-
DCMI_D5/PSSI_D5
-
-
-
-
EVENTOUT
PI5
-
-
DCMI_VSYNC/
PSSI_RDY
-
-
-
-
EVENTOUT
PI6
-
-
DCMI_D6/PSSI_D6
-
-
-
-
EVENTOUT
PI7
-
-
DCMI_D7/PSSI_D7
-
-
-
-
EVENTOUT
Port I
Port
147/334
Pinout, pin description and alternate functions
DS13086 Rev 6
1. For AF0 to AF7 refer to the previous table.
STM32U585xx
Table 29. Alternate function AF8 to AF15(1) (continued)
Electrical characteristics
STM32U585xx
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V.
They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have
an error less than or equal to the value indicated (mean ±2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 22.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 23.
Figure 22. Pin loading conditions
Figure 23. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MSv68045V1
148/334
DS13086 Rev 6
MSv68046V1
STM32U585xx
5.1.6
Electrical characteristics
Power supply scheme
Figure 24. STM32U585xx power supply scheme (without SMPS)
VBAT
Backup circuitry
(LSE, RTC, TAMP
backup registers,
backup SRAM)
1.65 – 3.6 V
VDDUSB
VDDUSB
100 nF
Power switch
VCAP
4.7 μF
VDD
VCORE
n x VDD
LDO
regulator
VCORE
GPIOs
IN
Level shifter
OUT
n x 100 nF
+ 1 x 10 μF
I/O
logic
Level shifter
VDDIO1
I/O
logic
Kernel logic
(CPU, digital
and
memories)
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x 100 nF
+ 4.7 μF
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
100 nF
+1 μF
100 nF+ 1 μF
VREF+
VREF-
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VSSA
MSv64358V3
Caution:
If there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF
(typical) capacitor (for a total around 4.4 µF).
DS13086 Rev 6
149/334
299
Electrical characteristics
STM32U585xx
Figure 25. STM32U585xQ power supply scheme (with SMPS)
Backup circuitry
(LSE, RTC, TAMP,
backup registers,
backup SRAM)
VBAT
1.65 – 3.6 V
VDDUSB
Power switch
VDDUSB
100 nF
VDD
VDDSMPS
10 μF
Voltage regulator
VCORE
SMPS
VLXSMPS
2.2 μH
SMPS ON
2 x VDD11
2 x 2.2 μF
Kernel logic
(CPU, digital
and memories)
VSSSMPS
SMPS OFF
VDD
LDO
n x VDD
n x 100 nF
+ 10 μF
GPIOs
IN
Level shifter
OUT
I/O
logic
Level shifter
VDDIO1
I/O
logic
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+ 4.7 μF
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
100 nF
+ 1 μF
100 nF+ 1 μF
VREF+
VREF-
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VSSA
MSv64359V3
Note:
150/334
SMPS and LDO regulators provide, in a concurrent way, the VCORE supply depending on
application requirements. However, only one of them is active at the same time. When
SMPS is active, it feeds the VCORE on the two VDD11 pins supplied by the filtered SMPS
VLXSMPS output pin. A 2.2 µH coil and a 2.2 µF capacitor on each VDD11 pin are then
required. When LDO is active, it supplies the VCORE and regulates it using the same
decoupling capacitors on VDD11 pins. It is recommended to add a decoupling capacitor of
100 nF near each VDD11 pin/ball, but it is not mandatory.
DS13086 Rev 6
STM32U585xx
Electrical characteristics
Caution:
Each power supply pair (such as VDD/VSS or VDDA/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
5.1.7
Current consumption measurement
The IDD parameters given in various tables in the next sections, represent the total MCU
consumption including the current supplying VDD, VDDIO2, VDDA, VDDUSB, VBAT and
VDDSMPS (if the device embeds the SMPS).
Figure 26. Current consumption measurement
VBAT
IDD_VBAT
IDD
VDD
VDDA
VDDUSB
VDDSMPS
VDDIO2
MSv62920V2
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 30, Table 31 and Table 32
may cause permanent damage to the device. These are stress ratings only and the
functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 qualification standard, extended
mission profiles are available on demand.
Table 30. Voltage characteristics(1)(2)
Symbol
Ratings
Min
Max
VDDX - VSS
External main supply voltage (including
VDDSMPS, VDDA, VDDUSB, VBAT, VREF+)
-0.3
4.0
I/O supply when HSLV = 0
-0.3
4.0
I/O supply when HSLV = 1
-0.3
2.75
VDDIOx(3) - VSS
VIN(4)
Unit
V
Input voltage on FT_xx pins except
FT_c pins
Min (min (VDD, VDDA, VDDUSB, VDDIO2)
VSS - 0.3
+ 4.0, 6.0)(5)(6)
Input voltage on FT_t pins in
VBAT mode
VSS - 0.3
DS13086 Rev 6
Min (min (VBAT, VDDA, VDDUSB,
VDDIO2) + 4.0, 6.0) (5)(6)
151/334
299
Electrical characteristics
STM32U585xx
Table 30. Voltage characteristics(1)(2) (continued)
Symbol
Min
Max
Input voltage on FT_c pins
VSS - 0.3
5.5
Input voltage on any other pins
VSS - 0.3
4.0
Allowed voltage difference for
VREF+ > VDDA
-
0.4
|∆VDDx|
Variations between different VDDx
power pins of the same domain
-
50.0
|VSSx-VSS|
Variations between all the different
ground pins(7)
-
50.0
VIN(4)
VREF+ - VDDA
Ratings
Unit
V
mV
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must
always be connected to the external power supply, in the permitted range.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
3. VDDIO1 or VDDIO2, VDDIO1 = VDD.
4. VIN maximum must always be respected. Refer to Table 31 for the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
7. Including VREF- pin.
Table 31. Current characteristics
Symbol
Ratings
Max
∑IVDD
Total current into sum of all VDD power lines (source)
(1)
200
∑IVSS
Total current out of sum of all VSS ground lines (sink)(1)
200
IVDD
Maximum current into each VDD power pin
(source)(1)
100
(sink)(1)
100
IVSS
Maximum current out of each VSS ground pin
IIO
Output current sunk by any I/O and control pin
∑I(PIN)
IINJ(PIN)(3)(4)
∑|IINJ(PIN)|
20
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins
Injected current on FT_xx, TT_xx, RST pins
Total injected current (sum of all I/Os and control
Unit
mA
120
(2)
120
-5/+0
pins)(5)
±25
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must
always be connected to the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 30 for the minimum
allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN) is the absolute sum of the negative
injected currents (instantaneous values).
152/334
DS13086 Rev 6
STM32U585xx
Electrical characteristics
Table 32. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Value
Storage temperature range
–65 to +150
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
140
Unit
°C
Table 33. General operating conditions
Symbol
Parameter
VDD
Standard operating
voltage
Conditions
Min
Typ
Max
HSLV(1) = 0
1.71(2)
-
3.6
HSLV = 1
1.71(2)
-
2.7
Supply voltage for
the internal SMPS
VDDSMPS
step-down
converter
VDDIO2
Supply voltage for
PG[15:2] I/Os
-
VDD
At least one I/O in
PG[15:2] used, HSLV = 0
1.08
-
3.6
At least one I/O in
PG[15:2] used, HSLV = 1
1.08
-
2.7
0
-
3.6
3.0
-
3.6
0
-
3.6
COMP used
1.58
-
3.6
DAC or OPAMP used
1.60
ADC used
1.62
-
3.6
VREFBUF used
(normal mode)
1.8
-
3.6
0
-
3.6
1.65(3)
-
3.6
PG[15:2] I/Os not used
VDDUSB
VDDA
USB supply voltage
Analog supply
voltage
USB used
USB not used
ADC, DAC, COMP,
OPAMP, and VREFBUF
not used
VBAT
Backup domain
supply voltage
-
Unit
DS13086 Rev 6
V
3.6
153/334
299
Electrical characteristics
STM32U585xx
Table 33. General operating conditions (continued)
Symbol
VIN
VCORE
fHCLK
Parameter
I/O input voltage
Internal regulator
ON
AHB clock
frequency
APB1, APB2,
APB3 clock
(x = 1, 2, 3) frequency
fPCLKx
Conditions
Min
Typ
Max
All I/Os except FT_c and
TT_xx pins
-0.3
-
Min(min(VDD, VDDA, VDDUSB,
VDDIO2) +3.6, 5.5)(4)(5)
Input voltage on FT_t pins
in VBAT mode
-0.3
-
Min(min(VBAT, VDDA,
VDDUSB, VDDIO2)+ 3.6,
5.5)(4)(5)
FT_c I/Os
-0.3
-
5.0
TT_xx I/Os
-0.3
-
VDDIOx + 0.3
Range 1
1.15
1.21
1.27
Range 2
1.05
1.1
1.15
Range 3
0.95
1.0
1.05
Range 4
0.81
0.9
0.99
Range 1
-
-
160
Range 2
-
-
110
Range 3
-
-
55
Range 4
-
-
25
Range 1
-
-
160
Range 2
-
-
110
Range 3
-
-
55
Range 4
-
-
25
Unit
V
MHz
LQFP48
UFQFPN48
LQFP64
PD
Power dissipation
at TA = 85 °C
for suffix 6(6)
WLCSP90
LQFP100
UFBGA132
LQFP144
See Section 6.9: Package thermal
characteristics for application appropriate
thermal resistance and package. The power
dissipation is then calculated according to
ambient temperature (TA) and maximum
junction temperature (TJ) and selected thermal
resistance.
UFBGA169
mW
LQFP48
UFQFPN48
LQFP64
PD
Power dissipation
at TA = 125 °C
for suffix 3(6)
WLCSP90
LQFP100
UFBGA132
LQFP144
See Section 6.9: Package thermal
characteristics for application appropriate
thermal resistance and package. The power
dissipation is then calculated according
ambient temperature (TA) and maximum
junction temperature (TJ) and selected thermal
resistance.
UFBGA169
154/334
DS13086 Rev 6
STM32U585xx
Electrical characteristics
Table 33. General operating conditions (continued)
Symbol
Parameter
Conditions
Typ
Max
Maximum power
dissipation
–40
85
Low-power dissipation(7)
–40
105
Ambient
temperature
for suffix 3
Maximum power
dissipation
–40
125
Low-power dissipation(7)
–40
130
Junction
temperature range
Suffix 6 version
–40
105
Suffix 3 version
–40
130
Ambient
temperature
for suffix 6
TA
TJ
Min
Unit
°C
1. HSLV means high-speed low-voltage mode (refer to the GPIO section of the product reference manual).
2. When RESET is released, the functionality is guaranteed down to VBORx min.
3. In VBAT mode, the functionality is guaranteed down to VBOR_VBAT min.
4. This formula has to be applied only on the power supplies related to the I/O structure described by the pin definition table.
The maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDDUSB, VDDIO2)+3.6 V, and 5.5V.
5. For operation with voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors
must be disabled.
6. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Section 6.9: Package thermal
characteristics).
7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Section 6.9:
Package thermal characteristics).
5.3.2
Operating conditions at power-up/power-down
The parameters given in the table below are derived from tests performed under the
ambient temperature condition summarized in Table 33.
Table 34. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Max
-
0
∞
ULPMEN = 0 (default value)
20
∞
Standby mode with ULPMEN = 1
250
∞
VDD rise-time rate
tVDD
5.3.3
VDD fall-time rate
Unit
µs/V
ms/V
Embedded reset and power control block characteristics
The parameters given in the table below are derived from tests performed under the
ambient temperature conditions summarized in Table 33.
Table 35. Embedded reset and power control block characteristics(1)
Symbol
tRSTTEMPO(2)
Parameter
Conditions
Reset temporization after BOR0 is
detected
VDD rising
DS13086 Rev 6
Min
Typ
Max
Unit
-
-
900
μs
155/334
299
Electrical characteristics
STM32U585xx
Table 35. Embedded reset and power control block characteristics(1) (continued)
Symbol
VBOR0
Parameter
Conditions
Brownout reset threshold 0
VBOR1
Brownout reset threshold 1
VBOR2
Brownout reset threshold 2
VBOR3
Brownout reset threshold 3
VBOR4
Brownout reset threshold 4
VPVD0
Programmable voltage detector
threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Min
Typ
Max
Rising edge
1.6
1.66
1.71
Falling edge, range 1, 2, 3
1.58
1.64
1.69
Falling edge, range 4 and
low-power modes
1.58
1.64
1.69
Rising edge
1.98
2.08
2.17
Falling edge
1.9
2.00
2.1
Rising edge
2.18
2.29
2.39
Falling edge
2.08
2.18
2.25
Rising edge
2.48
2.59
2.7
Falling edge
2.39
2.5
2.61
Rising edge
2.76
2.88
3.0
Falling edge
2.67
2.79
2.9
Rising edge
2.03
2.13
2.23
Falling edge
1.93
2.03
2.12
Rising edge
2.18
2.29
2.39
Falling edge
2.08
2.18
2.28
Rising edge
2.33
2.44
2.55
Falling edge
2.23
2.34
2.44
Rising edge
2.47
2.59
2.7
Falling edge
2.39
2.50
2.61
Rising edge
2.6
2.72
2.83
Falling edge
2.5
2.62
2.73
Rising edge
2.76
2.88
3.0
Falling edge
2.66
2.78
2.9
Rising edge
2.83
2.96
3.08
Falling edge
2.76
2.88
3.0
Unit
V
Vhyst_BOR0
Hysteresis voltage of BOR0
-
-
20
-
Vhyst_BOR_PVD
Hysteresis voltage of BOR
(except BOR0) and PVD
-
-
80
-
tBOR_PVD
BOR/PVD sampling period
ULPMEN = 1
-
30
55
ms
Additional BOR0 consumption if
ULPMEN = 0 versus ULPMEN = 1
Standby mode
-
60
-
nA
BOR(3) (except BOR0) and PVD
consumption from VDD(4)
-
-
1
1.5
µA
VBAT brownout reset threshold
-
1.58
-
1.65
V
_sampling
IDD_BOR0(2)
IDD_BOR_PVD(2)
VBOR_VBAT
156/334
DS13086 Rev 6
mV
STM32U585xx
Electrical characteristics
Table 35. Embedded reset and power control block characteristics(1) (continued)
Symbol
Parameter
tVBAT_BOR
Conditions
VBAT BOR sampling period
in VBAT mode
_sampling
Min
Typ
Max
Unit
-
0.5
2.5
s
Rising edge
1.61
1.68
1.75
Falling edge
1.58
1.65
1.71
Rising edge
1.77
1.86
1.95
Falling edge
1.73
1.82
1.9
MONEN = 0(5)
VAVM1
VDDA voltage monitor 1 threshold
VAVM2
VDDA voltage monitor 2 threshold
VIO2VM
VDDIO2 voltage monitor threshold
-
0.96
1.01
1.05
VUVM
VDDUSB voltage monitor threshold
-
1.15
1.22
1.28
Vhyst_AVM
Hysteresis of VDDA voltage monitor
-
-
40
-
IDD_VM(2)
Voltage monitor consumption from
VDD (AVM1, AVM2, IO2VM or UVM
single instance)
-
-
0.4
0.6
VDDA voltage monitor consumption
from VDDA (resistor bridge)
-
IDD_AVM_A(2)
V
mV
µA
-
1.25
1.85
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Specified by design. Not tested in production
3. BOR0 is enabled in all modes (except Shutdown), and its consumption is therefore included in the supply current
characteristics tables.
4. This is also the consumption saved in Standby mode when ULPMEN = 1.
5. VBAT brownout reset monitoring is discontinuous when MONEN = 0 in PWR_BDCR1, and is continuous when MONEN = 1.
5.3.4
Embedded voltage reference
The parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Table 33.
Table 36. Embedded internal voltage reference
Symbol
VREFINT(1)
tS_vrefint(2)(3)
tstart_vrefint
(3)
Parameter
Conditions
Internal reference voltage
Min
Typ
Max
Range 1, 2, 3
1.175
1.215
1.255
Range 4 and
low-power modes
1.170
1.215
1.260
4
-
-
Unit
V
ADC sampling time when reading
the internal reference voltage
-
Start time of reference voltage buffer
when the ADC is enabled
-
-
4
6
-
-
1.5
2.1
µA
µs
IDD(VREFINTBUF) VREFINT buffer consumption from
(3)
VDD when converted by the ADC
∆VREFINT(4)
Internal reference voltage spread
over the temperature range
VDD = 3 V
-
6
11.5
mV
TCoeff(4)
Average temperature coefficient
–40°C < TJ < +130 °C
-
40
125
ppm/°C
Long term stability
1000 hours, TJ = 25 °C
-
400
1000
ppm
ACoeff
(3)
DS13086 Rev 6
157/334
299
Electrical characteristics
STM32U585xx
Table 36. Embedded internal voltage reference (continued)
Symbol
VDDCoeff
Parameter
(4)
Conditions
Average voltage coefficient
3.0 V ≤ VDD ≤ 3.6 V
Min
Typ
Max
Unit
-
500
2900
ppm/V
VREFINT_DIV1(3)
1/4 reference voltage
-
24
25
26
(3)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(3)
3/4 reference voltage
-
74
75
76
VREFINT_DIV2
%
VREFINT
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
3. Specified by design. Not tested in production.
4. Evaluated by characterization. Not tested in production.
Figure 27. VREFINT versus temperature
MSv69159V1
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Section 5.1.7: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
158/334
•
All I/O pins are in analog input mode.
•
All peripherals are disabled except when explicitly mentioned.
•
The Flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the tables “Number of wait states according
to CPU clock (HCLK) frequency” available in the product reference manual).
•
When the peripherals are enabled, fPCLK = fHCLK.
DS13086 Rev 6
STM32U585xx
•
Electrical characteristics
The voltage scaling range is adjusted to fHCLK frequency as follows:
–
Voltage range 1 for 110 MHz < fHCLK ≤ 160 MHz
–
Voltage range 2 for 55 MHz < fHCLK ≤ 110 MHz
–
Voltage range 3 for 25 MHz < fHCLK ≤ 55 MHz
–
Voltage range 4 for fHCLK ≤ 25 MHz
The parameters given in the tables below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33.
DS13086 Rev 6
159/334
299
Symbol
Conditions
Parameter
-
fHCLK = fMSI,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
DS13086 Rev 6
Supply
current in
(Run) Run mode
IDD
fHCLK = PLL on HSE 16 MHz in
bypass mode,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
fHCLK = fHSE bypass mode,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
2. Evaluated by characterization. Not tested in production.
Voltage
scaling
Range 4
Range 1
Range 2
Range 3
fHCLK 25°C 55°C 85°C 105°C 125°C 30°C
(MHz)
Unit
55°C
85°C 105°C 125°C
24
1.75
2.10
3.10
4.65
7.70
2.60
3.40
6.40
12.00 21.00
16
1.30
1.65
2.65
4.20
7.25
2.10
2.90
5.90
11.00
20.00
12
1.05
1.40
2.40
3.95
7.00
1.80
2.70
5.60
11.00
20.00
4
0.49
0.82
1.85
3.40
6.40
1.20
2.00
5.00
9.80
19.00
2
0.37
0.70
1.70
3.25
6.30
1.10
1.90
4.90
9.60
19.00
1
0.30
0.63
1.65
3.20
6.20
0.94
1.80
4.80
9.60
19.00
0.4
0.26
0.59
1.60
3.15
6.15
0.89
1.80
4.80
9.50
19.00
0.1
0.24
0.57
1.55
3.15
6.15
0.87
1.80
4.70
9.50
19.00
160
13.50 14.50 16.00 18.50 23.50 17.00 19.00 26.00 37.00 57.00
140
12.00 12.50 14.50 17.00 21.50 15.00 17.00 24.00 35.00 55.00
120
10.50 11.00 13.00 15.50 20.00 14.00 15.00 23.00 33.00 53.00
110
8.80
9.35 10.50 1300
72
6.00
6.50 10.00 10.00 14.00
7.80
9.30
15.00 23.00 38.00
64
5.40
5.95
9.50
9.50
13.50
7.10
8.70
14.00 22.00 38.00
55
4.25
4.65
5.90
7.75
11.50
5.60
6.70
11.00 17.00 29.00
32
2.70
3.10
4.30
6.10
9.60
3.80
5.00
8.80
mA
16.50 11.00 13.00 18.00 26.00 41.00
15.00 27.00
STM32U585xx
1. The current consumption from SRAM is similar.
Max(2)
Typ
Electrical characteristics
160/334
Table 37. Current consumption in Run mode on LDO, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON(1)
Symbol
Parameter
-
fHCLK = fMSI,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
DS13086 Rev 6
Supply
current in
(Run) Run mode
IDD
fHCLK = PLL on HSE 16 MHz in
bypass mode,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
Voltage
scaling
Range 4
Range 1
Range 2
Range 3
1. The current consumption from SRAM is similar.
2. Evaluated by characterization. Not tested in production.
3. The maximum value is at VDD = 1.71 V in Run mode on SMPS.
Unit
fHCLK
(MHz)
25°C
55°C
85°C 105°C 125°C 30°C
55°C
85°C 105°C 125°C
24
1.15
1.35
2.05
3.10
5.20
2.30
2.40
4.50
7.80
15.00
16
0.88
1.10
1.75
2.80
4.90
1.60
2.00
4.20
7.50
15.00
12
0.62
0.97
1.60
2.65
4.70
1.30
1.80
4.00
7.30
14.00
4
0.34
0.56
1.20
2.20
4.40
0.77
1.40
3.50
6.80
14.00
2
0.22
0.46
1.15
2.20
4.25
0.64
1.30
3.50
6.80
14.00
1
0.18
0.40
1.10
2.15
4.20
0.60
1.20
3.40
6.70
14.00
0.4
0.16
0.36
1.05
2.10
4.20
0.57
1.10
3.40
6.70
14.00
0.1
0.15
0.34
1.05
2.10
4.20
0.55
1.10
3.40
6.70
14.00
160
10.50 11.00 12.50 14.50
18.00 14.00 15.00 21.00 28.00 44.00
140
9.30
9.85
11.00 13.00
16.50 13.00 14.00 19.00 27.00 42.00
120
8.50
9.05
10.50 12.50
16.50 11.00 13.00 18.00 26.00 42.00
110
6.95
7.40
8.55
10.00
13.00
8.90
9.90
14.00 20.00 32.00
72
4.35
4.70
5.65
7.10
9.80
6.00
6.80
11.00 17.00 28.00
64
3.95
4.30
5.25
6.65
9.40
5.40
6.30
11.00 16.00 27.00
55
3.05
3.40
4.25
5.60
7.95
4.10
4.90
7.90
13.00 21.00
32
1.85
2.10
2.85
3.95
6.15
2.70
3.40
6.20
11.00
19.00
mA
161/334
Electrical characteristics
fHCLK = fHSE bypass mode,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
Max at 1.71 V ≤ VDD ≤ 3.6 V(2)(3)
Typ at VDD = 1.8 V
Conditions
STM32U585xx
Table 38. Current consumption in Run mode on SMPS, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON(1)
Symbol
Parameter
-
fHCLK = fMSI,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
DS13086 Rev 6
Supply
current in
(Run) Run mode
IDD
fHCLK = PLL on HSE 16 MHz in
bypass mode,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
fHCLK = fHSE bypass mode,
all peripherals and AHB/APB
disabled,
Flash bank 2 in power down,
all SRAMs enabled
Max at VDD = 3.0 V(2)
Typ at VDD = 3.0 V
Conditions
Voltage
scaling
Range 4
Range 1
Range 2
Range 3
Unit
fHCLK
(MHz)
25°C
55°C
85°C 105°C 125°C 30°C
55°C
85°C 105°C 125°C
24
0.73
0.91
1.30
2.00
3.45
2.30
2.40
3.10
4.80
9.10
16
0.60
0.71
1.15
1.80
3.25
1.60
1.90
2.70
4.60
8.80
12
0.45
0.65
1.05
1.70
3.15
1.30
1.60
2.60
4.50
8.70
4
0.23
0.38
0.82
1.50
2.80
0.60
0.97
2.30
4.30
8.40
2
0.17
0.31
0.74
1.40
2.85
0.49
0.84
2.20
4.20
8.40
1
0.15
0.29
0.73
1.40
2.80
0.46
0.81
2.20
4.20
8.40
0.4
0.13
0.27
0.72
1.40
2.75
0.44
0.79
2.20
4.20
8.30
0.1
0.12
0.26
0.72
1.35
2.75
0.44
0.78
2.20
4.10
8.30
160
7.15
7.55
8.55
9.90
12.50 14.00 15.00 16.00 19.00 28.00
140
6.35
6.75
7.70
9.05
11.50 13.00 13.00 15.00 17.00 27.00
120
5.80
6.20
7.20
8.60
11.00 11.00 12.00 13.00 17.00 26.00
110
4.40
4.70
5.40
6.35
8.20
8.90
9.20
11.00 13.00 19.00
72
3.05
3.35
4.05
5.10
7.00
6.00
6.20
7.40
11.00
18.00
64
2.80
3.10
3.80
4.80
6.70
5.40
5.70
6.90
11.00
18.00
55
2.20
2.45
3.05
3.95
5.55
4.00
4.40
5.40
7.90
14.00
32
1.40
1.60
2.15
2.95
4.50
2.60
3.00
4.30
6.80
13.00
Electrical characteristics
162/334
Table 39. Current consumption in Run mode on SMPS, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON, VDD = 3.0 V(1)
mA
1. The current consumption from SRAM is similar.
STM32U585xx
2. Evaluated by characterization. Not tested in production.
Symbol
Conditions
Parameter
Voltage
scaling
-
Supply
current in
(Run) Run mode
IDD
fHCLK = fMSI = 24 MHz,
all peripherals disabled,
Flash bank 2 in power down,
SRAM2 enabled,
SRAM1, SRAM3, SRAM4 in
power down
Range 4
Typ
Typ
Unit
Unit
Code
1.8 V
3V
3.3 V
1.8 V
3V
3.3 V
Reduced Code
1.65
1.65
1.65
68.8
68.8
68.8
CoreMark
1.55
1.60
1.60
64.6
66.7
66.7
SecureMark
1.80
1.80
1.80
75.0
75.0
75.0
Dhrystone 2.1
1.65
1.65
1.65
68.8
68.8
68.8
Fibonacci
1.30
1.30
1.30
54.2
54.2
54.2
while(1)
1.20
1.20
1.20
50.0
50.0
50.0
mA
STM32U585xx
Table 40. Typical current consumption in Run mode on LDO, with different codes
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
µA/
MHz
Symbol
DS13086 Rev 6
Table 41. Typical current consumption in Run mode on LDO, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions
Parameter
Supply
current in
(Run) Run mode
IDD
-
Range 4
Typ
Unit
Unit
Code
1.8 V
3V
3.3 V
1.8 V
3V
3.3 V
Reduced Code
1.75
1.75
1.75
72.9
72.9
72.9
CoreMark
1.65
1.65
1.65
68.8
68.8
68.8
SecureMark
1.85
1.85
1.90
77.1
77.1
79.2
Dhrystone 2.1
1.75
1.75
1.75
72.9
72.9
72.9
Fibonacci
1.40
1.40
1.40
58.3
58.3
58.3
While(1)
1.30
1.30
1.30
54.2
54.2
54.2
mA
µA/
MHz
163/334
Electrical characteristics
fHCLK = fMSI = 24 MHz,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled
Voltage
scaling
Typ
Symbol
Conditions
Parameter
-
fHCLK = fPLL = 160 MHz,
PLL on HSE 16 MHz in bypass
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled
DS13086 Rev 6
Supply
current in
(Run) Run mode
IDD
fHCLK = fPLL = 110 MHz,
PLL on HSE 16 MHz in bypass
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled
fHCLK = fHSE = 55 MHz,
all peripherals disable,
Flash bank 2 in power down,
all SRAMs enabled
Voltage
scaling
Range 1
Range 2
Range 3
Typ
Typ
Unit
Unit
Code
1.8 V
3V
3.3 V
1.8 V
3V
3.3 V
Reduced Code
13.50
13.50
13.50
84.4
84.4
84.4
CoreMark
13.50
13.50
13.50
84.4
84.4
84.4
SecureMark
15.00
15.00
15.00
93.8
93.8
93.8
Dhrystone 2.1
14.00
14.00
14.00
87.5
87.5
87.5
Fibonacci
10.50
10.50
10.50
65.6
65.6
65.6
While(1)
10.00
10.00
10.00
62.5
62.5
62.5
Reduced Code
8.80
8.80
8.85
80.0
80.0
80.5
CoreMark
8.60
8.65
8.65
78.2
78.6
78.6
SecureMark
9.65
9.70
9.70
87.7
88.2
88.2
Dhrystone 2.1
9.05
9.05
9.10
82.3
82.3
82.7
Fibonacci
6.80
6.80
6.80
61.8
61.8
61.8
While(1)
6.55
6.55
6.60
59.5
59.5
60.0
Reduced Code
4.15
4.25
4.25
75.5
77.3
77.3
CoreMark
4.15
4.20
4.25
75.5
76.4
77.3
SecureMark
4.65
4.70
4.75
84.5
85.5
86.4
Dhrystone 2.1
4.35
4.40
4.40
79.1
80.0
80.0
Fibonacci
3.25
3.30
3.35
59.1
60.0
60.9
While(1)
3.05
3.10
3.15
55.5
56.4
57.3
mA
Electrical characteristics
164/334
Table 41. Typical current consumption in Run mode on LDO, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
µA/
MHz
1. The current consumption from SRAM is similar.
STM32U585xx
Symbol
IDD
(Run)
Conditions
Parameter
Voltage
scaling
-
Supply
current in
Run mode
fHCLK = fMSI = 24 MHz,
all peripherals disabled,
Flash bank 2 in power down,
SRAM2 enabled,
SRAM1, SRAM3, SRAM4 in
power down
Range 4
Typ
Typ
Unit
Unit
Code
1.8 V
3V
3.3 V
1.8 V
3V
3.3 V
Reduced Code
1.10
0.69
0.64
45.8
28.5
26.5
CoreMark
1.05
0.68
0.61
43.8
28.3
25.4
SecureMark
1.20
0.79
0.72
50.0
32.9
30.0
Dhrystone 2.1
1.10
0.69
0.64
45.8
28.5
26.7
Fibonacci
0.89
0.59
0.51
37.1
24.4
21.3
while(1)
0.77
0.54
0.47
32.1
22.3
19.5
mA
STM32U585xx
Table 42. Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
µA/
MHz
Symbol
DS13086 Rev 6
Table 43. Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON(1)
IDD
(Run)
Conditions
Parameter
-
Supply
current in
Run mode
Range 4
Typ
Unit
Unit
Code
1.8 V
3V
3.3 V
1.8 V
3V
3.3 V
Reduced Code
1.15
0.73
0.68
47.9
30.2
28.3
CoreMark
1.10
0.72
0.66
45.8
30.0
27.5
SecureMark
1.25
0.85
0.77
52.1
35.2
32.1
Dhrystone 2.1
1.15
0.75
0.69
47.9
31.0
28.8
Fibonacci
0.97
0.65
0.58
40.4
26.9
24.2
while(1)
0.89
0.61
0.55
36.9
25.2
22.7
mA
µA/
MHz
165/334
Electrical characteristics
fHCLK = fMSI = 24 MHz,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled
Voltage
scaling
Typ
Symbol
Conditions
Parameter
-
fHCLK = fPLL = 160 MHz,
PLL on HSE 16 MHz in bypass
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled
DS13086 Rev 6
IDD
(Run)
Supply
current in
Run mode
fHCLK = fPLL = 110 MHz,
PLL on HSE 16 MHz in bypass
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled
fHCLK = fHSE = 55 MHz,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled
Voltage
scaling
Range 1
Range 2
Range 3
Typ
Typ
Unit
Unit
Code
1.8 V
3V
3.3 V
1.8 V
3V
3.3 V
Reduced Code
10.50
7.15
6.70
65.6
44.7
41.9
CoreMark
10.50
7.05
6.55
65.6
44.1
40.9
SecureMark
11.50
7.85
7.35
71.9
49.1
45.9
Dhrystone 2.1
11.00
7.40
6.90
68.8
46.3
43.1
Fibonacci
8.25
5.65
5.30
51.6
35.3
33.1
while(1)
7.90
5.45
5.10
49.4
34.1
31.9
Reduced Code
6.40
4.40
4.15
58.2
40.0
37.7
CoreMark
6.25
4.30
4.05
56.8
39.1
36.8
SecureMark
7.00
4.80
4.50
63.6
43.6
40.9
Dhrystone 2.1
6.55
4.50
4.25
59.5
40.9
38.6
Fibonacci
5.00
3.50
3.30
45.5
31.8
30.0
while(1)
4.80
3.35
3.20
43.6
30.5
29.1
Reduced Code
3.05
2.20
2.15
55.5
40.0
39.1
CoreMark
3.05
2.20
2.10
55.5
40.0
38.2
SecureMark
3.40
2.45
2.30
61.8
44.5
41.8
Dhrystone 2.1
3.20
2.30
2.20
58.2
41.8
40.0
Fibonacci
2.40
1.80
1.75
43.6
32.7
31.8
while(1)
2.30
1.70
1.65
41.8
30.9
30.0
mA
Electrical characteristics
166/334
Table 43. Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
µA/
MHz
1. The current consumption from SRAM is similar.
STM32U585xx
Symbol
Conditions
Parameter
Voltage
scaling
-
fHCLK = fMSI,
all peripherals disabled
DS13086 Rev 6
Supply
IDD current in
(Sleep) Sleep
mode
Range 4
Range 1
fHCLK = PLL on HSE 16 MHz
in bypass mode,
all peripherals disabled
Range 2
fHCLK = fHSE bypass mode,
all peripherals disabled
Max(1)
Typ
Range 3
25°C
55°C
85°C
24
0.61
0.94
1.95
3.50
16
0.49
0.81
1.80
12
0.43
0.75
4
0.25
2
105°C 125°C
30°C
55°C
85°C
105°C 125°C
6.50
1.20
2.10
5.00
9.70
19.00
3.35
6.40
1.10
1.90
4.90
9.50
19.00
1.75
3.30
6.30
0.95
1.90
4.80
9.50
19.00
0.58
1.55
3.10
6.15
0.76
1.70
4.60
9.30
19.00
0.22
0.55
1.55
3.10
6.10
0.72
1.60
4.60
9.30
19.00
1
0.21
0.53
1.55
3.05
6.10
0.71
1.60
4.60
9.20
19.00
0.4
0.19
0.52
1.50
3.05
6.05
0.69
1.60
4.50
9.20
19.00
0.1
0.19
0.52
1.50
3.05
6.10
0.69
1.60
4.50
9.20
19.00
160
4.35
4.95
6.65
9.10
13.50
6.10
8.10
15.00
26.00
46.00
140
3.90
4.50
6.15
8.65
13.50
5.60
7.60
15.00
25.00
46.00
120
3.45
4.05
5.75
8.20
13.00
5.10
7.10
14.00
25.00
46.00
110
3.25
3.75
5.20
7.35
11.50
4.50
6.00
12.00
20.00
35.00
72
2.15
2.65
4.05
6.15
10.00
3.30
4.80
9.90
18.00
34.00
64
2.00
2.50
3.90
6.00
9.95
3.20
4.70
9.80
18.00
33.00
55
1.45
1.85
3.05
4.85
8.40
2.30
3.40
7.30
14.00
26.00
32
1.00
1.40
2.60
4.40
7.85
1.80
2.90
6.80
13.00
25.00
mA
167/334
Electrical characteristics
1. Evaluated by characterization. Not tested in production.
Unit
fHCLK
(MHz)
STM32U585xx
Table 44. Current consumption in Sleep mode on LDO, Flash memory in power down
Symbol
Parameter
-
fHCLK = fMSI,
all peripherals disabled
DS13086 Rev 6
IDD
(Sleep)
Voltage
scaling
Range 4
Supply
current in
Sleep mode
Range 1
fHCLK = PLL on HSE 16 MHz
in bypass mode,
all peripherals disabled
Range 2
fHCLK = fHSE bypass mode,
all peripherals disabled
Max at 1.71 V ≤ VDD ≤ 3.6 V(1) (2)
Typ at VDD = 1.8 V
Conditions
Range 3
fHCLK
(MHz)
Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C
85°C
105°C 125°C
24
0.41
0.63
1.25
2.25
4.40
0.73
1.40
3.60
6.80
14.00
16
0.27
0.53
1.20
2.20
4.30
0.57
1.30
3.50
6.70
14.00
12
0.24
0.48
1.15
2.20
4.25
0.53
1.20
3.50
6.70
14.00
4
0.14
0.34
1.05
2.05
4.10
0.42
1.10
3.40
6.50
13.00
2
0.12
0.34
1.05
2.05
4.10
0.39
1.00
3.40
6.50
13.00
1
0.11
0.33
1.05
2.05
4.10
0.38
0.99
3.40
6.50
13.00
0.4
0.10
0.31
1.05
2.05
4.10
0.38
0.97
3.40
6.50
13.00
0.1
0.10
0.31
1.05
2.05
4.10
0.37
0.97
3.40
6.50
13.00
160
3.50
3.95
5.20
7.00
10.50
4.80
6.20
12.00
19.00
34.00
140
3.10
3.60
4.80
6.60
10.00
4.30
5.80
12.00
19.00
34.00
120
2.80
3.25
4.50
6.30
9.70
4.00
5.40
11.00
19.00
33.00
110
2.60
3.00
4.10
5.75
8.65
3.50
4.70
8.80
15.00
26.00
72
1.65
2.00
2.90
4.30
7.00
2.40
3.50
7.40
13.00
24.00
64
1.55
1.90
2.80
4.20
6.90
2.30
3.40
7.30
13.00
24.00
55
1.10
1.40
2.25
3.55
5.90
1.70
2.50
5.60
9.80
19.00
32
0.85
1.10
1.90
3.15
5.60
1.40
2.20
5.10
9.40
18.00
Electrical characteristics
168/334
Table 45. Current consumption in Sleep mode on SMPS, Flash memory in power down
mA
1. Evaluated by characterization. Not tested in production.
2. The maximum value is at VDD = 1.71 V in Sleep mode on SMPS.
STM32U585xx
Symbol
Parameter
-
fHCLK = fMSI,
all peripherals disabled
DS13086 Rev 6
IDD
(Sleep)
Voltage
scaling
Range 4
Supply
current in
Sleep mode
Range 1
fHCLK = PLL on HSE 16 MHz
in bypass mode,
all peripherals disabled
Range 2
fHCLK = fHSE bypass mode,
all peripherals disabled
Range 3
fHCLK
(MHz)
Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C
85°C
105°C 125°C
24
0.26
0.40
0.83
1.50
2.80
0.66
1.20
2.20
4.20
8.20
16
0.20
0.33
0.77
1.40
2.80
0.54
0.99
2.10
4.10
8.20
12
0.17
0.31
0.75
1.40
2.75
0.49
0.92
2.10
4.10
8.10
4
0.10
0.24
0.66
1.30
2.70
0.30
0.71
2.00
3.90
8.10
2
0.08
0.22
0.66
1.30
2.65
0.27
0.68
2.00
3.90
8.00
1
0.08
0.22
0.66
1.30
2.65
0.26
0.67
2.00
3.90
8.00
0.4
0.07
0.21
0.65
1.30
2.65
0.26
0.64
2.00
3.90
8.00
0.1
0.07
0.21
0.65
1.30
2.65
0.26
0.65
2.00
3.90
8.00
160
2.50
2.85
3.75
5.05
7.40
4.50
5.00
7.40
13.00
22.00
140
2.25
2.60
3.50
4.75
7.15
4.00
4.60
7.20
12.00
22.00
120
2.05
2.40
3.25
4.55
6.90
3.60
4.20
6.90
12.00
21.00
110
1.95
2.25
3.00
4.10
6.05
3.20
3.60
5.70
9.30
17.00
72
1.30
1.55
2.20
3.20
5.10
2.20
2.60
4.80
8.30
16.00
64
1.20
1.45
2.15
3.15
5.00
2.00
2.50
4.70
8.20
16.00
55
0.92
1.10
1.70
2.55
4.15
1.40
1.90
3.60
6.30
12.00
32
0.70
0.89
1.45
2.30
3.95
1.10
1.60
3.30
6.00
12.00
mA
169/334
Electrical characteristics
1. Evaluated by characterization. Not tested in production.
Max at VDD = 3.0 V(1)
Typ at VDD = 3.0 V
Conditions
STM32U585xx
Table 46. Current consumption in Sleep mode on SMPS,
Flash memory in power down, VDD = 3.0 V
Conditions
Symbol
Parameter
-
IDD
(SRAM1)
LDO
IDD
(SRAM3)
DS13086 Rev 6
IDD
(SRAM1)
SMPS,
VDD = 3.0 V
IDD
(SRAM3)
Typ
Voltage
scaling
fHCLK
(MHz)
Max
Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
Range 4
24
0.02
0.05
0.16
0.33
0.68
0.06
0.15
0.48
1.00
2.05
SRAM1 supply current in
Range 1
Run/Sleep mode (SRAM1PD = 1
Range 2
versus SRAM1PD = 0)
160
0.04
0.10
0.28
0.55
1.07
0.15
0.30
0.83
1.65
3.20
110
0.03
0.08
0.23
0.47
0.94
0.11
0.24
0.70
1.41
2.82
Range 3
55
0.02
0.06
0.19
0.40
0.81
0.08
0.19
0.58
1.20
2.43
Range 4
24
0.04
0.13
0.41
0.87
1.78
0.15
0.39
1.24
2.62
5.34
SRAM3 supply current in
Range 1
Run/Sleep mode (SRAM3PD = 1
Range 2
versus SRAM3PD = 0)
160
0.11
0.26
0.73
1.44
2.80
0.39
0.79
2.18
4.31
8.40
110
0.08
0.21
0.60
1.22
2.44
0.28
0.62
1.81
3.67
7.32
Range 3
55
0.06
0.16
0.50
1.04
2.09
0.20
0.49
1.50
3.11
6.28
Range 4
24
0.01
0.02
0.06
0.10
0.26
0.02
0.06
0.19
0.31
0.78
SRAM1 supply current in
Range 1
Run/Sleep mode (SRAM1PD = 1
Range 2
versus SRAM1PD = 0)
160
0.02
0.05
0.14
0.28
0.55
0.07
0.15
0.43
0.84
1.64
110
0.01
0.04
0.12
0.23
0.46
0.05
0.12
0.36
0.70
1.37
Range 3
55
0.01
0.03
0.09
0.18
0.36
0.04
0.09
0.27
0.55
1.09
Range 4
24
0.02
0.05
0.17
0.32
0.69
0.06
0.16
0.51
0.95
2.07
SRAM3 supply current in
Range 1
Run/Sleep mode (SRAM3PD = 1
Range 2
versus SRAM3PD = 0)
160
0.06
0.13
0.37
0.73
1.43
0.20
0.40
1.12
2.20
4.28
100
0.04
0.10
0.30
0.61
1.19
0.14
0.31
0.91
1.84
3.57
Range 3
55
0.03
0.08
0.23
0.48
0.95
0.09
0.23
0.70
1.45
2.86
Electrical characteristics
170/334
Table 47. SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS
mA
STM32U585xx
Conditions
Symbol
Parameter
(SRAM1)
(SRAM3)
Unit
fHCLK
(MHz)
Range 4
24
0.01
0.03
0.11
0.17
0.43
0.04
0.11
0.34
0.55
1.37
SRAM1 supply current in
Range 1
Run/Sleep mode (SRAM1PD = 1
Range 2
versus SRAM1PD = 0)
160
0.03
0.09
0.24
0.47
0.91
0.13
0.27
0.75
1.47
2.88
110
0.02
0.07
0.20
0.39
0.76
0.09
0.21
0.63
1.23
2.41
Range 3
55
0.02
0.05
0.15
0.31
0.60
0.06
0.16
0.48
0.97
1.91
Range 4
24
0.03
0.09
0.28
0.53
1.15
0.11
0.28
0.89
1.66
3.62
SRAM3 supply current in
Range 1
Run/Sleep mode (SRAM3PD = 1
Range 2
versus SRAM3PD = 0)
160
0.09
0.22
0.62
1.22
2.38
0.35
0.71
1.96
3.87
7.52
100
0.06
0.17
0.51
1.02
1.98
0.24
0.54
1.60
3.22
6.26
Range 3
55
0.04
0.13
0.39
0.80
1.59
0.16
0.40
1.24
2.54
5.01
SMPS(1)
IDD
Max
Voltage
scaling
-
IDD
Typ
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
STM32U585xx
Table 47. SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS (continued)
mA
DS13086 Rev 6
1. The typical value is measured at VDD = 1.8 V. The maximum value is for 1.71 V ≤ VDD ≤ 3.6 V and is at VDD = 1.71 V in Run/Sleep mode on SMPS.
Table 48. Static power consumption of Flash banks, when supplied by LDO/SMPS
Typ
Symbol
Max
Parameter
Unit
25°C
55°C
85°C
105°C 125°C
30°C
55°C
85°C
105°C 125°C
(1)
(Flash_Bank1)
Flash bank 1 static consumption in normal mode
(PD1 = 1 versus PD1 = 0)
45.0
50.0
50.0
50.0
100.0
100.0 100.0 100.0
100.0
150.0
IDD
(1)
(Flash_Bank2)
Flash bank 2 static consumption in normal mode
(PD2 = 1 versus PD2 = 0)
45.0
50.0
50.0
50.0
100.0
100.0 100.0 100.0
100.0
150.0
One Flash bank additional static consumption in
(2) normal mode versus low-power mode
(Flash_Bank_LPM)
(LPM = 0 versus LPM = 1)
25.0
25.0
25.0
25.0
50.0
40.0
40.0
70.0
IDD
40.0
40.0
1. When one bank is in power down, this consumption is saved. When Flash memory is in power down in Sleep mode (SLEEP_PD =1 ), Bank 1 and Bank 2 are in
power down.
2. If no bank is in power-down, the Flash memory additional static consumption in normal mode versus low-power mode is 2 x IDD(Flash_Bank_LPM).
µA
171/334
Electrical characteristics
IDD
Conditions
Symbol
Max(1)
Typ
Parameter
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
110
280
770
1500
3000
400
840
2400
4500
9000
2.4
115
290
805
1600
3050
420
870
2500
4800
9200
3.0
115
295
820
1600
3150
420
890
2500
4800
9500
3.3
115
295
820
1600
3150
420
890
2500
4800
9500
3.6
115
295
825
1600
3150
420
890
2500
4800
9500
1.8
125
305
840
1650
3300
460
920
2600
5000
9900
2.4
125
315
875
1750
3400
460
950
2700
5300
11000
3.0
125
320
895
1800
3500
460
960
2700
5400
11000
3.3
130
320
890
1750
3500
470
960
2700
5300
11000
3.6
130
320
895
1800
3500
470
960
2700
5400
11000
Supply current in Stop 0 mode,
regulator in Range 4,
RTC disabled,
8-Kbyte SRAM2 + ICACHE
retained
IDD(Stop 0)
DS13086 Rev 6
Supply current in Stop 0 mode,
regulator in Range 4,
RTC disabled,
All SRAMs retained
Electrical characteristics
172/334
Table 49. Current consumption in Stop 0 mode on LDO
µA
1. Evaluated by characterization. Not tested in production.
STM32U585xx
Conditions
Symbol
Max(1)
Typ
Parameter
Supply current in Stop 0 mode,
regulator in Range 4,
RTC disabled,
8-Kbyte SRAM2 + ICACHE
retained
IDD(Stop 0)
DS13086 Rev 6
Supply current in Stop 0 mode,
regulator in Range 4,
RTC disabled,
All SRAM retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
54.5
160
535
1050
2100
200
480
1700
3200
6300
2.4
38.5
115
360
890
1650
140
350
1100
2700
5000
3.0
39.5
115
340
685
1400
150
350
1100
2100
4200
3.3
37.0
105
315
640
1300
140
320
950
2000
3900
3.6
35.5
100
295
605
1200
130
300
890
1900
3600
1.8
61.5
175
515
1200
2350
230
530
1600
3600
7100
2.4
43.5
125
400
930
1850
160
380
1200
2800
5600
3.0
44.5
125
370
770
1550
170
380
1200
2400
4700
3.3
41.5
115
345
705
1400
150
350
1100
2200
4200
3.6
40.0
110
325
665
1350
150
330
980
2000
4100
STM32U585xx
Table 50. Current consumption in Stop 0 mode on SMPS
µA
1. Evaluated by characterization. Not tested in production.
Table 51. Current consumption in Stop 1 mode on LDO
Conditions
Symbol
Max(1)
Typ
Parameter
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
82.0
250
755
1500
3000
300
750
2300
4500
9000
2.4
83.5
250
750
1500
3050
310
750
2300
4500
9200
770
2300
4700
9200
320
(2)
3.0
87.5
255
755
1550
3050
3.3
84.0
250
755
1550
3050
310
750
2300
4700
9200
3.6
95.5
255
760
1550
3050
350
770
2300
4700
9200
µA
173/334
Electrical characteristics
Supply current in Stop 1 mode,
RTC disabled,
IDD (Stop 1)
8-Kbyte SRAM2 + ICACHE
retained
Unit
VDD (V)
Conditions
Symbol
Max(1)
Typ
Parameter
Supply current in Stop 1 mode,
IDD (Stop 1) RTC disabled,
All SRAMs retained
DS13086 Rev 6
Supply current in Stop 1 mode,
RTC(3) clocked by LSI 32 kHz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 1 mode,
RTC(3) clocked by LSE
IDD(Stop 1 bypassed at 32768 Hz,
with RTC)
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 1 mode,
RTC(3) clocked by LSE quartz in
medium low-drive mode,
LSESYSEN = 0 in RCC_BDCR,
8-Kbyte SRAM2 + ICACHE
retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
89.0
255
760
1550
3100
330
770
2300
4700
9300
2.4
94.0
265
795
1600
3200
340
800
2400
4800
9600
3.0
100.0
270
815
1650
3300
370
810
2500
5000
9900
3.3
100.0
275
815
1650
3300
370
830
2500
5000
9900
3.6
110.0
275
825
1650
3300
400
830
2500
5000
9900
1.8
81.5
240
695
1400
2800
-
-
-
-
-
2.4
88.5
245
730
1450
2900
-
-
-
-
-
3.0
93.0
245
745
1500
2950
-
-
-
-
-
3.3
89.0
250
745
1500
2950
-
-
-
-
-
3.6
87.5
250
755
1500
2950
-
-
-
-
-
1.8
81.0
240
715
1450
2800
-
-
-
-
-
2.4
81.5
245
720
1450
2800
-
-
-
-
-
3.0
90.5
245
720
1450
2800
-
-
-
-
-
3.3
83.5
245
725
1450
2800
-
-
-
-
-
3.6
94.0
255
730
1450
2850
-
-
-
-
-
1.8
83.5
245
730
1500
2950
-
-
-
-
-
2.4
84.0
240
730
1500
2950
-
-
-
-
-
3.0
88.0
245
735
1500
2950
-
-
-
-
-
3.3
84.5
245
735
1500
2950
-
-
-
-
-
3.6
84.5
250
740
1500
2950
-
-
-
-
-
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
µA
STM32U585xx
1. Evaluated by characterization and not tested in production, unless otherwise specified.
Electrical characteristics
174/334
Table 51. Current consumption in Stop 1 mode on LDO (continued)
Conditions
Symbol
Typ
Parameter
Unit
VDD (V)
Wakeup clock is MSI 24 MHz
QDD(wakeup from Stop 1)
Electrical charge consumed during wakeup from
Stop 1 mode
25°C
2.08
Wakeup clock is HSI 16 MHz
3.0
2.03
Wakeup clock is MSI 1 MHz
STM32U585xx
Table 52. Current consumption during wakeup from Stop 1 mode on LDO
nAs
4.80
Table 53. Current consumption in Stop 1 mode on SMPS
Conditions
Symbol
Max(1)
Typ
Parameter
DS13086 Rev 6
Supply current in Stop 1 mode,
RTC disabled,
8-Kbyte SRAM2 + ICACHE
retained
IDD(Stop 1)
Supply current in Stop 1 mode,
RTC disabled,
All SRAMs retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
54.5
160
535
1050
2100
200
480
1700
3200
6300
2.4
38.5
115
350
890
1650
140
350
1100
2700
5000
350
1100
2100
4200
150
(2)
39.5
115
340
685
1400
3.3
37.0
105
315
640
1300
140
320
950
2000
3900
3.6
35.5
100
295
600
1200
130
300
890
1800
3600
1.8
61.5
175
515
1200
2350
230
530
1600
3600
7100
2.4
43.5
125
390
930
1850
160
380
1200
2800
5600
3.0
44.0
125
370
770
1550
160
380
1200
2400
4700
3.3
41.5
115
345
705
1400
150
350
1100
2200
4200
3.6
39.5
110
325
665
1350
150
330
980
2000
4100
µA
175/334
Electrical characteristics
3.0
Conditions
Symbol
Max(1)
Typ
Parameter
Supply current in Stop 1 mode,
RTC(3) clocked by LSI 32 kHz,
8-Kbyte SRAM2 + ICACHE
retained
DS13086 Rev 6
Supply current in Stop 1 mode,
RTC(3) clocked by LSE
IDD(Stop 1
bypassed at 32768 Hz,
with RTC)
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 1 mode,
RTC(3) clocked by LSE quartz
in medium low-drive mode,
LSESYSEN = 0 in RCC_BDCR,
8-Kbyte SRAM2 + ICACHE
retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
54.5
160
535
1050
2100
-
-
-
-
-
2.4
39.0
115
350
890
1650
-
-
-
-
-
3.0
40.0
115
340
685
1400
-
-
-
-
-
3.3
37.5
110
315
640
1300
-
-
-
-
-
3.6
36.0
100
295
600
1200
-
-
-
-
-
1.8
65.0
180
535
1050
2100
-
-
-
-
-
2.4
50.0
140
415
850
1700
-
-
-
-
-
3.0
42.0
120
345
705
1400
-
-
-
-
-
3.3
39.0
110
320
655
1250
-
-
-
-
-
3.6
38.0
105
300
620
1200
-
-
-
-
-
1.8
54.0
155
610
1050
2100
-
-
-
-
-
2.4
39.5
150
490
875
1600
-
-
-
-
-
3.0
39.5
115
335
680
1350
-
-
-
-
-
3.3
37.0
105
310
630
1250
-
-
-
-
-
3.6
35.5
100
295
590
1150
-
-
-
-
-
Electrical characteristics
176/334
Table 53. Current consumption in Stop 1 mode on SMPS (continued)
µA
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
STM32U585xx
Conditions
Symbol
Typ
Parameter
Unit
VDD (V)
Wakeup clock is MSI 24 MHz
QDD(wakeup from Stop 1)
Electrical charge consumed during wakeup from
Stop 1 mode
25°C
1.10
Wakeup clock is HSI 16 MHz
3.0
Wakeup clock is MSI 1 MHz
0.38
STM32U585xx
Table 54. Current consumption during wakeup from Stop 1 mode on SMPS
nAs
1.33
Table 55. Current consumption in Stop 2 mode on LDO
Conditions
Symbol
Max(1)
Typ
Parameter
DS13086 Rev 6
Supply current in Stop 2 mode,
RTC disabled,
8-Kbyte SRAM2 + ICACHE
retained
IDD(Stop 2)
Supply current in Stop 2 mode,
RTC disabled,
All SRAMs retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
8.90
23.5
70.0
145
305
33.0
71.0
210.0
440.0
920.0
2.4
8.90
23.5
70.5
145
310
33.0
71.0
220.0
440.0
930.0
72.0
220.0
450.0
950.0
(2)
9.05
24.0
71.5
150
315
33.0
3.3
9.30
24.5
73.0
150
320
34.0
74.0
220.0
450.0
960.0
3.6
10.00
26.0
75.5
155
325
37.0
78.0
230.0
470.0
980.0
1.8
20.00
48.5
145.0
310
680
73.0
150.0
440.0
930.0
2100.0
2.4
20.00
48.5
145.0
315
680
73.0
150.0
440.0
950.0
2100.0
3.0
20.50
48.5
145.0
315
685
74.0
150.0
440.0
950.0
2100.0
3.3
20.50
49.5
150.0
315
690
74.0
150.0
450.0
950.0
2100.0
3.6
22.00
51.0
150.0
320
700
80.0
160.0
450.0
960.0
2100.0
µA
177/334
Electrical characteristics
3.0
Conditions
Symbol
Max(1)
Typ
Parameter
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
9.45
24.0
71.5
150
315
35.0
72.0
220.0
450.0
950.0
2.4
9.50
24.0
71.5
150
315
35.0
72.0
220.0
450.0
950.0
3.0
9.60
24.5
73.0
150
320
35.0
74.0
220.0
450.0
960.0
3.3
9.30
25.0
74.0
155
325
34.0
75.0
230.0
470.0
980.0
3.6
11.00
26.5
77.0
160
335
40.0
80.0
240.0
480.0
1100.0
1.8
9.15
23.5
70.0
145
305
33.0
71.0
210.0
440.0
920.0
2.4
9.20
23.5
70.5
145
310
34.0
71.0
220.0
440.0
930.0
3.0
9.20
24.0
71.5
150
315
34.0
72.0
220.0
450.0
950.0
3.3
9.50
24.5
73.0
150
320
35.0
74.0
220.0
450.0
960.0
IDD(Stop 2
3.6
10.50
26.0
76.0
155
325
38.0
78.0
230.0
470.0
980.0
with RTC)
1.8
9.15
24.0
71.5
150
315
33.0
72.0
220.0
450.0
950.0
2.4
9.20
24.0
71.5
150
315
34.0
72.0
220.0
450.0
950.0
3.0
9.50
24.0
72.5
150
320
35.0
72.0
220.0
450.0
960.0
3.3
9.50
25.0
74.0
155
325
35.0
75.0
230.0
470.0
980.0
3.6
10.50
26.5
76.5
160
335
38.0
80.0
230.0
480.0
1100.0
1.8
9.35
23.5
70.5
145
305
-
-
-
-
-
2.4
9.40
24.0
71.0
150
310
-
-
-
-
-
3.0
9.25
24.0
72.0
150
315
-
-
-
-
-
3.3
9.65
25.0
73.5
150
320
-
-
-
-
-
3.6
10.50
26.5
76.0
155
325
-
-
-
-
-
Supply current in Stop 2 mode,
RTC(3) clocked by LSI 32 kHz,
8-Kbyte SRAM2 + ICACHE
retained
DS13086 Rev 6
Supply current in Stop 2 mode,
RTC(3) clocked by LSI 250 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 2 mode,
RTC(3) clocked by LSE
bypassed at 32768 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 2 mode,
RTC(3) clocked by LSE quartz in
medium low-drive mode,
8-Kbyte SRAM2 + ICACHE
retained
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
µA
STM32U585xx
1. Evaluated by characterization and not tested in production, unless otherwise specified.
Electrical characteristics
178/334
Table 55. Current consumption in Stop 2 mode on LDO (continued)
Max(1)
Typ
Symbol
Parameter
Unit
25°C
55°C
85°C 105°C 125°C 30°C
55°C
85°C 105°C 125°C
DS13086 Rev 6
SRAM1 64-Kbyte page x static consumption
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
0.8
2.0
6.0
13.2
28.6
3.0
6.0
18.0
40.0
86.0
IDD(SRAM2_8KB)(3)
SRAM2 8-Kbyte page 1 static consumption
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
0.2
0.4
1.4
3.1
6.5
0.7
1.4
4.4
10.0
20.0
IDD(SRAM2_56KB)(3)
SRAM2 56-Kbyte page 2 static consumption
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
1.0
2.6
8.0
17.6
37.9
3.6
7.7
25.0
53.0
120.0
IDD(SRAM3_64kB)(4)
SRAM3 64-Kbyte page x static consumption
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
0.8
1.9
5.7
12.6
27.5
3.0
5.8
18.0
38.0
83.0
IDD(SRAM4)
SRAM4 static consumption
(SRAM4PDS = 1 versus SRAM4PDS = 0)
0.3
0.6
1.8
3.9
8.2
1.0
1.8
5.4
12.0
25.0
IDD(ICRAM)
ICACHE SRAM static consumption
(ICRAMPDS = 1 versus ICRAMPDS = 0)
0.1
0.4
1.3
2.9
5.7
0.5
1.3
4.0
8.6
18.0
DCACHE1 SRAM static consumption
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
0.1
0.2
0.7
1.5
3.0
0.3
0.7
2.3
4.6
9.1
IDD(DMA2DRAM)
DMA2D SRAM static consumption
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
0.0
0.1
0.3
0.5
0.7
0.2
0.3
1.0
1.6
2.0
IDD(PRAM)
FMAC, FDCAN and USB SRAM static consumption
(PRAMPDS = 1 versus PRAMPDS = 0)
0.0
0.1
0.4
0.7
1.1
0.2
0.4
1.3
2.3
3.2
PKA SRAM static consumption
(PKARAMPDS = 1 versus PKARAMPDS = 0)
0.1
0.2
0.6
1.2
2.1
0.3
0.5
1.9
3.6
6.3
IDD(DC1RAM)
IDD(PKARAM)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
µA
179/334
Electrical characteristics
IDD(SRAM1_64kB)(2)
STM32U585xx
Table 56. SRAM static power consumption in Stop 2 when supplied by LDO
Conditions
Symbol
Typ
Parameter
Unit
VDD (V)
Wakeup clock is MSI 24 MHz
QDD(wakeup from Stop 2)
Electrical charge consumed during wakeup from
Stop 2 mode
25°C
0.81
Wakeup clock is HSI 16 MHz
3.0
0.79
Wakeup clock is MSI 1 MHz
nAs
1.98
Electrical characteristics
180/334
Table 57. Current consumption during wakeup from Stop 2 mode on LDO
Table 58. Current consumption in Stop 2 mode on SMPS
Conditions
Symbol
Max(1)
Typ
Parameter
DS13086 Rev 6
Supply current in Stop 2 mode,
RTC disabled,
8-Kbyte SRAM2 + ICACHE
retained
IDD(Stop 2)
Supply current in Stop 2 mode,
RTC disabled,
ALL SRAMs retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
5.30
14.0
42.0
88.5
195
19.0
42.0
130.0
270.0
580.0
2.4
3.50
9.6
29.5
63.5
140
13.0
29.0
87.0
190.0
410.0
30.0
93.0
200.0
440.0
(2)
3.0
3.90
10.0
31.5
68.0
150
14.0
3.3
3.90
10.0
30.5
65.5
145
14.0
30.0
89.0
190.0
420.0
3.6
4.55
11.0
31.0
65.0
145
16.0
32.0
89.0
190.0
420.0
1.8
12.00
28.5
83.5
180.0
440
44.0
86.0
250.0
540.0
1400.0
2.4
7.85
19.5
58.5
125.0
280
29.0
59.0
180.0
380.0
830.0
3.0
8.55
20.5
61.0
130.0
290
31.0
61.0
190.0
390.0
860.0
3.3
8.20
19.5
57.5
125.0
275
30.0
58.0
170.0
370.0
810.0
3.6
8.55
19.5
56.0
120.0
265
30.0
57.0
170.0
360.0
780.0
µA
STM32U585xx
Conditions
Symbol
Max(1)
Typ
Parameter
Unit
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
5.60
14.0
42.0
89.0
195
20.0
42.0
130.0
270.0
580.0
2.4
3.85
10.0
30.0
63.5
140
14.0
30.0
89.0
190.0
410.0
3.0
4.35
10.5
32.0
68.5
150
16.0
31.0
94.0
200.0
440.0
3.3
4.40
10.5
31.0
66.0
145
16.0
31.0
91.0
200.0
420.0
3.6
5.15
11.5
31.5
66.0
145
18.0
33.0
91.0
190.0
420.0
1.8
5.40
14.0
42.0
89.0
195
20.0
42.0
130.0
270.0
580.0
2.4
3.60
9.8
30.0
63.5
135
13.0
29.0
89.0
190.0
400.0
3.0
4.00
10.5
31.5
68.0
150
15.0
31.0
93.0
200.0
440.0
3.3
4.05
10.5
31.0
65.5
145
15.0
31.0
91.0
190.0
420.0
IDD(Stop 2
3.6
4.75
11.0
31.5
65.5
145
17.0
32.0
91.0
190.0
420.0
with RTC)
1.8
5.50
14.0
42.0
89.0
195
20.0
42.0
130.0
270.0
580.0
2.4
3.70
9.9
30.0
63.5
140
14.0
30.0
89.0
190.0
410.0
3.0
4.15
10.5
32.0
68.0
150
15.0
31.0
94.0
200.0
440.0
3.3
4.20
10.5
31.0
66.0
145
15.0
31.0
91.0
200.0
420.0
3.6
4.90
11.0
31.5
65.5
145
17.0
32.0
91.0
190.0
420.0
1.8
5.50
14.0
41.5
88.0
190
-
-
-
-
-
2.4
3.80
9.9
30.0
63.0
135
-
-
-
-
-
3.0
4.15
10.5
31.5
67.5
145
-
-
-
-
-
3.3
4.20
10.5
31.0
65.0
140
-
-
-
-
-
3.6
4.85
11.0
31.5
65.0
140
-
-
-
-
-
Supply current in Stop 2 mode,
RTC(3) clocked by LSI 32 kHz,
8-Kbyte SRAM2 + ICACHE
retained
DS13086 Rev 6
Supply current in Stop 2 mode,
RTC(3) clocked by LSI 250 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 2 mode,
RTC(3) clocked by LSE
bypassed at 32768 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 2 mode,
RTC(3) clocked by LSE quartz in
medium low-drive mode,
8-Kbyte SRAM2 + ICACHE
retained
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
181/334
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
µA
Electrical characteristics
VDD (V)
STM32U585xx
Table 58. Current consumption in Stop 2 mode on SMPS (continued)
Max(1)
Typ
Symbol
Parameter
Unit
25°C
55°C
85°C 105°C 125°C 30°C
55°C
85°C 105°C 125°C
DS13086 Rev 6
IDD(SRAM1_64kB)(2)
SRAM1 64-Kbyte page x static consumption
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
0.4
0.9
2.6
5.5
12.7
1.5
2.7
7.7
17.0
39.0
IDD(SRAM2_8KB)(3)
SRAM2 8-Kbyte page 1 static consumption
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
0.1
0.2
0.6
1.2
2.9
0.3
0.6
2.0
3.7
10.0
IDD(SRAM2_56KB)(3)
SRAM2 56-Kbyte page 2 static consumption
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
0.5
1.1
3.4
7.5
16.7
1.7
3.4
11.0
23.0
50.0
IDD(SRAM3_64kB)(4)
SRAM3 64-Kbyte page x static consumption
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
0.4
0.8
2.4
5.3
12.2
1.4
2.5
7.3
16.0
37.0
IDD(SRAM4)
SRAM4 static consumption
(SRAM4PDS = 1 versus SRAM4PDS = 0)
0.1
0.3
0.7
1.5
3.7
0.4
0.8
2.2
4.6
12.0
IDD(ICRAM)
ICACHE SRAM static consumption
(ICRAMPDS = 1 versus ICRAMPDS = 0)
0.1
0.2
0.5
1.0
2.6
0.3
0.5
2.0
3.1
7.9
DCACHE1 SRAM static consumption
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
0.0
0.1
0.3
0.4
1.3
0.2
0.3
1.0
1.4
4.0
IDD(DMA2DRAM)
DMA2D SRAM static consumption
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
0.0
0.0
0.1
0.2
0.4
0.1
0.1
0.2
0.6
1.1
IDD(PRAM)
FMAC, FDCAN and USB SRAM static consumption
(PRAMPDS = 1 versus PRAMPDS = 0)
0.0
0.0
0.1
0.2
0.6
0.1
0.1
0.3
0.6
1.8
PKA SRAM static consumption
(PKARAMPDS = 1 versus PKARAMPDS = 0)
0.0
0.1
0.2
0.3
1.0
0.1
0.2
0.6
0.9
2.9
IDD(DC1RAM)
IDD(PKARAM)
Electrical characteristics
182/334
Table 59. SRAM static power consumption in Stop 2 when supplied by SMPS
µA
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
STM32U585xx
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).
Conditions
Symbol
Typ
Parameter
Unit
VDD (V)
Wakeup clock is MSI 24 MHz
QDD(wakeup from Stop 2)
Electrical charge consumed during wakeup from
Stop 2 mode
25°C
0.57
Wakeup clock is HSI 16 MHz
3.0
Wakeup clock is MSI 1 MHz
0.18
STM32U585xx
Table 60. Current consumption during wakeup from Stop 2 mode on SMPS
nAs
1.19
Table 61. Current consumption in Stop 3 mode on LDO
Conditions
Symbol
Max(1)
Typ
Parameter
DS13086 Rev 6
Supply current in Stop 3 mode,
RTC disabled,
8-Kbyte SRAM2 + ICACHE
retained
IDD(Stop 3)
Supply current in Stop 3 mode,
RTC disabled,
all SRAMs retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
5.15
14.5
49.0
110
240
19.0
44.0
150.0
330.0
710.0
2.4
5.15
15.0
49.5
110
240
19.0
45.0
150.0
330.0
710.0
3.0
5.60
15.0
50.5
110
245
20.0
45.0
150.0
330.0
720.0
3.3
5.30
15.5
51.5
115
250
19.0
46.0
160.0
340.0
740.0
3.6
6.80
17.0
54.0
115
255
24.0
50.0
160.0
340.0
750.0
1.8
12.00
35.5
125.0
290
665
44.0
110.0
380.0
870.0
2000.0
2.4
12.00
36.0
125.0
295
670
44.0
110.0
380.0
890.0
2000.0
110.0
390.0
900.0
2100.0
47.0
(2)
13.00
36.5
130.0
300
675
3.3
14.50
37.0
130.0
300
685
52.0
120.0
390.0
900.0
2100.0
3.6
14.50
39.0
135.0
305
695
52.0
120.0
410.0
910.0
2100.0
183/334
Electrical characteristics
3.0
µA
Conditions
Symbol
Max(1)
Typ
Parameter
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
5.45
15.0
49.5
110
240
20.0
45.0
150.0
330.0
710.0
2.4
5.55
15.0
50.0
110
240
20.0
45.0
150.0
330.0
710.0
3.0
6.05
15.5
51.0
110
245
22.0
46.0
160.0
330.0
720.0
3.3
5.80
16.0
52.0
115
250
21.0
48.0
160.0
340.0
740.0
3.6
7.35
18.0
54.5
120
255
26.0
53.0
160.0
360.0
750.0
1.8
5.25
15.0
49.5
110
240
19.0
45.0
150.0
330.0
710.0
2.4
5.30
15.0
49.5
110
240
19.0
45.0
150.0
330.0
710.0
3.0
5.75
15.0
50.5
110
245
21.0
45.0
150.0
330.0
720.0
3.3
5.40
16.0
52.0
115
250
19.0
48.0
160.0
340.0
740.0
IDD(Stop 3
3.6
6.95
17.5
54.5
115
255
25.0
51.0
160.0
340.0
750.0
with RTC)
1.8
5.35
15.0
49.5
110
240
20.0
45.0
150.0
330.0
710.0
2.4
5.40
15.0
49.5
110
240
20.0
45.0
150.0
330.0
710.0
3.0
5.90
15.5
50.5
110
245
21.0
46.0
150.0
330.0
720.0
3.3
5.55
16.0
52.0
115
250
20.0
48.0
160.0
340.0
740.0
3.6
7.20
17.5
54.5
115
255
25.0
51.0
160.0
340.0
750.0
1.8
5.35
15.0
48.5
105
230
-
-
-
-
-
2.4
5.45
15.0
49.0
110
235
-
-
-
-
-
3.0
5.95
15.5
50.5
110
240
-
-
-
-
-
3.3
6.55
16.0
51.5
110
245
-
-
-
-
-
3.6
7.20
17.5
54.0
115
250
-
-
-
-
-
Supply current in Stop 3 mode,
RTC(3) clocked by LSI 32 kHz,
8-Kbyte SRAM2 + ICACHE
retained
DS13086 Rev 6
Supply current in Stop 3 mode,
RTC(3) clocked by LSI 250 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 3 mode,
RTC(3) clocked by LSE
bypassed at 32768 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 3 mode,
RTC(3) clocked by LSE quartz in
medium low-drive mode,
8-Kbyte SRAM2 + ICACHE
retained
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
µA
STM32U585xx
1. Evaluated by characterization and not tested in production, unless otherwise specified.
Electrical characteristics
184/334
Table 61. Current consumption in Stop 3 mode on LDO (continued)
Max(1)
Typ
Symbol
Parameter
Unit
25°C
55°C
85°C
105°C 125°C
30°C
55°C
85°C 105°C 125°C
DS13086 Rev 6
SRAM1 64-Kbyte page x static consumption
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
0.7
1.8
6.4
15.3
35.6
2.7
5.3
20.0
46.0
110.0
IDD(SRAM2_8KB)(3)
SRAM2 8-Kbyte page 1 static consumption
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
0.2
0.7
2.4
5.8
12.8
1.0
2.1
7.1
18.0
39.0
IDD(SRAM2_56KB)(3)
SRAM2 56-Kbyte page 2 static consumption
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
0.9
2.2
7.8
18.5
41.7
3.2
6.5
24.0
56.0
130.0
IDD(SRAM3_64kB)(4)
SRAM3 64-Kbyte page x static consumption
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
0.7
1.7
6.1
14.8
34.2
2.6
5.2
19.0
45.0
110.0
IDD(SRAM4)
SRAM4 static consumption
(SRAM4PDS = 1 versus SRAM4PDS = 0)
0.2
0.5
1.7
4.0
8.9
0.8
1.5
5.1
12.0
27.0
IDD(ICRAM)
ICACHE SRAM static consumption
(ICRAMPDS = 1 versus ICRAMPDS = 0)
0.0
0.3
1.3
2.9
6.3
0.0
1.1
3.9
8.9
19.0
DCACHE1 SRAM static consumption
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
0.0
0.0
0.0
0.3
1.2
0.0
0.0
0.0
1.0
3.7
IDD(DMA2DRAM)
DMA2D SRAM static consumption
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
0.0
0.1
0.3
0.6
1.1
0.2
0.2
1.0
1.9
3.4
IDD(PRAM)
FMAC, FDCAN and USB SRAM static consumption
(PRAMPDS = 1 versus PRAMPDS = 0)
0.1
0.1
0.4
0.8
1.5
0.2
0.3
1.3
2.3
4.6
PKA SRAM static consumption
(PKARAMPDS = 1 versus PKARAMPDS = 0)
0.1
0.2
0.6
1.3
2.8
0.3
0.5
1.9
4.0
8.4
IDD(DC1RAM)
IDD(PKARAM)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
µA
185/334
Electrical characteristics
IDD(SRAM1_64kB)(2)
STM32U585xx
Table 62. SRAM static power consumption in Stop 3 when supplied by LDO
Conditions
Symbol
Typ
Parameter
Unit
VDD (V)
Wakeup clock is MSI 24 MHz
QDD(wakeup from Stop 3)
Electrical charge consumed during wakeup from
Stop 3 mode
25°C
19.2
Wakeup clock is HSI 16 MHz
3.0
18.2
Wakeup clock is MSI 1 MHz
nAs
61.8
Electrical characteristics
186/334
Table 63. Current consumption during wakeup from Stop 3 mode on LDO
Table 64. Current consumption in Stop 3 mode on SMPS
Conditions
Symbol
Max(1)
Typ
Parameter
DS13086 Rev 6
Supply current in Stop 3 mode,
RTC disabled,
8-Kbyte SRAM2 + ICACHE
retained
IDD(Stop 3)
Supply current in Stop 3 mode,
RTC disabled,
all SRAMs retained
Unit
VDD (V)
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
2.10
6.55
22.5
50.5
115.0
7.4
20.0
66.0
150.0
340.0
2.4
1.85
5.95
20.5
46.5
110.0
6.5
18.0
60.0
140.0
320.0
3.0
1.70
5.30
18.5
42.0
98.5
5.9
16.0
54.0
130.0
280.0
3.3
1.80
5.55
18.5
41.5
97.0
6.1
16.0
53.0
120.0
280.0
3.6
2.65
6.55
19.5
42.5
98.0
8.6
19.0
55.0
120.0
280.0
1.8
5.20
15.50
55.0
130.0
355.0
19.0
47.0
170.0
390.0
1100.0
2.4
4.55
14.00
50.0
115.0
275.0
17.0
42.0
150.0
350.0
820.0
36.0
130.0
300.0
690.0
14.0
(2)
3.0
3.90
12.00
42.5
100.0
235.0
3.3
3.65
11.50
40.5
95.0
225.0
13.0
34.0
120.0
280.0
660.0
3.6
4.50
12.00
40.5
92.5
215.0
16.0
35.0
120.0
270.0
630.0
µA
STM32U585xx
Conditions
Symbol
Max(1)
Typ
Parameter
Unit
25°C
55°C
85°C
105°C
125°C
30°C
55°C
85°C
105°C
125°C
1.8
2.40
6.85
22.5
51.0
120.0
8.5
21.0
66.0
150.0
350.0
2.4
2.25
6.30
21.0
47.0
110.0
8.0
19.0
62.0
140.0
320.0
3.0
2.15
5.80
19.0
42.5
99.0
7.5
17.0
55.0
130.0
290.0
3.3
2.30
6.05
19.0
42.0
97.5
7.9
18.0
55.0
120.0
280.0
3.6
3.20
7.10
20.0
43.0
98.5
11.0
20.0
56.0
130.0
280.0
1.8
2.20
6.70
22.5
50.5
115.0
7.8
20.0
66.0
150.0
340.0
2.4
2.00
6.10
20.5
47.0
110.0
7.1
18.0
60.0
140.0
320.0
3.0
1.85
5.45
18.5
42.0
98.5
6.5
16.0
54.0
130.0
280.0
3.3
1.90
5.70
18.5
41.5
97.0
6.4
17.0
53.0
120.0
280.0
IDD(Stop 3
3.6
2.80
6.70
20.0
42.5
98.0
9.2
19.0
56.0
120.0
280.0
with RTC)
1.8
2.30
6.80
22.5
51.0
120.0
8.2
21.0
66.0
150.0
350.0
2.4
2.10
6.20
21.0
47.0
110.0
7.4
19.0
62.0
140.0
320.0
3.0
2.00
5.60
18.5
42.0
99.0
7.0
17.0
54.0
130.0
290.0
3.3
2.05
5.85
18.5
42.0
97.5
7.0
17.0
53.0
120.0
280.0
3.6
3.00
6.90
20.0
43.0
98.5
9.9
20.0
56.0
130.0
280.0
1.8
2.35
6.80
22.5
50.0
115.0
-
-
-
-
-
2.4
2.15
6.25
21.0
46.5
105.0
-
-
-
-
-
3.0
2.05
5.70
18.5
42.0
96.0
-
-
-
-
-
3.3
2.25
5.95
18.5
41.5
95.0
-
-
-
-
-
3.6
3.05
6.95
20.0
42.5
96.0
-
-
-
-
-
Supply current in Stop 3 mode,
RTC(3) clocked by LSI 32 kHz,
8-Kbyte SRAM2 + ICACHE
retained
DS13086 Rev 6
Supply current in Stop 3 mode,
RTC(3) clocked by LSI 250 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 3 mode,
RTC(3) clocked by LSE bypassed
at 32768 Hz,
8-Kbyte SRAM2 + ICACHE
retained
Supply current in Stop 3 mode,
RTC(3) clocked by LSE quartz in
medium low-drive mode,
8-Kbyte SRAM2 + ICACHE
retained
1. Evaluated by characterization and not tested in production, unless otherwise specificed.
2. Tested in production.
187/334
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
µA
Electrical characteristics
VDD (V)
STM32U585xx
Table 64. Current consumption in Stop 3 mode on SMPS (continued)
Max(1)
Typ
Symbol
Parameter
Unit
25°C
55°C
85°C
105°C 125°C
30°C
55°C
85°C 105°C 125°C
DS13086 Rev 6
IDD(SRAM1_64kB)(2)
SRAM1 64-Kbyte page x static consumption
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
0.2
0.6
2.2
5.4
12.6
0.7
2.0
8.0
17.0
38.0
IDD(SRAM2_8KB)(3)
SRAM2 8-Kbyte page 1 static consumption
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
0.1
0.2
0.8
2.0
4.6
0.2
1.0
2.5
5.9
14.0
IDD(SRAM2_56KB)(3)
SRAM2 56-Kbyte page 2 static consumption
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
0.2
0.7
2.7
6.4
14.8
1.0
3.0
8.0
20.0
45.0
IDD(SRAM3_64kB)(4)
SRAM3 64-Kbyte page x static consumption
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
0.2
0.6
2.1
5.0
12.0
1.0
2.0
6.3
16.0
36.0
IDD(SRAM4)
SRAM4 static consumption
(SRAM4PDS = 1 versus SRAM4PDS = 0)
0.0
0.1
0.6
1.4
3.0
0.5
1.0
2.0
4.1
8.9
IDD(ICRAM)
ICACHE SRAM static consumption
(ICRAMPDS = 1 versus ICRAMPDS = 0)
0.0
0.1
0.4
1.0
2.0
0.1
1.0
2.0
3.0
6.1
DCACHE1 SRAM static consumption
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
0.0
0.1
0.2
0.5
0.9
1.2
1.0
1.0
1.5
2.6
IDD(DMA2DRAM)
DMA2D SRAM static consumption
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
0.0
0.0
0.0
0.1
0.1
0.4
0.1
0.1
0.4
0.4
IDD(PRAM)
FMAC, FDCAN and USB SRAM static consumption
(PRAMPDS = 1 versus PRAMPDS = 0)
0.0
0.0
0.1
0.2
0.3
0.0
0.1
1.0
0.7
0.8
PKA SRAM static consumption
(PKARAMPDS = 1 versus PKARAMPDS = 0)
0.0
0.1
0.2
0.4
0.7
0.0
1.0
1.0
1.3
2.1
IDD(DC1RAM)
IDD(PKARAM)
Electrical characteristics
188/334
Table 65. SRAM static power consumption in Stop 3 when supplied by SMPS
µA
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
STM32U585xx
3. ???SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).
Conditions
Symbol
Typ
Parameter
Unit
-
VDD (V)
Wakeup clock is MSI 24 MHz
QDD(wakeup from Stop 3)
Electrical charge consumed during wakeup from
Stop 3 mode
Wakeup clock is HSI 16 MHz
Wakeup clock is MSI 1 MHz
25°C
7.44
3.0
7.25
STM32U585xx
Table 66. Current consumption during wakeup from Stop 3 mode on SMPS
nAs
26.0
DS13086 Rev 6
Electrical characteristics
189/334
Conditions
Symbol
Unit
-
No IWDG
ULPMEN = 1
No IWDG
ULPMEN = 0
DS13086 Rev 6
IDD(Standby)
Max(1)
Typ
Parameter
Supply current in
Standby mode (backup
registers retained),
RTC disabled
with IWDG
clocked by
LSI 32 kHz
ULPMEN = 0
with IWDG
clocked by
LSI 250 Hz
ULPMEN = 0
VDD (V)
25°C
55°C
85°C
105°C 125°C
30°C
55°C
85°C
105°C
125°C
1.8
0.21
0.71
3.30
9.10
28.40
0.55
1.70
7.40
20.00
58.00
2.4
0.21
0.74
3.47
9.54
29.70
0.58
1.80
7.90
22.00
61.00
3.0
0.36
1.08
4.41
11.50
34.20
1.10
2.70
11.00
27.00
73.00
3.3
0.64
1.69
5.68
13.70
38.40
2.00
4.20
14.00
32.00
83.00
3.6
1.51
3.04
8.07
17.40
44.20
4.80
7.70
20.00
41.00
98.00
1.8
0.28
0.76
3.28
8.95
27.70
0.63
1.70
7.40
20.00
57.00
2.4
0.29
0.83
3.52
9.46
29.10
0.67
1.90
7.90
22.00
61.00
3.0
0.43
1.16
4.43
11.40
33.40
1.10
2.80
11.00
27.00
72.00
3.3
0.75
1.75
5.68
13.60
37.40
2.20
4.30
14.00
32.00
82.00
3.6
1.58
3.10
8.07
17.20
43.30
4.90
7.70
20.00
41.00
97.00
1.8
0.52
1.03
3.55
9.04
26.57
0.79
1.90
7.20
19.00
57.00
2.4
0.64
1.18
3.81
9.51
27.47
0.93
2.10
7.80
20.00
61.00
3.0
0.87
1.62
4.81
11.48
31.63
1.50
3.10
11.00
25.00
72.00
3.3
1.23
2.26
6.12
13.68
35.58
2.60
4.60
14.00
30.00
83.00
3.6
2.13
3.67
8.55
17.34
41.46
5.30
8.10
20.00
39.00
97.00
1.8
0.38
0.88
3.44
9.15
28.00
0.77
1.90
7.60
21.00
57.00
2.4
0.40
0.94
3.63
9.58
29.20
0.79
2.00
8.00
22.00
61.00
3.0
0.55
1.28
4.55
11.50
33.50
1.30
2.90
11.00
27.00
72.00
3.3
0.87
1.90
5.83
13.70
37.50
2.30
4.40
14.00
32.00
82.00
3.6
1.71
3.26
8.22
17.30
43.30
5.10
7.90
20.00
41.00
97.00
Electrical characteristics
190/334
Table 67. Current consumption in Standby mode
µA
STM32U585xx
Conditions
Symbol
Max(1)
Typ
Parameter
Unit
RTC(2)
clocked
by LSI 32 kHz,
no IWDG(3)
ULPMEN = 0
DS13086 Rev 6
Supply current in
IDD(Standby with Standby mode (backup
registers retained),
RTC)
RTC enabled
RTC(2) clocked
by LSI 250 Hz,
no IWDG
ULPMEN = 0
RTC(2) clocked
by LSE
bypassed at
32768 Hz
ULPMEN = 0
25°C
55°C
85°C
105°C 125°C
30°C
55°C
85°C
105°C
125°C
1.8
0.56
1.05
3.60
9.29
28.10
0.81
1.90
7.50
20.00
57.00
2.4
0.64
1.18
3.88
9.82
29.40
0.93
2.20
8.20
22.00
61.00
3.0
0.88
1.61
4.88
11.80
33.80
1.50
3.20
11.00
27.00
72.00
3.3
1.25
2.26
6.19
14.10
37.80
2.60
4.70
14.00
33.00
83.00
3.6
2.13
3.67
8.63
17.70
43.70
5.30
8.20
20.00
42.00
97.00
1.8
0.39
0.88
3.44
9.14
28.00
0.77
1.90
7.60
21.00
57.00
2.4
0.40
0.94
3.63
9.58
29.20
0.79
2.00
8.00
22.00
61.00
3.0
0.56
1.29
4.56
11.50
33.40
1.30
2.90
11.00
27.00
72.00
3.3
0.89
1.90
5.83
13.70
37.50
2.30
4.40
14.00
32.00
82.00
3.6
1.73
3.27
8.23
17.30
43.30
5.10
7.90
20.00
41.00
97.00
1.8
0.47
0.96
3.51
9.22
28.10
0.95
2.10
7.70
21.00
57.00
2.4
0.50
1.04
3.75
9.72
29.40
1.10
2.30
8.30
22.00
61.00
3.0
0.69
1.42
4.71
11.70
33.80
1.60
3.30
11.00
27.00
73.00
3.3
1.04
2.06
6.00
13.90
37.80
2.70
4.80
15.00
33.00
83.00
3.6
1.91
3.46
8.43
17.60
43.70
5.50
8.30
21.00
42.00
98.00
1.8
0.47
0.97
3.50
9.14
27.20
-
-
-
-
-
2.4
0.50
1.05
3.72
9.60
28.20
-
-
-
-
-
3.0
0.66
1.40
4.66
11.50
32.50
-
-
-
-
-
3.3
0.98
2.01
5.93
13.70
36.50
-
-
-
-
-
3.6
1.82
3.37
8.32
17.40
42.30
-
-
-
-
-
µA
191/334
Electrical characteristics
RTC(2) clocked
by LSE quartz
in medium
low-drive mode
ULPMEN = 0
VDD (V)
STM32U585xx
Table 67. Current consumption in Standby mode (continued)
Conditions
Symbol
Parameter
Unit
-
Supply current in
IDD(Standby with Standby mode (backup
registers retained),
RTC)
RTC enabled
DS13086 Rev 6
Supply current to be
added in Standby mode
IDD(BKPSRAM)
when backup SRAM is
retained
IDD(SRAM2)
Max(1)
Typ
RTC(2) clocked
by LSE quartz
in medium
low-drive mode
ULPMEN = 1
-
Supply current to be
added in Standby mode
when full SRAM2 and
BKPSRAM are retained
LDO
Supply current to be
added in Standby mode
IDD(SRAM2_8K) when SRAM2 8-Kbyte
page 1 and BKPSRAM
are retained
VDD (V)
25°C
55°C
85°C
105°C 125°C
30°C
55°C
85°C
105°C
125°C
1.8
0.44
0.97
3.55
9.45
29.20
-
-
-
-
-
2.4
0.47
1.03
3.80
10.00
30.00
-
-
-
-
-
3.0
0.62
1.37
4.75
12.35
35.20
-
-
-
-
-
3.3
0.98
1.96
6.00
14.45
38.90
-
-
-
-
-
3.6
1.77
3.40
8.50
17.80
45.40
-
-
-
-
-
1.8
0.13
0.22
0.53
1.15
2.50
0.47
0.66
1.60
3.50
7.50
2.4
0.12
0.19
0.47
1.04
2.30
0.45
0.56
1.50
3.20
6.90
3.0
0.13
0.19
0.47
1.00
2.30
0.47
0.58
1.50
3.00
7.00
3.3
0.09
0.20
0.48
1.00
2.40
0.31
0.60
1.50
3.00
7.20
3.6
0.10
0.20
0.48
1.00
2.20
0.37
0.60
1.50
3.00
6.70
1.8
1.62
4.09
11.92
25.75
55.60
5.90
13.00
36.00
78.00
170.00
2.4
1.62
4.05
11.88
25.74
55.60
5.90
13.00
36.00
78.00
170.00
3.0
1.64
4.02
11.87
25.80
55.70
6.00
13.00
36.00
78.00
170.00
3.3
1.65
4.02
11.82
25.70
55.70
6.00
13.00
36.00
78.00
170.00
3.6
1.68
3.99
11.73
25.50
55.20
6.10
12.00
36.00
77.00
170.00
1.8
0.58
1.41
4.02
8.55
18.20
2.10
4.30
13.00
26.00
55.00
2.4
0.63
1.37
3.95
8.44
17.90
2.30
4.10
12.00
26.00
54.00
3.0
0.63
1.36
3.93
8.40
17.90
2.30
4.10
12.00
26.00
54.00
3.3
0.60
1.35
3.90
8.30
17.80
2.20
4.10
12.00
25.00
54.00
3.6
0.69
1.35
3.73
8.10
17.30
2.50
4.10
12.00
25.00
52.00
Electrical characteristics
192/334
Table 67. Current consumption in Standby mode (continued)
µA
STM32U585xx
Conditions
Symbol
Parameter
Unit
-
IDD(SRAM2)
Max(1)
Typ
Supply current to be
added in Standby mode
when full SRAM2 and
BKPSRAM are retained
SMPS
DS13086 Rev 6
Supply current to be
added in Standby mode
IDD(SRAM2_8K) when SRAM2 8-Kbyte
page 1 and BKPSRAM
are retained
VDD (V)
25°C
55°C
85°C
105°C 125°C
30°C
55°C
85°C
105°C
125°C
1.8
0.97
2.23
6.55
14.25
31.40
3.50
6.70
20.00
43.00
95.00
2.4
0.63
1.48
4.40
9.44
19.50
2.30
4.50
14.00
29.00
59.00
3.0
0.67
1.51
4.50
9.90
21.60
2.50
4.60
14.00
30.00
65.00
3.3
0.56
1.35
4.05
8.90
19.60
2.10
4.10
13.00
27.00
59.00
3.6
0.55
1.19
3.53
7.80
17.40
2.00
3.60
11.00
24.00
53.00
1.8
0.34
0.78
2.21
4.75
10.40
1.30
2.40
6.70
15.00
32.00
2.4
0.24
0.52
1.45
3.04
6.80
0.85
1.60
4.40
9.20
21.00
3.0
0.25
0.50
1.45
3.10
6.80
0.89
1.50
4.40
9.30
21.00
3.3
0.17
0.42
1.23
2.70
6.00
0.63
1.30
3.70
8.10
18.00
3.6
0.18
0.33
0.86
2.10
4.80
0.65
0.99
2.60
6.30
15.00
STM32U585xx
Table 67. Current consumption in Standby mode (continued)
µA
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but LPCAL = 1 in RTC_CALR.
3. Current consumption with IWDG enabled is similar.
Table 68. Current consumption during wakeup from Standby mode
Conditions
Symbol
Unit
-
Electrical charge consumed during wakeup from
Standby mode
Wakeup clock is MSI 4 MHz
Wakeup clock is MSI 1 MHz
VDD (V)
3.0
25°C
404
602
nAs
193/334
Electrical characteristics
QDD(wakeup from Standby)
Typ
Parameter
Conditions
Symbol
Unit
-
Supply current in
Shutdown mode (backup
IDD(Shutdown) registers retained),
RTC disabled
-
RTC(3) clocked by
LSE bypassed at
32768 Hz
DS13086 Rev 6
IDD(Shutdown
with RTC)
Max(1)
Typ
Parameter
Supply current in
Shutdown mode (backup
registers retained),
RTC enabled
RTC(3) clocked by
LSE quartz in
medium low-drive
mode
VDD (V)
25°C 55°C 85°C 105°C 125°C
30°C
55°C
85°C
105°C 125°C
1.8
0.16
0.62
2.65
7.05
18.50
0.49
1.60
6.70
18.00
47.00
2.4
0.17
0.68
2.85
7.65
20.00
0.53
1.70
7.20
20.00
50.00
2.70
9.70
25.00
63.00
25.00
0.95
(2)
3.0
0.31
1.05
3.85
9.75
3.3
0.64
1.65
5.15
12.00 29.00
2.00
4.20
13.00
30.00
73.00
3.6
1.55
3.05
7.60
15.50 35.00
4.90
7.70
19.00
39.00
88.00
1.8
0.33
0.80
2.85
7.25
19.00
0.67
1.80
6.90
18.00
47.00
2.4
0.37
0.88
3.10
7.85
20.50
0.75
2.00
7.40
20.00
51.00
3.0
0.57
1.30
4.15
10.00 25.50
1.30
2.90
10.00
25.00
64.00
3.3
0.94
2.00
5.50
12.50 29.50
2.40
4.60
14.00
31.00
74.00
3.6
1.90
3.45
8.00
16.00 35.50
5.20
8.10
20.00
40.00
89.00
1.8
0.39
0.87
3.00
7.60
20.00
-
-
-
-
-
2.4
0.43
0.93
3.20
8.05
21.00
-
-
-
-
-
3.0
0.57
1.25
4.10
9.95
25.50
-
-
-
-
-
3.3
0.89
1.90
5.40
12.00 29.50
-
-
-
-
-
3.6
1.75
3.25
7.80
16.00 35.50
-
-
-
-
-
Electrical characteristics
194/334
Table 69. Current consumption in Shutdown mode
µA
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
Table 70. Current consumption during wakeup from Shutdown mode
Unit
QDD(wakeup from
Shutdown)
Typ
Parameter
Electrical charge consumed during wakeup from
Shutdown mode
Wakeup clock is MSI 4 MHz
VDD (V)
25°C
3.0
3.75
μAs
STM32U585xx
Conditions
Symbol
Conditions
Symbol
Unit
-
IDD(VBAT)
Supply current in VBAT
mode (backup registers
retained),
RTC disabled
-
RTC(2) clocked
by LSE bypassed
at 32768 Hz
DS13086 Rev 6
IDD(VBAT with
RTC)
Max(1)
Typ
Parameter
Supply current in VBAT
mode (backup registers
retained),
RTC enabled
RTC(2) clocked
by LSE bypassed
at 32768 Hz,
LPCAL = 1 in
RTC_CALR
55°C
85°C 105°C 125°C 30°C
55°C
85°C 105°C 125°C
1.8
0.12
0.27
1.00
2.60
7.70
0.36
0.67
2.50
6.50
20.00
2.4
0.13
0.29
1.05
2.70
8.10
0.39
0.72
2.70
6.80
21.00
3.0
0.16
0.37
1.30
3.20
9.10
0.50
0.93
3.30
8.00
23.00
3.3
0.25
0.56
1.80
4.25
11.50
0.78
1.40
4.50
11.00
29.00
3.6
0.46
0.89
2.35
5.00
13.00
1.50
2.30
5.90
13.00
33.00
1.8
0.40
0.56
1.30
2.80
7.65
0.68
0.99
2.90
6.80
20.00
2.4
0.48
0.65
1.45
3.05
8.30
0.78
1.20
3.10
7.20
21.00
3.0
0.62
0.85
1.80
3.75
9.65
1.10
1.50
3.80
8.70
24.00
3.3
0.78
1.10
2.35
4.90
12.50
1.40
2.00
5.20
12.00
30.00
3.6
1.10
1.55
3.00
5.80
13.50
2.20
3.00
6.60
14.00
34.00
1.8
0.31
0.47
1.20
2.70
7.55
0.89
1.30
3.10
6.90
20.00
2.4
0.36
0.53
1.30
2.95
8.15
1.10
1.40
3.40
7.50
21.00
3.0
0.46
0.69
1.65
3.55
9.50
1.40
1.90
4.20
9.00
24.00
3.3
0.60
0.93
2.20
4.70
12.00
1.80
2.40
5.60
12.00
31.00
3.6
0.87
1.35
2.80
5.60
13.50
2.60
3.50
7.10
15.00
34.00
1.8
0.45
0.61
1.35
2.95
8.25
-
-
-
-
-
2.4
0.51
0.67
1.45
3.15
8.60
-
-
-
-
-
3.0
0.60
0.81
1.75
3.65
9.60
-
-
-
-
-
3.3
0.71
1.00
2.25
4.80
12.50
-
-
-
-
-
3.6
0.96
1.40
2.85
5.60
13.50
-
-
-
-
-
µA
195/334
Electrical characteristics
RTC(2) clocked
by LSE quartz in
medium low-drive
VBAT (V) 25°C
STM32U585xx
Table 71. Current consumption in VBAT mode
Conditions
Symbol
Parameter
Unit
-
IDD(VBAT with
RTC)
Max(1)
Typ
Supply current in VBAT
mode (backup registers
retained),
RTC enabled
RTC(2) clocked
by LSE quartz in
medium low-drive
mode,
LPCAL = 1 in
RTC_CALR
Supply current to be added
IDD(BKPSRAM) in VBAT mode when backup
SRAM is retained
-
VBAT (V) 25°C
55°C
85°C 105°C 125°C 30°C
55°C
85°C 105°C 125°C
DS13086 Rev 6
1.8
0.37
0.52
1.25
2.90
8.15
-
-
-
-
-
2.4
0.39
0.56
1.35
3.00
8.45
-
-
-
-
-
3.0
0.44
0.66
1.60
3.50
9.45
-
-
-
-
-
3.3
0.54
0.85
2.10
4.60
12.00
-
-
-
-
-
3.6
0.76
1.20
2.65
5.40
13.50
-
-
-
-
-
1.8
0.12
0.19
0.41
0.85
1.75
0.26
0.44
1.10
2.50
5.20
2.4
0.12
0.19
0.45
0.95
1.90
0.26
0.45
1.30
2.80
5.60
3.0
0.12
0.20
0.50
1.05
2.40
0.28
0.49
1.40
3.10
7.10
3.3
0.13
0.22
0.50
1.10
2.50
0.31
0.54
1.40
3.20
7.40
3.6
0.14
0.22
0.50
1.20
2.50
0.36
0.55
1.40
3.50
7.40
Electrical characteristics
196/334
Table 71. Current consumption in VBAT mode (continued)
µA
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration except otherwise specified
STM32U585xx
STM32U585xx
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up or pull-down generate current consumption when the
pin is externally held to the opposite level. The value of this current consumption can be
simply computed by using the pull-up/pull-down resistors values given in Section 5.3.14: I/O
port characteristics.
For the output pins, any internal or external pull-up or pull-down or external load must also
be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of the ADC input pins, that must be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the on-chip peripheral current consumption (see Table 72 for peripheral
current consumption in Run mode), the I/Os used by an application also contribute to the
current consumption. When an I/O pin switches, it uses the current from the I/O supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal
and external) connected to the pin:
I SW = V DDIOx × f SW × C
where:
•
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load.
•
VDDIOx is the I/O supply voltage.
•
fSW is the I/O switching frequency.
•
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS.
•
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS13086 Rev 6
197/334
299
Electrical characteristics
STM32U585xx
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the table below. The MCU is
placed under the following conditions:
•
All I/O pins are in analog mode.
•
The given value is calculated by measuring the difference of the current consumptions:
–
when the peripheral is clocked on
–
when the peripheral is clocked off
•
The ambient operating temperature and supply voltage conditions are summarized
in Table 33.
•
The power consumption of the digital part of the on-chip peripherals is given in the table
below. The power consumption of the analog part of the peripherals (where applicable)
is indicated in each related section of the datasheet.
Table 72. Typical dynamic current consumption of peripherals
Range2
Range3
Range4
Stop 1
Stop 2
Range1
Range2
Range3
Range4
Stop 1
Stop 2
AHB1
1.81
1.64
1.48
1.34
-
0.87
0.74
0.61
0.48
-
BKPRAM
0.90
0.80
0.74
0.67
-
0.44
0.37
0.31
0.24
-
CORDIC
0.56
0.51
0.45
0.41
-
0.27
0.23
0.19
0.15
-
CRC
0.34
0.30
0.27
0.25
-
0.17
0.14
0.12
0.09
-
DCACHE1
0.74
0.65
0.60
0.56
-
0.36
0.31
0.25
0.19
-
DMA2D
1.95
1.76
1.60
1.46
-
0.94
0.80
0.67
0.52
-
FLASH
2.21
2.01
1.82
1.65
-
1.07
0.91
0.76
0.59
-
FMAC
2.24
2.03
1.84
1.68
-
1.08
0.92
0.77
0.59
-
GPDMA1
3.71
3.38
3.05
2.75
-
1.80
1.52
1.27
0.98
-
GTZC1
0.39
0.34
0.31
0.30
-
0.18
0.16
0.13
0.10
-
ICACHE
0.76
0.68
0.63
0.57
-
0.37
0.32
0.26
0.20
-
MDF1
7.65
6.95
6.27
5.67
-
3.69
3.12
2.61
2.01
-
MDF1 indep(1)
0.84
0.76
0.68
0.63
-
0.4
0.34
0.29
0.22
-
RAMCFG
1.26
1.14
1.03
0.96
-
0.61
0.52
0.43
0.33
-
SRAM1
0.82
0.73
0.67
0.62
-
0.40
0.34
0.28
0.22
-
TSC
1.11
1.00
0.91
0.83
-
0.54
0.46
0.38
0.29
-
AHB2-1
2.08
1.88
1.71
1.54
-
1.00
0.85
0.71
0.55
-
ADC1
2.01
1.84
1.65
1.52
-
0.97
0.82
0.69
0.53
-
1.43
1.30
1.17
1.06
-
0.69
0.58
0.48
0.37
-
2.36
2.17
1.94
1.75
-
1.14
0.97
0.81
0.62
-
AHB2-1
AHB1
Bus
Peripheral
ADC1
AES
198/334
SMPS
Range1
LDO
indep(1)
DS13086 Rev 6
Unit
µA/
MHz
STM32U585xx
Electrical characteristics
Table 72. Typical dynamic current consumption of peripherals (continued)
Range2
Range3
Range4
Stop 1
Stop 2
Range1
Range2
Range3
Range4
Stop 1
Stop 2
DCMI
4.68
4.28
3.87
3.50
-
2.26
1.92
1.61
1.24
-
GPIOA
0.08
0.07
0.07
0.05
-
0.04
0.03
0.03
0.02
-
GPIOB
0.06
0.05
0.04
0.04
-
0.03
0.02
0.02
0.01
-
GPIOC
0.11
0.11
0.08
0.08
-
0.05
0.05
0.04
0.03
-
GPIOD
0.07
0.07
0.06
0.06
-
0.04
0.03
0.03
0.02
-
GPIOE
0.04
0.05
0.03
0.03
-
0.02
0.02
0.01
0.01
-
GPIOF
0.07
0.08
0.06
0.05
-
0.04
0.03
0.03
0.02
-
GPIOG
0.22
0.21
0.17
0.16
-
0.11
0.09
0.07
0.05
-
GPIOH
0.22
0.21
0.17
0.17
-
0.11
0.09
0.07
0.06
-
GPIOI
0.12
0.13
0.10
0.09
-
0.06
0.05
0.04
0.03
-
HASH1
1.18
1.10
0.98
0.88
-
0.57
0.49
0.41
0.31
-
OTFDEC1
1.86
1.72
1.52
1.38
-
0.90
0.76
0.64
0.49
-
OTFDEC2
2.05
1.89
1.68
1.52
-
0.99
0.84
0.70
0.54
-
PKA
7.93
7.24
6.54
5.91
-
3.83
3.24
2.72
2.09
-
RNG
0.82
0.76
0.67
0.60
-
0.39
0.33
0.28
0.21
-
0.10
0.06
0.06
0.06
-
0.06
0.02
0.02
0.02
-
SAES
2.80
2.57
2.30
2.08
-
1.35
1.14
0.96
0.74
-
SDMMC1
12.26 11.18 10.11
9.15
-
5.92
5.01
4.20
3.24
-
SDMMC1 indep(1)
1.47
1.22
1.09
-
0.71
0.60
0.50
0.40
-
SDMMC2
12.48 11.39 10.29
9.31
-
6.02
5.10
4.28
3.30
-
SDMMC2 indep
1.59
1.44
1.31
1.18
-
0.76
0.65
0.54
0.44
-
SRAM2
1.18
1.10
0.97
0.88
-
0.57
0.48
0.40
0.32
-
SRAM3
1.31
1.22
1.07
0.97
-
0.63
0.54
0.45
0.35
-
USB_OTG_FS
10.47
9.58
8.67
7.83
-
5.05
4.30
3.61
2.77
-
AHB2-2
0.79
0.74
0.64
0.58
-
0.38
0.32
0.26
0.20
-
FMC
5.34
4.87
4.42
3.99
-
2.58
2.19
1.84
1.42
-
OCTOSPI1
1.58
1.45
1.29
1.18
-
0.76
0.64
0.54
0.42
-
OCTOSPI1 indep(1)
1.11
1.01
0.91
0.83
-
0.54
0.45
0.38
0.29
-
OCTOSPI2
0.79
0.72
0.65
0.58
-
0.39
0.32
0.28
0.21
-
0.91
0.83
0.75
0.68
-
0.44
0.37
0.31
0.24
-
AHB2-1
Bus
Peripheral
RNG indep
(1)
(1)
AHB2-2
SMPS
Range1
LDO
OCTOSPI2
indep(1)
1.34
DS13086 Rev 6
Unit
µA/
MHz
199/334
299
Electrical characteristics
STM32U585xx
Table 72. Typical dynamic current consumption of peripherals (continued)
Range2
Range3
Range4
Stop 1
Stop 2
Range1
Range2
Range3
Range4
Stop 1
Stop 2
0.96
0.87
0.79
0.72
0.98
0.46
0.39
0.33
0.26
0.35
2.52
2.28
2.06
1.85
1.86
1.21
1.03
0.86
0.66
0.66
ADF1
0.97
0.87
0.79
0.72
0.97
0.47
0.39
0.33
0.25
0.34
ADF1 indep(1)
0.35
0.31
0.28
0.26
0.21
0.17
0.14
0.12
0.09
0.07
AHB3
0.34
0.34
0.28
0.24
-
0.17
0.14
0.11
0.09
-
DAC1
1.88
1.70
1.55
1.39
1.66
0.91
0.76
0.64
0.50
0.59
DAC1 indep(1)
1.30
1.17
1.06
0.96
0.92
0.63
0.52
0.44
0.34
0.33
GTZC2
0.34
0.32
0.30
0.29
-
0.16
0.14
0.12
0.11
-
LPDMA1
0.43
0.39
0.36
0.32
0.58
0.21
0.17
0.14
0.11
0.20
LPGPIO1
0.10
0.09
0.09
0.08
0.26
0.05
0.04
0.03
0.03
0.09
PWR
0.13
0.12
0.10
0.09
-
0.06
0.05
0.04
0.03
-
SRAM4
0.45
0.40
0.37
0.34
0.26
0.21
0.18
0.15
0.12
0.09
APB1
1.50
1.39
1.23
1.10
-
0.73
0.61
0.51
0.40
-
CRS
0.30
0.27
0.25
0.22
-
0.15
0.12
0.10
0.08
-
DTS
2.07
1.89
1.72
1.53
-
1.00
0.85
0.71
0.55
-
5.09
4.64
4.21
3.79
-
2.46
2.08
1.75
1.35
-
2.70
2.41
2.20
1.99
-
1.30
1.10
0.93
0.71
-
I2C1
0.98
0.90
0.81
0.72
-
0.48
0.40
0.34
0.26
-
I2C1 indep(1)
2.26
2.06
1.86
1.69
-
1.09
0.92
0.78
0.59
-
I2C2
3.24
2.95
2.67
2.40
-
1.57
1.33
1.11
0.86
-
2.30
2.09
1.90
1.72
-
1.11
0.94
0.79
0.61
-
I2C4
1.26
1.15
1.04
0.92
-
0.61
0.52
0.43
0.33
-
I2C4 indep(1)
2.43
2.21
2.00
1.81
-
1.17
0.99
0.84
0.64
-
Bus
Peripheral
ADC4
AHB3
ADC4 indep
(1)
FDCAN1
APB1
FDCAN1
indep(1)
I2C2 indep
200/334
SMPS
Range1
LDO
(1)
DS13086 Rev 6
Unit
µA/
MHz
STM32U585xx
Electrical characteristics
Table 72. Typical dynamic current consumption of peripherals (continued)
Range2
Range3
Range4
Stop 1
Stop 2
Range1
Range2
Range3
Range4
Stop 1
Stop 2
1.71
1.56
1.42
1.26
-
0.83
0.70
0.59
0.46
-
4.20
3.83
3.48
3.15
-
2.03
1.72
4.95
1.11
-
SPI2
1.90
1.73
1.57
1.40
-
0.92
0.77
0.66
0.51
-
SPI2 indep(1)
0.81
0.75
0.68
0.62
-
0.40
0.33
0.28
0.21
-
TIM2
4.01
3.64
3.31
2.99
-
1.93
1.64
1.37
1.06
-
TIM3
4.51
4.10
3.72
3.35
-
2.18
1.84
1.55
1.19
-
TIM4
4.27
3.88
3.52
3.16
-
2.06
1.74
1.46
1.12
-
TIM5
3.95
3.60
3.27
2.93
-
1.91
1.62
1.36
1.04
-
TIM6
0.95
0.86
0.78
0.69
-
0.46
0.39
0.33
0.25
-
TIM7
0.90
0.82
0.75
0.65
-
0.44
0.37
0.31
0.24
-
1.86
1.70
1.54
1.39
-
0.90
0.76
0.64
0.50
-
3.47
3.17
2.87
2.60
-
1.68
1.42
1.19
0.93
-
1.93
1.76
1.60
1.44
-
0.94
0.79
0.66
0.51
-
3.57
3.25
2.95
2.67
-
1.72
1.46
1.23
0.95
-
1.60
1.46
1.33
1.17
-
0.78
0.66
0.55
0.43
-
5.53
5.04
4.57
4.12
-
2.67
2.26
1.91
1.46
-
3.57
3.24
2.95
2.65
-
1.72
1.46
1.22
0.94
-
USART3
2.10
1.91
1.73
1.57
-
1.02
0.86
0.72
0.56
-
USART3 indep(1)
4.24
3.86
3.5
3.17
-
2.05
1.73
1.45
1.12
-
WWDG
0.37
0.34
0.31
0.25
-
0.18
0.15
0.13
0.10
-
APB2
0.60
0.58
0.50
0.42
-
0.29
0.25
0.20
0.16
-
SAI1
2.10
1.90
1.73
1.55
-
1.01
0.86
0.72
0.55
-
SAI1 indep(1)
1.36
1.23
1.11
0.95
-
0.66
0.55
0.46
0.34
-
SAI2
1.98
1.80
1.64
1.48
-
0.96
0.81
0.68
0.53
-
1.25
1.14
1.02
0.92
-
0.60
0.51
0.43
0.40
-
2.17
1.97
1.79
1.63
-
1.05
0.89
0.75
0.57
-
Bus
Peripheral
LPTIM2
APB1
LPTIM2 indep
(1)
UART4
UART4 indep
(1)
UART5
UART5
indep(1)
UCPD1
USART2
USART2 indep
APB2
SMPS
Range1
LDO
SAI2 indep
SPI1
(1)
(1)
DS13086 Rev 6
Unit
µA/
MHz
201/334
299
Electrical characteristics
STM32U585xx
Table 72. Typical dynamic current consumption of peripherals (continued)
Range2
Range3
Range4
Stop 1
Stop 2
Range1
Range2
Range3
Range4
Stop 1
Stop 2
SPI1 indep(1)
0.97
0.88
0.79
0.72
-
0.47
0.39
0.33
0.25
-
TIM1
6.14
5.59
5.08
4.60
-
2.96
2.52
2.11
1.63
-
TIM15
3.37
3.06
2.79
2.51
-
1.63
1.38
1.16
0.89
-
TIM16
2.60
2.36
2.15
1.94
-
1.25
1.06
0.90
0.69
-
TIM17
2.40
2.18
1.99
1.79
-
1.16
0.98
0.82
0.63
-
TIM8
6.24
5.69
5.16
4.66
-
3.01
2.55
2.15
1.65
-
USART1
2.38
2.16
1.96
1.76
-
1.14
0.97
0.81
0.62
-
USART1 indep(1)
4.48
4.09
3.71
3.35
-
2.17
1.84
1.54
1.19
-
APB3
0.49
0.48
0.40
0.36
-
0.24
0.20
0.16
0.13
-
COMP
0.20
0.18
0.16
0.14
0.15
0.10
0.08
0.06
0.05
0.05
I2C3
0.79
0.71
0.65
0.58
0.59
0.38
0.32
0.27
0.20
0.21
I2C3 indep(1)
1.84
1.66
1.50
1.36
1.36
0.89
0.75
0.63
0.48
0.48
LPTIM1
0.98
0.89
0.81
0.72
0.73
0.48
0.40
0.33
0.25
0.26
3.08
2.81
2.49
2.29
2.33
1.46
1.24
1.04
0.81
µA/
0.83 MHz
LPTIM3
1.07
0.98
0.89
0.80
0.80
0.52
0.44
0.37
0.28
0.28
LPTIM3 indep(1)
2.85
2.61
2.36
2.15
2.19
1.43
1.22
0.98
0.77
0.78
LPTIM4
0.58
0.52
0.48
0.42
0.43
0.28
0.24
0.20
0.15
0.15
1.67
1.50
1.38
1.26
1.30
0.8
0.70
0.57
0.44
0.46
LPUART1
1.18
1.07
0.97
0.87
0.88
0.57
0.48
0.41
0.31
0.31
LPUART1 indep(1)
1.96
1.78
1.62
1.45
1.46
0.95
0.80
0.67
0.52
0.52
OPAMP
0.19
0.17
0.16
0.12
0.14
0.09
0.07
0.07
0.04
0.05
RTC
2.33
2.12
1.92
1.73
1.63
1.12
0.95
0.80
0.61
0.58
SPI3
1.48
1.34
1.22
1.10
1.10
0.71
0.61
0.51
0.38
0.39
SPI3 indep(1)
0.57
0.52
0.47
0.42
0.42
0.28
0.24
0.20
0.15
0.15
SYSCFG
0.29
0.27
0.24
0.22
0.14
0.12
0.10
0.08
VREFBUF
0.13
0.11
0.10
0.08
0.06
0.05
0.04
0.03
APB2
Bus
Peripheral
LPTIM1
APB3
SMPS
Range1
LDO
LPTIM4
indep(1)
indep(1)
1. indep = independent clock domain.
202/334
DS13086 Rev 6
0.09
0.03
Unit
STM32U585xx
5.3.6
Electrical characteristics
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in the table below are the latency between the event and the
execution of the first user instruction (FSTEN = 1 in PWR_CR3 if not mentioned).
The device goes in low-power mode after the WFE (wait for event) instruction.
Table 73. Low-power mode wakeup timings on LDO(1)
Mode
twu(Sleep)
twu(Stop 0)
Parameter
Wakeup time from
Sleep to Run mode
Wakeup time from
Stop 0 to Run mode
All SRAMs retained
Typ
(3 V, 30 °C)
Max
(3 V)
Unit
SLEEP_PD = 0
14
17
Nb of
CPU
cycles
SLEEP_PD = 1 with MSI = 24 MHz
8.1
8.8
Wakeup in FLASH,
range 4, FLASHFWU = 1
and SRAM4FWU = 1 in
PWR_CR2
MSI 24 MHz
2.35
2.5
Wakeup in FLASH,
range 4, FLASHFWU = 0
and SRAM4FWU = 0 in
PWR_CR2
MSI 24 MHz
11.0
12.0
HSI 16 MHz
11.0
12.0
MSI 1 MHz
37.0
39.0
Wakeup in SRAM2,
range 4, FLASHFWU = 0
and SRAM4FWU = 0 in
PWR_CR2
MSI 24 MHz
4.75
5.00
HSI 16 MHz
6.75
7.4
MSI 1 MHz
34.00
36.0
MSI 24 MHz
13.0
15.0
Wakeup in FLASH,
FLASHFWU = 0 and
SRAM4FWU = 0 in
PWR_CR2
MSI 24 MHz
22.0
24.0
HSI 16 MHz
21.5
24.0
MSI 1 MHz
48.0
51.0
Wakeup in SRAM2,
range 4, FLASHFWU = 0
and SRAM4FWU = 0 in
PWR_CR2
MSI 24 MHz
15.5
18.0
HSI 16 MHz
17.5
20.0
MSI 1 MHz
45.0
48.0
Conditions
Wakeup in FLASH,
FLASHFWU = 1 and
SRAM4FWU = 1 in
PWR_CR2
twu(Stop 1)
Wakeup time from
Stop 1 to Run mode
All SRAMs retained
DS13086 Rev 6
µs
203/334
299
Electrical characteristics
STM32U585xx
Table 73. Low-power mode wakeup timings on LDO(1) (continued)
Mode
Parameter
Wakeup in FLASH,
SRAM4FWU = 1 in
PWR_CR2
twu(Stop 2)
Wakeup time from
Stop 2 to Run mode
All SRAMs retained
Wakeup in FLASH,
SRAM4FWU = 0 in
PWR_CR2
Wakeup in SRAM2,
range 4, SRAM4FWU = 0
in PWR_CR2
Wakeup in FLASH,
FSTEN = 0 in PWR_CR3
twu(Stop 3)
Wakeup time from
Stop 3 to Run mode
All SRAMs retained
Wakeup in FLASH,
FSTEN = 1 in PWR_CR3
Wakeup in SRAM2,
range 4, FLASHFWU = 0
and SRAM4FWU = 0 in
PWR_CR2
twu(Standby
with SRAM2)
twu(Standby)
twu(Shutdown)
Wakeup time from
Standby with SRAM2
to Run mode
Wakeup time from
Standby to Run mode
Wakeup time from
Shutdown to Run mode
Typ
(3 V, 30 °C)
Max
(3 V)
MSI 24 MHz
20.0
23.0
MSI 24 MHz
23.0
25.0(2)
HSI 16 MHz
22.5
25.0
MSI 1 MHz
57.0
60.0
MSI 24 MHz
16.5
19.0
HSI 16 MHz
18.5
21.0
MSI 1 MHz
54.0
57.0
MSI 24 MHz
68.0
130
MSI 24 MHz
28.50
37.0
HSI 16 MHz
28.0
36.0
MSI 1 MHz
68.50
91.0
MSI 24 MHz
22.50
31.0
HSI 16 MHz
24.0
32.0
MSI 1 MHz
64.5
85.0
MSI 4 MHz
64.5
110
MSI 4 MHz
64.5
83.0
MSI 1 MHz
155
240
MSI 4 MHz
340
420
MSI 4 MHz
100
130
MSI 1 MHz
210
290
MSI 4 MHz
610
710
Conditions
Wakeup in FLASH,
FSTEN = 0 in PWR_CR3
Wakeup in FLASH,
FSTEN = 1 in PWR_CR3
Wakeup in FLASH,
FSTEN = 0 in PWR_CR3
Wakeup in FLASH,
FSTEN = 1 in PWR_CR3
-
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production at 130°C.
204/334
DS13086 Rev 6
Unit
µs
STM32U585xx
Electrical characteristics
Table 74. Low-power mode wakeup timings on SMPS(1)
Mode
twu(Sleep)
twu(Stop 0)
Typ
(3 V,
30 °C)
Max
(3 V)
Unit
SLEEP_PD = 0
14
17
Nb of
CPU
cycles
SLEEP_PD = 1 with MSI = 24 MHz
8.1
8.8
Wakeup in FLASH, range 4,
FLASHFWU = 1 and
SRAM4FWU = 1 in
PWR_CR2
MSI 24 MHz
2.35
2.5
Wakeup in FLASH, range 4,
Wakeup time from Stop 0
FLASHFWU = 0 and
to Run mode
SRAM4FWU = 0 in
All SRAMs retained
PWR_CR2
MSI 24 MHz
11.0
12.0
HSI 16 MHz
11.0
12.0
MSI 1 MHz
37.0
39.0
Wakeup in SRAM2, range 4,
FLASHFWU = 0 and
SRAM4FWU = 0 in
PWR_CR2
MSI 24 MHz
4.75
5.0
HSI 16 MHz
6.75
7.4
MSI 1 MHz
34.0
36.0
MSI 24 MHz
7.7
8.3
MSI 24 MHz
16.5
18.0
HSI 16 MHz
16.0
18.0
MSI 1 MHz
42.5
45.0
MSI 24 MHz
10.0
11.0
HSI 16 MHz
12.0
13.0
MSI 1 MHz
39.5
42.0
MSI 24 MHz
17.5
19.0
MSI 24 MHz
20.5
22.0
HSI 16 MHz
20.0
22.0
MSI 1 MHz
54.0
70.0
MSI 24 MHz
14.0
16.0
HSI 16 MHz
16.0
18.0
MSI 1 MHz
51.5
74.0
Parameter
Wakeup time from Sleep
to Run mode
Conditions
Wakeup in FLASH,
FLASHFWU = 1 and
SRAM4FWU = 1 in
PWR_CR2
twu(Stop 1)
Wakeup in FLASH
Wakeup time from Stop 1
FLASHFWU = 0 and
to Run mode
SRAM4FWU = 0 in
All SRAMs retained
PWR_CR2
Wakeup in SRAM2, range 4,
FLASHFWU = 0 and
SRAM4FWU = 0 in
PWR_CR2
Wakeup in FLASH
SRAM4FWU = 1 in
PWR_CR2
twu(Stop 2)
Wakeup in FLASH
Wakeup time from Stop 2
SRAM4FWU = 0 in
to Run mode
PWR_CR2
All SRAMs retained
Wakeup in SRAM2, range 4,
SRAM4FWU = 0 in
PWR_CR2
DS13086 Rev 6
µs
205/334
299
Electrical characteristics
STM32U585xx
Table 74. Low-power mode wakeup timings on SMPS(1) (continued)
Mode
Parameter
Wakeup in FLASH,
FSTEN = 0 in PWR_CR3
twu(Stop 3)
Wakeup in FLASH,
Wakeup time from Stop 3
FSTEN = 1 in PWR_CR3
to Run mode
All SRAMs retained
Wakeup in SRAM2, range 4
twu(Standby
with SRAM2)
twu(Standby)
twu(Shutdown)
Wakeup time from
Standby with SRAM2 to
Run mode
Wakeup time from
Standby to Run mode
Typ
(3 V,
30 °C)
Max
(3 V)
MSI 24 MHz
130
160
MSI 24 MHz
32.5
37.0
HSI 16 MHz
32.0
36.0
MSI 1 MHz
72.5
94.0
MSI 24 MHz
26.5
31.0
HSI 16 MHz
28.0
32.0
MSI 1 MHz
68.5
89.0
MSI 4 MHz
61.5
80.0
MSI 4 MHz
61.5
80.0
MSI 1 MHz
150
240
MSI 4 MHz
340
420
MSI 4 MHz
100
130
MSI 1 MHz
210
290
MSI 4 MHz
610
710
Conditions
Wakeup in FLASH,
FSTEN = 0 in PWR_CR3
Wakeup in FLASH,
FSTEN = 1 in PWR_CR3
Wakeup in FLASH,
FSTEN = 0 in PWR_CR3
Wakeup in FLASH,
FSTEN = 1 in PWR_CR3
Wakeup time from
Shutdown to Run mode
-
Unit
µs
1. Evaluated by characterization. Not tested in production.
Table 75. Regulator mode transition times(1)
Symbol
tLDO(2)
tSMPS(2)
206/334
Parameter
SMSP to LDO transition time
LDO to SMPS transition time
Conditions
Typ (3 V, 30 °C)
Max (3 V)
Range 4
16.0
Range 3
15.0
17.0
Range 2
14.0
18.0
Range 1
14.0
16.0
Range 4
14.0
16.0(3)
Range 3
17.0
20.0
Range 2
16.0
19.0
Range 1
16.0
19.0
DS13086 Rev 6
Unit
(3)
20.0
µs
STM32U585xx
Electrical characteristics
Table 75. Regulator mode transition times(1) (continued)
Symbol
Parameter
Range 4 to range 3
Range 3 to range 2
tVOST(4)
Range 2 to range 1
Range 4 to range 1
Conditions
Typ (3 V, 30 °C)
Max (3 V)
LDO
19.0
21.0
SMPS
25.0
38.0
LDO
13.0
15.0
SMPS
13.0
23.0
LDO
12.0
14.0
SMPS
12.0
17.0
LDO
42.0
47.0
SMPS
48.0
76.0
Unit
µs
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Time to REGS change in PWR_SVMSR.
3. Tested in production at 30°C.
4. Time to VOSRDY = 1 in PWR_VOSR.
Table 76. Wakeup time using USART/LPUART(1)
Symbol
Parameter
Typ
Max
Unit
-
(2)
μs
Wakeup time needed to calculate the maximum USART/LPUART baudrate that
tWUUSART
is needed to wake up from Stop mode when the USART/LPUART kernel clock
tWULPUART
source is HSI16/MSI.
1. Specified by design. Not tested in production.
2. This wakeup time is the HSI16 (see Table 81) or the MSI (see Table 82) oscillator maximum startup time.
5.3.7
External clock timing characteristics
High-speed external user clock generated from an external source
In bypass mode, the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14: I/O port
characteristics. However, the recommended clock input waveform is shown in the figure
below.
Table 77. High-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Voltage scaling range 1, 2, 3
-
-
55
Voltage scaling range 4
-
-
25
Unit
fHSE_ext
User external clock source
frequency
VHSEH
OSC_IN input pin high-level voltage
-
0.7 × VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
-
VSS
-
0.3 × VDD
Voltage scaling range 1, 2, 3
7
-
-
Voltage scaling range 4
18
-
-
tw(HSEH)
OSC_IN high or low time
tw(HSEL)
MHz
V
ns
1. Specified by design. Not tested in production.
DS13086 Rev 6
207/334
299
Electrical characteristics
STM32U585xx
Figure 28. AC timing diagram for high-speed external clock source
VHSE
tw(HSEH)
VHSEH
70%
VHSEL
30%
t
tw(HSEL)
THSE
MSv67850V3
Low-speed external user clock generated from an external source
In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14: I/O port
characteristics. However, the recommended clock input waveform is shown in Figure 29
and Figure 30.
Table 78. Low-speed external user clock characteristics(1)
Symbol
fLSE_ext
VLSE_ext_PP
Parameter
Min
Typ
Max
Unit
5
32.768
40
kHz
0.3
-
VSW(2)
User external clock source frequency
OSC32_IN peak-to-peak amplitude
VLSE_ext
OSC32_IN input range
0
-
VSW(2)
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time for square signal input
10
-
-
1. Specified by design. Not tested in production.
2. VSW = VDD when VDD is above VBOR0, and VSW=VBAT when VDD is below VBOR0.
Figure 29. AC timing diagram for low-speed external square clock source
VLSE_ext
tw(LSEH)
VLSEH
70%
VLSE_ext_PP
VLSEL
30%
tLSE = 1/fLSE_ext
tw(LSEL)
t
MSv67851V3
208/334
DS13086 Rev 6
V
μs
STM32U585xx
Electrical characteristics
Figure 30. AC timing diagram for low-speed external sinusoidal clock source
VLSE_ext
VLSE_ext_PP
t
tLSE_ext = 1/fLSE_ext
MSv69160V1
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in the table below.
In the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins, in order to minimize the output distortion and startup
stabilization time. Refer to the crystal resonator manufacturer for more details on the
resonator characteristics (frequency, package, accuracy).
Table 79. HSE oscillator characteristics(1)
Symbol
fOSC_IN
RF
Conditions(2)
Min
Typ
Max
Unit
-
4
-
50
MHz
-
-
200
-
kΩ
-
-
8
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 4 MHz
-
670
-
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 8 MHz
-
530
-
VDD = 3 V, Rm = 45 Ω, CL = 10 pF @ 8 MHz
-
580
-
VDD = 3 V, Rm = 30 Ω, CL = 5 pF @ 48 MHz
-
980
-
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 48 MHz
-
1700
-
VDD = 3 V, Rm = 30 Ω, CL = 20 pF @ 48 MHz
-
2700
-
Maximum critical crystal
Startup
transconductance Gm
-
-
1.5
mA/V
Startup time
-
2
-
ms
Parameter
Oscillator frequency
Feedback resistor
During startup
IDD(HSE)
Gmcritmax
tsu(HSE)
(4)
HSE current
consumption
(3)
VDD stabilized
μA
1. Specified by design. Not tested in production.
DS13086 Rev 6
209/334
299
Electrical characteristics
STM32U585xx
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see the figure below). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance that is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).
Figure 31. Typical application with a 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
8 MHz
resonator
CL2
REXT (1)
fHSE
RF
Bias
controlled
gain
OSC_OUT
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in the table below. In the application,
the resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. Refer to
the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 80. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
IDD(LSE)
210/334
Parameter
LSE current
consumption
Conditions(2)
Min
Typ
Max
LSEDRV[1:0] = 01, medium low-drive capability
-
350
-
LSEDRV[1:0] = 10, medium high-drive capability
-
450
-
LSEDRV[1:0] = 11, high-drive capability
-
600
-
DS13086 Rev 6
Unit
nA
STM32U585xx
Electrical characteristics
Table 80. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (continued)
Symbol
Conditions(2)
Parameter
Maximum critical
Gmcritmax
crystal Gm
CS_PARA
Min
Typ
Max
LSEDRV[1:0] = 01, medium low-drive capability
-
-
0.75
LSEDRV[1:0] = 10, medium high-drive capability
-
-
1.7
LSEDRV[1:0] = 11, high-drive capability
-
-
2.7
-
3
-
pF
-
2
-
s
Internal stray
parasitic
capacitance(3)
-
tSU(LSE)(4) Startup time
VDD is stabilized
Unit
µA/V
1. Specified by design. Not tested in production.
2. Refer to the note below this table.
3. CS_PARA is the equivalent capacitance seen by the crystal due to OSC32_IN and OSC32_OUT internal parasitic
capacitances.
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).
Figure 32. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors
CL1
OSC32_IN
32.768 kHz resonator
fLSE
Drive
programmable
amplifier
CS
OSC32_OUT
CL2
Note: CL1 and CL2 are external load capacitances. Cs (stray capacitance) is the sum of the device OSC32_IN/OSC32_OUT pins
equivalent parasitic capacitance (CS_PARA), and the PCB parasitic capacitance.
Note:
MSv70418V1
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS13086 Rev 6
211/334
299
Electrical characteristics
5.3.8
STM32U585xx
Internal clock timing characteristics
The parameters given in the table below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33. The provided curves
are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 81. HSI16 oscillator characteristics
Symbol
Parameter
Conditions
fHSI16
fHSI16(1)
TRIM(2)
DuCy(HSI16)(2)
tsu(HSI16)
(2)
HSI16 frequency after factory
calibration
Min
Typ
Max
VDD = 3.0 V, TJ = 30 °C
15.92
16
16.08
TJ = –10 °C to 100 °C,
1.58 ≤ VDD ≤ 3.6 V
15.84
-
16.16
TJ = –40 °C to 130 °C,
1.58 ≤ VDD ≤ 3.6 V
15.65
-
16.25
MHz
HSI16 user trimming step
-
18
29
40
kHz
Duty cycle
-
45
-
55
%
HSI16 oscillator startup time
-
-
2.5
3.6
At 1% of target frequency
-
4
6
-
-
150
210
tstab(HSI16)(2)
HSI16 oscillator stabilization time
IDD(HSI16)(2)
HSI16 oscillator power consumption
1. Evaluated by characterization. Not tested in production. It does not take into account package and soldering effects.
2. Specified by design. Not tested in production.
212/334
Unit
DS13086 Rev 6
μs
μA
STM32U585xx
Electrical characteristics
Multi-speed internal (MSI) RC oscillator
Table 82. MSI oscillator characteristics(1)
Symbol
Parameter
Conditions
MSI mode
fMSI
MSI frequency
after factory
calibration
VDD = 3 V
TJ = 30 °C
Min
Typ
Max
MSI range 0
(MSIRC0)
47.74
48
48.70
MSI range 1
23.87
24
24.35
MSI range 2
15.91
16
16.23
MSI range 3
11.93
12
12.17
MSI range 4
(MSIRC1)
3.98
4
4.06
MSI range 5
1.99
2
2.03
MSI range 6
1.33
1.33
1.35
MSI range 7
0.99
1
1.01
MSI range 8
(MSIRC2)
3.05
3.08
3.12
MSI range 9
1.53
1.54
1.56
MSI range 10
1.02
1.03
1.04
MSI range 11
0.76
0.77
0.78
MSI range 12
(MSIRC3)
397.68
400
405.71
MSI range 13
198.84
200
202.86
MSI range 14
132.56
133
135.24
MSI range 15
99.42
100
101.43
MSI range 0
(MSIRC0)
-
48.005
-
MSI range 1
-
24.003
-
MSI range 2
-
16.002
-
MSI range 3
-
12.001
-
MSI range 4
(MSIRC1)
-
3.998
-
-
1.999
-
-
1.333
-
-
0.999
-
MSI range 8
(MSIRC2)
-
3.08
-
MSI range 9
-
1.54
-
MSI range 10
-
1.027
-
MSI range 11
-
0.77
-
PLL
mode(2)
MSI range 5
XTAL =
32.768 kHz MSI range 6
MSI range 7
DS13086 Rev 6
Unit
MHz
kHz
MHz
213/334
299
Electrical characteristics
STM32U585xx
Table 82. MSI oscillator characteristics(1) (continued)
Symbol
Parameter
fMSI (cont’d)
DuCy(MSI)
(3)
TRIM
MSI frequency
after factory
calibration
Duty cycle
∆FSAMPLING
(MSI)
(3)(4)
CC
jitter(MSI)(3)
MSI range 12
(MSIRC3)
RMS
cycle-to-cycle
jitter
Max
Unit
-
393
-
MHz
196.6
-
-
131
-
MSI range 15
-
98.3
-
MSI range 0, 4, 8, or 12
38
-
62
MSI range 2, 6, 10, or 14
31
-
69
Other MSI ranges
48
-
52
-
-
0.4
-
TJ = –40 to 130 °C
-4
-
2
MSI mode
MSI mode
PLL mode
P jitter(MSI)(3) RMS period jitter PLL mode
214/334
Typ
-
VDD = 3 V
TJ = 30 °C
MSI oscillator
frequency drift
MSI mode
over VDD
(reference is 3V)
MSI frequency
variation in
sampling mode
(MSIBIAS = 1)
Min
PLL mode
MSI range 13
XTAL =
32.768 kHz MSI range 14
User trimming
step
MSI oscillator
frequency drift
over
(4)
∆TEMP(MSI)
temperature
(reference is
30 °C)
∆VDD(MSI)(4)
Conditions
MSI range
0 to 3
1.58 ≤ VDD ≤ 3.6 V
-4
-
1
2.4 ≤ VDD ≤ 3.6 V
-1
-
1
MSI range
4 to 7
1.58 ≤ VDD ≤ 3.6 V
-3
-
1
2.4 ≤ VDD ≤ 3.6 V
-1
-
1
MSI range
8 to 11
1.58 ≤ VDD ≤ 3.6 V
-3
-
1
2.4 ≤ VDD ≤ 3.6 V
-1
-
1
MSI range
12 to 15
1.58 ≤ VDD ≤ 3.6 V
-3
-
1
2.4 ≤ VDD ≤ 3.6 V
-1
-
1
TJ = –40 to 130 °C
-
-
0.2
MSI range 0
-
60
-
MSI range 4
-
160
-
MSI range 8
-
200
-
MSI range 12
-
1100
-
MSI range 0
-
40
-
MSI range 4
-
130
-
MSI range 8
-
170
-
MSI range 12
-
800
-
DS13086 Rev 6
kHz
%
ps
STM32U585xx
Electrical characteristics
Table 82. MSI oscillator characteristics(1) (continued)
Conditions
MSI range 0 to 3
MSI oscillator
transition time(6)
MSI oscillator
PLL mode,
stabilization time MSIPLL
FAST = 0
PLL mode,
MSIPLL
FAST = 1
(3)
_PLLFAST)
-
4
MSIRC1
cycles +
11 MSI
cycles
-
4
MSIRC2
cycles +
11 MSI
cycles
-
4
MSIRC3
cycles +
11 MSI
cycles
-
-
3
destination MSI
cycles
-
-
10
-
-
200
-
-
0.8
-
MSI PLL-mode
oscillator power
consumption
when MSI is
disabled with
PLL accuracy
retention
-
-
Normal
mode
IDD(MSI_OFF
-
13
MSIRC0
cycles +
11 MSI
cycles
MSI oscillator
startup time(5)
MSI range 12 to 15
tstab(MSI)(3)
Max
-
MSI range 8 to 11
tswitch(MSI)(3)
Typ
-
MSI range 4 to 7
tsu(MSI)(3)
Min
Continuous
mode(7)
Sampling
mode(8)
All MSI
ranges
Final frequency
1% of final
frequency
µs
All MSI ranges
LDO
MSIPLL
EN = 1 and
MSIPLL
FAST = 1
SMPS
2
MSI range 0 to 3
-
6.6
-
MSI range 4 to 7
-
1.6
-
MSI range 8 to 11
-
1.4
-
MSI range 12 to 15
-
0.8
-
MSI range 0 to 3
-
4.7
-
MSI range 4 to 7
-
1.4
-
MSI range 8 to 11
-
1.3
-
MSI range 12 to 15
-
0.8
-
DS13086 Rev 6
Unit
cycles
Parameter
ms
cycles
Symbol
µA
215/334
299
Electrical characteristics
STM32U585xx
Table 82. MSI oscillator characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
MSI range 0 to 3
-
21 + 2.5
µA/MHz
-
MSI range 4 to 15
-
19 + 2.5
µA/MHz
-
MSI range 0 to 3
-
21 + 1,3
µA/MHz
-
MSI range 4 to 15
-
19 + 1,3
µA/MHz
-
Range 0 to 3
-
3 + 2.5
µA/MHz
-
Range 4 to 15
-
1+
2.5µA/
MHz
-
Range 0 to 3
-
3+1
µA/MHz
-
Range 4 to 15
-
1+1
µA/MHz
-
LDO
Continuous
mode(7)
SMPS(9)
IDD(MSI)(3)
MSI oscillator
power
consumption
LDO
Sampling
mode(8)
SMPS
Unit
µA
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. In PLL mode, the MSI accuracy is the LSE crystal accuracy.
3. Specified by design. Not tested in production.
4. This is a deviation for an individual part once the initial frequency has been measured.
5. The MSI startup time is the time when the four MSIRCs are in power down.
6. This delay is the time to switch from one MSIRC to another one. In case the destination MSIRC is in power down, the total
delay is tsu(MSI) + tswitch(MSI).
7. The MSI is in continuous mode when the internal regulator is in voltage range 1, 2 or 3.
8. The MSI is in sampling mode when MSIBIAS = 1 in RCC_ICSCR1, and the regulator is in voltage range 4, or when the
device is in Stop 1 or Stop 2 mode.
9. SMPS efficiency in range 1, based on VCORE current = 19.4 mA (CoreMark current on VCORE at 160 MHz).
High-speed internal 48 MHz (HSI48) RC oscillator
Table 83. HSI48 oscillator characteristics
Symbol
fHSI48
216/334
Parameter
Conditions
HSI48 frequency after factory calibration VDD = 3.0 V, TJ = 30 °C
DS13086 Rev 6
Min
Typ
Max
Unit
47.5
48
48.5
MHz
STM32U585xx
Electrical characteristics
Table 83. HSI48 oscillator characteristics (continued)
Symbol
TRIM
(1)
Parameter
Max
-
-
0.12
0.18
±4.5
±7.56
-
45
-
55
-
ACCHSI48_REL
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
Reference is 3 V and 30 °C(3).
∆VDD(HSI48)(1)
HSI48 frequency drift with VDD(4)
NT jitter(1)
Next transition jitter
Accumulated jitter on 28 cycles(5)
PT jitter(1)
tsu(HSI48)(1)
IDD(HSI48)
Typ
±63 steps
DuCy(HSI48)(1) Duty cycle
(1)
Min
User trimming step
USER TRIM
User trimming coverage
COVERAGE(2)
(2)
Conditions
Unit
%
1.58 V ≤ VDD ≤ 3.6 V,
TJ = –40 to 125 °C
-3
-
2
3.0 V ≤ VDD ≤ 3.6 V
-
0.025
0.05
1.58 V ≤ VDD ≤ 3.6 V
-
0.05
0.1
-
-
±0.15
-
Paired transition jitter
Accumulated jitter on 56 cycles(5)
-
-
±0.25
-
HSI48 oscillator startup time
-
-
2.5
6
μs
HSI48 oscillator power consumption
-
-
350
400
μA
ns
1. Specified by design. Not tested in production.
2. Evaluated by characterization. Not tested in production.
3. ∆fHSI = ACCHSI48_REL + ∆VDD.
4. These values are obtained with one of the following formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or
(Freq(3.6 V) - Freq(1.58 V)) / Freq(1.58 V).
5. Jitter measurements are performed without clock source activated in parallel.
Figure 33. HSI48 frequency versus temperature
MSv69123V1
DS13086 Rev 6
217/334
299
Electrical characteristics
STM32U585xx
Secure high-speed internal (SHSI) RC oscillator
Table 84. SHSI oscillator characteristics(1)
Symbol
Conditions
Min
Typ
Max
Unit
SHSI frequency
-
-
48
-
MHz
tSU(SHSI)
SHSI oscillator startup time
-
-
2.5
6
μs
IDD(SHSI)
SHSI oscillator power consumption
-
-
350
400
μA
fSHSI
Parameter
1. Specified by design. Not tested in production.
Low-speed internal (LSI) RC oscillator
Table 85. LSI oscillator characteristics
Symbol
fLSI
Parameter
Conditions
Min
Typ
Max
VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 0
31.4
-
32.6
VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 1
0.245
-
0.255
1.58 V≤ VDD ≤ 3.6 V, TJ = –40 to 125 °C
30.4(1)
-
33.6(1)
-
50
-
-
-
230
260
LSI oscillator stabilization time 5% of final frequency
-
230
260
LSIPREDIV = 0
-
140
255
LSIPREDIV = 1
-
130
240
LSI frequency
DuCy(LSI) LSI duty cycle
tSU(LSI)
(2)
tSTAB(LSI)
(2)
IDD(LSI)(2)
LSIPREDIV = 1
LSI oscillator startup time
LSI oscillator power
consumption
Unit
kHz
%
μs
nA
1. Evaluated by characterization. Not tested in production.
2. Specified by design. Not tested in production.
5.3.9
PLL characteristics
The parameters given in the table below are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 33.
Table 86. PLL characteristics(1)
Symbol
fPLL_IN
fPLL_OUT
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
4
-
16
MHz
PLL input clock
duty cycle
-
10
-
90
%
Voltage scaling range 1
1
-
160(2)
Voltage scaling range 2
1
-
110
Voltage scaling range 3
1
-
55
Voltage scaling range 1, 2
128
-
544
Voltage scaling range 3
128
-
330
Duty cycle with division 1
40
-
60
PLL P, Q, R
output clock
fVCO_OUT PLL VCO output
218/334
DS13086 Rev 6
MHz
%
STM32U585xx
Electrical characteristics
Table 86. PLL characteristics(1) (continued)
Symbol
Parameter
tLOCK(3)(4) PLL lock time
RMS cycle-tocycle jitter
Jitter
RMS period jitter
Long-term
jitter(5),
fPLL_IN = 8 MHz
IDD(PLL)
IDD(PLL)
PLL power
consumption on
VDD
with LDO
PLL power
consumption on
VDD
with SMPS
Conditions
Min
Typ
Max
Integer mode
-
25
50
Fractional mode
-
40
65
Integer mode, VCO = 544 MHz
-
20
-
Fractional mode, VCO = 544 MHz
-
70
-
Integer mode, VCO = 544 MHz
-
35
-
Fractional mode, VCO = 544 MHz
-
45
-
Integer mode, VCO = 544 MHz
-
160
-
Fractional mode, VCO = 544 MHz
-
170
-
VCO freq = 160 MHz,
Range 1
1 clock output
-
370
-
VCO freq = 160 MHz,
Range 1
3 clock outputs
-
390
-
-
460
-
-
435
-
-
410
-
VCO freq = 336 MHz,
Range 1
1 clock output
-
710
-
VCO freq = 544 MHz,
Range 1
1 clock output
-
1100
-
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA
1 clock output
-
260
-
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA
3 clock outputs
-
270
-
Range 1, IVCORE(6) = 19.4 mA
-
320
-
-
300
-
-
290
-
VCO freq = 336 MHz,
Range 1, IVCORE(6) = 19.4 mA
1 clock output
-
470
-
VCO freq = 544 MHz,
Range 1, IVCORE(6) = 19.4 mA
1 clock output
-
730
-
Range 1
VCO freq = 200 MHz,
Range 2
1 clock output
Range 3
VCO freq = 200 MHz,
Range 2, IVCORE(6) = 11.7 mA
1 clock output
Range 3, IVCORE(6) = 5.74 mA
Unit
μs
±ps
μA
1. Specified by design and not tested in production, unless otherwise specified.
2. PLL1 output Q and PLL2 output Q can be up to 200 MHz only when selected as OCTOSPI clock.
3. Evaluated by characterization. Not tested in production.
4. Lock time is the duration until PLLxRDY flag (2% of final frequency).
5. Measured on 5000 cycles.
6. SMPS efficiency based on CoreMark RUN current on VCORE at max frequency of each voltage range.
DS13086 Rev 6
219/334
299
Electrical characteristics
5.3.10
STM32U585xx
Flash memory characteristics
Table 87. Flash memory characteristics(1)
Symbol
tprog
128-bit programming time
tprog_bank One 1-Mbyte bank programming time
tME
Max(2)
Normal mode
118
118
Burst mode
48
48
fAHB = 160 MHz, normal mode
60.2
-
fAHB = 160 MHz, burst mode
24.5
-
fAHB = 160 MHz, normal mode
7710
-
fAHB = 160 MHz, burst mode
3140
-
10 k endurance cycles
1.5
2.4
100 k endurance cycles
1.7
3.4
195
308
390
616
Write mode
2.1
-
Erase mode
1.3
-
Write mode
2.6
-
Erase mode
3.0
-
Conditions
tprog_page One 8-Kbyte page programming time
tERASE
Typ
Parameter
One 8-Kbyte page erase time
Mass erase time (one bank)
10 k endurance cycles
Mass erase time (two banks)
Average consumption from VDD
IDD(3)
Maximum current (peak)
Unit
µs
ms
mA
1. Specified by design. Not tested in production.
2. Evaluated by characterization after cycling. Not tested in production.
3. Evaluated by characterization. Not tested in production.
Table 88. Flash memory endurance and data retention
Symbol
NEND
Parameter
Endurance
Min(1)
Conditions
Whole bank
Limited to 256 Kbytes per bank
10
TA = –40 to 125 °C
100
TA = 85 °C after 1 kcycle(2)
TA = 125 °C after 1
15
kcycle(2)
10
tRET
(2)
30
TA = 85 °C after 10 kcycles(2)
15
TA = 55 °C after 10 kcycles
Data retention
(2)
10
TA = 55 °C after 100
kcycles(2)
30
Limited to 256 Kbytes per bank TA = 85 °C after 100
kcycles(2)
15
TA = 105 °C after 10 kcycles
TA = 105 °C after 100 kcycles(2)
1. Evaluated by characterization. Not tested in production.
2. Cycling performed over the whole temperature range.
220/334
DS13086 Rev 6
kcycles
30
(2)
TA = 105 °C after 1 kcycle
Whole bank
Unit
10
Years
STM32U585xx
5.3.11
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling two LEDs through the
I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The
failure is indicated by the LEDs as follows:
•
Electrostatic discharge (ESD) (positive and negative): applied to all device pins until a
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB (fast transient voltage burst) (positive and negative): applied to VDD and VSS pins
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in the table below. They are based on the EMS levels and classes
defined in application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).
Table 89. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
BGA169 conforming to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS pins
to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
BGA169 conforming to IEC 61000-4-4
5A
Designing hardened software to avoid noise problems
The EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. Note that good EMC performance is
highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for the application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
DS13086 Rev 6
221/334
299
Electrical characteristics
STM32U585xx
to prevent unrecoverable errors occurring. See application note Software techniques for
improving microcontrollers EMC performance (AN1015) for more details.
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard that specifies the test board and the pin loading.
Table 90. EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz
Symbol Parameter
SEMI
Peak(1)
Conditions
VDD = 3.6 V, TA = 25 °C,
BGA169 package compliant
with IEC 61967-2
Level(2)
Monitored frequency
band
Value
0.1 MHz to 30 MHz
5
30 MHz to 130 MHz
6
130 MHz to 1 GHz
6
1 GHz to 2 GHz
7
0.1 MHz to 2 GHz
2
Unit
dBμV
-
1. Refer to the EMI radiated test section of the application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).
2. Refer to the EMI level classification section of the application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).
5.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, latch-up) using specific measurement methods, the
device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 91. ESD absolute maximum ratings(1)
Symbol
VESD(HBM)
Ratings
Electrostatic discharge
voltage (human body model)
Packages
Class
TA = 25 °C, conforming to
ANSI/ESDA/JEDEC JS-001
All
2
2000
LQFP100
LQFP144
C1
250
UFQFPN48
LQFP48
LQFP64
C2A
500
WLCSP90
UFBGA132
UFBGA169
C2B
750
Electrostatic discharge
TA = 25 °C, conforming to
VESD(CDM)
voltage (charge device model) ANSI/ESDA/JEDEC JS-002
1. Evaluated by characterization. Not tested in production.
222/334
Max
Unit
value
Conditions
DS13086 Rev 6
V
STM32U585xx
Electrical characteristics
Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin.
•
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.
Table 92. Electrical sensitivities(1)
Symbol
LU
Parameter
Static latch-up class
Conditions
Class
TJ = 130 °C conforming to JESD78E
2
1. Evaluated by characterization. Not tested in production.
5.3.13
I/O current injection characteristics
As a general rule, the current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) must be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller if
abnormal injection accidentally happens, some susceptibility tests are performed on a
sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating-input mode. While this current is injected
into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter, such as an ADC error above a certain
limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on
adjacent pins (out of the -5 µA/+0 µA range), or other functional failure (for example reset
occurrence or oscillator frequency deviation).
The characterization results are given in the table below. The negative induced leakage
current is caused by the negative injection. The positive induced leakage current is caused
by the positive injection.
Table 93. I/O current injection susceptibility(1)(2)
Functional susceptibility
Symbol
IINJ
Description
Unit
Negative injection
Positive injection
Injected current on OPAMP1_VINM,
OPAMP2_VINM, PA4, PA5, PB0, PE7, PB15,
PC11, and PD0 pins
0
0
Injected current on all other pins
5
N/A
mA
1. Evaluated by characterization. Not tested in production.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
DS13086 Rev 6
223/334
299
Electrical characteristics
5.3.14
STM32U585xx
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the conditions summarized in Table 33. All I/Os are designed as
CMOS- and TTL-compliant.
Note:
For information on GPIO configuration, refer to the application note ‘STM32 GPIO
configuration for hardware settings and low-power consumption’ (AN4899).
Sym
-bol
VIL(2)
VIH
(2)
Parameter
I/O input
low-level
voltage
I/O input
high-level
voltage
Vhys Input
(3)
hysteresis
Conditions
Min
Typ
Max
1.08 V ≤ VDDIOx ≤ 3.6 V
-
-
0.3 VDDIOx
All I/Os except FT_c
-
-
0.38 VDDIOx(3)
FT_c I/Os
-
-
0.3 VDDIOx
1.08 V ≤ VDDIOx ≤ 3.6 V
0.7 VDDIOx
-
-
All I/Os except FT_c
0.5 VDDIOx
+ 0.2(3)
-
-
FT_c I/Os
0.7 VDDIOx
-
-
-
250
-
VIN ≤ Max (VDDXXX)(5)
-
-
150
Max (VDDXXX) < VIN
≤ Max (VDDXXX) + 1 V(6)
-
-
2000
Max (VDDXXX) + 1 V < VIN
≤ 5.5 V(6)
-
-
500
VIN ≤ Max (VDDXXX)(5)
-
-
200
-
2500
TT_xx, FT_xx I/Os
all I/Os except FT_u,
FT_c, FT_d, FT_t,
TT_xx
FT_u I/Os
Input
(3)(4) leakage
current
Ilkg
FT_c I/Os
FT_d I/Os
FT_t I/Os
224/334
Max (VDDXXX) < VIN
≤ Max (VDDXXX) + 1 V(6)
Max (VDDXXX) + 1 V < VIN
≤ 5.5 V(6)
-
-
500
VIN ≤ Max (VDDXXX)
-
-
1500
Max (VDDXXX) < VIN ≤ 5 V(6)
-
-
2000
VIN ≤ Max (VDDXXX)
-
-
1500
Max (VDDXXX) < VIN ≤ 5.5 V(6)
-
-
5000
V
mV
nA
VIN ≤ Max (VDDXXX)
300
Max (VDDXXX) < VIN
≤ Max (VDDXXX) + 1 V(6)
3000
Max (VDDXXX) + 1 V < VIN
≤ 5.5 V(6)
600
DS13086 Rev 6
Unit
Table 94. I/O static characteristics(1)
STM32U585xx
Electrical characteristics
Sym
-bol
Parameter
Input
(3)(4) leakage
current
Ilkg
Conditions
TT_xx I/Os except
OPAMPx_VINM
(x = 1, 2)
VIN ≤ Max (VDDXXX)
Min
Typ
Max
-
-
500
nA
OPAMPx_VINM (x = 1, 2) dedicated input leakage
current
-
-
(7)
30
40
50
Weak
pull-up
RPU
equivalent
resistor(8)
-
Weak
pull-down
RPD
equivalent
resistor(8)
-
30
40
50
-
-
5
-
CIO
I/O pin
capacitance
Unit
Table 94. I/O static characteristics(1) (continued)
kΩ
pF
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. Refer to Figure 34: I/O input characteristics (all I/Os except BOOT0 and FT_c).
3. Specified by design. Not tested in production.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA+ [number of I/Os where VIN is applied on the pad] ₓ Ilkg max.
5. Max (VDDXXX) is the maximum value of all the I/O supplies. The I/O supplies depend on the I/O structure options, as
described in Table 26: Legend/abbreviations used in the pinout table.
6. To sustain a voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors must
be disabled.
7. Refer to Ibias in the OPAMP characteristics table for the values of the OPAMP dedicated input leakage current.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.
This PMOS/NMOS contribution to the series resistance is minimal (~10% order).
DS13086 Rev 6
225/334
299
Electrical characteristics
STM32U585xx
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in the figure below.
Figure 34. I/O input characteristics (all I/Os except BOOT0 and FT_c)
MSv69136V1
226/334
DS13086 Rev 6
STM32U585xx
Electrical characteristics
Output driving current
The GPIOs (except PC13, PC14, PC15) can sink or source up to ±8 mA, and sink or source
up to ± 20 mA (with a relaxed VOL/VOH). PC13, PC14, PC15 are limited to ±3 mA shared
between the three I/Os.
In the user application, the number of I/O pins tat can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2: Absolute maximum ratings:
•
The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 31: Current characteristics).
•
The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS
(see Table 31: Current characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 33. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).
Table 95. Output voltage characteristics(1)(2)(3)
Symbol
Parameter
VOL
Output low-level voltage
VOH
Output high-level voltage
VOL(5)
Output low-level voltage
VOH(5)
Output high-level voltage
VOL(5)
Output low-level voltage
VOH(5)
Output high-level voltage
VOL(5)
Output low-level voltage
VOH(5)
Output high-level voltage
VOL(5)
Output low-level voltage
VOH(5)
Output high-level voltage
VOLFM+(5)
Output low-level voltage for
a FT_f I/O pin in FM+ mode
Conditions
Min
Max
-
0.4
VDDIOx - 0.4
-
-
0.4
2.4
-
-
1.3
VDDIOx - 1.3
-
-
0.4
VDDIOx - 0.4
-
-
0.4
VDDIOx - 0.4
-
|IIO| = 20 mA,
2.7 V ≤ VDDIOx ≤ 3.6 V
-
0.4
|IIO| = 10 mA,
1.58 V ≤ VDDIOx ≤ 3.6 V
-
0.4
|IIO| = 2 mA,
1.08 V ≤ VDDIOx < 3.6 V
-
0.4
CMOS port(4), |IIO| = 8 mA,
2.7 V ≤ VDDIOx ≤ 3.6 V
TTL port(4),|IIO| = 8 mA,
2.7 V ≤ VDDIOx ≤ 3.6 V
All I/Os, |IIO| = 20 mA,
2.7 V ≤ VDDIOx ≤ 3.6 V
|IIO| = 4 mA,
1.58 V ≤ VDDIOx ≤ 3.6 V
|IIO| = 1 mA,
1.08 V ≤ VDDIOx @
'
WVX 1:$,79&/.+
'
WK &/.+1:$,79
WG &/.+1%/+
)0&B1%/
06Y9
Table 136. Synchronous multiplexed PSRAM write timings(1)
Symbol
tw(CLK)
Parameter
FMC_CLK period, 2.7 V ≤ VDD ≤ 3.6 V
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x = 0..2)
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x = 0..2)
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
DS13086 Rev 6
Min
Max
2 × tHCLK - 0.5
-
-
2
tHCLK + 1.5
-
-
2
Unit
ns
275/334
299
Electrical characteristics
STM32U585xx
Table 136. Synchronous multiplexed PSRAM write timings(1) (continued)
Symbol
Parameter
Min
Max
FMC_CLK low to FMC_NADV high
1
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x = 16..25)
-
3
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x = 16..25)
tHCLK
-
-
2.5
tHCLK + 1
-
td(CLKL-NADVH)
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
td(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
2
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
td(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK low
-
3
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
-
2
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
tHCLK + 0.5
-
3
-
2.5
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
1. Evaluated by characterization. Not tested in production.
Figure 57. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK)
tw(CLK)
FMC_CLK
td(CLKL-NExL)
td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV
td(CLKH-AIV)
td(CLKL-AV)
FMC_A[25:0]
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
FMC_D[15:0]
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
D1
tsu(NWAITV-CLKH)
tsu(NWAITV-CLKH)
tsu(NWAITV-CLKH)
th(CLKH-DV)
D2
th(CLKH-NWAITV)
t h(CLKH-NWAITV)
th(CLKH-NWAITV)
MS32759V1
276/334
DS13086 Rev 6
Unit
ns
STM32U585xx
Electrical characteristics
Table 137. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
tw(CLK)
FMC_CLK period
Min
Max
tHCLK - 0.5
-
-
1
tHCLK - 0.5
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x = 0..2)
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x = 0…2)
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
1.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
1
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x = 0…25)
-
2.5
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x = 0…25)
tHCLK - 0.5
-
-
1.5
tHCLK + 1
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
tsu(DV-CLKH)
FMC_D[15:0] valid data before FMC_CLK high
3
-
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK high
4
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
1
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
2.5
-
Unit
ns
1. Evaluated by characterization. Not tested in production.
Figure 58. Synchronous non-multiplexed PSRAM write timings
WZ &/.
WZ &/.
)0&B&/.
WG &/./1([/
WG &/.+1([+
'DWDODWHQF\
)0&B1([
WG &/./1$'9/
WG &/./1$'9+
)0&B1$'9
WG &/.+$,9
WG &/./$9
)0&B$> @
WG &/.+1:(+
WG &/./1:(/
)0&B1:(
WG &/./'DWD
WG &/./'DWD
)0&B'> @
'
'
)0&B1:$,7
:$,7&)* E:$,732/E
WVX 1:$,79&/.+
WG &/.+1%/+
WK &/.+1:$,79
)0&B1%/
06Y9
DS13086 Rev 6
277/334
299
Electrical characteristics
STM32U585xx
Table 138. Synchronous non-multiplexed PSRAM write timings(1)
Symbol
tw(CLK)
Parameter
FMC_CLK period
Min
Max
2 × tHCLK - 0.5
-
-
3
tHCLK + 1.5
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x = 0..2)
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x = 0..2)
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
2
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
1
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x = 16..25)
-
3
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x = 16..25)
tHCLK
-
-
2.5
tHCLK + 1
-
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
td(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK low
-
3
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
-
2
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
tHCLK + 0.5
-
3
-
2.5
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
Unit
ns
1. Evaluated by characterization. Not tested in production.
NAND controller waveforms and timings
Figure 59 to Figure 62 represent synchronous waveforms, and Table 139/Table 140 provide
the corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
•
COM.FMC_SetupTime = 0x01
•
COM.FMC_WaitSetupTime = 0x03
•
COM.FMC_HoldSetupTime = 0x02
•
COM.FMC_HiZSetupTime = 0x01
•
ATT.FMC_SetupTime = 0x01
•
ATT.FMC_WaitSetupTime = 0x03
•
ATT.FMC_HoldSetupTime = 0x02
•
ATT.FMC_HiZSetupTime = 0x01
•
Bank = FMC_Bank_NAND
•
MemoryDataWidth = FMC_MemoryDataWidth_16b
•
ECC = FMC_ECC_Enable
•
ECCPageSize = FMC_ECCPageSize_512Bytes
•
TCLRSetupTime = 0
•
TARSetupTime = 0
In all timing tables, the THCLK is the HCLK clock period.
278/334
DS13086 Rev 6
STM32U585xx
Electrical characteristics
Figure 59. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
th(NOE-ALE)
td(NCE-NOE)
FMC_NOE (NRE)
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MSv38003V1
Figure 60. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NWE-ALE)
td(NCE-NWE)
FMC_NWE
FMC_NOE (NRE)
th(NWE-D)
tv(NWE-D)
FMC_D[15:0]
MSv38004V1
Figure 61. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NOE-ALE)
td(NCE-NOE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MSv38005V1
DS13086 Rev 6
279/334
299
Electrical characteristics
STM32U585xx
Figure 62. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE)
tw(NWE)
th(NOE-ALE)
FMC_NWE
FMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FMC_D[15:0]
MSv38006V1
Table 139. Switching characteristics for NAND Flash read cycles(1)
Symbol
tw(N0E)
Parameter
FMC_NOE low width
Min
Max
4 × tHCLK - 0.5
4 × tHCLK + 0.5
tsu(D-NOE)
FMC_D[15-0] valid data before FMC_NOE high
10
-
th(NOE-D)
FMC_D[15-0] valid data after FMC_NOE high
0
-
td(ALE-NOE)
FMC_ALE valid before FMC_NOE low
-
3 × tHCLK + 0.5
th(NOE-ALE)
FMC_NWE high to FMC_ALE invalid
4 × tHCLK - 1
-
Unit
ns
1. Evaluated by characterization. Not tested in production.
Table 140. Switching characteristics for NAND Flash write cycles(1)
Symbol
tw(NWE)
Parameter
FMC_NWE low width
Min
Max
4 × tHCLK - 0.5
4 × tHCLK + 0.5
0
-
tv(NWE-D)
FMC_NWE low to FMC_D[15-0] valid
th(NWE-D)
FMC_NWE high to FMC_D[15-0] invalid
2 × tHCLK + 1
-
td(D-NWE)
FMC_D[15-0] valid before FMC_NWE high
5 × tHCLK - 5
-
-
3 × tHCLK + 0.5
2 × tHCLK - 0.5
-
td(ALE_NWE)
FMC_ALE valid before FMC_NWE low
th(NWE-ALE)
FMC_NWE high to FMC_ALE invalid
1. Evaluated by characterization. Not tested in production.
280/334
DS13086 Rev 6
Unit
ns
STM32U585xx
5.3.33
Electrical characteristics
OCTOSPI characteristics
Unless otherwise specified, the parameters given in Table 141 toTable 143 are derived from
tests performed under the ambient temperature, fAHB frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
Delay block enabled for DTR (with DQS)/HyperBus
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1 unless otherwise specified
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 141. OCTOSPI characteristics in SDR mode(1)(2)(3)
Symbol
f(CLK)
Parameter
OCTOSPI clock
frequency
Conditions
Min
Typ
Max
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 1
CL = 15 pF
-
-
93
2.7 V ≤ VDD ≤ 3.6 V
Voltage range1
CL = 15 pF
-
-
100
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4
CL = 15 pF
-
-
24
t(CLK)/2 - 0.5
-
t(CLK)/2
t(CLK)/2 - 0.5
-
t(CLK)/2
(n/2) × t(CLK)
/(n+1) - 0.5
-
(n/2) × t(CLK)
/(n+1)
((n/2)+1) × t(CLK)
/(n+1) - 0.5
-
((n/2)+1) × t(CLK)
/(n+1)
Voltage range 1
2.75
-
-
Voltage range 4
3
-
-
Voltage range 1
0.5
-
-
Voltage range 4
1
-
-
Voltage range 1
-
0.5
1
Voltage range 4
-
1.5
2.5
Voltage range 1
0.5
-
-
Voltage range 4
-0.25
-
-
tw(CLKH) OCTOSPI clock high
and low time
tw(CLKL) (even division)
PRESCALER[7:0] = n
(n = 1, 3, 5,..255)
tw(CLKH) OCTOSPI clock high
and low time
(odd division)
t
PRESCALER[7:0] = n
(n = 2, 4, 6,..254)
w(CLKL)
ts(IN)
Data input setup time
th(IN)
Data input hold time
tv(OUT)
Data output valid time
th(OUT)
Data output hold time
Unit
MHz
ns
1. Evaluated by characterization. Not tested in production.
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.
DS13086 Rev 6
281/334
299
Electrical characteristics
STM32U585xx
Table 142. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)
Sym
bol
f(CLK)
Parameter
OCTOSPI clock
frequency
tw(CLKH) OCTOSPI clock
high and low time
tw(CLKL) (even division)
tw(CLKH) OCTOSPI clock
high and low time
(odd division)
t
Conditions
Min
Typ
Max
1.71 V ≤ VDD ≤ 3.6 V Voltage
range 1, CL = 15 pF
-
-
93(4)
2.7 V ≤ VDD ≤ 3.6 V
Voltage range1, CL = 15 pF
-
-
100(4)
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4, CL = 15 pF
-
-
24(4)
t(CLK)/2 - 0.5
-
t(CLK)/2 + 0.5
t(CLK)/2 - 0.5
-
t(CLK)/2 + 0.5
(n/2) × t(CLK)
/(n+1) - 0.5
-
(n/2) × t(CLK)
/(n+1) + 0.5
((n/2)+1) × t(CLK)
/(n+1) - 0.5
-
((n/2)+1) × t(CLK)
/(n+1) + 0.5
PRESCALER[7:0] = n
(n = 1, 3, 5,..255)
PRESCALER[7:0] = n
(n = 2, 4, 6,..254)
w(CLKL)
tsr(IN)
tsf(IN)
Data input setup
time
Voltage range 1
3.25
-
-
Voltage range 4
3.75
-
-
thr(IN)
thf(IN)
Data input hold
time
Voltage range 1
1
-
-
Voltage range 4
1.5
-
-
Data output valid
time, DHQC = 0
Voltage range 1
-
6
9.25
Voltage range 4
-
13.25
19.75
Data output valid
time, DHQC = 1
Voltage range 1
All prescaler values (except 0)
-
t(CLK)/4
+ 0.75
t(CLK)/4 + 1.5
Data output hold
time DHQC = 0
Voltage range 1
4
-
-
Voltage range 4
8
-
-
Data output hold
time DHQC = 1
Voltage range 1
All prescaler values (except 0)
t(CLK)/4 - 0.5
-
-
tvr(OUT)
tvf(OUT)
thr(OUT)
thf(OUT)
1. Evaluated by characterization. Not tested in production.
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.
4. Activating DHQC is mandatory to reach this frequency.
282/334
DS13086 Rev 6
Unit
MHz
ns
STM32U585xx
Electrical characteristics
Table 143. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2)
Symbol
f(CLK)
tw(CLKH)
tw(CLKL)
tw(CLKH)
tw(CLKL)
Parameter
OCTOSPI clock
frequency
Conditions
Min
Typ
Max
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 1
CL = 15 pF
-
-
93(3)(4)
2.7 V ≤ VDD ≤ 3.6 V
Voltage range1
CL = 15 pF
-
-
100(3)(4)
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4
CL = 15 pF
-
-
24(4)
t(CLK)/2 - 0.5
-
t(CLK)/2 + 0.5
t(CLK)/2 - 0.5
-
t(CLK)/2 + 0.5
(n/2) × t(CLK)
/(n+1) - 0.5
-
(n/2) × t(CLK)
/(n+1) + 0.5
((n/2)+1) × t(CLK)
/(n+1) - 0.5
-
((n/2)+1) × t(CLK)
/(n+1) + 0.5
OCTOSPI clock
high and low time
(even division)
PRESCALER[7:0] = n
(n = 1, 3, 5,..255)
OCTOSPI clock
high and low time
(odd division)
PRESCALER[7:0] = n
(n = 2, 4, 6,..254)
tv(CLK)
Clock valid time
-
-
-
t(CLK) + 2
th(CLK)
Clock hold time
-
t(CLK)/2 - 0.5
-
-
975
-
1120
CLK, NCLK
crossing level on
CLK rising edge
VDD = 1.8 V
(5)
CLK, NCLK
crossing level on
CLK falling edge
VDD = 1.8 V
tw(CS)
Chip select high
time
tv(DQ)
Data input valid
time
tv(DS)
Data strobe input
valid time
th(DS)
Data strobe input
hold time
Data strobe output
valid time
VODr(CLK)
(5)
VODf(CLK)
tv(RWDS)
tsr(DQ)
tsf(DQ)
Data input setup
time
thr(DQ)
thf(DQ)
Data input hold
time
Unit
MHz
ns
mV
845
-
990
-
3 × t(CLK)
-
-
-
0
-
-
0
-
-
-
0
-
-
-
-
-
3 × t(CLK)
Voltage range 1
-0.5
-
t(CLK)/2 - 1.5(6)
Voltage range 4
-0.25
-
t(CLK)/2 - 1.75(6)
Voltage range 1
1.5
-
-
Voltage range 4
1.75
-
-
DS13086 Rev 6
ns
283/334
299
Electrical characteristics
STM32U585xx
Table 143. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2) (continued)
Symbol
tvr(OUT)
tvf(OUT)
Parameter
Conditions
Data output valid
time DHQC = 0
Data output valid
time DHQC = 1
thr(OUT)
thf(OUT)
Data output hold
time DHQC = 0
thr(OUT)
Data output hold
time DHQC = 1
Min
Typ
Max
Voltage range 1
-
6
9.5
Voltage range 4
-
13
19.5
Voltage range 1
All prescaler values
(except 0)
-
t(CLK)/4 + 0.5
t(CLK)/4 + 1.25
Voltage range 1
4
-
-
Voltage range 4
7.75
-
-
t(CLK)/4 - 0.5
-
-
Voltage range 1
All prescaler values
(except 0)
1. Evaluated by characterization. Not tested in production.
2. Delay block activated.
3. Maximum frequency values are given for a RWDS to DQ skew of maximum ±1.0 ns.
4. Activating DHQC is mandatory to reach this frequency.
5. Crossing results are in line with specification, except for PA3/PB5 CLK that exceed slightly the specification.
6. Data input maximum setup time does not take into account the data level switching duration.
Figure 63. OCTOSPI timing diagram - SDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
ts(IN)
Data input
D2
th(IN)
D0
D1
D2
MSv36878V3
Figure 64. OCTOSPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT)
Data output
thr(OUT)
D0
tvr(OUT)
D1
D2
thf(OUT)
D3
tsf(IN) thf(IN)
Data input
D0
D1
D4
D5
tsr(IN) thr(IN)
D2
D3
D4
D5
MSv36879V4
284/334
DS13086 Rev 6
Unit
ns
STM32U585xx
Electrical characteristics
Figure 65. OCTOSPI HyperBus clock
tr(CLK)
tf(NCLK)
tw(CLKH)
tw(NCLKL)
t(CLK)
t(NCLK)
tw(CLKL)
tw(NCLKH)
tf(CLK)
tr(NCLK)
NCLK
VOD(CLK)
CLK
MSv47732V3
Figure 66. OCTOSPI HyperBus read
tw(CS)
NCS
tv(CLK)
th(CLK)
t ACC= Initial access
CLK, NCLK
tv(RWDS)
tv(DS)
th(DS)
RWDS
tv(OUT)
47:40 39:32
DQ[7:0]
th(OUT)
31:24
23:16
Latency count
15:8
7:0
Command address
tv(DQ) ts(DQ)
th(DQ)
Dn
A
Dn+1
A
Dn
B
Dn+1
B
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS.
MSv47733V3
Figure 67. OCTOSPI HyperBus read with double latency
NCS
tRWR=Read/write recovery
Additional latency
tACC = Access
CLK, NCLK
tCKDS
RWDS
DQ[7:0]
High = 2x latency count
Low = 1x latency count
47:40 39:32 31:24 23:16 15:8
RWDS and data
are edge aligned
Dn
A
7:0
Command address
Dn
B
Dn+1 Dn+1
A
B
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS.
DS13086 Rev 6
MSv49351V3
285/334
299
Electrical characteristics
STM32U585xx
Figure 68. OCTOSPI HyperBus write
tw(CS)
NCS
Read write recovery
Access latency
tv(CLK)
th(CLK)
CLK, NCLK
tv(RWDS) High = 2x latency count
tv(OUT)
th(OUT)
tv(OUT)
th(OUT)
Low = 1x latency count
RWDS
Latency count
DQ[7:0]
tv(OUT)
th(OUT)
47:40
31:24
39:32
23:16
15:8
Dn
A
7:0
Command address
Dn
B
Dn+1
A
Dn+1
B
Host drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3
5.3.34
SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 144 and Table 145 are derived
from tests performed under the ambient temperature, fAHB frequency and VDD supply
voltage conditions summarized in Table 33, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.
Table 144. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2)
Symbol
fPP
Parameter
Clock frequency in data transfer mode
Conditions
Min
Typ
Max
Unit
-
0
-
100(3)
MHz
tW(CKL)
Clock low time
fPP = 52 MHz
8.5
9.5
-
tW(CKH)
Clock high time
fPP = 52 MHz
8.5
9.5
-
ns
CMD, D inputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes
tISU
Input setup time HS
-
3.5
-
-
tIH
Input hold time HS
-
1.5
-
-
Input valid window (variable window)
-
4.5
-
-
tIDW(5)
286/334
DS13086 Rev 6
ns
STM32U585xx
Electrical characteristics
Table 144. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D outputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes
tOV
Output valid time HS
-
-
5.5
6
tOH
Output hold time HS
-
4
-
-
ns
CMD, D inputs (referenced to CK) in SD default mode
tISU
Input setup time SD
-
3.5
-
-
tIH
Input hold time SD
-
1.5
-
-
ns
CMD, D outputs (referenced to CK) in SD default mode
tOV
Output valid default time SD
-
-
0.5
2
tOH
Output hold default time SD
-
0
-
-
ns
1. Evaluated by characterization. Not tested in production.
2. For SDMMC2 in SD/e.MMC DDR mode, the clock OSPEEDRy[1:0] is set to 01 while data OSPEEDRy[1:0] remains at 10.
3. With capacitive load CL = 20 pF.
4. For SD 1.8 V support, an external voltage converter is needed.
5. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 145. e•MMC characteristics (VDD = 1.71 V to 1.9 V)(1)(2)
Symbol
fPP
Parameter
Conditions
Clock frequency in data transfer mode
Min
Typ
Max
All modes
except DDR
-
-
84
DDR mode
-
-
40(3)
tW(CKL)
Clock low time
fPP = 52 MHz
8.5
9.5
-
tW(CKH)
Clock high time
fPP = 52 MHz
8.5
9.5
-
Unit
MHz
ns
CMD, D inputs (referenced to CK) in e•MMC mode
tISU
Input setup time HS
-
2.5
-
-
tIH
Input hold time HS
-
2
-
-
Input valid window (variable window)
-
4
-
-
tIDW(4)
ns
CMD, D outputs (referenced to CK) in e•MMC mode
tOV
Output valid time HS
-
-
10.5
13/15(5)
tOH
Output hold time HS
-
7
-
-
ns
1. Evaluated by characterization. Not tested in production.
2. With capacitive load CL = 20 pF.
3. For DDR mode, the maximum frequency is 40 MHz and HSLV must be OFF.
4. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.
5. tOV = 13 ns for SDMMC1 and tOV = 15 ns for SDMMC2.
DS13086 Rev 6
287/334
299
Electrical characteristics
STM32U585xx
Figure 69. SD high-speed mode
tC(CK)
tW(CKH)
tW(CKL)
CK
tOH
tOV
D, CMD output
tIH
tISU
D, CMD input
MSv69709V1
Figure 70. SD default mode
CK
tOV
tOH
D, CMD output
MSv69710V1
Figure 71. SDMMC DDR mode
Valid data
D input
tISU
Valid data
tIH
tISU
tIH
tW(CKH)
CK
tW(CKL)
tOV
tOV
tOH
tOH
D output
Valid data
Valid data
MSv69158V1
288/334
DS13086 Rev 6
STM32U585xx
5.3.35
Electrical characteristics
Delay block characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 33.
Table 146. Delay block characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
tinit
Initial delay
-
900
1300
2100
t∆
Unit delay
-
34
41
51
Unit
ps
1. Evaluated by characterization. Not tested in production.
5.3.36
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm): with a bitrate up to 100 Kbit/s
•
Fast-mode (Fm): with a bitrate up to 400 Kbit/s
•
Fast-mode Plus (Fm+): with a bitrate up to 1 Mbit/s
The I2C timings requirements are specified by design, not tested in production, when the
I2C peripheral is properly configured (refer to the product reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low-level output-current maximum requirement. Refer to Section 5.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics.
Table 147. I2C analog filter characteristics(1)
Symbol
tAF
Parameter
Maximum pulse width of spikes that are suppressed by the analog filter
Min
Max
Unit
50(2)
115(3)
ns
1. Specified by design. Not tested in production.
2. Spikes with widths below tAF min are filtered.
3. Spikes with width above tAF max are not filtered.
DS13086 Rev 6
289/334
299
Electrical characteristics
5.3.37
STM32U585xx
USART characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
Table 148. USART characteristics(1)
Symbol
fCK
Parameter
USART clock
frequency
Conditions
Min
Typ
Max
Master mode, 1.71 V ≤ VDD ≤ 3.6 V
-
-
20
Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V
-
-
53
Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V
-
-
28.5
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V
-
-
32
Tker(2) + 2
-
-
Slave mode
2
-
-
Master mode
1/fCK / 2 - 1
1/fCK / 2
1/fCK / 2 + 1
Master mode
14
-
-
Slave mode
1
-
-
4
-
-
1
-
-
Slave mode, 2.7 V ≤ VDD ≤ 3.6 V
-
11
17.5
Slave mode, 1.71 V ≤ VDD ≤ 3.6 V
-
11
15.5
Master mode
-
2.5
6.5
Slave mode
8.5
-
-
Master mode
2
-
-
tsu(NSS) NSS setup time Slave mode
th(NSS)
NSS hold time
tw(CKH) CK high and
tw(CKL) low time
tsu(RX)
th(RX)
th(RX)
tv(TX)
Data input
setup time
Data input hold Master mode
time
Slave mode
Data output
valid time
tv(TX)
th(TX)
th(TX)
Data output
hold time
1. Evaluated by characterization. Not tested in production.
2. Tker is the usart_ker_ck_pres clock period.
290/334
DS13086 Rev 6
Unit
MHz
ns
STM32U585xx
Electrical characteristics
Figure 72. USART timing diagram in master mode
CK output
CK output
1/fCK
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tw(CKL)
tsu(RX)
RX
INPUT
MSB IN
BIT6 IN
LSB IN
th(RX)
TX
OUTPUT
MSB OUT
tv(TX)
BIT1 OUT
LSB OUT
th(TX)
MSv65386V4
Figure 73. USART timing diagram in slave mode
NSS
input
1/fCK
CK input
tsu(NSS)
th(NSS)
tw(CKH)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
tw(CKL)
tv(TX)
First bit OUT
TX output
th(TX)
Next bits OUT
Last bit OUT
th(RX)
tsu(RX)
RX input
First bit IN
Next bits IN
Last bit IN
MSv65387V4
5.3.38
SPI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 33.
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
DS13086 Rev 6
291/334
299
Electrical characteristics
STM32U585xx
Table 149. SPI characteristics(1)
Symbol
Parameter
fSCK
SPI clock frequency
1/tc(SCK)
Conditions
Min
Typ
Max
Master mode, 2.7 V ≤ VDD ≤ 3.6 V,
voltage range 1
-
-
80
or 50(2)
Master mode, 1.71 V ≤ VDD < 2.7 V
voltage range 1
-
-
75
or 50(2)
Master mode, 1.08 V ≤ VDD ≤ 1.32 V(3)
-
-
15
Master transmitter mode,
2.7 V ≤ VDD ≤ 3.6 V, voltage range 1
-
-
80
or 50(2)
Master transmitter mode,
1.71 V ≤ VDD ≤ 2.7 V, voltage range 1
-
-
75
or 50(2)
Slave receiver mode,
1.71 V ≤ VDD ≤ 3.6 V, voltage range 1
-
-
100
Slave mode transmitter/full duplex(4),
1.71 V ≤ VDD < 2.7 V, voltage range 1
-
-
41.5
or 25.5(5)
Slave mode transmitter/full duplex(4),
2.7 V ≤ VDD ≤ 3.6 V, voltage range 1
-
-
38.5
or 24(5)
1.71 V ≤ VDD ≤ 3.6 V, voltage range 4
-
-
12.5
-
-
15
1.08 V ≤ VDD ≤ 1.32
V(3)
tsu(NSS)
NSS setup time
Slave mode
4
-
-
th(NSS)
NSS hold time
Slave mode
3
-
-
tw(SCKH)
SCK high and low time Master mode
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
MHz
tSCK(6)/2 - 1 tSCK/2 tSCK/2 + 1
Master mode
4.5
-
-
Slave mode
2.5
-
-
Master mode
3
-
-
Slave mode
1
-
-
ta(SO)
Data output access
time
Slave mode
9
-
34
tdis(SO)
Data output disable
time
Slave mode
9
-
16
292/334
Unit
DS13086 Rev 6
ns
STM32U585xx
Electrical characteristics
Table 149. SPI characteristics(1) (continued)
Symbol
Parameter
tv(SO)
Data output valid time
tv(MO)
th(SO)
Data output hold time
th(MO)
Conditions
Min
Typ
Max
Unit
Slave mode, 2.7 V ≤ VDD ≤ 3.6 V,
voltage range 1
-
10
13
or 20.5(5)
Slave mode, 1.71 V ≤ VDD < 2.7 V,
voltage range 1
-
10
12
or 19.5(5)
Slave mode, 1.71 V ≤ VDD ≤ 3.6 V,
voltage range 4
-
17
19.5
or 27(5)
Slave mode, 1.08 V ≤ VDD ≤ 1.32 V(3)
-
21
22.5
or 30(5)
Master mode
-
1.5
2 or 9.5(7)
or 12.5(8)
Slave mode, 1.71 V ≤ VDD ≤ 3.6 V
7
-
-
Slave mode, 1.08 V ≤ VDD ≤ 1.32 V(3)
18
-
-
Master mode
0
-
-
ns
1. Evaluated by characterization. Not tested in production.
2. When using PA5, PA9, PC10, PB3, PB13.
3. The SPI is mapped on port G I/Os, that is supplied by VDDIO2 specified down to 1.08V. The SPI is tested at this value.
4. The maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) that has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
5. When using PA11, PB4, PB14.
6. tSCK = tspi_ker_ck × baudrate prescaler.
7. When using PA12.
8. When using PB15.
Figure 74. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
SCK input
tsu(NSS)
th(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
MISO output
th(SO)
Next bits OUT
tf(SCK)
tdis(SO)
Last bit OUT
th(SI)
tsu(SI)
MOSI input
First bit IN
Next bits IN
Last bit IN
MSv41658V1
DS13086 Rev 6
293/334
299
Electrical characteristics
STM32U585xx
Figure 75. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
ta(SO)
tw(SCKL)
tf(SCK)
th(NSS)
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tv(SO)
th(SO)
First bit OUT
MISO output
tsu(SI)
tr(SCK)
Next bits OUT
tdis(SO)
Last bit OUT
th(SI)
First bit IN
MOSI input
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.3 VDD and 0.7 VDD levels.
Figure 76. SPI timing diagram - master mode
High
NSS input
SCK Output
CPHA= 0
CPOL=0
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
BIT6 IN
MSB IN
LSB IN
th(MI)
MOSI
OUTPUT
B I T1 OUT
MSB OUT
tv(MO)
LSB OUT
th(MO)
ai14136d
1. Measurement points are done at 0.3 VDD and 0.7 VDD levels.
294/334
DS13086 Rev 6
STM32U585xx
5.3.39
Electrical characteristics
SAI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized inTable 33, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK, SD, FS).
Table 150. SAI characteristics(1)
Symbol
fMCK
fSCK
Parameter
Conditions
Min
Max
-
-
50
Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V
-
26
Master transmitter, 1.71 V ≤ VDD ≤ 3.6 V
-
18
Master receiver, 1.71 V ≤ VDD ≤ 3.6 V
-
21.5
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V
-
30
Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V
-
20.5
Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V
-
50
Master mode, 2.7 V ≤ VDD ≤ 3.6 V
-
16
Master mode 1.71 V ≤ VDD ≤ 3.6 V
-
23
SAI main clock
output
SAI clock
frequency(2)
tv(FS)
FS valid time
th(FS)
FS hold time
Master mode
7
-
tsu(FS)
FS setup time
Slave mode
2.5
-
th(FS)
FS hold time
Slave mode
1
-
tsu(SD_A_MR) Data input setup
time
t
Master receiver
4
-
Slave receiver
3
-
th(SD_A_MR) Data input hold
time
t
Master receiver
1
-
Slave receiver
1
-
Slave transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V
-
16.5
Slave transmitter (after enable edge), 1.71 V ≤ VDD ≤ 3.6 V
-
24
Slave transmitter (after enable edge)
8
-
su(SD_B_SR)
h(SD_B_SR)
tv(SD_B_ST)
Data output valid
time
th(SD_B_ST)
Data output hold
time
DS13086 Rev 6
Unit
MHz
ns
295/334
299
Electrical characteristics
STM32U585xx
Table 150. SAI characteristics(1) (continued)
Symbol
Parameter
Data output valid
tv(SD_A_MT)
time
th(SD_A_MT)
Data output hold
time
Conditions
Min
Max
Master transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V
-
19
Master transmitter (after enable edge),
1.71 V ≤ VDD ≤ 3.6 V
-
27.5
Master transmitter (after enable edge)
8
-
1. Evaluated by characterization. Not tested in production.
2. APB clock frequency that must be at least twice SAI clock frequency.
Figure 77. SAI master timing diagram
1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output)
tv(FS)
th(SD_MT)
tv(SD_MT)
SAI_SD_X
(transmit)
Slot n
tsu(SD_MR)
SAI_SD_X
(receive)
Slot n+2
th(SD_MR)
Slot n
MS32771V1
Figure 78. SAI slave timing digram
1/fSCK
SAI_SCK_X
tw(CKH_X)
SAI_FS_X
(input)
tw(CKL_X)
tsu(FS)
th(FS)
SAI_SD_X
(transmit)
Slot n
tsu(SD_SR)
SAI_SD_X
(receive)
th(SD_ST)
tv(SD_ST)
Slot n+2
th(SD_SR)
Slot n
MS32772V1
296/334
DS13086 Rev 6
Unit
ns
STM32U585xx
5.3.40
Electrical characteristics
OTG_FS characteristics
Table 151. OTG_FS characteristics
Symbol
Conditions
Min
Typ
Max
Unit
USB transceiver operating supply voltage
-
3.0(1)
-
3.6
V
RPUI
Embedded USB_DP pullup value during idle
-
900
-
1575
RPUR
Embedded USB_DP pullup value during reception
-
1425
-
3090
ZDRV
Output driver impedance(2)
High and low driver
28
36
44
VDDUSB
Parameter
Ω
1. USB functionality is ensured down to 2.7 V, but some USB electrical characteristics are degraded in 2.7 to 3.0 V range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-). The matching impedance is
already included in the embedded driver.
5.3.41
UCPD characteristics
UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0
specifications.
Table 152. UCPD characteristics
Symbol
Parameter
VDD
UCPD operating supply voltage
5.3.42
Conditions
Sink mode only
Sink and source mode
Min
Typ
Max
3.0
3.3
3.6
3.135
3.3
3.465
Unit
V
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in the tables below are derived from tests
performed under the ambient temperature, fHCLKx frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.
Table 153. JTAG characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
2.7 V ≤ VDD ≤ 3.6 V
-
-
38
1.71 V ≤ VDD ≤ 3.6 V
-
-
26
FTCK
TCK clock frequency
tisu(TMS)
TMS input setup time
-
1
-
-
tih(TMS)
TMS input hold time
-
3
-
-
tisu(TDI)
TDI input setup time
-
2
-
-
tih(TDI)
TDI input hold time
-
1
-
-
DS13086 Rev 6
Unit
MHz
ns
297/334
299
Electrical characteristics
STM32U585xx
Table 153. JTAG characteristics(1) (continued)
Symbol
Parameter
tov(TDO)
TDO output valid time
toh(TDO)
TDO output hold time
Conditions
Min
Typ
Max
2.7 V ≤ VDD ≤ 3.6 V
-
9
13
1.71 V ≤ VDD ≤ 3.6 V
-
9
19
7
-
-
Min
Typ
Max
2.7 V ≤ VDD ≤ 3.6 V
-
-
66.5
1.71 V ≤ VDD ≤ 3.6 V
-
-
43
-
1
-
-
-
2.5
-
-
2.7 V ≤ VDD ≤ 3.6 V
-
10.5
15
1.71 V ≤ VDD ≤ 3.6 V
-
10.5
23
7.5
-
-
-
Unit
ns
1. Evaluated by characterization. Not tested in production.
Table 154. SWD characteristics(1)
Symbol
Parameter
FSWCLK
Conditions
SWCLK clock frequency
tisu(SWDIO) SWDIO input setup time
tih(SWDIO)
SWDIO input hold time
tov(SWDIO)
SWDIO output valid time
toh(SWDIO)
SWDIO output hold time
-
1. Evaluated by characterization. Not tested in production.
Figure 79. JTAG timing diagram
tc(TCK)
TCK
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO)
toh(TDO)
TDO
MSv40458V1
298/334
DS13086 Rev 6
Unit
MHz
ns
STM32U585xx
Electrical characteristics
Figure 80. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL) tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
DS13086 Rev 6
299/334
299
Package information
6
STM32U585xx
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1
UFQFPN48 package information
This UFQFPN is a 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package
Figure 81. UFQFPN48 - Outline
Pin 1 identifier
laser marking area
D
A
E
E
T
ddd
A1
Seating
plane
b
e
Detail Y
D
Exposed pad
area
Y
D2
1
L
48
C 0.500x45°
pin1 corner
E2
R 0.125 typ.
Detail Z
1
Z
48
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
300/334
DS13086 Rev 6
STM32U585xx
Package information
Table 155. UFQFPN48 - Mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
D
6.900
7.000
7.100
0.2717
0.2756
0.2795
E
6.900
7.000
7.100
0.2717
0.2756
0.2795
D2
5.500
5.600
5.700
0.2165
0.2205
0.2244
E2
5.500
5.600
5.700
0.2165
0.2205
0.2244
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
T
-
0.152
-
-
0.0060
-
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
e
-
0.500
-
-
0.0197
-
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 82. UFQFPN48 - Recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.50
0.55
5.80
0.75
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
DS13086 Rev 6
301/334
328
Package information
STM32U585xx
Device marking for UFQFPN48
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 83. UFQFPN48 marking example (package top view)
STM32U585
Product identification(1)
CIU6
Y WW
Pin 1 identifier
Date code
R
Revision code
MSv64351V2
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
302/334
DS13086 Rev 6
STM32U585xx
6.2
Package information
LQFP48 package information
This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package
Note:
See list of notes in the notes section.
Figure 84. LQFP48 - Outline(15)
BOTTOM VIEW
4x N/4 TIPS
aaa C A-B D
(2)
R1
R2
N
TI
O
(6)
B
SE
C
D 1/4
BB
H
GAUGE PLANE
0.25
E 1/4
S
B
bbb H A-B D 4x
0.05
A
(13)
(N – 4)x e
C
A2
A1
(12)
ddd
b
(10)
(3) A
(1) (11)
SECTION A-A
(4)
D1
D (3)
N
1
2
3
(L1)
ccc C
C A-B D
D
(2) (5)
L
b
(9) (11)
WITH PLATING
E 1/4
B (3)
(6)
c
D 1/4
E1
E
(2)
(5)
A
c1
(11)
(11)
(4)
A
b1
(Section A-A)
(11)
BASE METAL
SECTION B-B
TOP VIEW
5B_LQFP48_ME_V1
DS13086 Rev 6
303/334
328
Package information
STM32U585xx
Table 156. LQFP48 - Mechanical data
inches(14)
millimeters
Symbol
A
A1
(12)
A2
Min
Typ
Max
Min
Typ
Max
-
-
1.60
-
-
0.0630
0.05
-
0.15
0.0020
-
0.0059
1.35
1.40
1.45
0.0531
0.0551
0.0571
(9)(11)
0.17
0.22
0.27
0.0067
0.0087
0.0106
(11)
0.17
0.20
0.23
0.0067
0.0079
0.0090
0.09
-
0.20
0.0035
-
0.0079
0.09
-
0.16
0.0035
-
0.0063
b
b1
(11)
c
c1(11)
(4)
9.00 BSC
0.3543 BSC
(2)(5)
D
7.00 BSC
0.2756 BSC
E(4)
9.00 BSC
0.3543 BSC
E1(2)(5)
7.00 BSC
0.2756 BSC
e
0.50 BSC
0.1970 BSC
D1
L
0.45
L1
0.60
0.75
1.00 REF
0.0236
0.0295
0.0394 REF
N(13)
48
θ
0°
3.5°
7°
0°
3.5°
7°
θ1
0°
-
-
0°
-
-
θ2
10°
12°
14°
10°
12°
14°
θ3
10°
12°
14°
10°
12°
14°
R1
0.08
-
-
0.0031
-
-
R2
0.08
-
0.20
0.0031
-
0.0079
S
0.20
-
-
0.0079
-
-
aaa(1)(7)
0.20
0.0079
bbb(1)(7)
0.20
0.0079
(1)(7)
0.08
0.0031
(1)(7)
0.08
0.0031
ccc
ddd
304/334
0.0177
DS13086 Rev 6
STM32U585xx
Package information
Notes:
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All Dimensions are in millimeters.
8.
No intrusion allowed inwards the leads.
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
Figure 85. LQFP48 - Recommended footprint
0.50
1.20
36
25
37
24
0.30
0.20
9.70 7.30
48
13
12
1
5.80
9.70
5B_LQFP48_FP_V1
1. Dimensions are expressed in millimeters.
DS13086 Rev 6
305/334
328
Package information
STM32U585xx
Device marking for LQFP48
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 86. LQFP48 marking example (package top view)
STM32U585
Product identification(1)
CIT6
Y WW
Pin 1 identifier
Date code
R
Revision code
MSv67814V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
306/334
DS13086 Rev 6
STM32U585xx
6.3
Package information
LQFP64 package information
This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note:
See list of notes in the notes section.
Figure 87. LQFP64 - Outline(15)
BOTTOM VIEW
(2)
R1
R2
GAUGE PLANE
0.25
B
D 1/4
SE
C
TI
O
N
BB
H
(6)
S
B
E 1/4
4x N/4 TIPS
aaa C A-B D
L
(L1)
(1) (11)
bbb H A-B D 4x
SECTION A-A
(13) (N – 4)x e
C
A
0.05
A2 A1
(12)
b
ddd
C A-B D
ccc C
D
(9) (11)
D (3)
(10)
b
(4)
N
E 1/4
1
2
3
(3) A
(4)
D1
(5) (2)
WITH PLATING
(11)
(11)
c
D 1/4
B (3)
(6)
(5)
(2)
E1
A
(Section A-A)
c1
A
E
b1
(11)
BASE METAL
SECTION B-B
5W_LQFP64_ME_V1
TOP VIEW
DS13086 Rev 6
307/334
328
Package information
STM32U585xx
Table 157. LQFP64 - Mechanical data
Symbol
inches(14)
millimeters
Min
Typ
Max
Min
Typ
Max
A
-
-
1.60
-
-
0.0630
A1(12)
0.05
-
0.15
0.0020
-
0.0059
A2
1.35
1.40
1.45
0.0531
0.0551
0.0570
(9)(11)
0.17
0.22
0.27
0.0067
0.0087
0.0106
(11)
b
0.17
0.20
0.23
0.0067
0.0079
0.0091
c(11)
0.09
-
0.20
0.0035
-
0.0079
c1(11)
0.09
-
0.16
0.0035
-
0.0063
b1
(4)
12.00 BSC
0.4724 BSC
(2)(5)
10.00 BSC
0.3937 BSC
12.00 BSC
0.4724 BSC
10.00 BSC
0.3937 BSC
0.50 BSC
0.1970 BSC
D
D1
E(4)
(2)(5)
E1
e
L
0.45
L1
0.60
0.75
0.0236
0.0295
0.0394 REF
N(13)
θ
0.0177
1.00 REF
64
0°
3.5°
7°
0°
3.5°
7°
θ1
0°
-
-
0°
-
-
θ2
10°
12°
14°
10°
12°
14°
θ3
10°
12°
14°
10°
12°
14°
R1
0.08
-
-
0.0031
-
-
R2
0.08
-
0.20
0.0031
-
0.0079
S
0.20
-
-
0.0079
-
-
(1)
0.20
0.0079
(1)
0.20
0.0079
ccc
(1)
0.08
0.0031
ddd(1)
0.08
0.0031
aaa
bbb
Notes:
308/334
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All Dimensions are in millimeters.
8.
No intrusion allowed inwards the leads.
DS13086 Rev 6
STM32U585xx
Package information
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
Figure 88. LQFP64 - Recommended footprint
48
33
0.30
0.5
49
32
12.70
10.30
10.30
17
64
1.20
16
1
7.80
12.70
5W_LQFP64_FP_V2
1. Dimensions are expressed in millimeters.
DS13086 Rev 6
309/334
328
Package information
STM32U585xx
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 89. LQFP64 marking example (package top view)
STM32U585
Product identification(1)
RIT6
Y WW
Pin 1 identifier
Date code
R
Revision code
MSv64352V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
310/334
DS13086 Rev 6
STM32U585xx
6.4
Package information
WLSCP90 package information
WLCSP is a 90 balls, 4.20 x 3.95 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 90. WLCSP90 - Outline
bbb Z
A1 BALL LOCATION
A1
DETAIL A
e1
F
aaa
(4x)
G
A1
B4
B2
e2 E
e
e
A2
A
D
BOTTOM VIEW
TOP VIEW
A3
A2
SIDE VIEW
BUMP
A1
b
eee Z
FRONT VIEW
Z
b (90x)
ccc Z X Y
ddd Z
DETAIL A
ROTATED 90
SEATING PLANE
B01C_WLCSP90_ME_V2
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
DS13086 Rev 6
311/334
328
Package information
STM32U585xx
Table 158. WLCSP90 - Mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A(2)
-
-
0.59
-
-
0.023
A1
-
0.18
-
-
0.007
-
A2
-
0.38
-
-
0.015
-
-
0.025
-
-
0.001
-
b
0.22
0.25
0.28
0.009
0.010
0.011
D
4.19
4.20
4.21
0.165
0.165
0.166
E
3.93
3.95
3.97
0.155
0.156
0.156
e
-
0.40
-
-
0.016
-
e1
-
3.40
-
-
0.134
-
e2
-
3.12
-
-
0.123
-
F(4)
-
0.400
-
-
0.016
-
G(4)
-
0.416
-
-
0.016
-
aaa
-
-
0.10
-
-
0.004
bbb
-
-
0.10
-
-
0.004
ccc
-
-
0.10
-
-
0.004
ddd
-
-
0.05
-
-
0.002
eee
-
-
0.05
-
-
0.002
(3)
A3
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
Figure 91. WLCSP90 - Recommended footprint
Dpad
Dsm
B03P_WLCSP36_DIE464_FP_V1
312/334
DS13086 Rev 6
STM32U585xx
Package information
Table 159. WLCSP90 - Recommended PCB design rules
Dimension
Recommended values
Pitch
0.4 mm
Dpad
0,225 mm
Dsm
0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening
0.250 mm
Stencil thickness
0.100 mm
Device marking for WLCSP90
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 92. WLCSP90 marking example (package top view)
Pin 1 identifier
Product identification(1)
Date code
U585OI6Q
Y WW
R
Revision code
MSv67815V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS13086 Rev 6
313/334
328
Package information
6.5
STM32U585xx
LQFP100 package information
This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note:
See list of notes in the notes section.
Figure 93. LQFP100 - Outline(15)
θ1
θ2
(2)
R1
R2
(6)
B
D1/4
SE
C
TI
O
N
BB
H
GAUGE PLANE
S
θ3
4x N/4 TIPS
L
4x
aaa C A-B D
(L1)
bbb H A-B D
(1) (11)
SECTION A-A
BOTTOM VIEW
(N-4) x e
(13)
C
A
0.05
θ
B
E1/4
(9) (11)
b
A2 A1
(12)
aaa
b
ccc C
C A-BD
WITH PLATING
SIDE VIEW
D
D1
(2) (5)
(4)
(11)
D (3)
(10)
c
c1
(11)
(4)
N
b1
BASE METAL
(11)
1
2
3
E1/4
D1/4
SECTION B-B
(2)
(6)
B
A
(5)
E1
E
SECTION A-A
A
A
TOP VIEW
314/334
1L_LQFP100_ME_V3
DS13086 Rev 6
STM32U585xx
Package information
Table 160. LQFP100 - Mechanical data
inches(14)
millimeters
Symbol
A
(12)
A1
A2
Min
Typ
Max
Min
Typ
Max
-
1.50
1.60
-
0.0590
0.0630
0.05
-
0.15
0.0019
-
0.0059
1.35
1.40
1.45
0.0531
0.0551
0.0570
(9)(11)
0.17
0.22
0.27
0.0067
0.0087
0.0106
(11)
0.17
0.20
0.23
0.0067
0.0079
0.0090
0.09
-
0.20
0.0035
-
0.0079
0.09
-
0.16
0.0035
-
0.0063
b
b1
(11)
c
c1(11)
(4)
16.00
0.6299
(2)(5)
D
14.00
0.5512
E(4)
16.00
0.6299
E1(2)(5)
14.00
0.5512
D1
L1
e
-
0.50
-
-
0.0197
-
L
0.45
0.60
0.75
0.177
0.0236
0.0295
-
0.0394
-
(1)(11)
1.00
N
100
θ
0°
3.5°
7°
0°
3.5°
7°
θ1
0°
-
-
0°
-
-
θ2
10°
12°
14°
10°
12°
14°
θ3
10°
12°
14°
10°
12°
14°
R1
0.08
-
-
0.0031
-
-
R2
0.08
-
0.20
0.0031
-
0.0079
S
0.20
-
-
0.0079
-
-
aaa
0.20
0.0079
bbb
0.20
0.0079
ccc
0.08
0.0031
ddd
0.08
0.0031
DS13086 Rev 6
315/334
328
Package information
STM32U585xx
Notes:
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All Dimensions are in millimeters.
8.
No intrusion allowed inwards the leads.
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
Figure 94. LQFP100 - Recommended footprint
75
76
51
50
0.5
0.3
16.7
14.3
100
26
1.2
1
25
12.3
16.7
1L_LQFP100_FP_V1
1. Dimensions are expressed in millimeters.
316/334
DS13086 Rev 6
STM32U585xx
Package information
Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location. The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 95. LQFP100 marking example (package top view)
STM32U
Product identification(1)
585VIT6
R
Y WW
Revision code
Date code
Pin 1 identifier
MSv64353V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS13086 Rev 6
317/334
328
Package information
6.6
STM32U585xx
UFBGA132 package information
This UFBGA is a 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package.
Figure 96. UFBGA132 - Outline
A1 ball identifier
A
B
E1
e
E
Z
A
Z
D1
D
e
M
12
BOTTOM VIEW
1
Øb (132 balls)
Øeee M C A B
Ø fff M C
TOP VIEW
A4
ddd C
A2
A3
A1 A
b
SEATING
PLANE
UFBGA132_A0G8_ME_V2
1. Drawing is not to scale.
Table 161. UFBGA132 - Mechanical data
inches(1)
millimeters
Symbol
318/334
Min
Typ
Max
Min
Typ
Max
A
-
-
0.600
-
-
0.0236
A1
-
-
0.110
-
-
0.0043
A2
-
0.450
-
-
0.0177
-
A3
-
0.130
-
-
0.0051
-
A4
-
0.320
-
-
0.0126
-
b
0.240
0.290
0.340
0.0094
0.0114
0.0134
D
6.850
7.000
7.150
0.2697
0.2756
0.2815
D1
-
5.500
-
-
0.2165
-
E
6.850
7.000
7.150
0.2697
0.2756
0.2815
E1
-
5.500
-
-
0.2165
-
DS13086 Rev 6
STM32U585xx
Package information
Table 161. UFBGA132 - Mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
e
-
0.500
-
-
0.0197
-
Z
-
0.750
-
-
0.0295
-
ddd
-
0.080
-
-
0.0031
-
eee
-
0.150
-
-
0.0059
-
fff
-
0.050
-
-
0.0020
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 97. UFBGA132 - Recommended footprint
Dpad
Dsm
UFBGA132_A0G8_FP_V1
Table 162. UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA)
Dimension
Recommended values
Pitch
0.5 mm
Dpad
0.280 mm
Dsm
0.370 mm typ. (depends on the soldermask registration tolerance)
Stencil opening
0.280 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
Pad trace width
0.100 mm
Ball diameter
0.280 mm
DS13086 Rev 6
319/334
328
Package information
STM32U585xx
Device marking for UFBGA132
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 98. UFBGA132 marking example (package top view)
STM32U
Product identification(1)
585QII6
Date code
Y WW
R
Revision code
Pin 1 identifier
MSv64354V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
320/334
DS13086 Rev 6
STM32U585xx
6.7
Package information
LQFP144 package information
This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
Note:
See list of notes in the notes section.
Figure 99. LQFP144 - Outline(15)
BOTTOM VIEW
(2)
R1
R2
B
GAUGE PLANE
0.25
(6)
SE
C
TI
O
N
BB
H
D 1/4
S
B
L
E 1/4
(L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D
SECTION A-A
bbb H A-B D 4x
(N-4)x e
C
A
0.05
A2 A1
(12)
b
ddd
C A-B D
D
D1
(3)
(10)
ccc C
(4)
(2) (5)
D
1
2
3
(9) (11)
(4)
N
b
WITH PLATING
E 1/4
(11)
D 1/4
(6)
c1
(11)
(2)
(5)
B (3)
(3) A
c
E1
E
b1
(11)
BASE METAL
SECTION B-B
A
(Section A-A)
A
TOP VIEW
1A_LQFP144_ME_V2
DS13086 Rev 6
321/334
328
Package information
STM32U585xx
Table 163. LQFP144 - Mechanical data
inches(14)
millimeters
Symbol
A
(12)
A1
A2
b
Min
Typ
Max
Min
Typ
Max
-
-
1.60
-
-
0.0630
0.05
-
0.15
0.0020
-
0.0059
1.35
1.40
1.45
0.0531
0.0551
0.0571
(9)(11)
0.17
0.22
0.27
0.0067
0.0087
0.0106
(11)
0.17
0.20
0.23
0.0067
0.0079
0.0090
0.09
-
0.20
0.0035
-
0.0079
0.09
-
0.16
0.0035
-
0.0063
b1
c
(11)
c1(11)
(4)
22.00 BSC
0.8661 BSC
(2)(5)
D
20.00 BSC
0.7874 BSC
E(4)
22.00 BSC
0.8661 BSC
E1(2)(5)
20.00 BSC
0.7874 BSC
e
0.50 BSC
0.0197 BSC
D1
L
0.45
L1
0.60
0.75
0.0177
1.00 REF
0.0236
0.0295
0.0394 REF
N(13)
144
θ
0°
3.5°
7°
0°
3.5°
7°
θ1
0°
-
-
0°
-
-
θ2
10°
12°
14°
10°
12°
14°
θ3
10°
12°
14°
10°
12°
14°
R1
0.08
-
-
0.0031
-
-
R2
0.08
-
0.20
0.0031
-
0.0079
S
0.20
-
-
0.0079
-
-
aaa
0.20
0.0079
bbb
0.20
0.0079
ccc
0.08
0.0031
ddd
0.08
0.0031
Notes:
322/334
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
DS13086 Rev 6
STM32U585xx
Package information
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All Dimensions are in millimeters.
8.
No intrusion allowed inwards the leads.
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
Figure 100. LQFP144 - Recommended footprint
108
109
73
1.35
72
0.35
0.50
19.90
17.85
22.60
144
37
1
36
19.90
22.60
1A_LQFP144_FP
1. Dimensions are expressed in millimeters.
DS13086 Rev 6
323/334
328
Package information
STM32U585xx
Device marking for LQFP144
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 101. LQFP144 marking example (package top view)
Product identification(1)
STM32U585ZIT6
R
Y WW
Revision code
Date code
Pin 1 identifier
MSv64355V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
324/334
DS13086 Rev 6
STM32U585xx
6.8
Package information
UFBGA169 package information
This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 102. UFBGA169 - Outline
Z Seating plane
A2
A4
ddd Z
A
A3
A1
b
SIDE VIEW
A1 ball
identifier
A1 ball
index area
X
E
E1
e
F
A
F
D
D1
e
Y
N
13
1
BOTTOM VIEW
TOP VIEW
Øb (169 balls)
Ø eee M Z X Y
Ø fff M Z
A0YV_ME_V2
1. Drawing is not to scale.
Table 164. UFBGA169 - Mechanical data
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A3
-
0.130
-
-
0.0051
-
A4
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.230
0.280
0.330
0.0091
0.0110
0.0130
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
D1
5.950
6.000
6.050
0.2343
0.2362
0.2382
E
6.950
7.000
7.050
0.2736
0.2756
0.2776
E1
5.950
6.000
6.050
0.2343
0.2362
0.2382
e
-
0.500
-
-
0.0197
-
F
0.450
0.500
0.550
0.0177
0.0197
0.0217
DS13086 Rev 6
325/334
328
Package information
STM32U585xx
Table 164. UFBGA169 - Mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
ddd
-
-
0.100
-
-
0.0039
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 103. UFBGA169 - Recommended footprint
Dpad
Dsm
MS18965V2
Table 165. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA)
Dimension
Note:
Recommended values
Pitch
0.5 mm
Dpad
0.27 mm
Dsm
0.35 mm typ. (depends on the soldermask
registration tolerance)
Solder paste
0.27 mm aperture diameter.
Non-solder mask defined (NSMD) pads are recommended.
4 to 6 mils solder paste screen printing process.
326/334
DS13086 Rev 6
STM32U585xx
Package information
Device marking for UFBGA169
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 104. UFBGA169 marking example (package top view)
Pin 1 identifier
STM32U
Product identification(1)
585AII6
Date code
Y WW
R
Revision code
MSv64356V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
6.9
Package thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
where:
•
TA max is the maximum ambient temperature in °C.
•
ΘJA is the package junction-to-ambient thermal resistance in °C/W.
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max).
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins:
PI/O max = ∑(VOL × IOL) + ∑((VDDIOx - VOH) × IOH)
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the
application.
DS13086 Rev 6
327/334
328
Package information
STM32U585xx
Table 166. Package thermal characteristics
Symbol
ΘJA
ΘJB
ΘJC
328/334
Parameter
Package
Thermal resistance junction-ambient
Thermal resistance junction-board
Thermal resistance junction-top case
Value
LQFP48 7 x 7 mm
45.8
UFQFPN48 7 x 7 mm
26.9
LQFP64 10 x 10 mm
39.6
WLCSP90 4.2 x 3.95 mm
42.3
LQFP100 - 14 × 14 m
34.4
UFBGA132 7 x 7 mm
35.2
LQFP144 20 x 20 mm
35.9
UFBGA169 7 x 7 mm
33.7
LQFP48 7 x 7 mm
23.4
UFQFPN48 7 x 7 mm
11.2
LQFP64 10 x 10 mm
22
WLCSP90 4.2 x 3.95 mm
27.5
LQFP100 - 14 × 14 m
20.3
UFBGA132 7 x 7 mm
20.7
LQFP144 20 x 20 mm
24.8
UFBGA169 7 x 7 mm
19.3
LQFP48 7 x 7 mm
10.7
UFQFPN48 7 x 7 mm
8
LQFP64 10 x 10 mm
9.0
WLCSP90 4.2 x 3.95 mm
1.6
LQFP100 - 14 × 14 m
7.4
UFBGA132 7 x 7 mm
8.3
LQFP144 20 x 20 mm
7.6
UFBGA169 7 x 7 mm
8.3
DS13086 Rev 6
Unit
°C/W
STM32U585xx
7
Ordering information
Ordering information
Example:
STM32
U
585
V
I
T
6 Q TR
Device family
STM32 = Arm based 32-bit microcontroller
Product type
U = ultra-low-power
Device subfamily
585 = STM32U585xx with OTG and AES hardware encryption
Pin count
C = 48 pins
R = 64 pins
O = 90 pins
V = 100 pins
Q = 132 balls
Z = 144 pins
A = 169 balls
Flash memory size
I = 2 Mbytes
Package
T = LQFP
I = UFBGA (7 x 7 mm)
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C (105 °C junction)
3 = Industrial temperature range, –40 to 125 °C (130 °C junction)
Dedicated pinout
Q = Dedicated pinout supporting SMPS step-down converter
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.
DS13086 Rev 6
329/334
329
Important security notice
8
STM32U585xx
Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
330/334
•
ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
•
Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
•
Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
•
While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
•
All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS13086 Rev 6
STM32U585xx
9
Revision history
Revision history
Table 167. Document revision history
Date
Revision
02-Sep-2021
1
Initial release.
2
Updated:
– Figure 24 and Figure 25: STM32U585xQ power supply scheme (with SMPS)
– Figure 28: AC timing diagram for high-speed external clock source
– Figure 29: AC timing diagram for low-speed external square clock source
– VDDCoeff values in Table 36: Embedded internal voltage reference
– IDD(RUN) Range 2 values in Table 37 and Table 38
– New consumption Table 40, Table 42, Table 45, Table 46, Table 50, Table 52,
Table 54, Table 56, Table 58, Table 60, Table 66, Table 68
– All values in consumption Table 53, Table 55, Table 57, Table 59, Table 65
– All values in Table 71, Table 72, Table 73
– USER TROM COVERAGE removed in Table 80: MSI oscillator characteristics
– Table 84: PLL characteristics
3
Updated:
– Security and cryptography
– ‘legacy’ replaced by ‘without SMPS’ in Table 2: STM32U585xx features and
peripheral counts
– PSSI in Table 10: Functionalities depending on the working mode
– Table 38 and new Table 39: Current consumption in Run mode on SMPS, code with
data processing running from Flash memory, ICACHE ON (1-way), prefetch ON,
VDD = 3.0 V
– Table 45 and new Table 46: Current consumption in Sleep mode on SMPS, Flash
memory in power down, VDD = 3.0 V
– Table 47: SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and
SMPS
– twu(Sleep) max in Table 74: Low-power mode wakeup timings on SMPS
– Footnote 8 on Table 82: MSI oscillator characteristics
– tSU(RX) in Table 147: USART characteristics
– Section 6.5: LQFP100 package information
4
Updated:
– FMC_A16 and FMC_A17 in Table 26: STM32U585xx pin definitions and Table 28:
Alternate function AF8 to AF15
– New tVBAT_BOR_sampling in Table 34: Embedded reset and power control block
characteristics
– CS_PARA in Table 79: LSE oscillator characteristics (fLSE = 32.768 kHz)
– Figure 32: Typical application with a 32.768 kHz crystal
5
Updated:
– GPIOs and capacitive sensing in Table 2: STM32U585xx features and peripheral
counts
– Figure 1: STM32U585xx block diagram
– VBAT in Section 3.9.1: Power supply schemes
24-Sep-2021
19-Nov-2021
13-Dec-2021
13-Mar-2022
Changes
DS13086 Rev 6
331/334
333
Revision history
STM32U585xx
Table 167. Document revision history (continued)
Date
13-Mar-2022
332/334
Revision
Changes
– Backup domain in Figure 2 and Figure 3: STM32U585xx power supply overview
(without SMPS)
– IWDG in Table 10: Functionalities depending on the working mode
– New sentence beg. of Section 3.25: Octo-SPI interface (OCTOSPI)
– Section 3.25.1: OCTOSPI TrustZone security
– Figure 9: UFQFPN48_SMPS pinout
– PB2 I/O structure in Table 27: STM32U585xx pin definitions
– Notes of Table 51: Current consumption in Stop 1 mode on LDO
– Table 52: Current consumption during wakeup from Stop 1 mode on LDO
– Notes of Table 53: Current consumption in Stop 1 mode on SMPS
– Table 54: Current consumption during wakeup from Stop 1 mode on SMPS
– Table SRAM static power consumption in Stop 2 when supplied by LDO moved
– Notes of Table 55: Current consumption in Stop 2 mode on LDO
– Table 57: Current consumption during wakeup from Stop 2 mode on LDO
– Table SRAM static power consumption in Stop 2 when supplied by SMPS moved
– Table 60: Current consumption during wakeup from Stop 2 mode on SMPS
– Notes of Table 58: Current consumption in Stop 2 mode on SMPS
– Table SRAM static power consumption in Stop 3 when supplied by LDO moved
– Table 63: Current consumption during wakeup from Stop 3 mode on LDO
– Table SRAM static power consumption in Stop 3 when supplied by SMPS moved
– Notes of Table 64: Current consumption in Stop 3 mode on SMPS
– Table 66: Current consumption during wakeup from Stop 3 mode on SMPS
5 (cont’d)
– Table 68: Current consumption during wakeup from Standby mode
– Notes of Table 69: Current consumption in Shutdown mode
– Table 70: Current consumption during wakeup from Shutdown mode
– twu(Sleep) and notes of Table 73: Low-power mode wakeup timings on LDO
– Notes Table 75: Regulator mode transition times
– Output driving current
– Notes of Table 95: Output voltage characteristics
– New Table 96: Output voltage characteristics for FT_t I/Os in VBAT mode
– Notes of Table 97: Output AC characteristics, HSLV OFF (all I/Os except FT_c)
– Notes of Table 98: Output AC characteristics, HSLV ON (all I/Os except FT_c)
– Table 100: Output AC characteristics for FT_t I/Os in VBAT mode
– fAHB_CAL removed from Table 104: 14-bit ADC1 characteristics
– Table 114: DAC characteristics
– RLoad and en in Table 118: OPAMP characteristics
– New Figure 44: OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ and
Figure 45: OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ
– tLv(NOE_NE) in Table 131: Asynchronous multiplexed PSRAM/NOR read timings
– Section 6.2: LQFP48 package information
– Section 6.3: LQFP64 package information
– Section 6.5: LQFP100 package information
– Section 6.7: LQFP144 package information
– Disclaimer
DS13086 Rev 6
STM32U585xx
Revision history
Table 167. Document revision history (continued)
Date
2-Jun-2022
Revision
Changes
6
Added:
– Section 8: Important security notice
Updated:
– Up to 22 capacitive sensing channels
– Section 2: Description
– Table 2.: STM32U585xx features and peripheral counts
– Section 3.36: Touch sensing controller (TSC)
– TSC_G3_IO1/TSC_G1_IO4 are removed from PC2/PC3 in Table 27.: STM32U585xx
pin definitions and Table 29.: Alternate function AF8 to AF15
– Table 72.: Typical dynamic current consumption of peripherals
– Table 90: EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz
– Minimum value added for PSSR in Table 118.: OPAMP characteristics
– Disclaimer
DS13086 Rev 6
333/334
333
STM32U585xx
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
334/334
DS13086 Rev 6
工商网监
湘ICP备2023018690号
