STM32W108HB STM32W108CB
STM32W108CC STM32W108CZ
High-performance, IEEE 802.15.4 wireless system-on-chip with up
to 256 Kbyte of embedded Flash memory
Datasheet - not recommended for new design
Features
• Complete system-on-chip
– 32-bit ARM® Cortex®-M3 processor
– 2.4 GHz IEEE 802.15.4 transceiver and
lower MAC
– 128/192/256-Kbyte Flash, 8/12/16-Kbyte
RAM memory
– AES128 encryption accelerator
– Flexible ADC, SPI/UART/I2C serial
communications, and general-purpose
timers
– 24 highly configurable GPIOs with Schmitt
trigger inputs
• Industry-leading ARM® Cortex®-M3 processor
– Leading 32-bit processing performance
– Highly efficient Thumb®-2 instruction set
– Operation at 6, 12 or 24 MHz
– Flexible nested vectored interrupt controller
• Low power consumption, advanced
management
– Receive current (w/ CPU): 27 mA
– Transmit current (w/ CPU, +3 dBm TX):
31 mA
– Low deep sleep current, with retained RAM
and GPIO: 400 nA/800 nA with/without
sleep timer
– Low-frequency internal RC oscillator for
low-power sleep timing
– High-frequency internal RC oscillator for
fast (100 µs) processor start-up from sleep
• Exceptional RF performance
– Normal mode link budget up to 102 dB;
configurable up to 107 dB
– -99 dBm normal RX sensitivity;
configurable to -100 dBm (1% PER,
20 byte packet)
– +3 dB normal mode output power;
configurable up to +8 dBm
March 2015
VFQFPN48 (7 x 7 mm)
UFQFPN48 (7 x 7 mm)
VFQFPN46 (6 x 6 mm)
– Robust WiFi and Bluetooth coexistence
• Innovative network and processor debug
– Non-intrusive hardware packet trace
– Serial wire/JTAG interface
– Standard ARM debug capabilities: Flash
patch and breakpoint; data watchpoint and
trace; instrumentation trace macrocell
• Application flexibility
– Single voltage operation: 2.1-3.6 V with
internal 1.8 V and 1.25 V regulators
– Optional 32.768 kHz crystal for higher timer
accuracy
– Low external component count with single
24 MHz crystal
– Support for external power amplifier
– Small 7x7 mm 48-pin VFQFPN and
UFQFPN packages or 6x6 mm 40-pin
VFQFPN package
Applications
• Smart energy
• Building automation and control
• Home automation and control
• Security and monitoring
• ZigBee® Pro wireless sensor networking
• RF4CE products and remote controls
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Contents
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.2
ARM® Cortex®-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1
Memory organization and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3
Random-access memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4
5
5.2
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Direct memory access (DMA) to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.2
RAM memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.3
Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.4
Memory controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Radio frequency module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1
6
4.3.1
Receive (Rx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.1
Rx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.2
RSSI and CCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Transmit (Tx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.1
Tx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.2
TX_ACTIVE and nTX_ACTIVE signals . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4
Integrated MAC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5
Packet trace interface (PTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.6
Random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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6.2
6.3
6.4
6.5
6.6
Contents
Power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1
Internally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2
Externally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2.1
Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2.2
Reset recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2.3
Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2.4
Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.1
High-frequency internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . 55
6.3.2
High-frequency crystal oscillator (HSE OSC) . . . . . . . . . . . . . . . . . . . . 55
6.3.3
Low-frequency internal RC oscillator (LSI10K) . . . . . . . . . . . . . . . . . . . 55
6.3.4
Low-frequency crystal oscillator (LSE OSC) . . . . . . . . . . . . . . . . . . . . . 55
6.3.5
Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.6
Clock switching registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.1
MAC timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.2
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.3
Sleep timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.4
Event timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4.5
Slow timer (MAC timer, Watchdog, and Sleeptimer) control and status
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5.1
Wake sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5.2
Basic sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.5.3
Further options for deep sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.5.4
Use of debugger with sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.5.5
Power management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Security accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7
Integrated voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8
General-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.1.1
GPIO ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.1.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.1.3
Forced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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8.1.4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.1.5
nBOOTMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1.6
GPIO modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1.7
Wake monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.2
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3
Debug control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.4
GPIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.5
General-purpose input/output (GPIO) registers . . . . . . . . . . . . . . . . . . . 101
8.5.1
Port x configuration register (Low) (GPIOx_CRL) . . . . . . . . . . . . . . . . 101
8.5.2
Port x configuration register (High) (GPIOx_CRH) . . . . . . . . . . . . . . . 102
8.5.3
Port x input data register (GPIOx_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 103
8.5.4
Port x output data register (GPIOx_ODR) . . . . . . . . . . . . . . . . . . . . . . 103
8.5.5
Port x output set register (GPIOx_BSR) . . . . . . . . . . . . . . . . . . . . . . . 104
8.5.6
Port x output clear register (GPIOx_BRR) . . . . . . . . . . . . . . . . . . . . . . 104
8.5.7
External interrupt pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . 105
8.5.8
External interrupt x trigger selection register (EXTIx_TSR) . . . . . . . . . 105
8.5.9
External interrupt x configuration register (EXTIx_CR) . . . . . . . . . . . . 106
8.5.10
PC TRACE or debug select register (GPIO_PCTRACECR) . . . . . . . . 106
8.5.11
GPIO debug configuration register (GPIO_DBGCR) . . . . . . . . . . . . . . 107
8.5.12
GPIO debug status register (GPIO_DBGSR) . . . . . . . . . . . . . . . . . . . 107
8.5.13
General-purpose input/output (GPIO) register map . . . . . . . . . . . . . . . 108
Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9.3
SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4
9.5
9.3.1
Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.3.2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3.3
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.4.1
Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.4.2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.4.3
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.5.1
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Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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Contents
9.5.2
Constructing frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.5.3
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . 123
9.6.1
Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.6.2
FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.6.3
RTS/CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.6.4
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.6.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.7
Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.8
Serial controller common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.9
9.10
9.11
9.12
9.8.1
Serial controller interrupt status register (SCx_ISR) . . . . . . . . . . . . . . 129
9.8.2
Serial controller interrupt enable register (SCx_IER) . . . . . . . . . . . . . . 131
9.8.3
Serial controller interrupt control register 1 (SCx_ICR) . . . . . . . . . . . . 133
9.8.4
Serial controller data register (SCx_DR) . . . . . . . . . . . . . . . . . . . . . . . 134
9.8.5
Serial controller control register 2 (SCx_CR) . . . . . . . . . . . . . . . . . . . . 134
9.8.6
Serial controller clock rate register 1 (SCx_CRR1) . . . . . . . . . . . . . . . 135
9.8.7
Serial controller clock rate register 2 (SCx_CRR2) . . . . . . . . . . . . . . . 135
Serial controller: Serial peripheral interface (SPI) registers . . . . . . . . . . 136
9.9.1
Serial controller SPI status register (SCx_SPISR) . . . . . . . . . . . . . . . . 136
9.9.2
Serial controller SPI control register (SCx_SPICR) . . . . . . . . . . . . . . . 137
Serial controller: Inter-integrated circuit (I2C) registers . . . . . . . . . . . . . 138
9.10.1
Serial controller I2C status register (SCx_I2CSR) . . . . . . . . . . . . . . . . 138
9.10.2
Serial controller I2C control register 1 (SCx_I2CCR1) . . . . . . . . . . . . 139
9.10.3
Serial controller I2C control register 2 (SCx_I2CCR2) . . . . . . . . . . . . 140
Serial controller: Universal asynchronous receiver/
transmitter (UART) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.11.1
Serial controller UART status register (SC1_UARTSR) . . . . . . . . . . . 141
9.11.2
Serial controller UART control register (SC1_UARTCR) . . . . . . . . . . . 142
9.11.3
Serial controller UART baud rate register 1 (SC1_UARTBRR1) . . . . . 143
9.11.4
Serial controller UART baud rate register 2 (SC1_UARTBRR2) . . . . . 144
Serial controller: Direct memory access (DMA) registers . . . . . . . . . . . . 145
9.12.1
Serial controller receive DMA begin address channel A register
(SCx_DMARXBEGADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.12.2
Serial controller receive DMA end address channel A register
(SCx_DMARXENDADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.12.3
Serial controller receive DMA begin address channel B register
(SCx_ DMARXBEGADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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9.12.4
Serial controller receive DMA end address channel B register
(SCx_DMARXENDADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.12.5
Serial controller transmit DMA begin address channel A register
(SCx_DMATXBEGADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.12.6
Serial controller transmit DMA end address channel A register
(SCx_DMATXENDADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.12.7
Serial controller transmit DMA begin address channel B register
(SCx_DMATXBEGADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.12.8
Serial controller transmit DMA end address channel B register
(SCx_DMATXENDADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.12.9
Serial controller receive DMA counter channel A register
(SCx_DMARXCNTAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.12.10 Serial controller receive DMA count channel B register
(SCx_DMARXCNTBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.12.11 Serial controller transmit DMA counter register
(SCx_DMATXCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.12.12 Serial controller DMA status register (SCx_DMASR) . . . . . . . . . . . . . 151
9.12.13 Serial controller DMA control register (SCx_DMACR) . . . . . . . . . . . . . 153
9.12.14 Serial controller receive DMA channel A first error register
(SCx_DMARXERRAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.12.15 Serial controller receive DMA channel B first error register
(SCx_DMARXERRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.12.16 Serial controller receive DMA saved counter channel B register
(SCx_DMARXCNTSAVEDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
9.12.17 Serial interface (SC1/SC2) register map . . . . . . . . . . . . . . . . . . . . . . . 155
10
General-purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
10.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10.1.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10.1.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
10.1.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.1.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.1.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.1.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
10.1.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.1.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.1.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10.1.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
10.1.11 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10.1.12 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
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10.1.13 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 186
10.1.14 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.1.15 Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
10.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
10.3
General-purpose timers 1 and 2 registers . . . . . . . . . . . . . . . . . . . . . . . 197
10.3.1
Timer x interrupt and status register (TIMx_ISR) . . . . . . . . . . . . . . . . . 197
10.3.2
Timer x interrupt missed register (TIMx_MISSR) . . . . . . . . . . . . . . . . . 198
10.3.3
Timer x interrupt enable register (TIMx_IER) . . . . . . . . . . . . . . . . . . . . 198
10.3.4
Timer x control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 199
10.3.5
Timer x control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 201
10.3.6
Timer x slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . 202
10.3.7
Timer x event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 205
10.3.8
Timer x capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . 206
10.3.9
Timer x capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . 210
10.3.10 Timer x capture/compare enable register (TIMx_CCER) . . . . . . . . . . . 214
10.3.11 Timer x counter register (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 215
10.3.12 Timer x prescaler register (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 215
10.3.13 Timer x auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 216
10.3.14 Timer x capture/compare 1 register (TIMx_CCR1) . . . . . . . . . . . . . . . 216
10.3.15 Timer x capture/compare 2 register (TIMx_CCR2) . . . . . . . . . . . . . . . 217
10.3.16 Timer x capture/compare 3 register (TIMx_CCR3) . . . . . . . . . . . . . . . 217
10.3.17 Timer x capture/compare 4 register (TIMx_CCR4) . . . . . . . . . . . . . . . 218
10.3.18 Timer 1 option register (TIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
10.3.19 Timer 2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
10.3.20 General-purpose timers 1 and 2 (TIM1/TIM2) register map . . . . . . . . 220
11
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
11.1
11.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.1
Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.2
GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.3
Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.4
Offset/gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
11.1.5
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
11.1.6
ADC configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
11.1.7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
11.1.8
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
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11.3
Analog-to-digital converter (ADC) registers . . . . . . . . . . . . . . . . . . . . . . 233
11.3.1
ADC interrupt status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . . . . 233
11.3.2
ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 233
11.3.3
ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
11.3.4
ADC offset register (ADC_OFFSETR) . . . . . . . . . . . . . . . . . . . . . . . . . 235
11.3.5
ADC gain register (ADC_GAINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
11.3.6
ADC DMA control register (ADC_DMACR) . . . . . . . . . . . . . . . . . . . . . 236
11.3.7
ADC DMA status register (ADC_DMASR) . . . . . . . . . . . . . . . . . . . . . . 236
11.3.8
ADC DMA memory start address register (ADC_DMAMSAR) . . . . . . 237
11.3.9
ADC DMA number of data to transfer register (ADC_DMANDTR) . . . 237
11.3.10 ADC DMA memory next address register (ADC_DMAMNAR) . . . . . . 238
11.3.11
ADC DMA count number of data transferred register
(ADC_DMACNDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
11.3.12 Analog-to-digital converter (ADC) register map . . . . . . . . . . . . . . . . . . 239
12
13
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 241
12.2
Management interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12.2.2
Management interrupt mask register (MGMT_IER) . . . . . . . . . . . . . . . 244
12.2.3
Management interrupt (MGMT) register map . . . . . . . . . . . . . . . . . . . 244
STM32W108 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1
8/289
Management interrupt source register (MGMT_ISR) . . . . . . . . . . . . . 243
Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
13.1
14
12.2.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
14.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.3.2
Operating conditions at power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.3.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 250
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14.4
SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
14.5
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
14.6
Clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
14.6.1
High frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 259
14.6.2
High frequency external clock characteristics . . . . . . . . . . . . . . . . . . . 259
14.6.3
Low frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 260
14.6.4
Low frequency external clock characteristics . . . . . . . . . . . . . . . . . . . 260
14.7
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
14.8
Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
14.9
Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 267
14.10 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
14.10.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
14.10.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
14.10.3 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.1
VFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.2
VFQFPN40 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15.3
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
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List of tables
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List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
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Description of abbreviations used for bit field access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM32W108xx peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MEM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Generated resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RST register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
System clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
MACTMR, WDG, and SLPTMR register map and reset values . . . . . . . . . . . . . . . . . . . . . 73
PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
1.8 V integrated voltage regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
GPIO configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Timer 2 output configuration controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
GPIO forced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
IRQC/D GPIO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
GPIO signal assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SC1 GPIO usage and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SC2 GPIO usage and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SPI master GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI master mode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SPI slave GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SPI slave mode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I2C Master GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
I2C clock rate programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
I2C master frame segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
UART GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
UART baud rate divisors for common baud rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
UART RTS/CTS flow control configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SC1/SC2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Timer GPIO use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
EXTRIGSEL clock signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
TIM1/TIM2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
ADC GPIO pin usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
ADC inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Typical ADC input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
ADC sample times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
ADC gain and offset correction equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
NVIC exception table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
MGMT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
List of tables
POR HV thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
POR LVcore thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
POR LVmem thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Reset filter specification for RSTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
ADC module key parameters for 1 MHz sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
ADC module key parameters for input buffer disabled
and 6 MHz sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
ADC module key parameters for input buffer enabled
and 6MHz sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
High-frequency RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
High-frequency crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Low-frequency RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Low-frequency crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Digital I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Synthesizer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
VFQFPN48 - 48-pin, 7x7 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
VFQFPN40 - 40-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
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11
List of figures
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
12/289
STM32W108xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
48-pin VFQFPN pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
40-pin VFQFPN pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM32W108xB memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32W108CC and STM32W108CZ memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clocks block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Power management state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
GPIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Serial controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
I2C segment transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UART character frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
UART FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
RTS/CTS flow control connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 163
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not buffered) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Counter timing diagram, update event when ARPE = 1 (TIMx_ARR buffered) . . . . . . . . 166
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 168
Counter timing diagram, update event with ARPE = 1
(counter underflow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Counter timing diagram, update event with ARPE = 1
(counter overflow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Control circuit in Normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 170
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Control circuit in External Clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 173
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Edge-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Center-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 184
Example of encoder interface mode with IC1FP1 polarity inverted . . . . . . . . . . . . . . . . . 185
Control circuit in Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Control circuit in Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Control circuit in External clock mode 2 + Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 189
Master/slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
List of figures
Gating Timer 2 with OC1REF of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Gating Timer 2 with enable of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Triggering timer 2 with update of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Triggering Timer 2 with enable of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Triggering Timers 1 and 2 with Timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SWJ block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Transmit power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Transmit output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
VFQFPN48 - 48-pin, 7x7 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
VFQFPN48 - 48-pin, 7x7 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
VFQFPN40 - 40-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
VFQFPN40 - 40-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
VFQFPN40 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
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Description
1
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Description
The STM32W108xx is a fully integrated system-on-chip that integrates a 2.4 GHz, IEEE
802.15.4-compliant transceiver, 32-bit ARM® Cortex®-M3 microprocessor, Flash and RAM
memory, and peripherals of use to designers of 802.15.4-based systems.
The transceiver utilizes an efficient architecture that exceeds the dynamic range
requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated
receive channel filtering allows for robust co-existence with other communication standards
in the 2.4 GHz spectrum, such as IEEE 802.11 and Bluetooth. The integrated regulator,
VCO, loop filter, and power amplifier keep the external component count low. An optional
high performance radio mode (boost mode) is software-selectable to boost dynamic range.
The integrated 32-bit ARM® Cortex®-M3 microprocessor is highly optimized for high
performance, low power consumption, and efficient memory utilization. Including an
integrated MPU, it supports two different modes of operation: Privileged mode and
Unprivileged mode. This architecture could be used to separate the networking stack from
the application code and prevent unwanted modification of restricted areas of memory and
registers resulting in increased stability and reliability of deployed solutions.
The STM32W108xx has 128/192/256 Kbyte of embedded Flash memory and 8/12/16 Kbyte
of integrated RAM for data and program storage. The STM32W108xx HAL software
employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded
Flash.
To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003
standards, the STM32W108xx integrates a number of MAC functions into the hardware.
The MAC hardware handles automatic ACK transmission and reception, automatic backoff
delay, and clear channel assessment for transmission, as well as automatic filtering of
received packets. A packet trace interface is also integrated with the MAC, allowing
complete, non-intrusive capture of all packets to and from the STM32W108xx.
The STM32W108xx offers a number of advanced power management features that enable
long battery life. A high-frequency internal RC oscillator allows the processor core to begin
code execution quickly upon waking. Various deep sleep modes are available with less than
1 µA power consumption while retaining RAM contents. To support user-defined
applications, on-chip peripherals include UART, SPI, I2C, ADC and general-purpose timers,
as well as up to 24 GPIOs. Additionally, an integrated voltage regulator, power-on-reset
circuit, and sleep timer are available.
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Description
Figure 1. STM32W108xx block diagram
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1.1
Development tools
The STM32W108xx implements both the ARM Serial Wire and JTAG debug interfaces.
These interfaces provide real time, non-intrusive programming and debugging capabilities.
Serial Wire and JTAG provide the same functionality, but are mutually exclusive. The Serial
Wire interface uses two pins; the JTAG interface uses five. Serial Wire is preferred, since it
uses fewer pins.
The STM32W108xx also integrates the standard ARM system debug components: Flash
Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace
Macrocell (DWT).
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Description
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
1.2
Overview
1.2.1
Functional description
The STM32W108xx radio receiver is a low-IF, super-heterodyne receiver. The architecture
has been chosen to optimize co-existence with other devices in the 2.4 GHz band (namely,
WIFI and Bluetooth), and to minimize power consumption. The receiver uses differential
signal paths to reduce sensitivity to noise interference. Following RF amplification, the
signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.
The radio transmitter uses an efficient architecture in which the data stream directly
modulates the VCO frequency. An integrated power amplifier (PA) provides the output
power. Digital logic controls Tx path and output power calibration. If the STM32W108xx is to
be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the
timing of the external switching logic.
The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz
crystal with its loading capacitors is required to establish the PLL local oscillator signal.
The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC
provides hardware-based IEEE 802.15.4 packet-level filtering. It supplies an accurate
symbol time base that minimizes the synchronization effort of the software stack and meets
the protocol timing requirements. In addition, it provides timer and synchronization
assistance for the IEEE 802.15.4 CSMA-CA algorithm.
The STM32W108xx integrates an ARM® Cortex®-M3 microprocessor, revision r1p1. This
industry-leading core provides 32 bit performance and is very power efficient. It has
excellent code density using the ARM® Thumb 2 instruction set. The processor can be
operated at 12 MHz or 24 MHz when using the crystal oscillator, or at 6 MHz or 12 MHz
when using the integrated high frequency RC oscillator.
The STM32W108xx has 128/192/256 Kbyte of Flash memory, 8/12/16 Kbyte of SRAM onchip, and the ARM configurable memory protection unit (MPU).
The STM32W108xx contains 24 GPIO pins shared with other peripheral or alternate
functions. Because of flexible routing within the STM32W108xx, external devices can use
the alternate functions on a variety of different GPIOs. The integrated Serial Controller SC1
can be configured for SPI (master or slave), I2C (master-only), or UART operation, and the
Serial Controller SC2 can be configured for SPI (master or slave) or I2C (master-only)
operation.
The STM32W108xx has a general purpose ADC which can sample analog signals from six
GPIO pins in single-ended or differential modes. It can also sample the regulated supply
VDD_PADSA, the voltage reference VREF, and GND. The ADC has two selectable voltage
ranges: 0 V to 1.2 V for the low voltage (input buffer disabled) and 0.1 V to VDD_PADS
minus 0.1 V for the high voltage supply (input buffer enabled). The ADC has a DMA mode to
capture samples and automatically transfer them into RAM. The integrated voltage
reference for the ADC, VREF, can be made available to external circuitry. An external
voltage reference can also be driven into the ADC.
The STM32W108xx contains four oscillators: a high frequency 24 MHz external crystal
oscillator (24 MHz HSE OSC), a high frequency 12 MHz internal RC oscillator (12 MHz HSI
RC), an optional low frequency 32.768 kHz external crystal oscillator (32 kHz HSE OSC),
and a 10 kHz internal RC oscillator (10 kHz LSI RC).
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Description
The STM32W108xx has an ultra low power, deep sleep state with a choice of clocking
modes. The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator
or with a 1 kHz clock derived from the internal 10 kHz LSI RC oscillator. Alternatively, all
clocks can be disabled for the lowest power mode. In the lowest power mode, only external
events on GPIO pins will wake up the chip. The STM32W108xx has a fast startup time
(typically 100 µs) from deep sleep to the execution of the first ARM® Cortex®-M3 instruction.
The STM32W108xx contains three power domains. The always-on high voltage supply
powers the GPIO pads and critical chip functions. Regulated low voltage supplies power the
rest of the chip. The low voltage supplies are be disabled during deep sleep to reduce power
consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8 V voltages
from an unregulated supply voltage. The 1.8 V regulator output is decoupled and routed
externally to supply analog blocks, RAM, and Flash memories. The 1.25 V regulator output
is decoupled externally and supplies the core logic.
The digital section of the receiver uses a coherent demodulator to generate symbols for the
hardware-based MAC. The digital receiver also contains the analog radio calibration
routines and controls the gain within the receiver path.
In addition to 2 general-purpose timers, the STM32W108xx also contains a watchdog timer
to ensure protection against software crashes and CPU lockup, a 32-bit sleep timer
dedicated to system timing and waking from sleep at specific times and an ARM® standard
system event timer in the NVIC.
The STM32W108xx integrates hardware support for a Packet Trace module, which allows
robust packet-based debug.
Note:
The STM32W108xx is not pin-compatible with the previous generation chip, the SN250,
except for the RF section of the chip. Pins 1-11 and 45-48 are compatible, to ease migration
to the STM32W108xx.
1.2.2
ARM® Cortex®-M3 core
The STM32W108xx integrates the ARM® Cortex®-M3 microprocessor, revision r1p1,
developed by ARM Ltd, making the STM32W108xx a true system-on-a-chip solution. The
ARM® Cortex®-M3 is an advanced 32-bit modified Harvard architecture processor that has
separate internal program and data buses, but presents a unified program and data address
space to software. The word width is 32 bits for both the program and data sides. The ARM®
Cortex®-M3 allows unaligned word and half-word data accesses to support efficientlypacked data structures.
The ARM® Cortex®-M3 clock speed is configurable to 6 MHz, 12 MHz, or 24 MHz. For
normal operation 12 MHz is preferred over 24 MHz due to its lower power consumption. The
6 MHz operation can only be used when radio operations are not required since the radio
requires an accurate 12 MHz clock.
The ARM® Cortex®-M3 in the STM32W108xx has also been enhanced to support two
separate memory protection levels. Basic protection is available without using the MPU, but
the usual operation uses the MPU. The MPU protects unimplemented areas of the memory
map to prevent common software bugs from interfering with software operation. The
architecture could also separate the networking stack from the application code using a fine
granularity RAM protection module. Errant writes are captured and details are reported to
the developer to assist in tracking down and fixing issues.
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Documentation conventions
2
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Documentation conventions
Table 1. Description of abbreviations used for bit field access
Description(1)
Abbreviation
Read/Write (rw)
Software can read and write to these bits.
Read-only (r)
Software can only read these bits.
Write only (w)
Software can only write to this bit. Reading returns the reset value.
Software can read and write to these bits only in Privileged mode. For
Read/Write in (MPU)
more information, please refer to RAM memory protection on page 37
Privileged mode only (rws)
and Memory protection unit on page 42.
1. The conditions under which the hardware (core) sets or clears this field are explained in details in the bit
field description, as well as the events that may be generated by writing to the bit.
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
3
Pinout and pin description
Pinout and pin description
Figure 2. 48-pin VFQFPN pinout
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Embedded memory
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Flash may be programmed either through the Serial Wire/JTAG interface or through
bootloader software. Programming Flash through Serial Wire/JTAG requires the assistance
of RAM-based utility code. Programming through a bootloader requires specific software for
over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also
available preprogrammed into the FIB.
4.3
Random-access memory
The STM32W108xx has 8/12/16 Kbyte of static RAM on-chip. The start of RAM is mapped
to address 0x20000000. Although the ARM® Cortex®-M3 allows bit band accesses to this
address region, the standard MPU configuration does not permit use of the bit-band feature.
The RAM is physically connected to the AHB System bus and is therefore accessible to
both the ARM® Cortex®-M3 microprocessor and the debugger. The RAM can be accessed
for both instruction and data fetches as bytes, half words, or words. The standard MPU
configuration does not permit execution from the RAM, but for special purposes, such as
programming the main Flash block, the MPU may be disabled. To the bus, the RAM
appears as 32-bit wide memory and in most situations has zero wait state read or write
access. In the higher CPU clock mode the RAM requires two wait states. This is handled by
hardware transparent to the user application with no configuration required.
4.3.1
Direct memory access (DMA) to RAM
Several of the peripherals are equipped with DMA controllers allowing them to transfer data
into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general
purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full
duplex so that a read and a write to RAM may be requested at the same time. Thus there
are six DMA channels in total.
The STM32W108xx integrates a DMA arbiter that ensures fair access to the microprocessor
as well as the peripherals through a fixed priority scheme appropriate to the memory
bandwidth requirements of each master. The priority scheme is as follows, with the top
peripheral being the highest priority:
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1.
General Purpose ADC
2.
Serial Controller 2 Receive
3.
Serial Controller 2 Transmit
4.
MAC
5.
Serial Controller 1 Receive
6.
Serial Controller 1 Transmit
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
4.3.2
Embedded memory
RAM memory protection
The STM32W108xx integrates two memory protection mechanisms. The first memory
protection mechanism is through the ARM® Cortex®-M3 Memory Protection Unit (MPU)
described in the Memory Protection Unit section. The MPU may be used to protect any area
of memory. MPU configuration is normally handled by software. The second memory
protection mechanism is through a fine granularity RAM protection module. This allows
segmentation of the RAM into blocks where any block can be marked as write protected. An
attempt to write to a protected RAM block using a user mode write results in a bus error
being signaled on the AHB System bus. A system mode write is allowed at any time and
reads are allowed in either mode. The main purpose of this fine granularity RAM protection
module is to notify the stack of erroneous writes to system areas of memory. RAM protection
is configured using a group of registers that provide a bit map. Each bit in the map
represents a 32-byte block of RAM for STM32W108xB and 64 bytes of RAM for
STM32W108CC and STM32W108CZ.When the bit is set the block is write protected.
The fine granularity RAM memory protection mechanism is also available to the peripheral
DMA controllers. A register bit is provided to enable the memory protection to include DMA
writes to protected memory. If a DMA write is made to a protected location in RAM, a
management interrupt is generated. At the same time the faulting address and the
identification of the peripheral is captured for later debugging. Note that only peripherals
capable of writing data to RAM, such as received packet data or a received serial port
character, can generate this interrupt.
4.3.3
Memory controller
The STM32W108xx allows the RAM and DMA protection to be controlled using the memory
controller interface. The chip contains eight RAM protection registers and two DMA
protection registers. In addition, the chip contains a register, RAM_CR, for enabling the
protection of the memory.
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Embedded memory
4.3.4
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Memory controller registers
RAM is divided into 32 byte pages. Each page has a register bit that, when set, protects it
from being written in user mode. The protection registers (MEM_PROT) are arranged in the
register map as a 256-bit vector. Bit 0 of this vector protects page 0 which begins at location
0x2000 0000 and ends at 0x2000 001F. Bit 255 of this vector protects the top page which
starts at 0x20001FE0 and ends at 0x2000 1FFF.
Memory RAM protection register x (RAM_PROTRx)
Address: 0x 4000 5000 (RAM_PROTR1), 0x 4000 5004 (RAM_PROTR2),
0x 4000 5008 (RAM_PROTR3), 0x 4000 500C (RAM_PROTR4),
0x 4000 5010 (RAM_PROTR5), 0x 4000 5014 (RAM_PROTR6),
0x 4000 5018(RAM_PROTR7), and 0x 4000 501C (RAM_PROTR8).
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Memory page protection x[31:16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
Memory page protection x[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 Memory page protection x[31:0]:
Bit 0 in the RAM_PROTR1 protects page 0
…
Bit 31 in the RAM_PROTR1 protects page 31
Bit 0 in the RAM_PROTR2 protects page 32
…
Bit 31 in the RAM_PROTR2 protects page 63
Bit 0 in the RAM_PROTR3 protects page 64
…
Bit 31 in the RAM_PROTR3 protects page 95
Bit 0 in the RAM_PROTR4 protects page 96
…
Bit 31 in the RAM_PROTR4 protects page 127
Bit 0 in the RAM_PROTR5 protects page 128
…
Bit 31 in the RAM_PROTR5 protects page 159
Bit 0 in the RAM_PROTR6 protects page 160
…
Bit 31 in the RAM_PROTR6 protects page 191
Bit 0 in the RAM_PROTR7 protects page 192
…
Bit 31 in the RAM_PROTR7 protects page 223
Bit 0 in the RAM_PROTR8 protects page 224
….
Bit 31 in the RAM_PROTR8 protects page 255
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Embedded memory
Memory DMA protection register 1 (DMA_PROTR1)
Address: 0x 4000 5020
Reset value: 0x2000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Offset[18:3]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
Offset[2:0]
r
r
Address[11:0]
r
r
r
r
r
r
r
r
Reserved
Bits 31:13 Offset[18:0]:
Offset in RAM
Bits 12:1 Offset[11:0]:
DMA protection fault, faulting address.
Bit 0 Reserved, must be kept at reset value
Memory DMA protection register 2 (DMA_PROTR2)
Address: 0x 4000 5024
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Reserved
15
14
13
12
11
10
9
8
7
Channel[2:0]
Reserved
r
r
r
Bits 31:3 Reserved, must be kept at reset value
Bits 2:0 Channel[2:0]: Channel encoding
7: Not used
6: Not used
5: SC2_RX
4: Not used
3: ADC
2: Not used
1: SC1_RX
0: Not used
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Memory RAM control register (RAM_CR)
Address: 0x 4000 5028
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Reserved
15
14
13
12
11
10
9
8
7
WEN
Reserved
Bits 31:3 Reserved, must be kept at reset value
Bit 2 WEN: Makes all RAM writes appear as user mode
Bits 1:0 Reserved, must be kept at reset value
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Reserved
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Embedded memory
Memory controller (MEM) register map
Table 5 gives the MEM register map and reset values.
RAM_PROTR1
Memory page protection 1[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory page protection 2[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory page protection 3[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory protection 4[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory protection 5[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory protection 6[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory protection 7[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory protection 8[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_PROTR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Channel[2:0]
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RAM_CR
Res.
0x5028
Res.
Reset value
0
0
0
0
Res.
Reset value
Res.
Address[11:0]
Res.
Offset[18:0]
Res.
DMA_PROTR1
0
Res.
0x5024
0
RAM_PROTR8
Reset value
0x5020
0
RAM_PROTR7
Reset value
0x501C
0
RAM_PROTR6
Reset value
0x5018
0
RAM_PROTR5
Reset value
0x5014
0
RAM_PROTR4
Reset value
0x5010
0
RAM_PROTR3
Reset value
0x500C
0
RAM_PROTR2
Reset value
0x5008
0
Res.
0x5004
0
Res.
Reset value
WEN
0x5000
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 5. MEM register map and reset values
0
Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and
STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register
boundary addresses for the register boundary addresses of the peripherals available in all
STM32W108xx devices.
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4.4
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Memory protection unit
The STM32W108xx includes the ARM® Cortex®-M3 Memory Protection Unit, or MPU. The
MPU controls access rights and characteristics of up to eight address regions, each of
which may be divided into eight equal sub-regions. Refer to the ARM® Cortex®-M3
Technical Reference Manual (DDI 0337A) for a detailed description of the MPU.
ST software configures the MPU in a standard configuration and application software should
not modify it. The configuration is designed for optimal detection of illegal instruction or data
accesses. If an illegal access is attempted, the MPU captures information about the access
type, the address being accessed, and the location of the offending software. This simplifies
software debugging and increases the reliability of deployed devices. As a consequence of
this MPU configuration, accessing RAM and register bit-band address alias regions is not
permitted, and generates a bus fault if attempted.
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
5
Radio frequency module
Radio frequency module
The radio module consists of an analog front end and digital baseband as shown in
Figure 1: STM32W108xx block diagram.
5.1
Receive (Rx) path
The Rx path uses a low-IF, super-heterodyne receiver that rejects the image frequency
using complex mixing and polyphase filtering. In the analog domain, the input RF signal
from the antenna is first amplified and mixed down to a 4 MHz IF frequency. The mixers'
output is filtered, combined, and amplified before being sampled by a 12 Msps ADC. The
digitized signal is then demodulated in the digital baseband. The filtering within the Rx path
improves the STM32W108xx's co-existence with other 2.4 GHz transceivers such as IEEE
802.15.4, IEEE 802.11g, and Bluetooth radios. The digital baseband also provides gain
control of the Rx path, both to enable the reception of small and large wanted signals and to
tolerate large interferers.
5.1.1
Rx baseband
The STM32W108xx Rx digital baseband implements a coherent demodulator for optimal
performance. The baseband demodulates the O-QPSK signal at the chip level and
synchronizes with the IEEE 802.15.4-defined preamble. An automatic gain control (AGC)
module adjusts the analog gain continuously every ¼ symbol until the preamble is detected.
Once detected, the gain is fixed for the remainder of the packet. The baseband despreads
the demodulated data into 4-bit symbols. These symbols are buffered and passed to the
hardware-based MAC module for packet assembly and filtering.
In addition, the Rx baseband provides the calibration and control interface to the analog Rx
modules, including the LNA, Rx baseband filter, and modulation modules. The ST RF
software driver includes calibration algorithms that use this interface to reduce the effects of
silicon process and temperature variation.
5.1.2
RSSI and CCA
The STM32W108xx calculates the RSSI over every 8-symbol period as well as at the end of
a received packet. The linear range of RSSI is specified to be at least 40 dB over
temperature. At room temperature, the linear range is approximately 60 dB (-90 dBm to -30
dBm input signal).
The STM32W108xx Rx baseband provides support for the IEEE 802.15.4-2003 RSSI CCA
method, Clear channel reports busy medium if RSSI exceeds its threshold.
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Radio frequency module
5.2
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Transmit (Tx) path
The STM32W108xx Tx path produces an O-QPSK-modulated signal using the analog front
end and digital baseband. The area- and power-efficient Tx architecture uses a two-point
modulation scheme to modulate the RF signal generated by the synthesizer. The modulated
RF signal is fed to the integrated PA and then out of the STM32W108xx.
5.2.1
Tx baseband
The STM32W108xx Tx baseband in the digital domain spreads the 4-bit symbol into its
IEEE 802.15.4-2003-defined 32-chip sequence. It also provides the interface for software to
calibrate the Tx module to reduce silicon process, temperature, and voltage variations.
5.2.2
TX_ACTIVE and nTX_ACTIVE signals
For applications requiring an external PA, two signals are provided called TX_ACTIVE and
nTX_ACTIVE. These signals are the inverse of each other. They can be used for external
PA power management and RF switching logic. In transmit mode the Tx baseband drives
TX_ACTIVE high, as described in Table 17: GPIO signal assignments on page 99. In
receive mode the TX_ACTIVE signal is low. TX_ACTIVE is the alternate function of PC5,
and nTX_ACTIVE is the alternate function of PC6. See Section 8: General-purpose
input/output on page 92 for details of the alternate GPIO functions.
5.3
Calibration
The ST RF software driver calibrates the radio using dedicated hardware resources.
5.4
Integrated MAC module
The STM32W108xx integrates most of the IEEE 802.15.4 MAC requirements in hardware.
This allows the ARM® Cortex®-M3 CPU to provide greater bandwidth to application and
network operations. In addition, the hardware acts as a first-line filter for unwanted packets.
The STM32W108xx MAC uses a DMA interface to RAM to further reduce the overall ARM®
Cortex®-M3 CPU interaction when transmitting or receiving packets.
When a packet is ready for transmission, the software configures the Tx MAC DMA by
indicating the packet buffer RAM location. The MAC waits for the backoff period, then
switches the baseband to Tx mode and performs channel assessment. When the channel is
clear the MAC reads data from the RAM buffer, calculates the CRC, and provides 4-bit
symbols to the baseband. When the final byte has been read and sent to the baseband, the
CRC remainder is read and transmitted.
The MAC is in Rx mode most of the time. In Rx mode various format and address filters
keep unwanted packets from using excessive RAM buffers, and prevent the CPU from
being unnecessarily interrupted. When the reception of a packet begins, the MAC reads 4bit symbols from the baseband and calculates the CRC. It then assembles the received data
for storage in a RAM buffer. Rx MAC DMA provides direct access to RAM. Once the packet
has been received additional data, which provides statistical information on the packet to the
software stack, is appended to the end of the packet in the RAM buffer space.
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
Radio frequency module
The primary features of the MAC are:
5.5
•
CRC generation, appending, and checking
•
Hardware timers and interrupts to achieve the MAC symbol timing
•
Automatic preamble and SFD pre-pending on Tx packets
•
Address recognition and packet filtering on Rx packets
•
Automatic acknowledgement transmission
•
Automatic transmission of packets from memory
•
Automatic transmission after backoff time if channel is clear (CCA)
•
Automatic acknowledgement checking
•
Time stamping received and transmitted messages
•
Attaching packet information to received packets (LQI, RSSI, gain, time stamp, and
packet status)
•
IEEE 802.15.4 timing and slotted/unslotted timing
Packet trace interface (PTI)
The STM32W108xx integrates a true PHY-level PTI for effective network-level debugging. It
monitors all the PHY Tx and Rx packets between the MAC and baseband modules without
affecting their normal operation. It cannot be used to inject packets into the PHY/MAC
interface. This 500 kbps asynchronous interface comprises the frame signal (PTI_EN, PA4)
and the data signal (PTI_DATA, PA5).
5.6
Random number generator
Thermal noise in the analog circuitry is digitized to provide entropy for a true random
number generator (TRNG). The TRNG produces 16-bit uniformly distributed numbers. The
Software can use the TRNG to seed a pseudo random number generator (PNRG). The
TRNG is also used directly for cryptographic key generation.
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System modules
6
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
System modules
System modules encompass power, resets, clocks, system timers, power management, and
encryption. Figure 6 shows these modules and how they interact.
Figure 6. System module block diagram
&6
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