STM32WB30CEU5A

STM32WB50CG STM32WB30CE Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.3 or 802.15.4 radio solution Datasheet - production data Features • Include ST state-of-the-art patented technology • Radio – 2.4 GHz – RF transceiver supporting Bluetooth® 5.3 specification or IEEE 802.15.4-2011 PHY and MAC, supporting Thread and Zigbee® 3.0 – RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps), -100 dBm (802.15.4) – Programmable output power up to +4 dBm with 1 dB steps – Integrated balun to reduce BOM – Support for 1 Mbps – Support advertising extension – Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer – Accurate RSSI to enable power control – Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66 – Support for external PA – Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3) • Ultra-low-power platform – 2.0 to 3.6 V power supply – – 10 °C to +85 °C temperature range – 14 nA shutdown mode – 700 nA Standby mode + RTC + 32 KB RAM – 2.25 µA Stop mode + RTC + 128 KB RAM – Radio: Rx 7.9 mA / Tx at 0 dBm 8.8 mA June 2022 This is information on a product in full production. UFQFPN48 7 x 7 mm solder pad • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART™ Accelerator) allowing 0-wait-state execution from flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions • Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 219.48 CoreMark® (3.43 CoreMark/MHz at 64 MHz) • Energy benckmark – 303 ULPMark™ CP score • Supply and reset management – Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds – Ultra-low-power POR/PDR – Programmable voltage detector (PVD) – VBAT mode with RTC and backup registers • Clock sources – 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock) – 32 kHz crystal oscillator for RTC (LSE) – Internal low-power 32 kHz (±5%) RC (LSI1) – Internal low-power 32 kHz (stability ±500 ppm) RC (LSI2) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy) – High speed internal 16 MHz factory trimmed RC (±1%) – 1x PLL for system clock and ADC DS13047 Rev 7 1/121 www.st.com STM32WB50CG STM32WB30CE • Memories – 1 MB flash memory with sector protection (PCROP) against R/W operations, enabling radio stack and application – 128 KB SRAM, including 64 KB with hardware parity check – 20x 32-bit backup register – Boot loader supporting USART, SPI, I2C interfaces – OTA (over the air) Bluetooth® Low Energy and 802.15.4 update – 1 Kbyte (128 double words) OTP • Rich analog peripherals (down to 2.0 V) – 12-bit ADC 2.13 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps • System peripherals – Inter processor communication controller (IPCC) for communication with Bluetooth® Low Energy and 802.15.4 – HW semaphores for resources sharing between CPUs – 1x DMA controller (7x channels) supporting ADC, SPI, I2C, USART, AES, timers – 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode) – 1x SPI 32 Mbit/s – 1x I2C (SMBus/PMBus®) – 1x 16-bit, four channels advanced timer – 2x 16-bit, two channels timer – 1x 32-bit, four channels timer – 2x 16-bit ultra-low-power timer – 1x independent Systick – 1x independent watchdog – 1x window watchdog 2/121 • Security and ID – Secure firmware installation (SFI) for Bluetooth® Low Energy and 802.15.4 SW stack – 2x hardware encryption AES maximum 256-bit for the application, the Bluetooth® Low Energy and IEEE802.15.4 – Customer key storage / key manager services – HW public key authority (PKA) – Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p) – True random number generator (RNG) – Sector protection against R/W operation (PCROP) – CRC calculation unit – Die information: 96-bit unique ID – IEEE 64-bit unique ID, possibility to derive 802.15.4 64-bit and Bluetooth® Low Energy 48-bit EUI • Up to 30 fast I/Os, 28 of them 5 V-tolerant • Development support – Serial wire debug (SWD), JTAG for the application processor – Application cross trigger • Package is ECOPACK2 compliant DS13047 Rev 7 STM32WB50CG STM32WB30CE Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 15 3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 3.6.1 RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6.2 BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.3 802.15.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6.4 RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6.5 Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7.2 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7.3 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.8 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.9 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37 DS13047 Rev 7 3/121 5 Contents STM32WB50CG STM32WB30CE 3.13.2 3.14 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 38 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.15 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.16.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.16.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 40 3.16.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 41 3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.16.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.16.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.17 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 42 3.18 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.19 Universal synchronous/asynchronous receiver transmitter (USART) . . . 44 3.20 Serial peripheral interface (SPI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.21 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.21.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1 4/121 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DS13047 Rev 7 STM32WB50CG STM32WB30CE 7 Contents 6.3.3 RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.4 RF 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.5 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 63 6.3.6 Embedded reset and power control block characteristics . . . . . . . . . . . 63 6.3.7 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.9 Wake-up time from Low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.19 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.20 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 97 6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.24 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 105 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.1 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 114 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 DS13047 Rev 7 5/121 5 List of tables STM32WB50CG STM32WB30CE List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 6/121 STM32WB50CG and STM32WB30CE device features and peripheral counts . . . . . . . . . 11 Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 16 RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features over all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32WB50CG and STM32WB30CE modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STM32WB50CG and STM32WB30CE CPU1 peripherals interconnect matrix . . . . . . . . . 32 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32WB50CG and STM32WB30CE pin and ball definitions . . . . . . . . . . . . . . . . . . . . . 47 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 RF transmitter 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 RF receiver 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 RF 802.15.4 power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 63 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Current consumption in Run and Low-power run modes, code with data processing running from flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . . . 66 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typical current consumption in Run and Low-power run modes, with different codes running from flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . . . 67 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Current consumption in Sleep and Low-power sleep modes, flash memory ON . . . . . . . . 68 Current consumption in Low-power sleep modes, flash memory in Power down. . . . . . . . 69 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DS13047 Rev 7 STM32WB50CG STM32WB30CE Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. List of tables Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Wake-up time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HSE clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32 MHz / 64 MHz, 32 MHz . . . . . . . . 89 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ADC accuracy - Limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC accuracy - Limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ADC accuracy - Limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 DS13047 Rev 7 7/121 7 List of figures STM32WB50CG STM32WB30CE List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. 8/121 STM32WB50CGxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STM32WB30CExx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32WB50CG and STM32WB30CE RF front-end block diagram . . . . . . . . . . . . . . . . . 19 External components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32WB50CG and STM32WB30CE UFQFPN48 pinout(1) (2). . . . . . . . . . . . . . . . . . . . . 46 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical link quality indicator code vs. Rx level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Typical energy detection (T = 27°C, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 HSI48 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 STM32WB50CG UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . 113 STM32WB30CE UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . 113 DS13047 Rev 7 STM32WB50CG STM32WB30CE 1 Introduction Introduction This document provides the ordering information and mechanical device characteristics of the STM32WB50CG and STM32WB30CE microcontrollers, based on Arm® cores(a). This document must be read in conjunction with the reference manual (RM0471), available from the STMicroelectronics website www.st.com. For information on the device errata with respect to the datasheet and reference manual refer to the STM32WB50CG and STM32WB30CE errata sheet (ES0492), available from the STMicroelectronics website www.st.com. For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the Cortex®-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference Manual, both available on the www.arm.com website. For information on 802.15.4 refer to the IEEE website (www.ieee.org). For information on Bluetooth® refer to www.bluetooth.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS13047 Rev 7 9/121 45 Description 2 STM32WB50CG STM32WB30CE Description The STM32WB50CG and STM32WB30CE multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.3 or with IEEE 802.15.4-2011. It contains a dedicated Arm® Cortex®-M0+ for performing all the real-time low layer operation. The devices are designed to be extremely low-power and are based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security. Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors. The devices embed high-speed memories (1 Mbyte of flash memory for STM32WB50xx, 512 Kbytes for STM32WB30xx, 128 Kbytes of SRAM for STM32WB50xx, 96 Kbytes for STM32WB30xx) and an extensive range of enhanced I/Os and peripherals. Direct data transfer between memory and peripherals and from memory to memory is supported by seven DMA channels with a full flexible channel mapping by the DMAMUX peripheral. The devices feature several mechanisms for embedded flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex® -M0+ exclusive access. The AES encryption engine, PKA and RNG enable lower layer MAC and upper layer cryptography. A customer key storage feature may be used to keep the keys hidden. The devices offer a fast 16-bit ADC. These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose 32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers. The STM32WB50CG and STM32WB30CE also feature standard and advanced communication interfaces, namely one USART (ISO 7816, IrDA, Modbus and Smartcard mode), one I2C (SMBus/PMBus), one SPI up to 32 MHz. The STM32WB50CG and STM32WB30CE operate in the -10 to +85 °C (+105 °C junction) temperature range from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The devices include independent power supplies for analog input for ADC. A VBAT dedicated supply allows the device to back up the LSE 32.768 kHz oscillator, the RTC and the backup registers, thus enabling the STM32WB50CG and STM32WB30CE to supply these functions even if the main VDD is not present through a CR2032-like battery, a Supercap or a small rechargeable battery. The STM32WB50CG and STM32WB30CE are available in a 48-pin UFQFPN package. 10/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Description Table 1. STM32WB50CG and STM32WB30CE device features and peripheral counts Feature STM32WB50CG STM32WB30CE 1 M bytes 512 Kbytes SRAM density 128 Kbytes 96 Kbytes SRAM1 64 Kbytes 32 Kbytes SRAM2 64 Kbytes 64 Kbytes Flash memory density BLE 5.3 802.15.4 Yes Advanced Timers 1 (16 bits) General purpose 2 (16 bits) + 1 (32 bits) Low power 2 (16 bits) SysTick 1 SPI Communication I2C interface USART(1) 1 1 RTC 1 Tamper pin 1 Wake-up pin 2 GPIOs 30 1 12-bit ADC Number of channels 13 channels (incl. 3 internal) Yes Internal Vref Max CPU frequency 64 MHz Ambient operating temperature:-10 to +85 °C Junction temperature: -10 to 105 °C Operating temperature Operating voltage 2.0 to 3.6 V Package UFQFPN48, 7 mm x 7 mm, 0.5 mm pitch, solder pad 1. USART peripheral can be used as SPI. DS13047 Rev 7 11/121 45 Description STM32WB50CG STM32WB30CE Figure 1. STM32WB50CGxx block diagram BLE / 802.15.4 RF IP LSI2 32 kHz HSE2 32 MHz 32 kB SRAM2a Backup Memory WKUP BLE 32 kB SRAM2b Memory RTC2 LSE 32 kHz I-WDG LSI1 32 kHz TAMP Cortex-M4 (DSP) CTI 802.15.4 PKA + RAM NVIC FPU RCC2 BLE IP ARBITER + ART 1 MB Flash Shared Memory JTAG/SWD Cortex-M0+ AHB asynchronous AHB Lite NVIC HSEM AHB Lite (Shared) CTI APB asynchronous RNG IPCC RCC + CSS MPU PWR HSI 1% 16 MHz PLL1 MSI up to 48 MHz Power Supply POR/ PDR/BOR/PVD/AVD DMA1 7 channels AHB Lite EXTI AES2 64 KB SRAM1 DMAMUX Memory GPIO Ports A, B, C, E, H Temp (oC) sensor CRC ADC1 12-bit ULP 2.13 Msps / 13 ch RC48 WWDG DBG SPI1 I2C1 APB LPTIM1 TIM1 LPTIM2 TIM2 USART1 SYSCFG TIM16, TIM17 MSv63012V2 12/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Description Figure 2. STM32WB30CExx block diagram AHB Lite NVIC Cortex-M0+ AHB asynchronous CTI APB asynchronous RCC2 BLE IP 802.15.4 BLE / 802.15.4 RF IP RTC2 LSE 32 kHz I-WDG LSI1 32 kHz TAMP HSEM AHB Lite (Shared) Cortex-M4 (DSP) CTI WKUP BLE PKA + RAM NVIC FPU HSE2 32 MHz 32 kB SRAM2b Arbiter + ART Shared Memory 512 KB Flash JTAG/SWD 32 KB SRAM2a Backup LSI2 32 kHz RNG IPCC RCC + CSS MPU PWR HSI 1% 16 MHz PLL1 MSI up to 48 MHz Power Supply POR/ PDR/BOR/PVD/AVD AHB Lite EXTI AES2 DMA1 7 channels DMAMUX GPIO Ports A, B, C, E, H CRC RC48 WWDG 32 KB SRAM1 DBG Temp (oC) sensor ADC1 12-bit ULP 2.13 Msps / 13 ch SPI1 I2C1 APB LPTIM1 TIM1 LPTIM2 TIM2 USART1 SYSCFG TIM16, TIM17 MS53595V1 DS13047 Rev 7 13/121 45 Functional overview STM32WB50CG STM32WB30CE 3 Functional overview 3.1 Architecture The STM32WB50CG and STM32WB30CE multiprotocol wireless device embeds a BLE or an 802.15.4 RF subsystem that interfaces with a generic microcontroller subsystem using an Arm® Cortex®-M4 CPU (called CPU1) on which the host application resides. The RF subsystem is composed of an RF analog front end, BLE or 802.15.4 digital MAC blocks as well as of a dedicated Arm® Cortex®-M0+ microcontroller (called CPU2), plus proprietary peripherals. The RF subsystem performs all of the BLE or 802.15.4 low layer stack, reducing the interaction with the CPU1 to high level exchanges. Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU (CPU1): • Flash memories • SRAM1, SRAM2a and SRAM2b (SRAM2a can be retained in Standby mode) • Security peripherals (RNG, PKA) • Clock RCC • Power control (PWR) The communication and the sharing of peripherals between the RF subsystem and the Cortex®-M4 CPU is performed through a dedicated inter processor communication controller (IPCC) and semaphore mechanism (HSEM). 3.2 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU is a processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions enabling efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm® core, the STM32WB50CG and STM32WB30CE are compatible with all Arm® tools and software. Figure 1 and Figure 2 show the general block diagram of, respectively, the STM32WB50CG and STM32WB30CE devices. 14/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview 3.3 Memories 3.3.1 Adaptive real-time memory accelerator (ART Accelerator) The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over flash memory technologies, which normally require the processor to wait for the flash memory at higher frequencies. To release the processor near 80 DMIPS performance at 64 MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from flash memory at a CPU frequency up to 64 MHz. 3.3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to eight protected areas, which can be divided up into eight subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location prohibited by the MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.3.3 Embedded flash memory The STM32WB50CG and STM32WB30CE devices feature, respectively, 1 Mbyte and 512 Kbytes of embedded flash memory available for storing programs and data, as well as some customer keys. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the flash memory cannot be read from or written to if either debug features are connected, boot in SRAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex®-M4 and Cortex®-M0+ JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. DS13047 Rev 7 15/121 45 Functional overview STM32WB50CG STM32WB30CE Table 2. Access status vs. readout protection level and execution modes Area Debug, boot from SRAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Backup registers SRAM2a SRAM2b 2 Yes (1) No 1 Yes Yes 2 Yes Yes 1 Yes Yes 2 Yes Yes No Yes Yes Yes (1) N/A N/A N/A (2) No No N/A(2) N/A N/A N/A No No No(2) N/A N/A N/A N/A N/A (2) Yes Yes 1. The option byte can be modified by the RF subsystem. 2. Erased when RDP changes from Level 1 to Level 0. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 4-Kbyte granularity. • Proprietary code readout protection (PCROP): two parts of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. Two areas can be selected, with 2-Kbyte granularity. An additional option bit (PCROP_RDP) makes possible to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. A section of the flash memory is secured for the RF subsystem CPU2, and cannot be accessed by the host CPU1. The whole non-volatile memory embeds the error correction code (ECC) feature supporting: • single error detection and correction • double error detection • the address of the ECC fail can be read in the ECC register The embedded flash memory is shared between CPU1 and CPU2 on a time sharing basis. A dedicated HW mechanism allows both CPUs to perform Write/Erase operations. 3.3.4 Embedded SRAM The STM32WB50CG device features 128 Kbytes of embedded SRAM, split in three blocks: 16/121 • SRAM1: 64 Kbytes mapped at address 0x2000 0000 • SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby mode) • SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and mirrored at 0x1000 8000 with hardware parity check DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview The STM32WB30CG device features 96 Kbytes of embedded SRAM, split in three blocks: • SRAM1: 32 Kbytes mapped at address 0x2000 0000 • SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby mode) • SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and mirrored at 0x1000 8000 with hardware parity check SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the host CPU1. The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock speeds. 3.4 Security and safety The STM32WB50CG and STM32WB30CE contain many security blocks both for the BLE or IEEE 802.15.4 and the Host application. It includes: • Customer storage of the BLE or 802.15.4 keys • Secure flash memory partition for RF subsystem-only access • Secure SRAM partition, that can be accessed only by the RF subsystem • True random number generator (RNG) • Advance encryption standard hardware accelerators (AES-256bit, supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM) • Private key acceleration (PKA) including: • – Modular arithmetic including exponentiation with maximum modulo size of 3136 bits – Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits Cyclic redundancy check calculation unit (CRC) A specific mechanism is in place to ensure that all the code executed by the RF subsystem CPU2 can be secure, whatever the Host application. 3.5 Boot modes and FW update At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options: • Boot from user flash • Boot from system memory • Boot from embedded SRAM The devices always boot on CPU1 core. The embedded bootloader code makes it possible to boot from various peripherals: • UART • I2C • SPI DS13047 Rev 7 17/121 45 Functional overview STM32WB50CG STM32WB30CE Secure Firmware update (especially BLE or 802.15.4) from system boot and over the air is provided. 3.6 RF subsystem The STM32WB50CG and STM32WB30CE embed an ultra-low power multi-standard radio Bluetooth® Low Energy (BLE) or 802.15.4 network processor, compliant with Bluetooth® specification 5.3 and IEEE® 802.15.4-2011. The BLE features 1 Mbps transfer rate, supports multiple roles simultaneously acting at the same time as BLE sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key agreement protocol, thus ensuring a secure connection. The BLE stack or 802.15.4 Low Level layer run on an embedded Arm® Cortex®-M0+ core (CPU2). The stack is stored on the embedded flash memory, which is also shared with the Arm® Cortex®-M4 (CPU1) application, making it possible in-field stack update. 3.6.1 RF front-end block diagram The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF architecture in Rx mode. Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna (single ended connection, impedance close to 50 Ω). The natural bandpass behavior of the internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band interferer rejection. In Transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean power ramp-up. In receive mode the circuit can be used in standard high performance or in reduced power consumption (user programmable). The Automatic gain control (AGC) is able to reduce the chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent linearity can be achieved. The bill of material is reduced thanks to the high degree of integration. The radio frequency source is synthesized form an external 32 MHz crystal that does not need any external trimming capacitor network thanks to a dual network of user programmable integrated capacitors. 18/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview AGC control Timer and Power control AGC RF control Interrupt Wakeup AHB BLE modulator APB BLE demodulator APB 802.15.4 modulator G BP filter ADC BLE controller ADC RF_TX_MOD_EXT_PA Figure 3. STM32WB50CG and STM32WB30CE RF front-end block diagram LNA G RF1 PLL See note PA ramp generator Adjust 802.15.4 demodulator PA Wakeup Modulator Interrupt 802.15.4 MAC Adjust Trimmed bias HSE LDO LDO VDD OSC_IN LDO Max PA level VDDRF OSC_OUT 32 MHz Note: UFQFPN48: VSS through exposed pad, and VSSRF pin must be connected to ground plane MSv63013V2 3.6.2 BLE general description The BLE block is a master/slave processor, compliant with Bluetooth specification 5.3 standard. It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a complete power-optimized stack for Bluetooth Low Energy protocol runs, providing master / slave role support • GAP: central, peripheral, observer or broadcaster roles • ATT/GATT: client and server • SM: privacy, authentication and authorization • L2CAP • Link layer: AES-128 encryption and decryption DS13047 Rev 7 19/121 45 Functional overview STM32WB50CG STM32WB30CE In addition, according to Bluetooth specification 5.3, the BLE block provides: • Multiple roles simultaneous support • Master/slave and multiple roles simultaneously • LE data packet length extension (making it possible to reach 800 kbps at application level) • LE privacy 1.2 • LE secure connections • Flexible Internet connectivity options The devices support Piconet topology (master with up to eight slaves), Scatternet topology (master with up to six slaves and dynamically as slave with up to two masters, or master with up to four slaves and dynamically as slave with up to four masters), and multi slave topology (slave with up to eight masters). The device allows the applications to meet the tight peak current requirements imposed by the use of standard coin cell batteries. Ultra-low-power sleep modes and very short transition time between operating modes result in very low average current consumption during real operating conditions, resulting in longer battery life. The BLE block integrates a full bandpass balun, thus reducing the need for external components. The link between the Cortex®-M4 application processor (CPU1) running the application, and the BLE stack running on the dedicated Cortex®-M0+ (CPU2) is performed through a normalized API, using a dedicated IPCC. 20/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE 3.6.3 Functional overview 802.15.4 general description The STM32WB50CG and STM32WB30CE embed a dedicated 802.15.4 hardware MAC: • Support for 802.15.4 release 2011 • Advanced MAC frame filtering; hardwired firewall: Programmable filters based on source/destination addresses, frame version, security enabled, frame type • 256-byte RX FIFO; Up to 8 frames capacity, additional frame information (timing, mean RSSI, LQI) • 128-byte TX FIFO with retention – 3.6.4 Content not lost, retransmissions possible under CPU2 control • Automatic frame acknowledgment, with programmable delay • Advanced channel access features – Full CSMA-CA support – Superframe timer – Beaconing support (require LSE) – Flexible TX control with programmable delay • Configuration registers with retention available down to Standby mode for software/auto-restore • Autonomous sniffer, wake-up based on timer or CPU2 request • Automatic frame transmission/reception/sleep periods, Interrupt to the CPU2 on particular events RF pin description The RF block contains dedicated pins, listed in Table 3. : Name Table 3. RF pin list Type RF1 Description RF Input/output, must be connected to the antenna through a low-pass matching network OSC_OUT I/O OSC_IN RF_TX_ MOD_EXT_PA VDDRF (1) VSSRF 32 MHz main oscillator, also used as HSE source External PA transmit control VDD Dedicated supply, must be connected to VDD VSS To be connected to GND 1. The exposed pad must be connected to GND plane for correct RF operation. 3.6.5 Typical RF application schematic The schematic in Figure 4 and the external components listed in Table 3 are purely indicative. For more details refer to the “Reference design” provided in separate documents. DS13047 Rev 7 21/121 45 Functional overview STM32WB50CG STM32WB30CE Figure 4. External components for the RF part OSC_IN X1 32 MHz OSC_OUT VDD VDDRF STM32WB microcontroller C1 Antenna VSSRF (including exposed pad) Lf1 Cf1 RF1 Cf2 Antenna filter Lf2 MS53575V1 Table 4. Typical external components Component C1 X1 Antenna filter Antenna Description Decoupling capacitance for RF 32 MHz crystal(1) Antenna filter and matching network 2.4 GHz band antenna Value 100 nF // 100 pF 32 MHz Refer to AN5165, on www.st.com - 1. e.g. NDK reference: NX2016SA 32 MHz EXS00A-CS06654. Note: For more details refer to AN5165 “Development of RF hardware using STM32WB microcontrollers” available on www.st.com. 3.7 Power supply management 3.7.1 Power supply schemes The devices have different voltage supplies (see Figure 6) and can operate within the following voltage ranges: 22/121 • VDD = 2.0 to 3.6 V: external power supply for I/Os (VDDIO), the internal regulator and system functions such as RF, reset, power management and internal clocks. It is provided externally through VDD pins. VDDRF must be always connected to VDD pins. • VDDA = 2.0 to 3.6 V: external analog power supply for ADC,. The VDDA voltage level can be independent from the VDD voltage. When not used VDDA must be connected to VDD. DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview During power up/down, the following power sequence requirements must be respected: • When VDD is below 1 V the other power supply (VDDA), must remain below VDD + 300 mV • When VDD is above 1 V all power supplies are independent. Figure 5. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDX refers to VDDA. During the power down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling capacitors to be discharged with different time constants during the power down transient phase. Note: VDD and VDDRF must be wired together, so they can follow the same voltage sequence. DS13047 Rev 7 23/121 45 Functional overview STM32WB50CG STM32WB30CE Figure 6. Power supply overview Level shifter Interruptible domain (VDD12I) IOs (CPU1, CPU2, peripherals, SRAM1, SRAM2b) IO logic On domain (VDD12O) SysConfig, EXTI, RCC, PwrCtrl, LPTIM Power switch Power switch VSS VSS VDD VSS MR RFR LPR VDDRF RF domain Backup domain VBKP12 Radio SRAM2a Power switch VSSRF VSS VSS (including exposed pad) Wakeup domain (VDDIO) VDD HSI, HSE, PLL, LSI1, LSI2, IWDG, RF Power switch VSW VBAT VSS Switch domain (VSW) VBAT IOs IO logic LSE, RTC, backup registers VSS VSS Analog domain VDDA ADC VREF+ = = VREFVSS MS53186V2 24/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE 3.7.2 Functional overview Linear voltage regulator Three embedded linear voltage regulators supply most of the digital and RF circuitries, the main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the SRAM2a in Standby with retention. • The RFR is used to supply the RF analog part, its activity is automatically managed by the RF subsystem. All the regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down, inducing zero consumption. VCORE can also be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. In this case the CPU is running at up to 2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the RF subsystem is not available). 3.7.3 Power supply supervisor An integrated ultra-low-power brown-out reset (BOR) is active in all modes except Shutdown ensuring proper operation after power-on and during power down. The devices remain in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 2.0 V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it with the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.7.4 Low-power modes These ultra-low-power devices support several low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wake-up sources. By default, the microcontroller is in Run mode, after a system or a power on reset. It is up to the user to select one of the low-power modes described below: • Sleep In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem, continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator operating current. The code can be executed from SRAM or from the flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. The RF subsystem is not available in this mode and must be OFF. • Low-power sleep This mode is entered from the low-power run mode. Only the CPU1 clock is stopped. When wake-up is triggered by an event or an interrupt, the system reverts to the DS13047 Rev 7 25/121 45 Functional overview STM32WB50CG STM32WB30CE low-power run mode. The RF subsystem is not available in this mode and must be OFF. • Stop 0, Stop 1 and Stop 2 Stop modes achieve the lowest power consumption while retaining the content of all the SRAM and registers. The LSE (or LSI) is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wake-up capability can enable the HSI16 RC during Stop modes to detect their wake-up condition. Three modes are available: Stop 0, Stop 1 and Stop 2. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wake-up sources, a smaller wake-up time but a higher consumption than Stop 2. In Stop 0 mode the main regulator remains ON, allowing a very fast wake-up time but with higher consumption. In these modes the RF subsystem can wait for incoming events in all Stop modes. The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem is used the exits must be set to HSI16 only. • Standby The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The RTC can remain active (Standby mode with RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1, SRAM2b and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be retained in Standby mode, supplied by the low-power regulator (Standby with 32 KB SRAM2a retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wake-up, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or from the RF system wake-up). The system clock after wake-up is 16 MHz, derived from the HSI16. In this mode the RF can be used. 26/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE • Functional overview Shutdown This mode achieves the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wake-up, timestamp, tamper). The system clock after wake-up is 4 MHz, derived from the MSI. In this mode the RF is no longer operational. When the RF subsystem is active, it changes the power state according to its needs (Run, Stop, Standby). This operation is transparent for the CPU1 host application and managed by a dedicated HW state machine. At any given time the effective power state reached is the higher one needed by both the CPU1 and RF sub-system. Table 5 summarizes the peripheral features over all available modes. Wake-up capability is detailed in gray cells. Table 5. Features over all modes(1) Wake-up capability - Wake-up capability - CPU1 Y - Y - - - - - - - - - - CPU2 Y - Y - - - - - - - - - - Radio system (BLE, 802.15.4) Y Y - - Y Y Y Y Y(2) Y(2) Y(3) Y O(4) O(4) R - R - R - R - R Y Y(5) Y Y(5) R - R - - - - - - SRAM2a Y (5) Y Y Y(5) R - R - R(6) - - - - SRAM2b Y Y(5) Y Y(5) R - R - - - - - - Backup registers Y Y Y Y R - R - R - R - R Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable voltage detector (PVD) O O O O O O O O - - - - - DMA1 O O O O - - - - - - - - - High speed internal (HSI16) O O O O O(7) - O(7) - - - - - - Flash memory SRAM1 - DS13047 Rev 7 VBAT Wake-up capability - Peripheral Wake-up capability Low-power sleep Shutdown Low-power run Standby Sleep Stop 2 Run Stop0/Stop1 27/121 45 Functional overview STM32WB50CG STM32WB30CE Table 5. Features over all modes(1) (continued) Wake-up capability - Wake-up capability - O O - - - - - - - - - - - O O O O - - - - - - - - - O O O O O - O - O - - - - O O O O O - O - O - O - O 48 O 48 O - - - - - - - - - 344 O - - - - - - - - - - - Clock security system (CSS) O O O O O O(10) O O(10) - - - - - Clock security system on LSE O O O O O O O O O O - - - RTC / Auto wake-up O O O O O O O O O O O O O Number of RTC tamper pins 1 1 1 1 1 O 1 O 1 O 1 O 1 O O (11) O(11) - - - - - - - O(12) - - - - - - - Oscillator HSI48 High speed external (HSE) (8) Low speed internal (LSI1 or LSI2) Low speed external (LSE) Multi speed internal (MSI)(9) PLL VCO maximum frequency USART1 O O O - VBAT Wake-up capability - Peripheral Wake-up capability Low-power sleep Shutdown Low-power run Standby Sleep Stop 2 Run Stop0/Stop1 I2C1 O O O O O(12) SPI1 O O O O - - - - - - - - - ADC1 O O O O - - - - - - - - - Temperature sensor O O O O - - - - - - - - - Timers TIMx (x=1, 2, 16, 17) O O O O - - - - - - - - - Low-power Timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power Timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - True random number generator (RNG) O O - - - - - - - - - - - AES2 hardware accelerator O O O O - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - IPCC O - O - - - - - - - - - - HSEM O - O - - - - - - - - - - 28/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview Table 5. Features over all modes(1) (continued) Wake-up capability - Wake-up capability - PKA O O O O - - - - - - - - - GPIOs O O O O O O O O (13) 5 pins (14) 5 pins - - VBAT Wake-up capability - Peripheral Wake-up capability Low-power sleep Shutdown Low-power run Standby Sleep Stop 2 Run Stop0/Stop1 1. Legend: Y = Yes (enabled), O = Optional (disabled by default, can be enabled by software), R = Data retained, - = Not available. 2. Standby with SRAM2a Retention mode only. 3. Flash memory programming only possible in Run, not in Low Power Run. 4. The Flash memory can be configured in Power-down mode. By default, it is not in Power-down Run. 5. The SRAM clock can be gated on or off. 6. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register. 7. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 8. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx). 9. MSI maximum frequency. 10. In case RF will be used and HSE will fail. 11. UART reception is functional in Stop mode, and generates a wake-up interrupt on Start, address match or received frame event. 12. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match. 13. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. DS13047 Rev 7 29/121 45 DS13047 Rev 7 Regulator CPU1 Flash SRAM Clocks DMA and peripherals Wake-up source Consumption(1) Wake-up time Run MR Yes ON(2) ON Any All N/A 107 µA/MHz N/A LPRun LPR Yes ON(2) ON Any except PLL All except RF, RNG N/A 103 µA/MHz 15.33 µs Sleep MR No ON(2) ON(3) Any All Any interrupt or event 41 µA/MHz 9 cycles LPSleep LPR No ON(2) ON(3) Any except PLL All except RF, RNG Any interrupt or event 45 µA/MHz 9 cycles LSE, LSI, HSE(4), HSI16(5) RF, BOR, PVD RTC, IWDG USART1(6) I2C1(7) LPTIMx (x=1, 2) All other peripherals are frozen. Reset pin, all I/Os, RF, BOR, PVD RTC, IWDG USART1 I2C1 LPTIMx (x=1, 2) 105 µA 1.7 µs ON LSE, LSI, HSE(4), HSI16(5) RF, BOR, PVD RTC, IWDG USART1(6) I2C1(7) LPTIMx (x=1, 2) All other peripherals are frozen. Reset pin, all I/Os RF, BOR, PVD RTC, IWDG USART1 I2C1 LPTIMx (x=1, 2) 9.25 µA w/o RTC 9.45 µA w RTC 4.7 µs ON LSE, LSI RF, BOR, PVD RTC, IWDG LPTIM1 All other peripherals are frozen. Reset pin, all I/Os RF, BOR, PVD RTC, IWDG LPTIM1 1.85 µA w/o RTC 2.25 µA w RTC 5.71 µs Stop 0 Stop 1 Stop 2 MR LPR LPR No No No OFF OFF OFF ON STM32WB50CG STM32WB30CE Mode Functional overview 30/121 Table 6. STM32WB50CG and STM32WB30CE modes overview Mode Regulator CPU1 Flash SRAM2a ON(8) LPR Standby No OFF OFF Shutdown OFF SRAM OFF No OFF OFF Clocks DMA and peripherals Wake-up source LSE, LSI RF, BOR, RTC, IWDG All other peripherals are powered off. I/O configuration can be floating, pull-up or pull-down RF, Reset pin 2 I/Os (WKUPx)(9) BOR, RTC, IWDG LSE RTC All other peripherals are powered off. I/O configuration can be floating, pull-up or pull-down(10) 2 I/Os (WKUPx)(9), RTC Consumption(1) Wake-up time 0.32 µA w/o RTC 0.60 µA w RTC 0.11 µA w/o RTC 0.39 µA w RTC 0.028 µA w/o RTC 0.315 µA w/ RTC 51 µs - STM32WB50CG STM32WB30CE Table 6. STM32WB50CG and STM32WB30CE modes overview (continued) 1. Typical current at VDD = 2.4 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C. 2. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM. DS13047 Rev 7 3. The SRAM1 and SRAM2 clocks can be gated off independently. 4. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem. 5. HSI16 (16 MHz) automatically used by some peripherals. 6. U(S)ART reception is functional in Stop mode, and generates a wake-up interrupt on Start, Address match or Received frame event. 7. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match. 8. SRAM1 and SRAM2b are OFF. 9. The I/Os with wake-up from Standby/Shutdown capability are: PA0, PA2. 10. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode. Functional overview 31/121 Functional overview 3.7.5 STM32WB50CG STM32WB30CE Reset mode To improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.8 VBAT operation The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers) from an external battery, an external supercapacitor, or from VDD when no external battery nor an external supercapacitor are present. One anti-tamper detection pin is available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.9 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU1 resources and, consequently, reducing power supply consumption. In addition, these hardware connections result in fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and Sleep, Stop 0, Stop 1 and Stop 2 modes. 32/121 Stop 2 All clock sources (internal and external) Stop 0 / Stop 1 RTC Low-power ADC Low-power run TIMx Sleep Source Run Table 7. STM32WB50CG and STM32WB30CE CPU1 peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADC1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - TIM1 Timer triggered by analog watchdog Y Y Y Y - - TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tamper Y Y Y Y Y Y(1) TIM2 TIM16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - Destination Action DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview GPIO LPTIMERx ADC1 Stop 2 TIMx Stop 0 / Stop 1 TIM1 TIM16,17 Low-power CSS CPU (hard fault) SRAM (parity error) Flash memory (ECC error) PVD Low-power run Destination Sleep Source Run Table 7. STM32WB50CG and STM32WB30CE CPU1 peripherals interconnect matrix (continued) Timer break Y Y Y Y - - External trigger Y Y Y Y - (1) Action External trigger Y Y Y Y Y Conversion external trigger Y Y Y Y - Y - 1. LPTIM1 only. DS13047 Rev 7 33/121 45 Functional overview 3.10 STM32WB50CG STM32WB30CE Clocks and startup The STM32WB50CG and STM32WB30CE devices integrate several clock sources: • LSE: 32.768 kHz external oscillator, for accurate RTC and calibration with other embedded RC oscillators • LSI1: 32 kHz on-chip low-consumption RC oscillator • LSI2: almost 32 kHz, on-chip high-stability RC oscillator, can be used by the RF subsystem instead of LSE • HSE: high quality 32 MHz external oscillator with trimming, needed by the RF subsystem • HSI16: 16 MHz high accuracy on-chip RC oscillator • MSI: 100 kHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed using the LSE signal • HSI48: 48 MHz on-chip RC oscillator The clock controller (see Figure 7) distributes the clocks coming from the different oscillators to the core and the peripherals including the RF subsystem. It also manages clock gating for low power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: • 34/121 – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL. – System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of 64 MHz. Auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5%. The LSI source can be either the LSI1 or the LSI2 on-chip oscillator. • Peripheral clock sources: Several peripherals (RNG, USARTs, I2C, LPTimers, ADC) have their own independent clock whatever the system clock. A PLL having three independent outputs for the highest flexibility can generate independent clocks for the ADC and the RNG. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If an HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software interrupt is generated if enabled. LSE failure can also be detected and an interrupt generated. • Clock-out capability: – MCO (microcontroller clock output): it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSIx, LSE) are available down to Stop 1 low power state. – LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes down to Standby. Several prescalers allow the user to configure the AHB frequencies, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 64 MHz. DS13047 Rev 7 35/121 45 Functional overview STM32WB50CG STM32WB30CE Figure 7. Clock tree LSI1 RC 32 kHz to IWDG LSI LSI2 RC 32 kHz LSI LSCO to RTC LSE OSC32_OUT LSE OSC 32.768 kHz to BLE wakeup LSE OSC32_IN to 802.15.4 wakeup LSE CSS LSI1 /32 CPU1 HPRE /1,2,...,512 LSI2 /32 LSE to CPU1 FCLK HSE MCO to CPU1, AHB1, AHB2, and SRAM1 HCLK1 to CPU1 system timer /8 SYSCLK /1 - 16 PLLRCLK SYS clock source control HSI16 APB1 PPRE1 /1,2,4,8,16 PCLK1 APB2 PPRE2 /1,2,4,8,16 PCLK2 MSI PLLRCLK RC48 OSC_OUT OSC_IN HSI16 HSE OSC 32 MHz SYSCLK HSE HSEPRE/1,2 CPU2 C2HPRE 1,2,...,512 MSI HSE CSS to APB1 to APB1 TIMx to APB2 to APB2 TIMx to CPU2 to CPU2 FCLK /8 HSI48 RC 48 MHz x1 or x2 HCLK2 HSI16 RC 16 MHz MSI RC 100 kHz - 48 MHz x1 or x2 AHB4 SHDHPRE /1,2,...,512 to CPU2 system timer to AHB4, Flash memory, SRAM2 HCLK4 to APB3 HSI16 MSI HSE HSI16 /M to AHB5 HCLK5 /2 to RF PLL xN MSI /P /Q PLLPCLK HSI48 /3 PLLQCLK to RNG LSI /R PLLRCLK PCLKn LSE SYSCLK to USART1 HSI16 LSE PCLKn PCLKn to ADC SYSCLK SYSCLK HSI16 HSI16 to I2Cx to LPTIMx LSI LSE MSv63019V5 3.11 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked, if needed, following a specific sequence in order to avoid spurious writing to the I/Os registers. 36/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE 3.12 Functional overview Direct memory access controller (DMA) The device embeds one DMA. Refer to Table 8 for the features implementation. Direct memory access (DMA) is used to provide high-speed data transfer between peripherals and memory as well as between memories. Data can be quickly moved by DMA without any CPU action. This keeps CPU resources free for other operations. The DMA controller has seven channels in total, a full cross matrix allows any peripheral to be mapped on any of the available DMA channels. The DMA has an arbiter for handling the priority between DMA requests. The DMA supports: • seven independently configurable channels (requests) • A full cross matrix between peripherals and all the DMA channels exist. There is also a HW trigger possibility through the DMAMUX. • Priorities between requests from DMA channels are software programmable (four levels consisting in very high, high, medium and low) or hardware in case of equality (request 1 has priority over request 2, etc.). • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management. • Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically OR-ed together in a single interrupt request for each channel. • Memory-to-memory transfer. • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers. • Access to flash memory, SRAM, APB and AHB peripherals as source and destination. • Programmable number of data to be transferred: up to 65536. Table 8. DMA implementation DMA features DMA1 Number of regular channels 7 A DMAMUX block makes it possible to route any peripheral source to any DMA channel. 3.13 Interrupts and events 3.13.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU. DS13047 Rev 7 37/121 45 Functional overview STM32WB50CG STM32WB30CE The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.13.2 Extended interrupts and events controller (EXTI) The EXTI manages wake-up through configurable and direct event inputs. It provides wake-up requests to the Power control, and generates interrupt requests to the CPUx NVIC and events to the CPUx event input. Configurable events/interrupts come from peripherals able to generate a pulse, and make it possible to select the Event/Interrupt trigger edge and/or a SW trigger. Direct events/interrupts are coming from peripherals having their own clearing mechanism. 3.14 Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • Up to 16-bit resolution with 256 oversampling ratio • 2.13 Msps maximum conversion rate with full resolution Down to 78 ns sampling time – Increased conversion rate for lower resolution (up to 3.55 Msps for 6-bit resolution) • Up to ten external channels and three internal channels: internal reference voltages, temperature sensor • Single-ended and differential mode inputs • Low-power design • 38/121 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: two groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – The ADC supports multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into three data register or in SRAM with DMA controller support DS13047 Rev 7 STM32WB50CG STM32WB30CE 3.14.1 Functional overview – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 input channel, which is used to convert the sensor output voltage into a digital value. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored in the system memory area, accessible in read-only mode. Table 9. Temperature sensor calibration values 3.14.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 10. Internal voltage reference calibration values Calibration value name VREFINT 3.15 Description Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = 3.6 V (± 10 mV) Memory address 0x1FFF 75AA - 0x1FFF 75AB True random number generator (RNG) The devices embed a true RNG that delivers 32-bit random numbers generated by an integrated analog circuit. DS13047 Rev 7 39/121 45 Functional overview 3.16 STM32WB50CG STM32WB30CE Timers and watchdogs The STM32WB50CG and STM32WB30CE include one advanced 16-bit timer, one generalpurpose 32-bit timer, two 16-bit basic timers, two low-power timers, two watchdog timers and a SysTick timer. Table 11 compares the features of the advanced control, general purpose and basic timers. Table 11. Timer features Capture/ compare channels Complementary outputs Up, down, Up/down 4 3 32-bits Up, down, Up/down 4 No TIM16 16-bits Up 2 1 General purpose TIM17 16-bits Up 2 1 Low power LPTIM1 LPTIM2 16-bits Up 1 1 Timer type Timer Counter resolution Counter type Advanced control TIM1 16-bits General purpose TIM2 General purpose 3.16.1 Prescaler factor Any integer between 1 and 65536 DMA request generation Yes Advanced-control timer (TIM1) The advanced-control timer can be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The four independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0 to 100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.16.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 3.16.2 General-purpose timers (TIM2, TIM16, TIM17) There are up to three synchronizable general-purpose timers embedded in the STM32WB50CG and STM32WB30CE (see Table 11 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2 – 40/121 Full-featured general-purpose timer DS13047 Rev 7 STM32WB50CG STM32WB30CE • 3.16.3 Functional overview – Features four independent channels for input capture/output compare, PWM or one-pulse mode output. Can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. – The counter can be frozen in debug mode. – Independent DMA request generation, support of quadrature encoders. TIM16 and TIM17 – General-purpose timers with mid-range features: – 16-bit auto-reload upcounters and 16-bit prescalers. – 1 channel and 1 complementary channel. – All channels can be used for input capture/output compare, PWM or one-pulse mode output. – The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. – The counters can be frozen in debug mode. Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers, having an independent clock running in Stop mode if they are clocked by LSE, LSIx or by an external clock. They are able to wake-up the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 modes. The low-power timers support the following features: 3.16.4 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application) • Programmable digital glitch filter • Encoder mode (LPTIM1 only) Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. DS13047 Rev 7 41/121 45 Functional overview 3.16.5 STM32WB50CG STM32WB30CE System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.16.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.17 • a 24-bit down counter • autoreload capability • a maskable system interrupt generation when the counter reaches 0 • a programmable clock source. Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter, supporting the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • One anti-tamper detection pin with programmable filter. • Timestamp feature, which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable resolution and period. The RTC and the 20 backup registers are supplied through a switch that takes power either from the VDD supply (when present) or from the VBAT pin. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: 42/121 • a 32.768 kHz external crystal (LSE) • an external resonator or oscillator (LSE) • one of the internal low power RC oscillators (LSI1 or LSI2, with typical frequency of 32 kHz) • the high-speed external clock (HSE) divided by 32. DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (alarm, wake-up timer, timestamp or tamper) can generate an interrupt and wake-up the device from the low-power modes. 3.18 Inter-integrated circuit interface (I2C) The devices embed one I2C. Refer to Table 12 for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBus™) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 7: Clock tree. • Wake-up from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 12. I2C implementation I2C features(1) I2C1 Standard-mode (up to 100 kbit/s) X Fast-mode (up to 400 kbit/s) X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X Programmable analog and digital noise filters X SMBus/PMBus hardware support X DS13047 Rev 7 43/121 45 Functional overview STM32WB50CG STM32WB30CE Table 12. I2C implementation (continued) I2C features(1) I2C1 Independent clock X Wake-up from Stop 0 / Stop 1 mode on address match X Wake-up from Stop 2 mode on address match - 1. X: supported. 3.19 Universal synchronous/asynchronous receiver transmitter (USART) The devices embed one universal synchronous receiver transmitter. This interface provides asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and has LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals, and RS485 driver enable. The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. The USART supports synchronous operation (SPI mode), and can be used as an SPI master. The USART has a clock domain independent from the CPU clock, allowing it to wake up the MCU from Stop mode using baudrates up to 200 kbaud. The wake up events from Stop mode are programmable and can be: • the start bit detection • any received data frame • a specific programmed data frame. The USART interface can be served by the DMA controller. 3.20 Serial peripheral interface (SPI1) The SPI interface enables communication up to 32 Mbit/s in master and up to 24 Mbit/s in slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interface supports NSS pulse mode, TI mode and Hardware CRC calculation. The SPI interface can be served by the DMA controller. 3.21 Development support 3.21.1 Serial wire JTAG debug port (SWJ-DP) The embedded Arm® SWJ-DP interface is a combined JTAG and serial wire debug port that enables either a serial wire debug, or a JTAG probe to be connected to the target. 44/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Functional overview Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DS13047 Rev 7 45/121 45 Pinouts and pin description 4 STM32WB50CG STM32WB30CE Pinouts and pin description VDD PB7 PB6 PB5 PB4 PB3 PA15 PA14 VDD PA13 PA12 PA11 48 47 46 45 44 43 42 41 40 39 38 37 Figure 8. STM32WB50CG and STM32WB30CE UFQFPN48 pinout(1)(2) VBAT 1 36 PA10 PC14-OSC32_IN 2 35 VDD PC15-OSC32_OUT 3 34 VDD PH3-BOOT0 4 33 VDD PB8 5 32 VSS PB9 6 31 VDD NRST 7 30 PE4 VDDA 8 29 PB1 PA0 9 28 PB0 PA1 10 27 AT1 PA2 11 26 AT0 PA3 12 25 OSC_IN 13 14 15 16 17 18 19 20 21 22 23 24 PA4 PA5 PA6 PA7 PA8 PA9 PB2 VDD RF1 VSSRF VDDRF OSC_OUT UFQFPN48 MSv63017V2 1. The above figure shows the package top view. 2. The exposed pad must be connected to ground plane. Table 13. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin Pin type I/O structure Definition I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RF RF I/O RST Bidirectional reset pin with weak pull-up resistor Option for TT or FT I/Os Notes _f (1) I/O, Fm+ capable _a (2) I/O, with Analog switch function supplied by VDDA Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 14 are: FT_f, FT_fa. 46/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Pinouts and pin description 2. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a. Pin type I/O structures Notes Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions Alternate functions S - - - FT (1)(2) CM4_EVENTOUT OSC32_IN CM4_EVENTOUT OSC32_OUT Number Pin (UFQFPN48) Name (function after reset) 1 VBAT 2 PC14-OSC32_IN I/O Additional functions - 3 PC15-OSC32_OUT I/O FT (1)(2) 4 PH3-BOOT0 I/O FT - CM4_EVENTOUT, LSCO(3) - 5 PB8 I/O FT_f - TIM1_CH2N, I2C1_SCL, TIM16_CH1, CM4_EVENTOUT - 6 PB9 I/O FT_fa - TIM1_CH3N, I2C1_SDA, IR_OUT, TIM17_CH1, CM4_EVENTOUT - 7 NRST I/O RST - - - - - 8 VDDA S - (4) 9 PA0 I/O FT_a - TIM2_CH1, TIM2_ETR, CM4_EVENTOUT ADC1_IN5, RTC_TAMP2/WKUP1 10 PA1 I/O FT_a - TIM2_CH2, I2C1_SMBA, SPI1_SCK, CM4_EVENTOUT ADC1_IN6 11 PA2 I/O FT_a - LSCO(3), TIM2_CH3, CM4_EVENTOUT ADC1_IN7, WKUP4 12 PA3 I/O FT_a - TIM2_CH4, CM4_EVENTOUT ADC1_IN8 13 PA4 I/O FT_a - SPI1_NSS, LPTIM2_OUT, CM4_EVENTOUT ADC1_IN9 14 PA5 I/O FT_a - TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, CM4_EVENTOUT ADC1_IN10 15 PA6 I/O FT_a - TIM1_BKIN, SPI1_MISO, TIM16_CH1, CM4_EVENTOUT ADC1_IN11 16 PA7 I/O FT_fa - TIM1_CH1N, SPI1_MOSI, TIM17_CH1, CM4_EVENTOUT ADC1_IN12 17 PA8 I/O FT_a - MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT, CM4_EVENTOUT ADC1_IN15 18 PA9 I/O FT_fa - TIM1_CH2, I2C1_SCL, USART1_TX, CM4_EVENTOUT ADC1_IN16 19 PB2 I/O FT_a - RTC_OUT, LPTIM1_OUT, SPI1_NSS, CM4_EVENTOUT - 20 VDD S - - - - - - 21 RF1 I/O RF (5) 22 VSSRF S - - - - 23 VDDRF S - - - - DS13047 Rev 7 47/121 52 Pinouts and pin description STM32WB50CG STM32WB30CE Pin type I/O structures Notes Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions (continued) Alternate functions O RF (6) - - RF (6) - - - - - - Number Pin (UFQFPN48) Name (function after reset) 24 OSC_OUT 25 OSC_IN I Additional functions 26 AT0 O RF (7) 27 AT1 O RF (7) 28 PB0 I/O TT (8) CM4_EVENTOUT, RF_TX_MOD_EXT_PA - 29 PB1 I/O TT (8) LPTIM2_IN1, CM4_EVENTOUT - 30 PE4 I/O FT - CM4_EVENTOUT - 31 VDD S - - - - 32 VSS S - - - - 33 VDD S - - - - 34 VDD S - - - - 35 VDD S - - - - 36 PA10 I/O FT_f - TIM1_CH3, I2C1_SDA, USART1_RX, TIM17_BKIN, CM4_EVENTOUT - 37 PA11 I/O FT - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, CM4_EVENTOUT - 38 PA12 I/O FT - TIM1_ETR, SPI1_MOSI, USART1_RTS, CM4_EVENTOUT - 39 PA13(JTMS_SWDIO) I/O FT (9) JTMS-SWDIO, IR_OUT, CM4_EVENTOUT - - - 40 VDD S - - 41 PA14 (JTCK_SWCLK) I/O FT (9) JTCK-SWCLK, LPTIM1_OUT, I2C1_SMBA, CM4_EVENTOUT - 42 PA15 (JTDI) I/O FT (9) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS, CM4_EVENTOUT, MCO - 43 PB3 (JTDO) I/O FT_a - JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, USART1_RTS, CM4_EVENTOUT - 44 PB4 (NJTRST) I/O FT_a (9) NJTRST, SPI1_MISO, USART1_CTS, TIM17_BKIN, CM4_EVENTOUT - 45 PB5 I/O FT - LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, TIM16_BKIN, CM4_EVENTOUT - 46 PB6 I/O FT_fa - LPTIM1_ETR, I2C1_SCL, USART1_TX, TIM16_CH1N, MCO, CM4_EVENTOUT - 48/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Pinouts and pin description 47 PB7 48 VDD I/O FT_fa S - Notes Name (function after reset) Pin type Number Pin (UFQFPN48) I/O structures Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions (continued) - Alternate functions LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, TIM17_CH1N, CM4_EVENTOUT - - Additional functions PVD_IN - 1. PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the use of the PC14 and PC15 GPIOs in output mode is limited: - the speed must not exceed 2 MHz with a maximum load of 30 pF - these GPIOs must not be used as current sources (e.g. to drive an LED). 2. After a Backup domain power-up, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the reference manual RM0471, available on www.st.com. 3. The clock on LSCO is available in Run, Stop, and on PA2 in Standby and Shutdown modes. 4. On UFQFPN48 VDDA is connected to VREF+. 5. RF pin, use the nominal PCB layout. 6. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165). 7. Reserved for production, must be kept unconnected. 8. High frequency (above 32 KHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0 and 1) during RF operation. 9. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and PB4 pins and the internal pull-down on PA14 pin are activated. DS13047 Rev 7 49/121 52 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF12 AF11 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 TIM1 I2C1 SPI1 RF USART1 IR TIM1 - TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PA0 - TIM2_CH1 - - - - - - - - - TIM2_ETR CM4_ EVENTOUT PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK - - - - - - CM4_ EVENTOUT PA2 LSCO TIM2_CH3 - - - - - - - - - - CM4_ EVENTOUT PA3 - TIM2_CH4 - - - - - - - - - - CM4_ EVENTOUT PA4 - - - - - SPI1_NSS - - - - - LPTIM2_OUT CM4_ EVENTOUT PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - - - - - LPTIM2_ETR CM4_ EVENTOUT PA6 - TIM1_BKIN - - - SPI1_MISO - - - TIM1_BKIN - TIM16_CH1 CM4_ EVENTOUT PA7 - TIM1_CH1N - - - SPI1_MOSI - - - - - TIM17_CH1 CM4_ EVENTOUT PA8 MCO TIM1_CH1 - - - - - USART1_CK - - - LPTIM2_OUT CM4_ EVENTOUT PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX - - - - CM4_ EVENTOUT PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX - - - TIM17_BKIN CM4_ EVENTOUT PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS - TIM1_BKIN2 - - CM4_ EVENTOUT PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS - - - - CM4_ EVENTOUT PA13 JTMSSWDIO - - - - - - - IR_OUT - - - CM4_ EVENTOUT PA14 JTCKSWCLK LPTIM1_OUT - - I2C1_SMBA - - - - - - - CM4_ EVENTOUT PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS MCO - - - - - CM4_ EVENTOUT Port DS13047 Rev 7 A STM32WB50CG STM32WB30CE AF0 Pinouts and pin description 50/121 Table 15. Alternate functions AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF12 AF11 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 TIM1 I2C1 SPI1 RF USART1 IR TIM1 - TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PB0 - - - - - - RF_TX_ MOD_EXT_PA - - - - - CM4_ EVENTOUT PB1 - - - - - - - - - - - LPTIM2_IN1 CM4_ EVENTOUT PB2 RTC_ OUT LPTIM1_OUT - - - SPI1_NSS - - - - - - CM4_ EVENTOUT PB3 JTDOTRACE SWO TIM2_CH2 - - - SPI1_SCK - USART1_RTS - - - - CM4_ EVENTOUT PB4 NJTRST - - - - SPI1_MISO - USART1_CTS - - - TIM17_BKIN CM4_ EVENTOUT PB5 - LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI - USART1_CK - - - TIM16_BKIN CM4_ EVENTOUT PB6 MCO LPTIM1_ETR - - I2C1_SCL - - USART1_TX - - - TIM16_CH1N CM4_ EVENTOUT PB7 - LPTIM1_IN2 - TIM1_BKIN I2C1_SDA - - USART1_RX - - - TIM17_CH1N CM4_ EVENTOUT PB8 - TIM1_CH2N - - I2C1_SCL - - - - - - TIM16_CH1 CM4_ EVENTOUT PB9 - TIM1_CH3N - - I2C1_SDA - - - IR_OUT - - TIM17_CH1 CM4_ EVENTOUT PC14 - - - - - - - - - - - - CM4_ EVENTOUT PC15 - - - - - - - - - - - - CM4_ EVENTOUT E PE4 - - - - - - - - - - - - CM4_ EVENTOUT H PH3 LSCO - - - - - - - - - - - CM4_ EVENTOUT Port DS13047 Rev 7 B C 51/121 Pinouts and pin description AF0 STM32WB50CG STM32WB30CE Table 15. Alternate functions (continued) Memory mapping 5 STM32WB50CG STM32WB30CE Memory mapping The STM32WB50CG and STM32WB30CE devices feature a single physical address space that can be accessed by the application processor and by the RF subsystem. A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure, exclusively accessible by the CPU2, protected against execution, read and write from CPU1 and DMA. In case of shared resources the SW should implement arbitration mechanism to avoid access conflicts. This happens for peripherals Reset and clock controller (RCC), Power controller (PWC), EXTI and Flash interface, and can be implemented using the built-in semaphore block (HSEM). By default the RF subsystem and CPU2 operate in secure mode. This implies that part of the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by the CPU2. In this case the Host processor (CPU1) has no access to these resources. The detailed memory map and the peripheral mapping of the devices can be found in the reference manual RM0471. 52/121 DS13047 Rev 7 STM32WB50CG STM32WB30CE Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on VDD = VDDA = VDDRF = 3 V, TA = 25 °C. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 DS13047 Rev 7 MS19211V1 53/121 110 Electrical characteristics 6.1.6 STM32WB50CG STM32WB30CE Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (LSE, RTC and backup registers) 1.55 V to 3.6 V Power switch VDD VCORE n x VDD Regulator VDDIO1 Level shifter OUT GPIOs n x 100 nF + 1 x 4.7 μF IN IO logic Kernel logic (CPU, digital and memories VSS VDDA VDDA VREF+ 10 nF + 1 μF VREF- ADC VSS VDDRF 100 nF + 100 pF Radio VSSRF Exposed pad VSS To all modules MS53513V2 Caution: 54/121 Each power supply pair (such as VDD / VSS, VDDA / VSS) must be decoupled with filtering ceramic capacitors as shown in Figure 11. These capacitors must be placed as close as possible to (or below) the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS13047 Rev 7 STM32WB50CG STM32WB30CE 6.1.7 Electrical characteristics Current consumption measurement Figure 12. Current consumption measurement scheme IDDRF VDDRF IDDVBAT VBAT IDD VDD IDDA VDDA MSv63021V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 16, Table 17 and Table 18 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 16. Voltage characteristics(1) Symbol VDDX - VSS Ratings External main supply voltage (including VDD, VDDA, VDDRF, VBAT) Min Max -0.3 4.0 min (VDD, VDDA, VDDRF) + 4.0(3)(4) Input voltage on FT_xxx pins VIN(2) Input voltage on TT_xx pins Unit VSS-0.3 Input voltage on any other pin V 4.0 4.0 |∆VDDx| Variations between different VDDX power pins of the same domain - 50 |VSSx-VSS| Variations between all the different ground pins - 50 mV 1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 17 for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. DS13047 Rev 7 55/121 110 Electrical characteristics STM32WB50CG STM32WB30CE Table 17. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) 130 ∑IVSS (sink)(1) 130 Total current out of sum of all VSS ground lines IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100 IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100 Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 IIO(PIN) ∑IIO(PIN) IINJ(PIN)(3) ∑|IINJ(PIN)| Total output current sunk by sum of all I/Os and control pins(2) Total output current sourced by sum of all I/Os and control pins Unit mA 100 (2) 100 Injected current on FT_xxx, TT_xx, RST and B pins, except PB0 and PB1 –5 / +0(4) Injected current on PB0 and PB1 -5/0 Total injected current (sum of all I/Os and control pins)(5) 25 1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count packages. 3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 16 for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). Table 18. Thermal characteristics Symbol TSTG TJ 56/121 Ratings Storage temperature range Maximum junction temperature DS13047 Rev 7 Value –65 to +150 110 Unit °C STM32WB50CG STM32WB30CE Electrical characteristics 6.3 Operating conditions 6.3.1 Summary of main performance Table 19. Main performance at VDD = 3.3 V Parameter Test conditions Typ VBAT (VBAT = 1.8 V, VDD = 0 V) 0.002 Shutdown (VDD = 2.0 V) 0.014 Standby (VDD = 2.0 V, 32 KB RAM retention) 0.35 Stop2 1.85 Sleep (16 MHz) 845 LP run (2 MHz) 320 Run (64 MHz) 8150 Core current ICORE consumption Radio RX IPERI Peripheral current consumption (1) 7900 Radio TX 0 dBm output power(1) 8800 Advertising with Stop2(2) (Tx = 0 dBm; Period 1.28 s; 31 bytes, 3 channels) 20 Advertising with Stop2(2) (Tx = 0 dBm, 6 bytes; period 10.24 s, 3 channels) 4 LP timers - 6 RTC - 2.5 BLE Unit µA 1. Power consumption including RF subsystem and digital processing. 2. Power consumption averaged over 100 s including Cortex M4, RF subsystem, digital processing and Cortex M0+. 6.3.2 General operating conditions Table 20. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 64 fPCLK1 Internal APB1 clock frequency - 0 64 fPCLK2 Internal APB2 clock frequency - 0 64 - 2.0(1) 3.6 VDD Standard operating voltage VDDA Analog supply voltage VBAT Backup operating voltage - 1.55 3.6 Minimum RF voltage - 2.0 3.6 –0.3 VDD + 0.3 –0.3 min (min (VDD, VDDA) + 3.6 V, 5.5 V)(3)(4) VDDRF ADC used 2.0 ADC not used(2) 2.0 TT_xx I/O VIN I/O input voltage All I/O except TT_xx DS13047 Rev 7 3.6 Unit MHz V V 57/121 110 Electrical characteristics STM32WB50CG STM32WB30CE Table 20. General operating conditions (continued) Symbol Parameter PD Power dissipation at TA = 85 °C for suffix 5 TA Ambient temperature TJ Junction temperature range Conditions Min Max Unit - 803 mW –10 85 UFQFPN48 Maximum power dissipation Low-power dissipation(5) 105 - –10 °C 105 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. When not used, VDDA must be connected to VDD. 3. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between min (VDD, VDDA) + 3.6 V and 5.5V. 4. For operation with voltage higher than min (VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be disabled. 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics). 6.3.3 RF BLE characteristics Table 21. RF transmitter BLE characteristics Symbol Parameter Test conditions Min Typ Max Unit Fop Frequency operating range - 2402 - 2480 Fxtal Crystal frequency - - 32 - ∆F Delta frequency - - 250 - kHz Rgfsk On air data rate - - 1 - Mbps RF channel spacing - - 2 - MHz PLLres MHz Table 22. RF transmitter BLE characteristics (1 Mbps)(1) Symbol Prf Pband BW6dB IBSE fd maxdr 58/121 Parameter Test conditions Min Typ Max Unit Maximum output power - - 4.0 - 0 dBm output power - - 0 - Minimum output power - - -20 - -0.5 - 0.4 dB kHz dBm Output power variation over the band Tx = 0 dBm - Typical 6 dB signal bandwidth Tx = Maximum output power - 670 - 2 MHz Bluetooth® Low Energy:-20 dBm - -50 - ≥ 3 MHz Bluetooth® Low Energy: -30 dBm - -53 - Bluetooth® Low Energy: ±50 kHz -50 - +50 kHz -20 - +20 kHz/ 50 µs In band spurious emission Frequency drift Maximum drift rate ® Bluetooth Low Energy: ±20 kHz / 50 µs DS13047 Rev 7 dBm STM32WB50CG STM32WB30CE Electrical characteristics Table 22. RF transmitter BLE characteristics (1 Mbps)(1) (continued) Symbol Parameter Test conditions ® Min Typ Max - +150 Frequency offset Bluetooth Low Energy: ±150 kHz -150 ∆f1 Frequency deviation average Bluetooth® Low Energy: between 225 and 275 kHz 225 - 275 ∆fa Frequency deviation ∆f2 (average) / ∆f1 (average) Bluetooth® Low Energy:> 0.80 0.80 - - fo OBSE(2) Out of band spurious emission Unit kHz < 1 GHz - - -61 - ≥ 1 GHz - - -46 - dBm 1. :Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and impedance matching networks to interface with a 50 Ω antenna. 2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan). Table 23. RF receiver BLE characteristics (1 Mbps) Symbol Parameter Prx_max Maximum input signal Psens(1) High sensitivity mode Test conditions PER