STM32WB55CGU6

STM32WB55xx STM32WB35xx Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 and 802.15.4 radio solution Datasheet - production data Features .  Include ST state-of-the-art patented technology  Radio – 2.4 GHz – RF transceiver supporting Bluetooth® 5.2 specification, IEEE 802.15.4-2011 PHY and MAC, supporting Thread and  Zigbee® 3.0 – RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps), -100 dBm (802.15.4) – Programmable output power up to +6 dBm with 1 dB steps – Integrated balun to reduce BOM – Support for 2 Mbps – Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer – Accurate RSSI to enable power control – Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66 – Support for external PA – Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3 or  MLPF-WB-02E3)  Ultra-low-power platform – 1.71 to 3.6 V power supply – – 40 °C to 85 / 105 °C temperature ranges – 13 nA shutdown mode – 600 nA Standby mode + RTC + 32 KB RAM – 2.1 µA Stop mode + RTC + 256 KB RAM – Active-mode MCU: < 53 µA / MHz when RF and SMPS on – Radio: Rx 4.5 mA / Tx at 0 dBm 5.2 mA April 2021 This is information on a product in full production. UFQFPN48 7 x 7 mm solder pad VFQFPN68 8 x 8 mm solder pad FBGA WLCSP100 0.4 mm pitch UFBGA129 0.5 mm pitch  Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions  Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 219.48 CoreMark® (3.43 CoreMark/MHz at 64 MHz)  Energy benckmark – 303 ULPMark™ CP score  Supply and reset management – High efficiency embedded SMPS  step-down converter with intelligent bypass mode – Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds – Ultra-low-power POR/PDR – Programmable voltage detector (PVD) – VBAT mode with RTC and backup registers  Clock sources – 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock) – 32 kHz crystal oscillator for RTC (LSE) – Internal low-power 32 kHz (±5%) RC (LSI1) – Internal low-power 32 kHz (stability ±500 ppm) RC (LSI2) DS11929 Rev 11 1/193 www.st.com STM32WB55xx STM32WB35xx – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy) – High speed internal 16 MHz factory trimmed RC (±1%) – 2x PLL for system clock, USB, SAI and ADC  Memories – Up to 1 MB Flash memory with sector protection (PCROP) against R/W operations, enabling radio stack and application – Up to 256 KB SRAM, including 64 KB with hardware parity check – 20x32-bit backup register – Boot loader supporting USART, SPI, I2C and USB interfaces – OTA (over the air) Bluetooth® Low Energy and 802.15.4 update – Quad SPI memory interface with XIP – 1 Kbyte (128 double words) OTP  Rich analog peripherals (down to 1.62 V) – 12-bit ADC 4.26 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps – 2x ultra-low-power comparator – Accurate 2.5 V or 2.048 V reference voltage buffered output  System peripherals – Inter processor communication controller (IPCC) for communication with Bluetooth® Low Energy and 802.15.4 – HW semaphores for resources sharing between CPUs – 2x DMA controllers (7x channels each) supporting ADC, SPI, I2C, USART, QSPI, SAI, AES, timers – 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode) – 1x LPUART (low power) – 2x SPI 32 Mbit/s – 2x I2C (SMBus/PMBus) – 1x SAI (dual channel high quality audio) – 1x USB 2.0 FS device, crystal-less, BCD and LPM – Touch sensing controller, up to 18 sensors – LCD 8x40 with step-up converter – 1x 16-bit, four channels advanced timer – 2x 16-bit, two channels timer – 1x 32-bit, four channels timer – 2x 16-bit ultra-low-power timer – 1x independent Systick – 1x independent watchdog – 1x window watchdog  Security and ID – Secure firmware installation (SFI) for Bluetooth® Low Energy and 802.15.4 SW stack – 3x hardware encryption AES maximum 256-bit for the application, the Bluetooth® Low Energy and IEEE802.15.4 – Customer key storage / key manager services – HW public key authority (PKA) – Cryptographic algorithms: RSA,  Diffie-Helman, ECC over GF(p) – True random number generator (RNG) – Sector protection against R/W operation (PCROP) – CRC calculation unit – Die information: 96-bit unique ID – IEEE 64-bit unique ID. Possibility to derive 802.15.4 64-bit and Bluetooth® Low Energy 48-bit EUI  Up to 72 fast I/Os, 70 of them 5 V-tolerant  Development support – Serial wire debug (SWD), JTAG for the application processor – Application cross trigger with input / output – Embedded Trace Macrocell™ for application  All packages are ECOPACK2 compliant Table 1. Device summary Reference Part numbers STM32WB55xx STM32WB55CC, STM32WB55CE, STM32WB55CG, STM32WB55RC, STM32WB55RE, STM32WB55RG, STM32WB55VC, STM32WB55VE, STM32WB55VG, STM32WB55VY STM32WB35xx STM32WB35CC, STM32WB35CE 2/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.1 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 19 3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 3.6.1 RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6.2 BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6.3 802.15.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6.4 RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6.5 Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7.1 Power supply distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7.3 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7.4 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7.6 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.8 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.9 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DS11929 Rev 11 3/193 6 Contents STM32WB55xx STM32WB35xx 3.14 3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 44 3.13.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 45 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.15 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.17 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.18 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.19 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.20.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 50 3.20.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 51 3.20.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.20.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.21 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 52 3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 54 3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 54 3.25 Serial peripheral interface (SPI1, SPI2) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.26 Serial audio interfaces (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.27 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.28 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.28.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.28.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.1 4/193 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DS11929 Rev 11 STM32WB55xx STM32WB35xx Contents 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.3 RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.4 RF 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.5 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 96 6.3.6 Embedded reset and power control block characteristics . . . . . . . . . . . 96 6.3.7 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.9 Wakeup time from Low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.19 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.20 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 140 6.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 152 6.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.25 SMPS step-down converter characteristics . . . . . . . . . . . . . . . . . . . . . 156 6.3.26 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.3.28 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 DS11929 Rev 11 5/193 6 Contents STM32WB55xx STM32WB35xx 6.3.29 7 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 158 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.1 UFBGA129 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.2 WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.3 VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 184 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32WB55xx and STM32WB35xx devices features and peripheral counts . . . . . . . . . . 14 Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 20 RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power supply typical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Features over all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM32WB55xx and STM32WB35xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix . . . . . . . . . . . 39 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32WB55xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32WB35xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Alternate functions (STM32WB55xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Alternate functions (STM32WB35xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 RF transmitter BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 RF receiver BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 RF transmitter 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 RF receiver 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 RF 802.15.4 power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 96 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . 100 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V . . . . . . . . . . . . 102 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . 103 Current consumption in Sleep and Low-power sleep modes, Flash memory ON . . . . . . 104 Current consumption in Low-power sleep modes, Flash memory in Power down . . . . . . 104 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 DS11929 Rev 11 7/193 9 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. 8/193 STM32WB55xx STM32WB35xx Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 HSE clock source requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Low-speed external user clock characteristics – Bypass mode . . . . . . . . . . . . . . . . . . . . 122 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ADC accuracy - Limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ADC accuracy - Limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 ADC accuracy - Limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 ADC accuracy - Limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DS11929 Rev 11 STM32WB55xx STM32WB35xx Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. List of tables USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 UFBGA129 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 UFBGA129 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 WLCSP100 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 VFQFPN68 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 DS11929 Rev 11 9/193 9 List of figures STM32WB55xx STM32WB35xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 10/193 STM32WB55xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32WB35xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32WB55xx and STM32WB35xx RF front-end block diagram . . . . . . . . . . . . . . . . . . . 23 External components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32WB55xx - Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32WB35xx - Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout(1) (2). . . . . . . . . . . . . . . . . . . . . . 58 STM32WB55Rx VFQFPN68 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32WB55Vx WLCSP100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32WB55Vx UFBGA129 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Power supply scheme (all packages except UFBGA129 and WLCSP100) . . . . . . . . . . . . 82 Power supply scheme (UFBGA129 and WLCSP100 packages) . . . . . . . . . . . . . . . . . . . . 83 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical link quality indicator code vs. Rx level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Typical energy detection (T = 27°C, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 HSI48 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 UFBGA129 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 UFBGA129 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 UFBGA129 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 WLCSP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 VFQFPN68 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 VFQFPN68 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 VFQFPN68 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 DS11929 Rev 11 STM32WB55xx STM32WB35xx Figure 49. Figure 50. List of figures STM32WB55xx UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . 182 STM32WB35xx UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . 182 DS11929 Rev 11 11/193 11 Introduction 1 STM32WB55xx STM32WB35xx Introduction This document provides the ordering information and mechanical device characteristics of the STM32WB55xx and STM32WB35xx microcontrollers, based on Arm® cores(a). This document must be read in conjunction with the reference manual (RM0434), available from the STMicroelectronics website www.st.com. For information on the device errata with respect to the datasheet and reference manual refer to the STM32WB55xx and STM32WB35xx errata sheet (ES0394), available from the STMicroelectronics website www.st.com. For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the Cortex®-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference Manual, both available on the www.arm.com website. For information on 802.15.4 refer to the IEEE website (www.ieee.org). For information on Bluetooth® refer to www.bluetooth.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 2 Description Description The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.2 and with IEEE 802.15.4-2011. They contain a dedicated Arm® Cortex®-M0+ for performing all the real-time low layer operation. The devices are designed to be extremely low-power and are based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security. Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors. The devices embed high-speed memories (up to 1 Mbyte of Flash memory for STM32WB55xx, up to 512 Kbytes for STM32WB35xx, up to 256 Kbytes of SRAM for STM32WB55xx, 96 Kbytes for STM32WB35xx), a Quad-SPI Flash memory interface (available on all packages) and an extensive range of enhanced I/Os and peripherals. Direct data transfer between memory and peripherals and from memory to memory is supported by fourteen DMA channels with a full flexible channel mapping by the DMAMUX peripheral. The devices feature several mechanisms for embedded Flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex® -M0+ exclusive access. The two AES encryption engines, PKA and RNG enable lower layer MAC and upper layer cryptography. A customer key storage feature may be used to keep the keys hidden. The devices offer a fast 12-bit ADC and two ultra-low-power comparators associated with a high accuracy reference voltage generator. These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose 32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers. In addition, up to 18 capacitive sensing channels are available for STM32WB55xx (not on UFQFPN48 package). The STM32WB55xx also embed an integrated LCD driver up to 8x40 or 4x44, with internal step-up converter. The STM32WB55xx and STM32WB35xx also feature standard and advanced communication interfaces, namely one USART (ISO 7816, IrDA, Modbus and Smartcard mode), one low- power UART (LPUART), two I2Cs (SMBus/PMBus), two SPIs (one for STM32WB35xx) up to 32 MHz, one serial audio interface (SAI) with two channels and three PDMs, one USB 2.0 FS device with embedded crystal-less oscillator, supporting BCD and LPM and one Quad-SPI with execute-in-place (XIP) capability. The STM32WB55xx and STM32WB35xx operate in the -40 to +105 °C (+125 °C junction) and -40 to +85 °C (+105 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The devices include independent power supplies for analog input for ADC. DS11929 Rev 11 13/193 57 Description STM32WB55xx STM32WB35xx The STM32WB55xx and STM32WB35xx integrate a high efficiency SMPS step-down converter with automatic bypass mode capability when the VDD falls below VBORx (x=1, 2, 3, 4) voltage level (default is 2.0 V). It includes independent power supplies for analog input for ADC and comparators, as well as a 3.3 V dedicated supply input for USB. A VBAT dedicated supply allows the devices to back up the LSE 32.768 kHz oscillator, the RTC and the backup registers, thus enabling the STM32WB55xx and STM32WB35xx to supply these functions even if the main VDD is not present through a CR2032-like battery, a Supercap or a small rechargeable battery. The STM32WB55xx offer four packages, from 48 to 129 pins. The STM32WB35xx offer one package, 48 pins. Table 2. STM32WB55xx and STM32WB35xx devices features and peripheral counts Feature Flash Memory SRAM density (bytes) SRAM1 STM32WB55Cx 256 K 512 K 1M STM32WB55Rx 256 K 512 K 1M 64 K 192 K 64 K 192 K 1M 64 K STM32WB35Cx 640 K 256 K 192 K 256 K 512 K 96 K 32 KB 64 K BLE 5.2 (2 Mbps) 802.15.4 Yes Advanced 1 (16 bits) General purpose 2 (16 bits) + 1 (32 bits) Low power 2 (16 bits) SysTick Communication interfaces 256 K 512 K 128 K 256 K 256 K 128 K 256 K 256 K 128 K 256 K SRAM2 Timers STM32WB55Vx SPI 1 1 2 I2C 2 USART(1) 1 LPUART 1 SAI 1 2 channels USB FS Yes QSPI 1 RTC 1 Tamper pin 1 3 1 Wakeup pin 2 5 2 LCD, COMxSEG Yes, 4x13 Yes, 4x28 Yes, 8x40 or 4x44 No GPIOs 30 49 72 30 Capacitive sensing No 6 18 No 12-bit ADC Number of channels 13 channels (incl. 3 internal) 19 channels (incl. 3 internal) Yes Internal Vref 14/193 DS11929 Rev 11 13 channels (incl. 3 internal) STM32WB55xx STM32WB35xx Description Table 2. STM32WB55xx and STM32WB35xx devices features and peripheral counts (continued) Feature STM32WB55Cx STM32WB55Rx STM32WB55Vx 2 Max CPU frequency 64 MHz Operating temperature Analog comparator Ambient -40 to +85 and -40 to +105 °C -40 to -40 to +85 and +85 40 to +105 °C °C Junction -40 to +105 and -40 to +125 °C -40 to -40 to +105 and +105 -40 to +125 °C °C Operating voltage Package STM32WB35Cx 1.71 to 3.6 V UFQFPN48 7 mm x 7 mm 0.5 mm pitch, solder pad VFQFPN68 8 mm x 8 mm 0.4 mm pitch, solder pad WLCSP100 0.4 mm pitch UFBGA129 0.5 mm pitch - UFQFPN48 7 mm x 7 mm 0.5 mm pitch, solder pad 1. USART peripheral can be used as SPI. DS11929 Rev 11 15/193 57 Description STM32WB55xx STM32WB35xx Figure 1. STM32WB55xx block diagram AHB Lite NVIC Cortex-M0+ AHB asynchronous CTI APB asynchronous RCC2 BLE IP 802.15.4 BLE / 802.15.4 RF IP RTC2 LSE 32 kHz I-WDG LSI1 32 kHz TAMP NVIC Cortex-M4 (DSP) CTI WKUP BLE PKA + RAM HSEM AHB Lite (Shared) ETM HSE2 32 MHz 32 KB SRAM2b Arbiter + ART Shared memory Up to 1 MB Flash JTAG/SWD 32 KB SRAM2a Backup LSI2 32 kHz RNG IPCC PLL1 and PLL2 RCC + CSS HSI 1% 16 MHz MSI up to 48 MHz PWR Power supply POR/ PDR/BOR/PVD/AVD QSPI - XIP EXTI CRS DMA1 7 channels AES2 USB FS + RAM MPU DMA2 7 channels DMAMUX GPIO Ports A, B, C, D, E, H AHB Lite FPU Up to 192 KB SRAM1 WWDG DBG Temp (oC) sensor CRC ADC1 16-bit ULP 4.26 Msps / 19 ch TSC LCD AES1 RC48 SPI1 SPI2 I2C1 APB I2C3 LPTIM1 TIM1 LPUART1 LPTIM2 TIM2 USART1 SAI1 TIM16, TIM17 SYSCFG/COMP/VREF MS41407V6 16/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Description Figure 2. STM32WB35xx block diagram AHB Lite NVIC Cortex-M0+ AHB asynchronous CTI APB asynchronous RCC2 BLE IP 802.15.4 BLE / 802.15.4 RF IP CTI AHB Lite (Shared) RNG IPCC GPIO Ports A, B, C, E, H CRC I-WDG LSI1 32 kHz PLL1 And PLL2 RCC + CSS AHB Lite QSPI - XIP DMAMUX LSE 32 kHz HSEM MPU DMA2 7 channels RTC2 TAMP Cortex-M4 (DSP) DMA1 7 channels WKUP BLE PKA + RAM NVIC FPU HSE2 32 MHz 32 KB SRAM2b Arbiter + ART Shared memory Up to 512 KB Flash JTAG/SWD 32 KB SRAM2a Backup LSI2 32 kHz HSI 1% 16 MHz MSI up to 48 MHz PWR Power supply POR/ PDR/BOR/PVD/AVD EXTI CRS AES2 USB FS + RAM RC48 WWDG 32 KB SRAM1 DBG Temp (oC) sensor ADC1 16-bit ULP 4.26 Msps / 19 ch SPI1 I2C1 AES1 APB I2C3 LPTIM1 TIM1 LPUART1 LPTIM2 TIM2 USART1 SAI1 TIM16, TIM17 SYSCFG/COMP MS53592V1 DS11929 Rev 11 17/193 57 Functional overview STM32WB55xx STM32WB35xx 3 Functional overview 3.1 Architecture The STM32WB55xx and STM32WB35xx multiprotocol wireless devices embed a BLE and an 802.15.4 RF subsystem that interfaces with a generic microcontroller subsystem using an Arm® Cortex®-M4 CPU (called CPU1) on which the host application resides. The RF subsystem is composed of an RF analog front end, BLE and 802.15.4 digital MAC blocks as well as of a dedicated Arm® Cortex®-M0+ microcontroller (called CPU2), plus proprietary peripherals. The RF subsystem performs all of the BLE and 802.15.4 low layer stack, reducing the interaction with the CPU1 to high level exchanges. Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU (CPU1):  Flash memories  SRAM1, SRAM2a and SRAM2b (SRAM2a can be retained in Standby mode)  Security peripherals (RNG, AES1, PKA)  Clock RCC  Power control (PWR) The communication and the sharing of peripherals between the RF subsystem and the Cortex®-M4 CPU is performed through a dedicated inter processor communication controller (IPCC) and semaphore mechanism (HSEM). 3.2 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU is a processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional  code-efficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions enabling efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm® core, the STM32WB55xx and STM32WB35xx are compatible with all Arm® tools and software. Figure 1 and Figure 2 show the general block diagram of, respectively, the STM32WB55xx and STM32WB35xx devices. 18/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview 3.3 Memories 3.3.1 Adaptive real-time memory accelerator (ART Accelerator) The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally require the processor to wait for the Flash memory at higher frequencies. To release the processor near 80 DMIPS performance at 64 MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 64 MHz. 3.3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to eight protected areas, which can be divided up into eight subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS  (real-time operating system). If a program accesses a memory location prohibited by the MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.3.3 Embedded Flash memory The STM32WB55xx and STM32WB35xx devices feature, respectively, up to 1 Mbyte and 512 Kbytes of embedded Flash memory available for storing programs and data, as well as some customer keys. Flexible protections can be configured thanks to option bytes:  Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in SRAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex®-M4 and Cortex®-M0+ JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. DS11929 Rev 11 19/193 57 Functional overview STM32WB55xx STM32WB35xx Table 3. Access status vs. readout protection level and execution modes Area Debug, boot from SRAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Backup registers SRAM2a SRAM2b 2 Yes (1) No 1 Yes Yes 2 Yes Yes 1 Yes Yes 2 Yes Yes No Yes Yes Yes (1) N/A N/A N/A (2) No No N/A(2) N/A N/A N/A No No No(2) N/A N/A N/A N/A N/A (2) Yes Yes 1. The option byte can be modified by the RF subsystem. 2. Erased when RDP changes from Level 1 to Level 0.  Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 4-Kbyte granularity.  Proprietary code readout protection (PCROP): two parts of the Flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. Two areas can be selected, with 2-Kbyte granularity. An additional option bit (PCROP_RDP) makes possible to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be accessed by the host CPU1. The whole non-volatile memory embeds the error correction code (ECC) feature supporting:  single error detection and correction  double error detection  the address of the ECC fail can be read in the ECC register The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis. A dedicated HW mechanism allows both CPUs to perform Write/Erase operations. 20/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 3.3.4 Functional overview Embedded SRAM The STM32WB55xx devices feature up to 256 Kbytes of embedded SRAM, split in three blocks:  SRAM1: up to 192 Kbytes mapped at address 0x2000 0000  SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby mode)  SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and mirrored at 0x1000 8000 with hardware parity check The STM32WB35xx devices feature 96 Kbytes of embedded SRAM, split in three blocks:  SRAM1: 32 Kbytes mapped at address 0x2000 0000  SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby mode)  SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and mirrored at 0x1000 8000 with hardware parity check SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the host CPU1. The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock speeds. 3.4 Security and safety The STM32WB55xx and STM32WB35xx contain many security blocks both for the BLE or IEEE 802.15.4 and the Host application. It includes:  Customer storage of the BLE and 802.15.4 keys  Secure Flash memory partition for RF subsystem-only access  Secure SRAM partition, that can be accessed only by the RF subsystem  True random number generator (RNG)  Advance encryption standard hardware accelerators (AES-128bit and AES-256bit, supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM)  Private key acceleration (PKA) including:  – Modular arithmetic including exponentiation with maximum modulo size of 3136 bits – Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits Cyclic redundancy check calculation unit (CRC) A specific mechanism is in place to ensure that all the code executed by the RF subsystem CPU2 can be secure, whatever the Host application. For the AES1 a customer key can be managed by the CPU2 and used by the CPU1 to encrypt/decrypt data. DS11929 Rev 11 21/193 57 Functional overview 3.5 STM32WB55xx STM32WB35xx Boot modes and FW update At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:  Boot from user Flash  Boot from system memory  Boot from embedded SRAM The devices always boot on CPU1 core. The embedded bootloader code makes it possible to boot from various peripherals:  USB  UART  I2C  SPI Secure Firmware update (especially BLE and 802.15.4) from system boot and over the air is provided. 3.6 RF subsystem The STM32WB55xx and STM32WB35xx embed an ultra-low power multi-standard radio Bluetooth® Low Energy (BLE) and 802.15.4 network processor, compliant with Bluetooth® specification 5.2 and IEEE® 802.15.4-2011. The BLE features 1 Mbps and 2 Mbps transfer rates, supports multiple roles simultaneously acting at the same time as BLE sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key agreement protocol, thus ensuring a secure connection. The BLE stack and 802.15.4 Low Level layer run on an embedded Arm® Cortex®-M0+ core (CPU2). The stack is stored on the embedded Flash memory, which is also shared with the Arm® Cortex®-M4 (CPU1) application, making it possible in-field stack update. 3.6.1 RF front-end block diagram The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF architecture in Rx mode. Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna (single ended connection, impedance close to 50 Ω). The natural bandpass behavior of the internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band interferer rejection. In Transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean power ramp-up. In receive mode the circuit can be used in standard high performance or in reduced power consumption (user programmable). The Automatic gain control (AGC) is able to reduce the chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent linearity can be achieved. The bill of material is reduced thanks to the high degree of integration. The radio frequency source is synthesized form an external 32 MHz crystal that does not need any external 22/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview trimming capacitor network thanks to a dual network of user programmable integrated capacitors. AGC control Timer and Power control AGC RF control Interrupt Wakeup AHB G BLE modulator APB BLE demodulator APB 802.15.4 modulator BP filter ADC BLE controller ADC RF_TX_MOD_EXT_PA Figure 3. STM32WB55xx and STM32WB35xx RF front-end block diagram LNA G RF1 802.15.4 MAC PLL See notes PA ramp generator Adjust 802.15.4 demodulator PA Wakeup Modulator Interrupt Adjust Trimmed bias HSE SMPS VDDSMPS VSSSMPS VLXSMPS OSC_IN LDO LDO VFBSMPS LDO Max PA level VDDRF OSC_OUT 32 MHz Notes: - UFQFPN48 and VFQFPN68: VSS through exposed pad, and VSSRF pin must be connected to ground plane - WLCSP100 and UFBGA129: VSSRF pins must be connected to ground plane MS45477V7 3.6.2 BLE general description The BLE block is a master/slave processor, compliant with Bluetooth specification 5.2 standard (2 Mbps). DS11929 Rev 11 23/193 57 Functional overview STM32WB55xx STM32WB35xx It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a complete power-optimized stack for Bluetooth Low Energy protocol runs, providing master / slave role support  GAP: central, peripheral, observer or broadcaster roles  ATT/GATT: client and server  SM: privacy, authentication and authorization  L2CAP  Link layer: AES-128 encryption and decryption In addition, according to Bluetooth specification 5.2, the BLE block provides:  Multiple roles simultaneous support  Master/slave and multiple roles simultaneously  LE data packet length extension (making it possible to reach 800 kbps at application level)  LE privacy 1.2  LE secure connections  Flexible Internet connectivity options  High data rate (2 Mbps) The device allows the applications to meet the tight peak current requirements imposed by the use of standard coin cell batteries. When the high efficiency embedded SMPS  step-down converter is used, the RF front end consumption (Itmax) is only 8.1 mA at the highest output power (+6 dBm). The power efficiency of the subsystem is optimized: while running with the radio and the applicative cores simultaneously using the SMPS, the Cortex®-M4 core consumption reaches 53 µA / MHz in active mode. Ultra-low-power sleep modes and very short transition time between operating modes result in very low average current consumption during real operating conditions, resulting in longer battery life. The BLE block integrates a full bandpass balun, thus reducing the need for external components. The link between the Cortex®-M4 application processor (CPU1) running the application, and the BLE stack running on the dedicated Cortex®-M0+ (CPU2) is performed through a normalized API, using a dedicated IPCC. 24/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 3.6.3 Functional overview 802.15.4 general description The STM32WB55xx and STM32WB35xx embed a dedicated 802.15.4 hardware MAC:  Support for 802.15.4 release 2011  Advanced MAC frame filtering; hardwired firewall: Programmable filters based on source/destination addresses, frame version, security enabled, frame type  256-byte RX FIFO; Up to 8 frames capacity, additional frame information (timing, mean RSSI, LQI)  128-byte TX FIFO with retention – 3.6.4 Content not lost, retransmissions possible under CPU2 control  Automatic frame acknowledgment, with programmable delay  Advanced channel access features – Full CSMA-CA support – Superframe timer – Beaconing support (require LSE) – Flexible TX control with programmable delay  Configuration registers with retention available down to Standby mode for software/auto-restore  Autonomous sniffer, Wakeup based on timer or CPU2 request  Automatic frame transmission/reception/sleep periods, Interrupt to the CPU2 on particular events RF pin description The RF block contains dedicated pins, listed in Table 4. : Name Table 4. RF pin list Type RF1 Description RF Input/output, must be connected to the antenna through a low-pass matching network OSC_OUT I/O OSC_IN RF_TX_ MOD_EXT_PA VDDRF (1) VSSRF 32 MHz main oscillator, also used as HSE source External PA transmit control VDD Dedicated supply, must be connected to VDD VSS To be connected to GND 1. On packages with exposed pad, this pad must be connected to GND plane for correct RF operation. 3.6.5 Typical RF application schematic The schematic in Figure 4 and the external components listed in Table 4 are purely indicative. For more details refer to the “Reference design” provided in separate documents. DS11929 Rev 11 25/193 57 Functional overview STM32WB55xx STM32WB35xx Figure 4. External components for the RF part OSC_IN X1 32 MHz OSC_OUT VDD VDDRF STM32WB microcontroller C1 Antenna VSSRF (including exposed pad) Lf1 Cf1 RF1 Cf2 Antenna filter Lf2 MS53575V1 Table 5. Typical external components Component C1 X1 Antenna filter Antenna Description Decoupling capacitance for RF 32 MHz crystal(1) Antenna filter and matching network 2.4 GHz band antenna Value 100 nF // 100 pF 32 MHz Refer to AN5165, on www.st.com - 1. e.g. NDK reference: NX2016SA 32 MHz EXS00A-CS06654. Note: For more details refer to AN5165 “Development of RF hardware using STM32WB microcontrollers” available on www.st.com. 3.7 Power supply management 3.7.1 Power supply distribution The device integrate an SMPS step-down converter to improve low power performance when the VDD voltage is high enough. This converter has an intelligent mode that automatically enters in bypass mode when the VDD voltage falls below a specific BORx  (x = 1, 2, 3 or 4) voltage. By default, at Reset the SMPS is in bypass mode. The device can be operated without the SMPS by just wiring its output to VDD. This is the case for applications where the voltage is low, or where the power consumption is not critical. 26/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview Figure 5. Power distribution VDD VDD VDDSMPS VDDSMPS SMPS SMPS VLXSMPS SMPS mode or BYPASS mode L1 VLXSMPS LPR VFBSMPS VFBSMPS C2 RFR (not used) LPR MR RFR SMPS configuration MR LDO configuration MS41409V4 Table 6. Power supply typical components Component C2 L1(2) Description Value SMPS output capacitor(1) 4.7 µF For 8 SMPS inductance MHz(3) 2.2 µH (4) 10 µH For 4 MHz 1. e.g. GRM155R60J475KE19. 2. An extra 10 nH inductor in series with L1 is needed to improve the receiver performance,  e.g Murata LQG15WZ10NJ02D 3. e.g. Wurth 74479774222. 4. e.g. Murata LQM21FN100M70L. The SMPS can also be switched on or set in bypass mode at any time by the application software, for example when very accurate ADC measurement are needed. 3.7.2 Power supply schemes The devices have different voltage supplies (see Figure 7 and Figure 8) and can operate within the following voltage ranges:  VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO), the internal regulator and system functions such as RF, SMPS, reset, power management and internal clocks. It is provided externally through VDD pins. VDDRF and VDDSMPS must be always connected to VDD pins.  VDDA = 1.62 (ADC/COMPs) to 3.6 V: external analog power supply for ADC, comparators and voltage reference buffer. The VDDA voltage level can be independent from the VDD voltage. When not used VDDA must be connected to VDD.  VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. When not used VDDUSB must be connected to VDD.  VLCD = 2.5 to 3.6 V: the LCD controller can be powered either externally through the VLCD pin, or internally from an internal voltage generated by the embedded step-up converter. This converter can generate a VLCD voltage up to 3.6 V if VDD is higher than 2.0 V. Note that the LCD is available only on STM32WB55xx devices. DS11929 Rev 11 27/193 57 Functional overview STM32WB55xx STM32WB35xx During power up/down, the following power sequence requirements must be respected:  When VDD is below 1 V the other power supplies (VDDA, VDDUSB, VLCD), must remain below VDD + 300 mV  When VDD is above 1 V all power supplies are independent. Figure 6. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDUSB and VLCD. During the power down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling capacitors to be discharged with different time constants during the power down transient phase. Note: 28/193 VDD, VDDRF and VDDSMPS must be wired together, so they can follow the same voltage sequence. DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview Figure 7. STM32WB55xx - Power supply overview Level shifter Interruptible domain (VDD12I) IOs (CPU1, CPU2, peripherals, SRAM1, SRAM2b) IO logic On domain (VDD12O) SysConfig, AIEC, RCC, PwrCtrl, LPTIM, LPUSART Power switch Power switch VSS VSS VFBSMPS VLXSMPS VDDSMPS VSSSMPS VSS MR SMPS RFR LPR VDDRF RF domain Backup domain Radio VBKP12 VSSRF SRAM2a Power switch VSS (including exposed pad) VSS Wakeup domain (VDDIO) VDD HSI, HSE1, 2xPLL, LSI1, LSI2, IWDG, RF Power switch VSW VBAT VSS Switch domain (VSW) VBAT IOs LSE, RTC, backup registers IO logic VSS VLCD VSS LCD VDDA Analog domain REF_BUF VREF+ ADC = VREF+ = VREF- VSSA VDDUSB VUSB IOs USB transceiver(1) USB domain (VUSB) VSS VSS MS41410V7 1. The USB transceiver is powered by VDDUSB, and the GPIOs associated with USB are powered by VDDUSB when USB alternate function (PA11 and PA12) is selected. When USB alternate function is not selected the GPIOs associated with USB are powered as standard GPIOs. DS11929 Rev 11 29/193 57 Functional overview STM32WB55xx STM32WB35xx Figure 8. STM32WB35xx - Power supply overview Level shifter Interruptible domain (VDD12I) IOs (CPU1, CPU2, peripherals, SRAM1, SRAM2b) IO logic On domain (VDD12O) SysConfig, AIEC, RCC, PwrCtrl, LPTIM, LPUSART Power switch Power switch VSS VSS VFBSMPS VLXSMPS VDDSMPS VSSSMPS VSS MR SMPS RFR LPR VDDRF RF domain Backup domain Radio VBKP12 VSSRF SRAM2a Power switch VSS (including exposed pad) VSS Wakeup domain (VDDIO) VDD HSI, HSE1, 2xPLL, LSI1, LSI2, IWDG, RF Power switch VSW VBAT VSS Switch domain (VSW) VBAT IOs LSE, RTC, backup registers IO logic VSS VSS VDDA Analog domain ADC = VREF+ = VREFVSS VDDUSB VUSB IOs USB transceiver(1) USB domain (VUSB) VSS VSS MS53593V1 1. The USB transceiver is powered by VDDUSB, and the GPIOs associated with USB are powered by VDDUSB when USB alternate function (PA11 and PA12) is selected. When USB alternate function is not selected the GPIOs associated with USB are powered as standard GPIOs. 30/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 3.7.3 Functional overview Linear voltage regulator Three embedded linear voltage regulators supply most of the digital and RF circuitries, the main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).  The MR is used in the Run and Sleep modes and in the Stop 0 mode.  The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the SRAM2a in Standby with retention.  The RFR is used to supply the RF analog part, its activity is automatically managed by the RF subsystem. All the regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down, inducing zero consumption. The ultralow-power STM32WB55xx and STM32WB35xx support dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two voltage and frequency ranges:  Range 1, with the CPU running up to 64 MHz  Range 2, with a maximum CPU frequency of 16 MHz (note that HSE can be active in this mode). All peripheral clocks are also limited to 16 MHz. VCORE can also be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. In this case the CPU is running at up to 2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the RF subsystem is not available). 3.7.4 Power supply supervisor An integrated ultra-low-power brown-out reset (BOR) is active in all modes except Shutdown ensuring proper operation after power-on and during power down. The devices remain in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it with the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the devices embed a peripheral voltage monitor (PVM) that compares the independent supply voltage VDDA with a fixed threshold to ensure that the peripheral is in its functional supply range. Any BOR level can also be used to automatically switch the SMPS step-down converter in bypass mode when the VDD voltage drops below a given voltage level. The mode of operation is selectable by register bit, the BOR level is selectable by option byte. 3.7.5 Low-power modes These ultra-low-power devices support several low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources. DS11929 Rev 11 31/193 57 Functional overview STM32WB55xx STM32WB35xx By default, the microcontroller is in Run mode, Range 1, after a system or a power on Reset. It is up to the user to select one of the low-power modes described below:  Sleep In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem, continue to operate and can wake up the CPU when an interrupt/event occurs.  Low-power run This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator operating current. The code can be executed from SRAM or from the Flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. The RF subsystem is not available in this mode and must be OFF.  Low-power sleep This mode is entered from the low-power run mode. Only the CPU1 clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the  low-power run mode. The RF subsystem is not available in this mode and must be OFF.  Stop 0, Stop 1 and Stop 2 Stop modes achieve the lowest power consumption while retaining the content of all the SRAM and registers. The LSE (or LSI) is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop modes to detect their wakeup condition. Three modes are available: Stop 0, Stop 1 and Stop 2. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode the main regulator remains ON, allowing a very fast wakeup time but with higher consumption. In these modes the RF subsystem can wait for incoming events in all Stop modes. The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem or the SMPS is used the exits must be set to HSI16 only. If used, the SMPS is restarted automatically.  Standby The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The RTC can remain active (Standby mode with RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1, SRAM2b and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be retained in Standby mode, supplied by the low-power regulator (Standby with 32 KB SRAM2a retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or from the RF system wakeup). 32/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview The system clock after wakeup is 16 MHz, derived from the HSI16. If used, the SMPS is restarted automatically. In this mode the RF can be used.  Shutdown The Shutdown mode allows to achieve the ultimate lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is 4 MHz, derived from the MSI. In this mode the RF is no longer operational. When the RF subsystem is active, it changes the power state according to its needs (Run, Stop, Standby). This operation is transparent for the CPU1 host application and managed by a dedicated HW state machine. At any given time the effective power state reached is the higher one needed by both the CPU1 and RF sub-system. Table 7 summarizes the peripheral features over all available modes. Wakeup capability is detailed in gray cells. Table 7. Features over all modes(1) Wakeup capability CPU1 Y - Y - - - - - - - - - - CPU2 Y - Y - - - - - - - - - - Y - - Y Y Y Y O(6) O(6) R - R - R - R - R Y Y(7) R - R - - - - - - - - - - Radio system (BLE, 802.15.4) Flash memory SRAM1 Y(3) Y Y (5) Y (7) VBAT Wakeup capability - - Wakeup capability Wakeup capability - Run Range 2 - Peripheral(2) Run Range 1 Low-power sleep Standby Shutdown Low-power run Stop 2 Sleep Stop0/Stop1 Y(4) Y(4) Y Y Y Y(7) Y Y(7) R - R - R(8) SRAM2b Y (7) Y Y(7) R - R - - - - - - Quad-SPI O O O O - - - - - - - - - Backup registers Y Y Y Y R - R - R - R - R Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - SRAM2a Y DS11929 Rev 11 33/193 57 Functional overview STM32WB55xx STM32WB35xx Table 7. Features over all modes(1) (continued) Wakeup capability Programmable voltage detector (PVD) O O O O O O O O - - - - - Peripheral voltage monitor PVMx (x=1, 3) O O O O O O O O - - - - - SMPS O O O O O(9) - - - - - - - - DMAx (x = 1, 2) O O O O - - - - - - - - - High speed internal (HSI16) O O O O O(10) - O(10) - - - - - - Oscillator HSI48 O O - - - - - - - - - - - High speed external (HSE)(11) O O O O - - - - - - - - - Low speed internal (LSI1 or LSI2) O O O O O - O - O - - - - Low speed external (LSE) O O O O O - O - O - O - O VBAT Wakeup capability - - Wakeup capability Wakeup capability - Run Range 2 - Peripheral(2) Run Range 1 Low-power sleep Standby Shutdown Low-power run Stop 2 Sleep Stop0/Stop1 Multi-speed internal (MSI)(12) 48 24 O 48 O - - - - - - - - - PLLx VCO maximum frequency 344 128 O - - - - - - - - - - - Clock security system (CSS) O O O O O O(13) O O(13) - - - - - Clock security system on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 LCD O O O O O O O O - - - - - O - - - O - - - - - - - O(14) - - - - - - - USB FS O - USART1 O O O O O(14) Low-power UART (LPUART1) O O O O O(14) O(14) O(14) O(14) - - - - - I2C1 O O O O O(15) O(15) - - - - - I2C3 O O O O O(15) O(15) O(15) O(15) - - - - - SPIx (x=1, 2) O O O O - - - - - - - - - SAI1 O O O O - - - - - - - - - 34/193 DS11929 Rev 11 - - STM32WB55xx STM32WB35xx Functional overview Table 7. Features over all modes(1) (continued) Wakeup capability ADC1 O O O O - - - - - - - - - VREFBUF O O O O O - - - - - - - - COMPx (x=1, 2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers TIMx (x=1, 2, 16, 17) O O O O - - - - - - - - - Low-power Timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power Timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - O - - - - - - - - - - - True random number generator (RNG) O - VBAT Wakeup capability - - Wakeup capability Wakeup capability - Run Range 2 - Peripheral(2) Run Range 1 Low-power sleep Standby Shutdown Low-power run Stop 2 Sleep Stop0/Stop1 AES2 hardware accelerator O O O O - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - IPCC O - O - - - - - - - - - - HSEM O - O - - - - - - - - - - PKA O O O O - - - - - - - - - GPIOs O O O O O O O O (16) 5 pins - 5 (17) pins 1. Legend: Y = Yes (Enabled), O = Optional (Disabled by default, can be enabled by software), R = Data retained,  - = Not available. 2. Available peripherals depend upon package, STM32WB35xx features one SPI, no LCD, no TSC and two wakeup pins. See Table 2: STM32WB55xx and STM32WB35xx devices features and peripheral counts for more details. 3. Bluetooth® Low Energy not possible in this mode. 4. Standby with SRAM2a retention mode only. 5. Flash memory programming only possible in Range 1 voltage, not in Range 2 and not in Low Power mode. 6. The Flash memory can be configured in Power-down mode. By default, it is not in Power-down mode. 7. The SRAM clock can be gated on or off. DS11929 Rev 11 35/193 57 Functional overview STM32WB55xx STM32WB35xx 8. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register. 9. Stop 0 only. SMPS is automatically switched to Bypass or Open mode during Low power operation. 10. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 11. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx). 12. MSI maximum frequency. 13. In case RF will be used and HSE will fail. 14. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 15. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 16. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 17. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 36/193 DS11929 Rev 11 Mode Run LPRun Sleep LPSleep Regulator Range 1 Range 2 LPR Range 1 Range 2 LPR DS11929 Rev 11 Clocks Yes ON(3)(4) ON Any Yes ON(3) ON Any except PLL No ON(3) ON(5) Any No ON(3) ON(5) Any except PLL All except RF, RNG and USB-FS Any interrupt or event 45 µA/MHz 9 cycles LSE, LSI, HSE(6), HSI16(7) RF, BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1, 2) USART1(8) LPUART1(8) I2Cx (x=1, 3)(9) LPTIMx (x=1, 2), SMPS All other peripherals are frozen. Reset pin, all I/Os, RF, BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1, 2) USART1 LPUART1 I2Cx (x=1, 3) LPTIMx (x=1, 2) USB 100 µA 1.7 µs LSE, LSI, HSE(6), HSI16(7) RF, BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1, 2) USART1(8) LPUART1(8) I2Cx (x=1, 3)(9) LPTIMx (x=1, 2) All other peripherals are frozen. Reset pin, all I/Os RF, BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1, 2) USART1 LPUART1 I2Cx (x=1, 3) LPTIMx (x=1, 2) USB 9.2 µA w/o RTC 9.6 µA w RTC 4.7 µs No OFF ON Range 2 Stop 1 LPR No OFF ON All except RNG and USB-FS N/A 107 µA/MHz 100 µA/MHz All except RF, RNG and USB-FS N/A 103 µA/MHz All Any interrupt or event 41 µA/MHz All except RNG and USB-FS 46 µA/MHz Wakeup time N/A 15.33 µs 9 cycles 37/193 Functional overview SRAM All Wakeup source Consumption(2) Flash Range 1 Stop 0 DMA and peripherals(1) CPU1 STM32WB55xx STM32WB35xx Table 8. STM32WB55xx and STM32WB35xx modes overview Mode Stop 2 Regulator LPR CPU1 No Flash OFF No OFF OFF DS11929 Rev 11 Shutdown OFF ON SRAM2a ON(10) LPR Standby SRAM OFF No OFF OFF Clocks DMA and peripherals(1) Wakeup source Consumption(2) Wakeup time LSE, LSI RF, BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1, 2) LPUART1(8) I2C3(9) LPTIM1 All other peripherals are frozen. Reset pin, all I/Os RF, BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1, 2) LPUART1 I2C3 LPTIM1 1.85 µA w/o RTC 2.1 µA w RTC 5.71 µs LSE, LSI RF, BOR, RTC, IWDG All other peripherals are powered off. I/O configuration can be floating, pull-up or pull-down RF, Reset pin 5 I/Os (WKUPx)(11) BOR, RTC, IWDG LSE RTC All other peripherals are powered off. I/O configuration can be floating, pull-up or pull-down(12) 5 I/Os (WKUPx)(11), RTC Functional overview 38/193 Table 8. STM32WB55xx and STM32WB35xx modes overview (continued) 0.32 µA w/o RTC 0.60 µA w RTC 0.11 µA w/o RTC 0.390 µA w RTC 0.028 µA w/o RTC 0.315 µA w/ RTC 51 µs - 1. Available peripherals depend upon package, STM32WB35xx features one SPI, no LCD, no TSC and two wakeup pins. See Table 2: STM32WB55xx and STM32WB35xx devices features and peripheral counts for more details. 2. Typical current at VDD = 1.8 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C. 3. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM. 5. The SRAM1 and SRAM2 clocks can be gated off independently. 6. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem. 7. HSI16 (16 MHz) automatically used by some peripherals. 8. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event. 9. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 10. SRAM1 and SRAM2b are OFF. 11. I/Os with wakeup from Standby/Shutdown capability: PA0, PC13, PC12, PA2, PC5. 12. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode. STM32WB55xx STM32WB35xx 4. Flash memory programming is only possible in Range 2 voltage. STM32WB55xx STM32WB35xx 3.7.6 Functional overview Reset mode To improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.8 VBAT operation The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers) from an external battery, an external supercapacitor, or from VDD when no external battery nor an external supercapacitor are present. Three anti-tamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.9 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU1 resources and, consequently, reducing power supply consumption. In addition, these hardware connections result in fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and Sleep, Stop 0, Stop 1 and Stop 2 modes. Low-power run Low-power Stop 0 / Stop 1 Stop 2 TIMx Sleep Source Run Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADC1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - Comparator output blanking Y Y Y Y - - Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y Y(1) TIM1 Timer triggered by analog watchdog Y Y Y Y - - Destination COMPx COMPx ADC1 TIM1 TIM2 Action DS11929 Rev 11 39/193 57 Functional overview STM32WB55xx STM32WB35xx Stop 2 CSS CPU (hard fault) SRAM (parity error) Flash memory (ECC error) COMPx PVD Stop 0 / Stop 1 USB Low-power All clock sources (internal and external) Action Low-power run RTC Destination Sleep Source Run Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix (continued) TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y Y(1) TIM2 TIM16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - Timer triggered by USB SOF Y Y - - - - Timer break Y Y Y Y - - External trigger Y Y Y Y - (1) TIM2 TIM1 TIM16,17 TIMx GPIO LPTIMERx ADC1 External trigger Y Y Y Y Y Conversion external trigger Y Y Y Y - 1. LPTIM1 only. 40/193 DS11929 Rev 11 Y - STM32WB55xx STM32WB35xx 3.10 Functional overview Clocks and startup The STM32WB55xx and STM32WB35xx devices integrate several clock sources:  LSE: 32.768 kHz external oscillator, for accurate RTC and calibration with other embedded RC oscillators  LSI1: 32 kHz on-chip low-consumption RC oscillator  LSI2: almost 32 kHz, on-chip high-stability RC oscillator, used by the RF subsystem  HSE: high quality 32 MHz external oscillator with trimming, needed by the RF subsystem  HSI16: 16 MHz high accuracy on-chip RC oscillator  MSI: 100 kHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed using the LSE signal  HSI48: 48 MHz on-chip RC oscillator, for USB crystal-less purpose The clock controller (see Figure 9) distributes the clocks coming from the different oscillators to the core and the peripherals including the RF subsystem. It also manages clock gating for low power modes and ensures clock robustness. It features:  Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler  Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.  Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.  System clock source: four different clock sources can be used to drive the master clock SYSCLK:   – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL. – System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of 64 MHz. Auxiliary clock source: two ultralow-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5%. The LSI source can be either the LSI1 or the LSI2 on-chip oscillator. Peripheral clock sources: Several peripherals (RNG, SAI, USARTs, I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock. Two PLLs, each DS11929 Rev 11 41/193 57 Functional overview STM32WB55xx STM32WB35xx having three independent outputs for the highest flexibility, can generate independent clocks for the ADC, the RNG and the SAI.  Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.  Clock security system (CSS): this feature can be enabled by software. If an HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software interrupt is generated if enabled. LSE failure can also be detected and an interrupt generated.  Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSIx, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby. Several prescalers allow the user to configure the AHB frequencies, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 64 MHz. 42/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview Figure 9. Clock tree LSI1 RC 32 kHz to IWDG LSI LSI2 RC 32 kHz LSI LSCO to RTC and LCD(1) LSE OSC32_OUT LSE OSC 32.768 kHz to BLE wakeup LSE OSC32_IN to 802.15.4 wakeup LSE CSS LSI1 /32 CPU1 HPRE /1,2,...,512 LSI2 /32 LSE HCLK1 to CPU1, AHB1, AHB2, AHB3, and SRAM1 to CPU1 FCLK HSE MCO to CPU1 system timer /8 SYSCLK /1 - 16 PLLRCLK SYS clock source control HSI16 APB1 PPRE1 /1,2,4,8,16 PCLK1 APB2 PPRE2 /1,2,4,8,16 PCLK2 MSI PLLRCLK RC48 OSC_OUT OSC_IN HSI16 HSE OSC 32 MHz SYSCLK HSE HSEPRE/1,2 CPU2 C2HPRE 1,2,...,512 MSI HSE CSS to APB2 to APB2 TIMx to CPU2 to CPU2 FCLK /8 HSI48 RC 48 MHz x1 or x2 to APB1 to APB1 TIMx HCLK2 HSI16 RC 16 MHz MSI RC 100 kHz - 48 MHz x1 or x2 AHB4 SHDHPRE /1,2,...,512 to CPU2 system timer to AHB4, Flash memory, SRAM2 HCLK4 to APB3 HSI16 MSI HSE HSI16 /M to AHB5 HCLK5 /2 to RF PLL xN HSI16 MSI /P /Q PLLPCLK HSI48 SMPSDIV /1,2,3,4,6,8,12 MSI to USB /2 to SMPS HSE PLLQCLK /3 /R PLLRCLK to RNG SMPS clock source control LSI PCLKn SYSCLK LSE PLLSAI1 xN /P HSI16 HSI16 to SAI1 PLLSAI1PCLK to USART1 to LPUART1 LSE SAI1_EXTCLK /Q PLLSAI1QCLK PCLKn PCLKn /R PLLSAI1RCLK to ADC1 SYSCLK SYSCLK HSI16 HSI16 to I2Cx to LPTIMx LSI LSE MS45402V8 1. The LCD is not available on STM32WB35xx devices. 3.11 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. DS11929 Rev 11 43/193 57 Functional overview STM32WB55xx STM32WB35xx The I/Os alternate function configuration can be locked, if needed, following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.12 Direct memory access controller (DMA) The device embeds two DMAs. Refer to Table 10 for the features implementation. Direct memory access (DMA) is used to provide high-speed data transfer between peripherals and memory as well as between memories. Data can be quickly moved by DMA without any CPU action. This keeps CPU resources free for other operations. The two DMA controllers have fourteen channels in total, a full cross matrix allows any peripheral to be mapped on any of the available DMA channels. Each DMA has an arbiter for handling the priority between DMA requests. The DMA supports:  fourteen independently configurable channels (requests)  A full cross matrix between peripherals and all the DMA channels exist. There is also a HW trigger possibility through the DMAMUX.  Priorities between requests from DMA channels are software programmable (four levels consisting in very high, high, medium and low) or hardware in case of equality (request 1 has priority over request 2, etc.).  Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.  Support for circular buffer management.  Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically OR-ed together in a single interrupt request for each channel.  Memory-to-memory transfer.  Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers.  Access to Flash memory, SRAM, APB and AHB peripherals as source and destination.  Programmable number of data to be transferred: up to 65536. Table 10. DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 A DMAMUX block makes it possible to route any peripheral source to any DMA channel. 3.13 Interrupts and events 3.13.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the  Cortex®-M4 with FPU. 44/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview The NVIC benefits are the following:  Closely coupled NVIC gives low latency interrupt processing  Interrupt entry vector table address passed directly to the core  Allows early processing of interrupts  Processing of late arriving higher priority interrupts  Support for tail chaining  Processor state automatically saved  Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.13.2 Extended interrupts and events controller (EXTI) The EXTI manages wakeup through configurable and direct event inputs. It provides  wake-up requests to the Power control, and generates interrupt requests to the CPUx NVIC and events to the CPUx event input. Configurable events/interrupts come from peripherals able to generate a pulse, and make it possible to select the Event/Interrupt trigger edge and/or a SW trigger. Direct events/interrupts are coming from peripherals having their own clearing mechanism. 3.14 Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features:  12-bit native resolution, with built-in calibration  Up to 16-bit resolution with 256 oversampling ratio  4.26 Msps maximum conversion rate with full resolution – Down to 39 ns sampling time – Increased conversion rate for lower resolution (up to 7.11 Msps for 6-bit resolution)  Up to sixteen external channels and three internal channels: internal reference voltages, temperature sensor  Single-ended and differential mode inputs  Low-power design  – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: two groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – The ADC supports multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into three data register or in SRAM with DMA controller support DS11929 Rev 11 45/193 57 Functional overview 3.14.1 STM32WB55xx STM32WB35xx – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 input channel, which is used to convert the sensor output voltage into a digital value. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored in the system memory area, accessible in read-only mode. Table 11. Temperature sensor calibration values 3.14.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 12. Internal voltage reference calibration values 46/193 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.6 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB DS11929 Rev 11 STM32WB55xx STM32WB35xx 3.15 Functional overview Voltage reference buffer (VREFBUF) The STM32WB55xx devices embed a voltage reference buffer that can be used as voltage reference for the ADC and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages:  2.048 V  2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on UFQFPN48 package, hence the internal voltage reference buffer is not available on a dedicated pin, but user can still use the VDDA value. 3.16 Comparators (COMP) The STM32WB55xx and STM32WB35xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following:  External I/O  Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.17 Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric such as glass or plastic. The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library (free to use) and enables reliable touch sensing functionality in the end application. DS11929 Rev 11 47/193 57 Functional overview STM32WB55xx STM32WB35xx The main features of the touch sensing controller are the following: Note: 48/193  Proven and robust surface charge transfer acquisition principle  Supports up to 18 capacitive sensing channels  Up to six capacitive sensing channels can be acquired in parallel offering a very good response time  Spread spectrum feature to improve system robustness in noisy environments  Full hardware management of the charge transfer acquisition sequence  Programmable charge transfer frequency  Programmable sampling capacitor I/O pin  Programmable channel I/O pin  Programmable max count value to avoid long acquisition when a channel is faulty  Dedicated end of acquisition and max count error flags with interrupt capability  One sampling capacitor for up to three capacitive sensing channels to reduce the system components  Compatible with proximity, touchkey, linear and rotary touch sensor implementation  Designed to operate with STMTouch touch sensing firmware library The number of capacitive sensing channels is dependent upon the package (not available on QFPN48) and subject to I/O availability. DS11929 Rev 11 STM32WB55xx STM32WB35xx 3.18 Functional overview Liquid crystal display controller (LCD) The STM32WB55xx devices embed an LCD controller with the following characteristics:  Highly flexible frame rate control.  Supports Static, 1/2, 1/3, 1/4 and 1/8 duty.  Supports Static, 1/2, 1/3 and 1/4 bias.  Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed. – LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive)  Software selectable LCD output voltage (contrast) from VLCDmin to VLCDmax.  No need for external analog components:  – A step-up converter is embedded to generate an internal VLCD voltage higher than VDD (up to 3.6 V if VDD > 2.0 V) – Software selection between external and internal VLCD voltage source. In case of an external source, the internal boost circuit is disabled to reduce power consumption – A resistive network is embedded to generate intermediate VLCD voltages – The structure of the resistive network is configurable by software to adapt the power consumption to match the capacitive charge required by the LCD panel – Integrated voltage output buffers for higher LCD driving capability. The contrast can be adjusted using two different methods: – When using the internal step-up converter, the software can adjust VLCD between VLCDmin and VLCDmax – Programmable dead time (up to eight phase periods) between frames.  Full support of low-power modes: the LCD controller can be displayed in Sleep,  Low-power run, Low-power sleep and Stop modes, or can be fully disabled to reduce power consumption.  Built in phase inversion for reduced power consumption and EMI (electromagnetic interference).  Start of frame interrupt to synchronize the software when updating the LCD data RAM.  Blink capability: – 1, 2, 3, 4, 8 or all pixels can be programmed to blink at a configurable frequency – Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz. Used LCD segment and common pins should be configured as GPIO alternate functions and unused segment and common pins can be used for general purpose I/O or for another peripheral alternate function. Note: When the LCD relies on the internal step-up converter, the VLCD pin should be connected to VSS with a capacitor. Its typical value is 1 μF. 3.19 True random number generator (RNG) The devices embed a true RNG that delivers 32-bit random numbers generated by an integrated analog circuit. DS11929 Rev 11 49/193 57 Functional overview 3.20 STM32WB55xx STM32WB35xx Timers and watchdogs The STM32WB55xx and STM32WB35xx include one advanced 16-bit timer, one generalpurpose 32-bit timer, two 16-bit basic timers, two low-power timers, two watchdog timers and a SysTick timer. Table 13 compares the features of the advanced control, general purpose and basic timers. Table 13. Timer features Capture/ compare channels Complementary outputs Up, down, Up/down 4 3 32-bits Up, down, Up/down 4 No TIM16 16-bits Up 2 1 General purpose TIM17 16-bits Up 2 1 Low power LPTIM1 LPTIM2 16-bits Up 1 1 Timer type Timer Counter resolution Counter type Advanced control TIM1 16-bits General purpose TIM2 General purpose 3.20.1 Prescaler factor Any integer between 1 and 65536 DMA request generation Yes Advanced-control timer (TIM1) The advanced-control timer can be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted  dead-times. They can also be seen as complete general-purpose timers. The four independent channels can be used for:  Input capture  Output compare  PWM generation (edge or center-aligned modes) with full modulation capability (0 to 100%)  One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.20.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 3.20.2 General-purpose timers (TIM2, TIM16, TIM17) There are up to three synchronizable general-purpose timers embedded in the STM32WB55xx and STM32WB35xx (see Table 13 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.  TIM2 – 50/193 Full-featured general-purpose timer DS11929 Rev 11 STM32WB55xx STM32WB35xx  3.20.3 Functional overview – Features four independent channels for input capture/output compare, PWM or one-pulse mode output. Can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. – The counter can be frozen in debug mode. – Independent DMA request generation, support of quadrature encoders. TIM16 and TIM17 – General-purpose timers with mid-range features: – 16-bit auto-reload upcounters and 16-bit prescalers. – 1 channel and 1 complementary channel. – All channels can be used for input capture/output compare, PWM or one-pulse mode output. – The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. – The counters can be frozen in debug mode. Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers, having an independent clock running in Stop mode if they are clocked by LSE, LSIx or by an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 modes. The low-power timers support the following features: 3.20.4  16-bit up counter with 16-bit autoreload register  16-bit compare register  Configurable output: pulse, PWM  Continuous/ one shot mode  Selectable software/hardware input trigger  Selectable clock source – Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application)  Programmable digital glitch filter  Encoder mode (LPTIM1 only) Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. DS11929 Rev 11 51/193 57 Functional overview 3.20.5 STM32WB55xx STM32WB35xx System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.21  a 24-bit down counter  autoreload capability  a maskable system interrupt generation when the counter reaches 0  a programmable clock source. Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter, supporting the following features:  Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.  Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.  Two programmable alarms.  On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.  Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.  Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.  Three anti-tamper detection pins with programmable filter.  Timestamp feature, which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode.  17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 20 backup registers are supplied through a switch that takes power either from the VDD supply (when present) or from the VBAT pin. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: 52/193  a 32.768 kHz external crystal (LSE)  an external resonator or oscillator (LSE)  one of the internal low power RC oscillators (LSI1 or LSI2, with typical frequency of 32 kHz)  the high-speed external clock (HSE) divided by 32. DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (alarm, wakeup timer, timestamp or tamper) can generate an interrupt and wakeup the device from the low-power modes. 3.22 Inter-integrated circuit interface (I2C) The devices embed two I2Cs. Refer to Table 14 for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports:   I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert  Power System Management Protocol (PMBus™) specification rev 1.1 compatibility  Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 9: Clock tree.  Wakeup from Stop mode on address match  Programmable analog and digital noise filters  1-byte buffer with DMA capability Table 14. I2C implementation I2C features(1) I2C1 I2C3 Standard-mode (up to 100 kbit/s) X X Fast-mode (up to 400 kbit/s) X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X Programmable analog and digital noise filters X X SMBus/PMBus hardware support X X DS11929 Rev 11 53/193 57 Functional overview STM32WB55xx STM32WB35xx Table 14. I2C implementation (continued) I2C features(1) I2C1 I2C3 Independent clock X X Wakeup from Stop 0 / Stop 1 mode on address match X X Wakeup from Stop 2 mode on address match - X 1. X: supported 3.23 Universal synchronous/asynchronous receiver transmitter (USART) The devices embed one universal synchronous receiver transmitter. This interface provides asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and has LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals, and RS485 driver enable. The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. The USART supports synchronous operation (SPI mode), and can be used as an SPI master. The USART has a clock domain independent from the CPU clock, allowing it to wake up the MCU from Stop mode using baudrates up to 200 kbaud. The wake up events from Stop mode are programmable and can be:  the start bit detection  any received data frame  a specific programmed data frame. The USART interface can be served by the DMA controller. 3.24 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART, enabling asynchronous serial communication with minimum power consumption. The LPUART supports half duplex single wire communication and modem operations (CTS/RTS), allowing multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 kbaud. The wake up events from Stop mode are programmable and can be:  the start bit detection  any received data frame  a specific programmed data frame. Only a 32.768 kHz clock (LSE) is needed for LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an 54/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. The LPUART interfaces can be served by the DMA controller. 3.25 Serial peripheral interface (SPI1, SPI2) Two SPI interfaces enable communication up to 32 Mbit/s in master and up to 24 Mbit/s in slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. The SPI interfaces can be served by the DMA controller. 3.26 Serial audio interfaces (SAI1) The device embeds a dual channel SAI peripheral that supports full duplex audio operation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports:  One independent audio sub-block that can be a transmitter or a receiver, with the respective FIFO  8-word integrated FIFOs  Synchronous or asynchronous mode  Master or slave configuration  Clock generator to target independent audio frequency sampling when audio sub-block is configured in master mode  Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit  Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out  Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame  Number of bits by frame may be configurable  Frame synchronization active level configurable (offset, bit length, level)  First active bit position in the slot is configurable  LSB first or MSB first for data transfer  Mute mode  Stereo/Mono audio frame capability  Communication clock strobing edge configurable (SCK)  Error flags with associated interrupts if enabled respectively – Overrun and underrun detection – Anticipated frame synchronization signal detection in slave mode – Late frame synchronization signal detection in slave mode – Codec not ready for the AC’97 mode in reception DS11929 Rev 11 55/193 57 Functional overview   STM32WB55xx STM32WB35xx Interruption sources when enabled: – Errors – FIFO requests DMA interface with two dedicated channels to handle access to the dedicated integrated FIFO of the SAI audio sub-block. The PDM (Pulse Density Modulation) block allows the user to manage up to three digital microphone pairs (with two different clocks). This block performs Right and Left microphone  de-interleaving and time alignment through programmable delay lines in order to properly feed the SAI. 3.27 Quad-SPI memory interface (QUADSPI) The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes:  Indirect mode: all the operations are performed using the QUADSPI registers  Status polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting  Memory-mapped mode: the external Flash memory is mapped and is seen by the system as if it were an internal memory. This mode can be used for the Execute In Place (XIP) The Quad-SPI interface supports: 56/193  Three functional modes: indirect, status-polling, and memory-mapped  SDR and DDR support  Fully programmable opcode for both indirect and memory mapped mode  Fully programmable frame format for both indirect and memory mapped mode  Each of the five following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase  Integrated FIFO for reception and transmission  8, 16, and 32-bit data accesses are allowed  DMA channel for indirect mode operations  Programmable masking for external Flash memory flag management  Timeout management  Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error DS11929 Rev 11 STM32WB55xx STM32WB35xx Functional overview 3.28 Development support 3.28.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.28.2 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32WB55xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DS11929 Rev 11 57/193 57 Pinouts and pin description 4 STM32WB55xx STM32WB35xx Pinouts and pin description VDD PB7 PB6 PB5 PB4 PB3 PA15 PA14 VDDUSB PA13 PA12 PA11 48 47 46 45 44 43 42 41 40 39 38 37 Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout(1)(2) VBAT 1 36 PA10 PC14-OSC32_IN 2 35 VDD PC15-OSC32_OUT 3 34 VDDSMPS PH3-BOOT0 4 33 VLXSMPS PB8 5 32 VSSSMPS PB9 6 31 VFBSMPS NRST 7 30 PE4 VDDA 8 29 PB1 PA0 9 28 PB0 PA1 10 27 AT1 PA2 11 26 AT0 PA3 12 25 OSC_IN 13 14 15 16 17 18 19 20 21 22 23 24 PA4 PA5 PA6 PA7 PA8 PA9 PB2 VDD RF1 VSSRF VDDRF OSC_OUT UFQFPN48 MS42406V4 1. The above figure shows the package top view. 2. The exposed pad must be connected to ground plane. VDD PB7 PB6 PB5 PB4 PB3 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDDUSB PA13 PA12 PA11 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 Figure 11. STM32WB55Rx VFQFPN68 pinout(1)(2) VBAT 1 51 PA10 PC13 2 50 PC6 PC14-OSC32_IN 3 49 PB15 PC15-OSC32_OUT 4 48 PB14 PH3-BOOT0 5 47 PB13 PB8 6 46 PB12 PB9 7 45 VDD NRST 8 44 VDDSMPS PC0 9 43 VLXSMPS PC1 10 42 VSSSMPS PC2 11 41 VFBSMPS PC3 12 40 PE4 VREF+ 13 39 PB1 VDDA 14 38 PB0 PA0 15 37 AT1 PA1 16 36 AT0 PA2 17 35 OSC_IN 22 23 24 25 26 27 28 29 30 31 32 PA7 PA8 PA9 PC4 PC5 PB2 PB10 PB11 VDD RF1 VSSRF 34 21 PA6 33 20 PA5 VDDRF 19 PA4 OSC_OUT 18 PA3 VFQFPN68 MS45417V3 1. The above figure shows the package top view. 2. The exposed pad must be connected to ground plane. 58/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Pinouts and pin description Figure 12. STM32WB55Vx WLCSP100 ballout(1) 1 2 3 4 5 6 7 8 9 10 A PA11 PA12 PA14 PA15 PA13 PC10 PD2 PD7 PB3 VDD B VDD VSS VDDUSB PC9 PA10 PC11 PD5 PD12 VSS PE1 C PB13 PD3 PD1 PD0 PC12 PD6 PB4 PE0 PD13 VBAT D VDDSMPS PC6 PD4 PD8 PD9 PB5 PB7 PD14 PC15OSC32_OUT PC14OSC32_IN E VLXSMPS PB14 PC7 PD10 PD11 PE2 PD15 PH3-BOOT0 PH1 PH0 F VSSSMPS VFBSMPS PB15 PC8 PB6 PA2 PB8 PC0 NRST PB9 G PE4 PE3 PB12 PC4 PC13 PA1 PA0 PC1 PC2 PC3 H PB1 PB0 AT0 AT1 PC5 PA7 PA6 VREF+ VDDA VSSA J OSC_IN OSC_OUT VDDRF VSSRF VSS PB11 PA8 PA3 VSS VDD K VSSRF VSSRF VSSRF RF1 VDD PB10 PB2 PA9 PA5 PA4 Radio USB SMPS VDD VSS MS42407V3 1. The above figure shows the package top view. Figure 13. STM32WB55Vx UFBGA129 ballout(1) 1 2 3 A PE1 PB6 PB5 B PE2 PE0 PB4 C PD13 4 VSS PA11 PD7 PD4 PD1 PC11 PA15 PA14 VSS PA10 PC9 PC6 PC8 PC7 PB14 PB13 VLXSMPS VDDSMPS VDDSMPS VLXSMPS VSSSMPS VSSSMPS VFBSMPS PE3 PE4 VSS_DCAP3 VDD_DCAP3 PC15OSC32_OUT PC14OSC32_IN VSS _DCAP1 F PH0 G PH3-BOOT0 PH1 PB8 H PC1 NRST PC0 PC2 PC3 VSSA VDDA VSS PA1 PA4 PA9 PA6 N PA7 No pin PD6 VSS VDD _DCAP1 PA5 13 PA12 PD0 E PA3 12 VDDUSB PC12 D PA2 11 PA13 PC10 PB3 PA0 10 VSS _DCAP4 PD9 M 9 PD2 PB7 L 8 VDD _DCAP4 PD8 PD14 VREF+ 7 PD10 PD11 PD15 K 6 PD5 PD12 VBAT J 5 PC13 VSS VSS VDD VSS PB9 VDD VDD VDD VSS VSS PC5 PC4 Power supply PB15 VSS VDD VSS PA8 PD3 PB12 VSS VSSRF AT0 AT1 PB10 VSSRF VSSRF VSSRF VSSRF VSSRF VSSRF PB1 PB11 VSS _DCAP2 VSSRF RF1 VSSRF VSSRF VSSRF OSC_IN PB2 VDD _DCAP2 VSSRF VSSRF VDDRF OSC_OUT SMPS USB Radio PB0 MS51777V4 1. The above figure shows the package top view. DS11929 Rev 11 59/193 80 Pinouts and pin description STM32WB55xx STM32WB35xx Table 15. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RF RF I/O RST Bidirectional reset pin with weak pull-up resistor I/O structure Option for TT or FT I/Os _f (1) I/O, Fm+ capable _l (2) I/O, with LCD function supplied by VLCD _u(3) I/O, with USB function supplied by VDDUSB _a(4) (5) Notes I/O, with Analog switch function supplied by VDDA Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_fl, FT_fla. 2. The related I/O structures in Table 16 are: FT_l, FT_fl, FT_lu. 3. The related I/O structures in Table 16 are: FT_u, FT_lu. 4. The related I/O structures in Table 16 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la. 5. Analog switch for the TSC function is supplied by VDD. 60/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Pinouts and pin description Table 16. STM32WB55xx pin and ball definitions UFQFPN48 VFQFPN68 WLCSP100 UFBGA129 Pin type I/O structures Notes Pin number - - C8 B2 PE0 I/O FT_l - TIM1_ETR, TSC_G7_IO3, LCD_SEG36, TIM16_CH1, CM4_EVENTOUT - - - B10 A1 PE1 I/O FT_l - TSC_G7_IO2, LCD_SEG37, TIM17_CH1, CM4_EVENTOUT - - Pin name (function after reset) Alternate functions Additional functions - - E6 B1 PE2 I/O FT_l - TRACECK, SAI1_PDM_CK1, TSC_G7_IO1, LCD_SEG38, SAI1_MCLK_A, CM4_EVENTOUT - - C9 C1 PD13 I/O FT_l - TSC_G6_IO4, LCD_SEG33, LPTIM2_OUT, CM4_EVENTOUT - - - D8 D3 PD14 I/O FT_l - TIM1_CH1, LCD_SEG34, CM4_EVENTOUT - - - E7 C2 PD15 I/O FT_l - TIM1_CH2, LCD_SEG35, CM4_EVENTOUT - 1 1 C10 D2 VBAT S - - - 2 G5 F4 PC13 I/O FT 2 3 D10 E3 PC14OSC32_IN I/O FT 3 4 D9 E2 PC15OSC32_OUT I/O FT - - - E5 VSS S - - - - - - - F6 VDD S - - - - - - E10 F1 PH0 I/O FT - CM4_EVENTOUT - - - E9 G2 PH1 I/O FT - CM4_EVENTOUT - 4 5 E8 G1 PH3-BOOT0 I/O FT - CM4_EVENTOUT, LSCO(3) - - TIM1_CH2N, SAI1_PDM_CK1, I2C1_SCL, QUADSPI_BK1_IO1, LCD_SEG16, SAI1_MCLK_A, TIM16_CH1, CM4_EVENTOUT - 5 6 F7 G3 PB8 I/O (1) (2) (1) (2) (1) (2) FT_fl - - CM4_EVENTOUT RTC_TAMP1/RTC_TS/ RTC_OUT/WKUP2 CM4_EVENTOUT OSC32_IN CM4_EVENTOUT OSC32_OUT DS11929 Rev 11 61/193 80 Pinouts and pin description STM32WB55xx STM32WB35xx 6 7 F10 H4 PB9 7 8 F9 H2 NRST - 9 F8 H3 PC0 Notes Pin name (function after reset) Pin type UFBGA129 WLCSP100 VFQFPN68 UFQFPN48 Pin number I/O structures Table 16. STM32WB55xx pin and ball definitions (continued) Alternate functions I/O FT_fla - TIM1_CH3N, SAI1_PDM_DI2, I2C1_SDA, SPI2_NSS, IR_OUT, TSC_G7_IO4, QUADSPI_BK1_IO0, LCD_COM3, SAI1_FS_A, TIM17_CH1, CM4_EVENTOUT I/O - - - LPTIM1_IN1, I2C3_SCL, LPUART1_RX, LCD_SEG18, LPTIM2_IN1, CM4_EVENTOUT ADC1_IN1 ADC1_IN2 ADC1_IN3 RST I/O FT_fla Additional functions - - - 10 G8 H1 PC1 I/O FT_fla - LPTIM1_OUT, SPI2_MOSI, I2C3_SDA, LPUART1_TX, LCD_SEG19, CM4_EVENTOUT - 11 G9 J2 PC2 I/O FT_la - LPTIM1_IN2, SPI2_MISO, LCD_SEG20, CM4_EVENTOUT - - - E7 VSS S - - - - - - - H6 VDD S - - - - - 12 G10 LPTIM1_ETR, SAI1_PDM_DI1, SPI2_MOSI, LCD_VLCD, SAI1_SD_A, ADC1_IN4 LPTIM2_ETR, CM4_EVENTOUT J3 PC3 I/O FT_a - - - - - H10 K2 VSSA S - - - 13 H8 L1 VREF+ S - - - - VREFBUF_OUT 8 14 H9 K3 VDDA S - (4) - - J9 E9 VSS S - - - - - - J10 F8 VDD S - - - - 9 15 G7 M1 PA0 I/O FT_a - TIM2_CH1, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, CM4_EVENTOUT COMP1_INM, ADC1_IN5, RTC_TAMP2/WKUP1 10 16 G6 L2 PA1 I/O FT_la - TIM2_CH2, I2C1_SMBA, SPI1_SCK, LCD_SEG0, CM4_EVENTOUT COMP1_INP, ADC1_IN6 62/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Pinouts and pin description 11 17 12 18 F6 J8 13 19 K10 14 20 15 21 16 22 17 23 18 24 K9 H7 H6 J7 N1 PA2 I/O Notes Pin name (function after reset) Pin type UFBGA129 WLCSP100 VFQFPN68 UFQFPN48 Pin number I/O structures Table 16. STM32WB55xx pin and ball definitions (continued) FT_la Alternate functions Additional functions - LSCO(3), TIM2_CH3, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG1, COMP2_OUT, CM4_EVENTOUT COMP2_INM, ADC1_IN7, WKUP4 COMP2_INP, ADC1_IN8 M2 PA3 I/O FT_la - TIM2_CH4, SAI1_PDM_CK1, LPUART1_RX, QUADSPI_CLK, LCD_SEG2, SAI1_MCLK_A, CM4_EVENTOUT L3 PA4 I/O FT_a - SPI1_NSS, SAI1_FS_B, LPTIM2_OUT, LCD_SEG5, CM4_EVENTOUT COMP1_INM, COMP2_INM, ADC1_IN9 - TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, SAI1_SD_B, CM4_EVENTOUT COMP1_INM, COMP2_INM, ADC1_IN10 - TIM1_BKIN, SPI1_MISO, LPUART1_CTS, QUADSPI_BK1_IO3, LCD_SEG3, TIM16_CH1, CM4_EVENTOUT ADC1_IN11 - TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, COMP2_OUT, TIM17_CH1, CM4_EVENTOUT ADC1_IN12 - MCO, TIM1_CH1, SAI1_PDM_CK2, USART1_CK, LCD_COM0, SAI1_SCK_A, LPTIM2_OUT, CM4_EVENTOUT ADC1_IN15 COMP1_INM, ADC1_IN16 COMP1_INM, ADC1_IN13 N2 M3 N3 M4 PA5 PA6 PA7 PA8 I/O I/O FT_a FT_la I/O FT_fla I/O FT_la K8 L4 PA9 I/O FT_fla - TIM1_CH2, SAI1_PDM_DI2, I2C1_SCL, SPI2_SCK, USART1_TX, LCD_COM1, SAI1_FS_A, CM4_EVENTOUT LCD_SEG22, CM4_EVENTOUT - 25 G4 M5 PC4 I/O FT_la - - - - F3 VSS_DCAP1 S - - - - - - - G7 VDD S - - - - DS11929 Rev 11 63/193 80 Pinouts and pin description STM32WB55xx STM32WB35xx WLCSP100 UFBGA129 26 H5 L5 19 27 - 28 K7 K6 N6 L6 PC5 I/O PB2 PB10 I/O I/O Notes VFQFPN68 - Pin name (function after reset) Pin type UFQFPN48 Pin number I/O structures Table 16. STM32WB55xx pin and ball definitions (continued) FT_la - SAI1_PDM_DI3, LCD_SEG23, CM4_EVENTOUT COMP1_INP, ADC1_IN14, WKUP5 - RTC_OUT, LPTIM1_OUT, I2C3_SMBA, SPI1_NSS, LCD_VLCD, SAI1_EXTCLK, CM4_EVENTOUT COMP1_INP - TIM2_CH3, I2C3_SCL, SPI2_SCK, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A, CM4_EVENTOUT - TIM2_CH4, I2C3_SDA, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG11, COMP2_OUT, CM4_EVENTOUT - FT_a FT_fl Alternate functions Additional functions - 29 J6 M6 PB11 I/O FT_fl - - - - G5 VSS S - - - - - - - G9 VSS S - - - - K5 H8 VDD S - - - - 20 30 - - - N8 VSSRF S - - - - - - J4 L7 VSSRF S - - - - - - - L8 VSSRF S - - - - - - - M8 VSSRF S - - - - - - 21 31 K4 M9 RF1 I/O RF (5) 22 32 K3 M10 VSSRF S - - - - - - K2 M11 VSSRF S - - - - - - - K8 VSSRF S - - - - - - - L9 VSSRF S - - - - - - - L10 VSSRF S - - - - - - - N11 VSSRF S - - - - J3 N12 VDDRF S - - - - 23 33 - - K1 K10 VSSRF S - - - - - - - M12 VSSRF S - - - - J2 N13 OSC_OUT O RF (6) - - 24 34 64/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Pinouts and pin description Table 16. STM32WB55xx pin and ball definitions (continued) WLCSP100 UFBGA129 Pin type I/O structures Notes Alternate functions 25 35 J1 M13 OSC_IN I RF (6) - - L11 VSSRF S - - - - - - - - UFQFPN48 VFQFPN68 Pin number - - Pin name (function after reset) Additional functions - 26 36 H3 K11 AT0 O RF (7) 27 37 H4 K12 AT1 O RF (7) 28 38 H2 L13 PB0 I/O TT (8) COMP1_OUT, CM4_EVENTOUT,  RF_TX_MOD_EXT_PA - 29 39 H1 L12 PB1 I/O TT (8) LPUART1_RTS_DE, LPTIM2_IN1, CM4_EVENTOUT - - - J5 - VSS S - - - - - - - M7 VSS_DCAP2 S - - - - - - G2 H12 PE3 I/O FT - CM4_EVENTOUT - 30 40 G1 H13 PE4 I/O FT - CM4_EVENTOUT - 31 41 F2 H11 VFBSMPS S - - - - - G13 VSSSMPS S - - - - 32 42 F1 G12 VSSSMPS S - - - - 33 43 E1 F11 VLXSMPS S - - - - - G11 VLXSMPS S - - - - D1 F12 VDDSMPS S - - - - - - - - 34 44 - - - F13 VDDSMPS S - - - - - - - K4 VSS S - - - - B1 - VDD S - - - - 35 45 - - 46 47 G3 C1 H10 E12 PB12 PB13 I/O I/O FT_l FT_fl - TIM1_BKIN, I2C3_SMBA, SPI2_NSS, LPUART1_RTS, TSC_G1_IO1, LCD_SEG12, SAI1_FS_A, CM4_EVENTOUT - - TIM1_CH1N, I2C3_SCL, SPI2_SCK, LPUART1_CTS, TSC_G1_IO2, LCD_SEG13, SAI1_SCK_A, CM4_EVENTOUT - DS11929 Rev 11 65/193 80 Pinouts and pin description STM32WB55xx STM32WB35xx 48 E11 PB14 Pin type UFBGA129 WLCSP100 E2 Pin name (function after reset) I/O FT_fl Notes - VFQFPN68 UFQFPN48 Pin number I/O structures Table 16. STM32WB55xx pin and ball definitions (continued) Alternate functions Additional functions - TIM1_CH2N, I2C3_SDA, SPI2_MISO, TSC_G1_IO3, LCD_SEG14, SAI1_MCLK_A, CM4_EVENTOUT - - - 49 F3 F10 PB15 I/O FT_l - RTC_REFIN, TIM1_CH3N, SPI2_MOSI, TSC_G1_IO4, LCD_SEG15, SAI1_SD_A, CM4_EVENTOUT - 50 D2 D10 PC6 I/O FT_l - TSC_G4_IO1, LCD_SEG24, CM4_EVENTOUT - - - E3 D12 PC7 I/O FT_l - TSC_G4_IO2, LCD_SEG25, CM4_EVENTOUT - - - F4 D11 PC8 I/O FT_l - TSC_G4_IO3, LCD_SEG26, CM4_EVENTOUT - TIM1_BKIN, TSC_G4_IO4, USB_NOE, LCD_SEG27, SAI1_SCK_B, CM4_EVENTOUT - - - B4 C13 PC9 I/O FT_l - - - - K6 VSS S - - - - - - B2 - VSS S - - - - 36 51 B5 C12 PA10 I/O FT_fl - TIM1_CH3, SAI1_PDM_DI1, I2C1_SDA, USART1_RX, USB_CRS_SYNC, LCD_COM2, SAI1_SD_A, TIM17_BKIN, CM4_EVENTOUT 37 52 A1 B13 PA11 I/O FT_u - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, USB_DM, CM4_EVENTOUT - TIM1_ETR, SPI1_MOSI, LPUART1_RX, USART1_RTS_DE, USB_DP, CM4_EVENTOUT - JTMS-SWDIO, IR_OUT, USB_NOE, SAI1_SD_B, CM4_EVENTOUT - 38 53 A2 A13 39 54 A5 A11 40 55 B3 A12 VDDUSB - C11 VSS - - 66/193 PA12 - I/O FT_u - PA13 I/O (JTMS_SWDIO) FT_u (9) S - - - - S - - - - DS11929 Rev 11 STM32WB55xx STM32WB35xx Pinouts and pin description - - - - 58 59 Pin type Notes 42 57 Alternate functions Additional functions FT_l (9) JTCK-SWCLK, LPTIM1_OUT, I2C1_SMBA, LCD_SEG5, SAI1_FS_B, CM4_EVENTOUT - JTDI, TIM2_CH1, TIM2_ETR, (9) SPI1_NSS, TSC_G3_IO1, LCD_SEG17, CM4_EVENTOUT, MCO - UFBGA129 41 56 Pin name (function after reset) WLCSP100 VFQFPN68 UFQFPN48 Pin number I/O structures Table 16. STM32WB55xx pin and ball definitions (continued) A3 PA14 C10 I/O (JTCK_SWCLK) A4 C9 PA15 (JTDI) I/O FT_l - J11 VSS_DCAP3 S - A6 B6 B9 C8 PC10 PC11 I/O I/O - FT_l FT_l - - - TRACED1, TSC_G3_IO2, LCD_COM4/LCD_SEG28/ LCD_SEG40, CM4_EVENTOUT - - TSC_G3_IO3, LCD_COM5/LCD_SEG29/ LCD_SEG41, CM4_EVENTOUT - - 60 C5 B10 PC12 I/O FT_l - LSCO(3), TRACED3, TSC_G3_IO4, LCD_COM6/LCD_SEG30/ LCD_SEG42, CM4_EVENTOUT - 61 C4 B11 PD0 I/O FT - SPI2_NSS, CM4_EVENTOUT - - 62 C3 C7 PD1 I/O FT - SPI2_SCK, CM4_EVENTOUT - - - A7 B7 PD2 I/O FT_l - TRACED2, TSC_SYNC, LCD_COM7/LCD_SEG31/LC D_SEG43, CM4_EVENTOUT - - - C2 D8 PD3 I/O FT - SPI2_SCK, SPI2_MISO, QUADSPI_BK1_NCS, CM4_EVENTOUT - - - D3 C6 PD4 I/O FT - SPI2_MOSI, TSC_G5_IO1, QUADSPI_BK1_IO0, CM4_EVENTOUT - - TSC_G5_IO2, QUADSPI_BK1_IO1, SAI1_MCLK_B, CM4_EVENTOUT - - - B7 A6 PD5 I/O FT DS11929 Rev 11 RTC_TAMP3/WKUP3 67/193 80 Pinouts and pin description STM32WB55xx STM32WB35xx - - C6 D6 PD6 I/O Notes Pin name (function after reset) Pin type UFBGA129 WLCSP100 VFQFPN68 UFQFPN48 Pin number I/O structures Table 16. STM32WB55xx pin and ball definitions (continued) FT Alternate functions Additional functions - SAI1_PDM_DI1, TSC_G5_IO3, QUADSPI_BK1_IO2, SAI1_SD_A, CM4_EVENTOUT - TSC_G5_IO4, QUADSPI_BK1_IO3, LCD_SEG39, CM4_EVENTOUT - - - A8 C5 PD7 I/O FT_l - - - B9 B12 VSS S - - - - D4 B6 PD8 I/O FT_l - TIM1_BKIN2, LCD_SEG28, CM4_EVENTOUT - - - D5 D4 PD9 I/O FT_l - TRACED0, LCD_SEG29, CM4_EVENTOUT - - - E4 A7 PD10 I/O FT_l - TRIG_INOUT, TSC_G6_IO1, LCD_SEG30, CM4_EVENTOUT - - - E5 B5 PD11 I/O FT_l - TSC_G6_IO2, LCD_SEG31, LPTIM2_ETR, CM4_EVENTOUT - - - B8 B4 PD12 I/O FT_l - TSC_G6_IO3, LCD_SEG32, LPTIM2_IN1, CM4_EVENTOUT - 43 63 44 64 45 65 68/193 A9 C7 D6 C4 B3 A3 PB3 (JTDO) PB4 (NJTRST) PB5 I/O FT_la - JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, (9) USART1_RTS_DE, LCD_SEG7, SAI1_SCK_B, CM4_EVENTOUT - COMP2_INM NJTRST, I2C3_SDA, SPI1_MISO, USART1_CTS, I/O FT_fla (9) TSC_G2_IO1, LCD_SEG8, COMP2_INP SAI1_MCLK_B, TIM17_BKIN, CM4_EVENTOUT I/O FT_l - LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, LPUART1_TX, TSC_G2_IO2, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, CM4_EVENTOUT DS11929 Rev 11 - STM32WB55xx STM32WB35xx Pinouts and pin description 46 66 47 67 F5 A2 PB6 D7 C3 PB7 Notes Pin name (function after reset) Pin type UFBGA129 WLCSP100 VFQFPN68 UFQFPN48 Pin number I/O structures Table 16. STM32WB55xx pin and ball definitions (continued) I/O FT_fla I/O FT_fla Alternate functions Additional functions - LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, LCD_SEG6, SAI1_FS_B, TIM16_CH1N, MCO, CM4_EVENTOUT COMP2_INP - LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, TSC_G2_IO4, LCD_SEG21, TIM17_CH1N, CM4_EVENTOUT COMP2_INM, PVD_IN - - - J5 VSS S - - - - - - - J7 VSS S - - - - - - - J9 VSS S - - - - - - - B8 VSS_DCAP4 S - - - - - VDD S - - - - 48 68 A10 - - - A8 VDD_DCAP4 S - - - - - - - F2 VDD_DCAP1 S - - - - - - - J12 VDD_DCAP3 S - - - - - - - N7 VDD_DCAP2 S - - - - 1. PC13, PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the use of the PC13, PC14 and PC15 GPIOs in output mode is limited: - the speed must not exceed 2 MHz with a maximum load of 30 pF - these GPIOs must not be used as current sources (e.g. to drive a LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the reference manual RM0434, available on www.st.com. 3. The clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes. 4. On UFQFPN48 VDDA is connected to VREF+. 5. RF pin, use the nominal PCB layout. 6. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165). 7. Reserved, must be kept unconnected. 8. High frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0 and 1) during RF operation. 9. After reset these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and PB4 pins and the internal pull-down on PA14 pin are activated. DS11929 Rev 11 69/193 80 Pinouts and pin description STM32WB55xx STM32WB35xx Number Name (function after reset) Pin type I/O structures Notes Table 17. STM32WB35xx pin and ball definitions Alternate functions 1 VBAT S - - - 2 PC14-OSC32_IN I/O FT (1) (2) CM4_EVENTOUT FT (1) (2) CM4_EVENTOUT Pin 3 PC15-OSC32_OUT I/O 4 5 PH3-BOOT0 PB8 I/O I/O FT FT_f Additional functions OSC32_IN OSC32_OUT LSCO(3) - CM4_EVENTOUT, - TIM1_CH2N, SAI1_PDM_CK1, I2C1_SCL, QUADSPI_BK1_IO1, SAI1_MCLK_A, TIM16_CH1, CM4_EVENTOUT - TIM1_CH3N, SAI1_PDM_DI2, I2C1_SDA, IR_OUT, QUADSPI_BK1_IO0, SAI1_FS_A, TIM17_CH1, CM4_EVENTOUT - - 6 PB9 I/O FT_f - 7 NRST I/O RST - - - 8 VDDA S - - - - 9 PA0 I/O FT_a - TIM2_CH1, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, CM4_EVENTOUT COMP1_INM, ADC1_IN5, RTC_TAMP2/WKUP1 10 PA1 I/O FT_a - TIM2_CH2, I2C1_SMBA, SPI1_SCK, CM4_EVENTOUT COMP1_INP, ADC1_IN6 11 PA2 I/O FT_a - LSCO(3), TIM2_CH3, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, CM4_EVENTOUT COMP2_INM, ADC1_IN7, WKUP4 12 PA3 I/O FT_a - TIM2_CH4, SAI1_PDM_CK1, LPUART1_RX, QUADSPI_CLK, SAI1_MCLK_A, CM4_EVENTOUT COMP2_INP, ADC1_IN8 13 PA4 I/O FT_a - SPI1_NSS, SAI1_FS_B, LPTIM2_OUT, CM4_EVENTOUT COMP1_INM, COMP2_INM, ADC1_IN9 14 PA5 I/O FT_a - TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, SAI1_SD_B, CM4_EVENTOUT COMP1_INM, COMP2_INM, ADC1_IN10 15 PA6 I/O FT_a - TIM1_BKIN, SPI1_MISO, LPUART1_CTS, QUADSPI_BK1_IO3, ADC1_IN11 TIM16_CH1, CM4_EVENTOUT 16 PA7 I/O FT_fa - TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, COMP2_OUT, ADC1_IN12 TIM17_CH1, CM4_EVENTOUT 17 PA8 I/O FT_a - MCO, TIM1_CH1, SAI1_PDM_CK2, USART1_CK, SAI1_SCK_A, LPTIM2_OUT, CM4_EVENTOUT 70/193 DS11929 Rev 11 ADC1_IN15 STM32WB55xx STM32WB35xx Pinouts and pin description Number Name (function after reset) Pin type I/O structures Notes Table 17. STM32WB35xx pin and ball definitions (continued) 18 PA9 I/O FT_fa - TIM1_CH2, SAI1_PDM_DI2, I2C1_SCL, USART1_TX, SAI1_FS_A, COMP1_INM, ADC1_IN16 CM4_EVENTOUT 19 PB2 I/O FT_a - RTC_OUT, LPTIM1_OUT, I2C3_SMBA, SPI1_NSS, SAI1_EXTCLK, CM4_EVENTOUT 20 VDD S - - - - - - Pin Alternate functions Additional functions COMP1_INP 21 RF1 I/O RF (4) 22 VSSRF S - - - - 23 VDDRF S - - - - RF (5) - - - - 24 OSC_OUT O 25 OSC_IN I RF (5) 26 AT0 O RF (6) - - - - 27 AT1 O RF (6) 28 PB0 I/O TT (7) COMP1_OUT, CM4_EVENTOUT, RF_TX_MOD_EXT_PA - 29 PB1 I/O TT (7) LPUART1_RTS_DE, LPTIM2_IN1, CM4_EVENTOUT - 30 PE4 I/O FT - CM4_EVENTOUT - 31 VFBSMPS S - - - - 32 VSSSMPS S - - - - 33 VLXSMPS S - - - - 34 VDDSMPS S - - - - 35 VDD S - - - - 36 PA10 I/O FT_f - TIM1_CH3, SAI1_PDM_DI1, I2C1_SDA, USART1_RX, USB_CRS_SYNC, SAI1_SD_A, TIM17_BKIN, CM4_EVENTOUT 37 PA11 I/O FT_u - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, USB_DM, CM4_EVENTOUT - 38 PA12 I/O FT_u - TIM1_ETR, SPI1_MOSI, LPUART1_RX, USART1_RTS_DE, USB_DP, CM4_EVENTOUT - 39 PA13 (JTMS-SWDIO) I/O FT (8) JTMS-SWDIO, IR_OUT, USB_NOE, SAI1_SD_B, CM4_EVENTOUT - 40 VDDUSB S - - - DS11929 Rev 11 - - 71/193 80 Pinouts and pin description STM32WB55xx STM32WB35xx Number Name (function after reset) Pin type I/O structures Notes Table 17. STM32WB35xx pin and ball definitions (continued) Alternate functions 41 PA14 (JTCK-SWCLK) I/O FT (8) JTCK-SWCLK, LPTIM1_OUT, I2C1_SMBA, SAI1_FS_B, CM4_EVENTOUT - 42 PA15 (JTDI) I/O FT (8) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS, CM4_EVENTOUT, MCO - 43 PB3 (JTDO) I/O FT_a - JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, USART1_RTS_DE, SAI1_SCK_B, CM4_EVENTOUT COMP2_INM 44 PB4 (NJTRST) I/O FT_fa (8) NJTRST, I2C3_SDA, SPI1_MISO, USART1_CTS, SAI1_MCLK_B, TIM17_BKIN, CM4_EVENTOUT COMP2_INP Pin 45 PB5 I/O FT_a - LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, LPUART1_TX, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, CM4_EVENTOUT Additional functions - 46 PB6 I/O FT_fa - LPTIM1_ETR, I2C1_SCL, USART1_TX, SAI1_FS_B, TIM16_CH1N, MCO, CM4_EVENTOUT 47 PB7 I/O FT_fa - LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, TIM17_CH1N, COMP2_INM, PVD_IN CM4_EVENTOUT 48 VDD S - - COMP2_INP - - 1. PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the use of the PC14 and PC15 GPIOs in output mode is limited: - the speed must not exceed 2 MHz with a maximum load of 30 pF - these GPIOs must not be used as current sources (e.g. to drive a LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the reference manual RM0434, available on www.st.com. 3. The clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes. 4. RF pin, use the nominal PCB layout. 5. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165). 6. Reserved, must be kept unconnected. 7. High frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0 and 1) during RF operation. 8. After reset these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and PB4 pins and the internal pull-down on PA14 pin are activated. 72/193 DS11929 Rev 11 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2/ SAI1/ TIM1 I2C1/ I2C3 SPI1/ SPI2 RF USART1 LPUART1 TSC USB/ QUADSPI LCD COMP1/ COMP2/ TIM1 SAI1 TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PA0 - TIM2_ CH1 - - - - - - - - - - COMP1_ OUT SAI1_ EXTCLK TIM2_ ETR CM4_ EVENTOUT PA1 - TIM2_ CH2 - - I2C1_ SMBA SPI1_ SCK - - - - LCD_SEG0 - - - CM4_ EVENTOUT PA2 LSCO TIM2_ CH3 - - - - - - LPUART1 _TX - QUADSPI_ BK1_NCS LCD_SEG1 COMP2_ OUT - - CM4_ EVENTOUT PA3 - TIM2_ CH4 - SAI1_ PDM_CK1 - - - - LPUART1 _RX - QUADSPI_ CLK LCD_SEG2 - SAI1 _MCLK_A - CM4_ EVENTOUT PA4 - - - - SPI1_ NSS - - - - - LCD_SEG5 - SAI1 _FS_B LPTIM2_ OUT CM4_ EVENTOUT PA5 - TIM2_ CH1 TIM2_ ETR - SPI1_ SCK - - - - - - - SAI1 _SD_B LPTIM2_ ETR CM4_ EVENTOUT PA6 - TIM1_ BKIN - - SPI1_ MISO - - LPUART1 _CTS - QUADSPI_ BK1_IO3 LCD_SEG3 TIM1_ BKIN - TIM16 _CH1 CM4_ EVENTOUT PA7 - TIM1_ CH1N - - I2C3_ SCL SPI1_ MOSI - - - - QUADSPI_ BK1_IO2 LCD_SEG4 COMP2_ OUT - TIM17 _CH1 CM4_ EVENTOUT PA8 MCO TIM1_ CH1 - SAI1_ PDM_CK2 - - - USART1_ CK - - LCD_COM0 - SAI1 _SCK_A LPTIM2_ OUT CM4_ EVENTOUT PA9 - TIM1_ CH2 - SAI1_ PDM_DI2 I2C1_ SCL SPI2_ SCK - USART1_ TX - - LCD_COM1 - SAI1 _FS_A - CM4_ EVENTOUT PA10 - TIM1_ CH3 - SAI1_ PDM_DI1 I2C1_ SDA - USART1_ RX - - USB_CRS _SYNC LCD_COM2 - SAI1 _SD_A TIM17 _BKIN CM4_ EVENTOUT PA11 - TIM1_ CH4 TIM1_ BKIN2 - - SPI1_ MISO - USART1_ CTS - - USB_DM - TIM1_ BKIN2 - - CM4_ EVENTOUT PA12 - TIM1_ ETR - - - SPI1_ MOSI - USART1_ RTS_DE LPUART1 _RX - USB_DP - - - - CM4_ EVENTOUT PA13 JTMSSWDIO - - - - - - - IR_OUT - USB_NOE - - SAI1 _SD_B - CM4_ EVENTOUT PA14 JTCKSWCLK LPTIM1_ OUT - - I2C1_ SMBA - - - - - - LCD_SEG5 - SAI1 _FS_B - CM4_ EVENTOUT PA15 JTDI TIM2_ CH1 TIM2_ ETR - SPI1_ NSS MCO - - - LCD_SEG17 - - - CM4_ EVENTOUT Port DS11929 Rev 11 A 73/193 Pinouts and pin description AF0 STM32WB55xx STM32WB35xx Table 18. Alternate functions (STM32WB55xx) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2/ SAI1/ TIM1 I2C1/ I2C3 SPI1/ SPI2 RF USART1 LPUART1 TSC USB/ QUADSPI LCD COMP1/ COMP2/ TIM1 SAI1 TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PB0 - - - - - - RF_TX_ MOD_ EXT_PA - - - - COMP1_ OUT - - CM4_ EVENTOUT PB1 - - - - - - - - LPUART1 _RTS_DE - - - - - LPTIM2_ IN1 CM4_ EVENTOUT PB2 RTC_ OUT LPTIM1_ OUT - - I2C3_ SMBA SPI1_ NSS - - - - - LCD_VLCD - SAI1_ EXTCLK - CM4_ EVENTOUT PB3 JTDOTRACE SWO TIM2_ CH2 - - - SPI1_ SCK - USART1_ RTS_DE - - - LCD_SEG7 - SAI1_ SCK_B - CM4_ EVENTOUT PB4 NJTRST - - - I2C3_ SDA SPI1_ MISO - USART1_ CTS - TSC_G2 _IO1 - LCD_SEG8 - SAI1_ MCLK_B TIM17_ BKIN CM4_ EVENTOUT PB5 - LPTIM1_ IN1 - - I2C1_ SMBA SPI1_ MOSI - USART1_ CK LPUART1 _TX TSC_G2 _IO2 - LCD_SEG9 COMP2_ OUT SAI1_ SD_B TIM16_ BKIN CM4_ EVENTOUT PB6 MCO LPTIM1_ ETR - - I2C1_ SCL - - USART1_ TX - TSC_G2 _IO3 - LCD_SEG6 - SAI1_ FS_B TIM16_ CH1N CM4_ EVENTOUT PB7 - LPTIM1_ IN2 - TIM1_ BKIN I2C1_ SDA - - USART1_ RX - TSC_G2 _IO4 - LCD_SEG21 - - TIM17_ CH1N CM4_ EVENTOUT PB8 - TIM1_ CH2N - SAI1_ PDM_CK1 I2C1_ SCL - - - - - QUADSPI_ LCD_SEG16 BK1_IO1 - SAI1_ MCLK_A TIM16_ CH1 CM4_ EVENTOUT PB9 - TIM1_ CH3N - SAI1_ PDM_DI2 I2C1_ SDA SPI2_ NSS - - IR_OUT TSC_G7 _IO4 QUADSPI_ BK1_IO0 - SAI1_ FS_A TIM17_ CH1 CM4_ EVENTOUT PB10 - TIM2_ CH3 - - I2C3_ SCL SPI2_SC K - - LPUART1 _RX TSC _SYNC QUADSPI_ COMP1_ LCD_SEG10 CLK OUT SAI1_ SCK_A - CM4_ EVENTOUT PB11 - TIM2_ CH4 - - I2C3_ SDA - - - LPUART1 _TX - COMP2_ OUT - - CM4_ EVENTOUT PB12 - TIM1_ BKIN - TIM1_ BKIN I2C3_ SMBA SPI2_ NSS - - LPUART1 _RTS TSC_G1 _IO1 - LCD_SEG12 - SAI1_ FS_A - CM4_ EVENTOUT PB13 - TIM1_ CH1N - - I2C3_ SCL SPI2_ SCK - - LPUART1 _CTS TSC_G1 _IO2 - LCD_SEG13 - SAI1_ SCK_A - CM4_ EVENTOUT PB14 - TIM1_ CH2N - - I2C3_ SDA SPI2_ MISO - - - TSC_G1 _IO3 - LCD_SEG14 - SAI1_ MCLK_A - CM4_ EVENTOUT PB15 RTC_ REFIN TIM1_ CH3N - - - SPI2_ MOSI - - - TSC_G1 _IO4 - LCD_SEG15 - SAI1_ SD_A - CM4_ EVENTOUT Port DS11929 Rev 11 B LCD_COM3 QUADSPI_ LCD_SEG11 BK1_NCS STM32WB55xx STM32WB35xx AF0 Pinouts and pin description 74/193 Table 18. Alternate functions (STM32WB55xx) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2/ SAI1/ TIM1 I2C1/ I2C3 SPI1/ SPI2 RF USART1 LPUART1 TSC USB/ QUADSPI LCD COMP1/ COMP2/ TIM1 SAI1 TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PC0 - LPTIM1_ IN1 - - I2C3 _SCL - - - LPUART1 _RX - - LCD_SEG18 - - LPTIM2_ IN1 CM4_ EVENTOUT PC1 - LPTIM1_ OUT - SPI2_ MOSI I2C3 _SDA - - LPUART1 _TX - - LCD_SEG19 - - - CM4_ EVENTOUT PC2 - LPTIM1_ IN2 - - - SPI2_ MISO - - - - - LCD_SEG20 - - - CM4_ EVENTOUT PC3 - LPTIM1_ ETR - SAI1_ PDM_DI1 - SPI2_ MOSI - - - - - LCD_VLCD - SAI1 _SD_A LPTIM2_ ETR CM4_ EVENTOUT PC4 - - - - - - - - - - - LCD_SEG22 - - - CM4_ EVENTOUT PC5 - - - SAI1_ PDM_DI3 - - - - - - - LCD_SEG23 - - - CM4_ EVENTOUT PC6 - - - - - - - - - TSC_G4 _IO1 - LCD_SEG24 - - - CM4_ EVENTOUT PC7 - - - - - - - - - TSC_G4 _IO2 - LCD_SEG25 - - - CM4_ EVENTOUT PC8 - - - - - - - - - TSC_G4 _IO3 - LCD_SEG26 - - - CM4_ EVENTOUT PC9 - - - TIM1 _BKIN - - - - - TSC_G4 _IO4 USB_NOE LCD_SEG27 - SAI1 _SCK_B - CM4_ EVENTOUT PC10 TRACE D1 - - - - - - - - TSC_G3 _IO2 - LCD_COM4 LCD_SEG28 LCD_SEG40 - - - CM4_ EVENTOUT PC11 - - - - - - - - - TSC_G3 _IO3 - LCD_COM5 LCD_SEG29 LCD_SEG41 - - - CM4_ EVENTOUT PC12 TRACE D3 - - - - - LSCO - - TSC_G3 _IO4 - LCD_COM6 LCD_SEG30 LCD_SEG42 - - - CM4_ EVENTOUT PC13 - - - - - - - - - - - - - - - CM4_ EVENTOUT PC14 - - - - - - - - - - - - - - - CM4_ EVENTOUT PC15 - - - - - - - - - - - - - - - CM4_ EVENTOUT Port DS11929 Rev 11 C 75/193 Pinouts and pin description AF0 STM32WB55xx STM32WB35xx Table 18. Alternate functions (STM32WB55xx) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2/ SAI1/ TIM1 I2C1/ I2C3 SPI1/ SPI2 RF USART1 LPUART1 TSC USB/ QUADSPI LCD COMP1/ COMP2/ TIM1 SAI1 TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PD0 - - - - - SPI2_ NSS - - - - - - - - - CM4_ EVENTOUT PD1 - - - - - SPI2_ SCK - - - - - - - - - CM4_ EVENTOUT PD2 TRACE D2 - - - - - - - - TSC_ SYNC - LCD_COM7 LCD_SEG31 LCD_SEG43 - - - CM4_ EVENTOUT PD3 - - - SPI2_SCK - SPI2_ MISO - - - - QUADSPI_ BK1_NCS - - - - CM4_ EVENTOUT PD4 - - - - - SPI2_ MOSI - - - TSC_ G5_IO1 QUADSPI_ BK1_IO0 - - - - CM4_ EVENTOUT PD5 - - - - - - - - - TSC_ G5_IO2 QUADSPI_ BK1_IO1 - - SAI1_ MCLK_B - CM4_ EVENTOUT PD6 - - - SAI1_ PDM_DI1 - - - - - TSC_ G5_IO3 QUADSPI_ BK1_IO2 - - SAI1_ SD_A - CM4_ EVENTOUT PD7 - - - - - - - - - TSC_ G5_IO4 QUADSPI_ LCD_SEG39 BK1_IO3 - - - CM4_ EVENTOUT PD8 - - TIM1 _BKIN2 - - - - - - - - LCD_SEG28 - - - CM4_ EVENTOUT PD9 TRACE D0 - - - - - - - - - - LCD_SEG29 - - - CM4_ EVENTOUT PD10 TRIG _INOUT - - - - - - - - TSC_ G6_IO1 - LCD_SEG30 - - - CM4_ EVENTOUT PD11 - - - - - - - - - TSC_ G6_IO2 - LCD_SEG31 - - LPTIM2_ ETR CM4_ EVENTOUT PD12 - - - - - - - - - TSC_ G6_IO3 - LCD_SEG32 - - LPTIM2_ IN1 CM4_ EVENTOUT PD13 - - - - - - - - - TSC_ G6_IO4 - LCD_SEG33 - - LPTIM2_ OUT CM4_ EVENTOUT PD14 - TIM1_ CH1 - - - - - - - - - LCD_SEG34 - - - CM4_ EVENTOUT PD15 - TIM1_ CH2 - - - - - - - - - LCD_SEG35 - - - CM4_ EVENTOUT Port DS11929 Rev 11 D STM32WB55xx STM32WB35xx AF0 Pinouts and pin description 76/193 Table 18. Alternate functions (STM32WB55xx) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2/ SAI1/ TIM1 I2C1/ I2C3 SPI1/ SPI2 RF USART1 LPUART1 TSC USB/ QUADSPI LCD COMP1/ COMP2/ TIM1 SAI1 TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PE0 - TIM1_ ETR - - - - - - - TSC_ G7_IO3 - LCD_SEG36 - - TIM16_ CH1 CM4_ EVENTOUT PE1 - - - - - - - - - TSC_ G7_IO2 - LCD_SEG37 - - TIM17_ CH1 CM4_ EVENTOUT PE2 TRACECK - - SAI1_ PDM_CK1 - - - - - TSC_ G7_IO1 - LCD_SEG38 - SAI1_ MCLK_A - CM4_ EVENTOUT PE3 - - - - - - - - - - - - - - - CM4_ EVENTOUT PE4 - - - - - - - - - - - - - - - CM4_ EVENTOUT PH0 - - - - - - - - - - - - - - - CM4_ EVENTOUT PH1 - - - - - - - - - - - - - - - CM4_ EVENTOUT PH3 LSCO - - - - - - - - - - - - - - CM4_ EVENTOUT Port E DS11929 Rev 11 H STM32WB55xx STM32WB35xx Table 18. Alternate functions (STM32WB55xx) (continued) Pinouts and pin description 77/193 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF10 AF12 AF13 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SAI1/ TIM1 I2C1/ I2C3 SPI1 RF USART1 LPUART1 USB/ QUADSPI COMP1/ COMP2/ TIM1 SAI1 TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PA0 - TIM2_ CH1 - - - - - - - - COMP1_ OUT SAI1_ EXTCLK TIM2_ ETR CM4_ EVENTOUT PA1 - TIM2_ CH2 - - I2C1_ SMBA SPI1_ SCK - - - - - - CM4_ EVENTOUT PA2 LSCO TIM2_ CH3 - - - - - - LPUART1 _TX QUADSPI_ COMP2_ BK1_NCS OUT - - CM4_ EVENTOUT PA3 - TIM2_ CH4 - SAI1_ PDM_CK1 - - - - LPUART1 _RX QUADSPI_ CLK - SAI1 _MCLK_A - CM4_ EVENTOUT PA4 - - - - SPI1_ NSS - - - - - SAI1 _FS_B LPTIM2_ OUT CM4_ EVENTOUT PA5 - TIM2_ CH1 TIM2_ ETR - SPI1_ SCK - - - - - SAI1 _SD_B LPTIM2_ ETR CM4_ EVENTOUT PA6 - TIM1_ BKIN - - SPI1_ MISO - - LPUART1 _CTS QUADSPI_ BK1_IO3 TIM1_ BKIN - TIM16 _CH1 CM4_ EVENTOUT PA7 - TIM1_ CH1N - - I2C3_ SCL SPI1_ MOSI - - - - TIM17 _CH1 CM4_ EVENTOUT PA8 MCO TIM1_ CH1 - SAI1_ PDM_CK2 - - - USART1_ CK - - SAI1 _SCK_A LPTIM2_ OUT CM4_ EVENTOUT PA9 - TIM1_ CH2 - SAI1_ PDM_DI2 I2C1_ SCL - - USART1_ TX - - SAI1 _FS_A - CM4_ EVENTOUT PA10 - TIM1_ CH3 - SAI1_ PDM_DI1 I2C1_ SDA - - USART1_ RX - USB_CRS _SYNC - SAI1 _SD_A TIM17 _BKIN CM4_ EVENTOUT PA11 - TIM1_ CH4 TIM1_ BKIN2 - - SPI1_ MISO - USART1_ CTS - USB_DM TIM1_ BKIN2 - - CM4_ EVENTOUT PA12 - TIM1_ ETR - - - SPI1_ MOSI - USART1_ RTS_DE LPUART1 _RX USB_DP - - - CM4_ EVENTOUT PA13 JTMSSWDIO - - - - - - - IR_OUT USB_NOE - SAI1 _SD_B - CM4_ EVENTOUT PA14 JTCKSWCLK LPTIM1_ OUT - - I2C1_ SMBA - - - - - - SAI1 _FS_B - CM4_ EVENTOUT PA15 JTDI TIM2_ CH1 TIM2_ ETR - SPI1_ NSS MCO - - - - - - CM4_ EVENTOUT Port DS11929 Rev 11 A QUADSPI_ COMP2_ BK1_IO2 OUT STM32WB55xx STM32WB35xx AF0 Pinouts and pin description 78/193 Table 19. Alternate functions (STM32WB35xx) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF10 AF12 AF13 AF14 AF15 SYS_AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SAI1/ TIM1 I2C1/ I2C3 SPI1 RF USART1 LPUART1 USB/ QUADSPI COMP1/ COMP2/ TIM1 SAI1 TIM2/ TIM16/ TIM17/ LPTIM2 EVENTOUT PB0 - - - - - - RF_TX_ MOD_EXT_PA - - COMP1_ OUT - - CM4_ EVENTOUT PB1 - - - - - - - - LPUART1 _RTS_DE - - - LPTIM2_ IN1 CM4_ EVENTOUT PB2 RTC_ OUT LPTIM1_ OUT - - I2C3_ SMBA SPI1_ NSS - - - - - SAI1_ EXTCLK - CM4_ EVENTOUT PB3 JTDOTRACE SWO TIM2_ CH2 - - - SPI1_ SCK - USART1_ RTS_DE - - - SAI1_ SCK_B - CM4_ EVENTOUT PB4 NJTRST - - - I2C3_ SDA SPI1_ MISO - USART1_ CTS - - - SAI1_ MCLK_B TIM17_ BKIN CM4_ EVENTOUT PB5 - LPTIM1_ IN1 - - I2C1_ SMBA SPI1_ MOSI - USART1_ CK LPUART1 _TX - COMP2_ OUT SAI1_ SD_B TIM16_ BKIN CM4_ EVENTOUT PB6 MCO LPTIM1_ ETR - - I2C1_ SCL - - USART1_ TX - - - SAI1_ FS_B TIM16_ CH1N CM4_ EVENTOUT PB7 - LPTIM1_ IN2 - TIM1_ BKIN I2C1_ SDA - - USART1_ RX - - - - TIM17_ CH1N CM4_ EVENTOUT PB8 - TIM1_ CH2N - SAI1_ PDM_CK1 I2C1_ SCL - - - - QUADSPI_ BK1_IO1 - SAI1_ MCLK_A TIM16_ CH1 CM4_ EVENTOUT PB9 - TIM1_ CH3N - SAI1_ PDM_DI2 I2C1_ SDA - - - IR_OUT QUADSPI_ BK1_IO0 - SAI1_ FS_A TIM17_ CH1 CM4_ EVENTOUT PC14 - - - - - - - - - - - - - CM4_ EVENTOUT PC15 - - - - - - - - - - - - - CM4_ EVENTOUT E PE4 - - - - - - - - - - - - - CM4_ EVENTOUT H PH3 LSCO - - - - - - - - - - - - CM4_ EVENTOUT Port DS11929 Rev 11 B C 79/193 Pinouts and pin description AF0 STM32WB55xx STM32WB35xx Table 19. Alternate functions (STM32WB35xx) (continued) Memory mapping 5 STM32WB55xx STM32WB35xx Memory mapping The STM32WB55xx and STM32WB35xx devices feature a single physical address space that can be accessed by the application processor and by the RF subsystem. A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure, exclusively accessible by the CPU2, protected against execution, read and write from CPU1 and DMA. In case of shared resources the SW should implement arbitration mechanism to avoid access conflicts. This happens for peripherals Reset and Clock Controller (RCC), Power Controller (PWC), EXTI and Flash interface, and can be implemented using the built-in semaphore block (HSEM). By default the RF subsystem and CPU2 operate in secure mode. This implies that part of the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by the CPU2. In this case the Host processor (CPU1) has no access to these resources. The detailed memory map and the peripheral mapping can be found in the reference manual RM0434. 80/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on VDD = VDDA = VDDRF = 3 V and  TA = 25 °C. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 14. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 15. Figure 14. Pin loading conditions Figure 15. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 DS11929 Rev 11 MS19211V1 81/193 169 Electrical characteristics 6.1.6 STM32WB55xx STM32WB35xx Power supply scheme Figure 16. Power supply scheme (all packages except UFBGA129 and WLCSP100) VBAT Backup circuitry (LSE, RTC and backup registers) 1.55 V to 3.6 V Power switch VDD VCORE n x VDD Regulator VDDIO1 Level shifter OUT GPIOs n x 100 nF + 1 x 4.7 μF IN IO logic Kernel logic (CPU, digital and memories VSS VDDA VDDA VREF 10 nF + 1 μF VREF+(2) 100 nF + 1 μF ADC COMPs VREFVSS VDD VDDSMPS SMPS SMPS Regulator VLXSMPS 4.7 μF L1 (1) VFBSMPS 4.7 μF VSSSMPS VDD USB transceiver VDDUSB VDD 100 nF 100 nF + 100 pF VDDRF Radio VSSRF Exposed pad VSS To all modules MS53167V5 1. The value of L1 depends upon the frequency, as indicated in Table 6. 2. VREF+ connection is not available on UFQFPN48 package. 82/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Figure 17. Power supply scheme (UFBGA129 and WLCSP100 packages) VDD_DCAPx(2) 1 x 100 nF VSS_DCAPx(2) Backup circuitry (LSE, RTC and backup registers) VBAT 1.55 to 3.6 V Power switch VDD VCORE n x VDD Regulator OUT n x 100 nF + 1 x 4.7 μF(3) GPIOs IN Level shifter VDDIO1 IO logic Kernel logic (CPU, digital and memories n x VSS VDDA VDDA VREF VREF+ 10 nF + 1 μF 100 nF 1 μF VREF- ADCs OPAMPs COMPs VREFBUF VSSA VDD VDDSMPS SMPS SMPS Regulator VLXSMPS 4.7 μF L1(1) VFBSMPS 4.7 μF VSSSMPS VDD VDDUSB 100 nF VDD 100 nF + 100 pF USB transceiver VDDRF VSSRF Radio MS53132V2 1. The value of L1 depends upon the frequency, as indicated in Table 6. 2. For UFBGA129 package VDD_DCAPx and VSS_DCAPx balls are connected to VDD and VSS internally, to simplify the 2-layer board layout and especially the ground plane below the BGA. VDD power supply can be made with a single connection to the center of the BGA on the board bottom layer. The decoupling 100 nF capacitors are connected without cutting the board ground plane. 3. n x 100 nF only for WLCSP package. DS11929 Rev 11 83/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Caution: Each power supply pair (VDD / VSS, VDDA / VSSA etc.) must be decoupled with filtering ceramic capacitors as shown in Figure 16. These capacitors must be placed as close as possible to (or below) the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 6.1.7 Current consumption measurement Figure 18. Current consumption measurement scheme IDDSMPS VDDSMPS IDDRF VDDRF IDDUSB VDDUSB IDDVBAT VBAT IDD VDD IDDA VDDA MS45416V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 20, Table 21 and Table 22 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. 84/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Table 20. Voltage characteristics(1) Symbol VDDX - VSS Ratings External main supply voltage (including VDD, VDDA, VDDUSB, VLCD, VDDRF, VDDSMPS, VBAT, VREF+) Min Max -0.3 4.0 Input voltage on FT_xxx pins VIN(2) VSS-0.3 Input voltage on TT_xx pins min (VDD, VDDA, VDDUSB, VLCD, VDDRF, VDDSMPS) + 4.0(3)(4) |VSSx-VSS| V 4.0 Input voltage on any other pin |∆VDDx| Unit 4.0 Variations between different VDDX power pins of the same domain - 50 Variations between all the different ground pins(5) - 50 - 0.4 VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA mV V 1. All main power (VDD, VDDRF, VDDA, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 21 for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 5. Include VREF- pin. Table 21. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) 130 ∑IVSS Total current out of sum of all VSS ground lines (sink) (1) 130 IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100 IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100 Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 IIO(PIN) ∑IIO(PIN) IINJ(PIN)(3) ∑|IINJ(PIN)| Total output current sunk by sum of all I/Os and control pins(2) Total output current sourced by sum of all I/Os and control pins Unit mA 100 (2) Injected current on FT_xxx, TT_xx, RST and B pins, except PB0 and PB1 100 –5 / +0(4) Injected current on PB0 and PB1 -5/0 Total injected current (sum of all I/Os and control pins)(5) 25 1. All main power (VDD, VDDRF, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count packages. 3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values. DS11929 Rev 11 85/193 169 Electrical characteristics STM32WB55xx STM32WB35xx 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). Table 22. Thermal characteristics Symbol TSTG TJ 86/193 Ratings Storage temperature range Maximum junction temperature DS11929 Rev 11 Value –65 to +150 130 Unit °C STM32WB55xx STM32WB35xx Electrical characteristics 6.3 Operating conditions 6.3.1 Summary of main performance Table 23. Main performance at VDD = 3.3 V Parameter Test conditions Typ VBAT (VBAT = 1.8 V, VDD = 0 V) 0.002 Shutdown (VDD = 1.8 V) 0.013 Standby (VDD = 1.8 V, 32 Kbytes RAM retention) 0.320 Stop2 1.85 Sleep (16 MHz) 740 LP run (2 MHz) 320 Run (64 MHz) 5000 Core current ICORE consumption Radio RX (1) 4500 Radio TX 0 dBm output IPERI Peripheral current consumption power(1) 5200 Advertising with Stop 2(2) (Tx = 0 dBm; Period 1.28 s; 31 bytes, 3 channels) 13 Advertising with Stop 2(2) (Tx = 0 dBm, 6 bytes; period 10.24 s, 3 channels) 4 LP timers - 6 I2C3 - 7.1 LPUART - 7.7 RTC - 2.5 BLE Unit µA 1. Power consumption including RF subsystem and digital processing. 2. Power consumption integrated over 100 s, including Cortex-M4, RF subsystem, digital processing and Cortex-M0+. 6.3.2 General operating conditions Table 24. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 64 fPCLK1 Internal APB1 clock frequency - 0 64 fPCLK2 Internal APB2 clock frequency - 0 64 Standard operating voltage - 1.71(1)(2) 3.6 VDD VDDA VBAT Analog supply voltage ADC or COMP used 1.62 VREFBUF used 2.4 ADC, COMP, VREFBUF not used Backup operating voltage - DS11929 Rev 11 3.6 Unit MHz V 0 1.55 3.6 87/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 24. General operating conditions (continued) Symbol Parameter Conditions Min Max - 1.4 3.6 - 1.71 3.6 3.0 3.6 0 3.6 TT_xx I/O –0.3 VDD + 0.3 All I/O except TT_xx –0.3 min (min (VDD, VDDA, VDDUSB, VLCD) + 3.6 V, 5.5 V)(3)(4) UFQFPN48 - 803 VFQFPN68 - 425 WLCSP100 - 558 UFBGA129 - 481 VFBSMPS SMPS Feedback voltage VDDRF Minimum RF voltage USB used VDDUSB USB supply voltage USB not used VIN I/O input voltage PD Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(5) Ambient temperature for the suffix 6 version Maximum power dissipation Ambient temperature for the suffix 7 version Maximum power dissipation TA TJ Junction temperature range Low-power dissipation(6) Low-power dissipation(6) Suffix 6 version V mW 85 –40 105 105 –40 °C 125 105 –40 Suffix 7 version Unit 125 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. When VDDmin is lower then 1.95 V, the SMPS operation mode must be conditioned by enabling the BORH configuration to force SMPS bypass mode, or the SMPS must not be enabled. 3. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between min (VDD, VDDA, VDDUSB, VLCD) + 3.6 V and 5.5V. 4. For operation with voltage higher than min (VDD, VDDA, VDDUSB, VLCD) + 0.3 V, the internal pull-up and pull-down resistors must be disabled. 5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics). 6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics). 6.3.3 RF BLE characteristics RF characteristics are given at 1 Mbps, unless otherwise specified. Table 25. RF transmitter BLE characteristics Symbol Parameter Test conditions Min Typ Max Fop Frequency operating range - 2402 - 2480 Fxtal Crystal frequency - - 32 - ∆F Delta frequency - - 250 - 88/193 DS11929 Rev 11 Unit MHz kHz STM32WB55xx STM32WB35xx Electrical characteristics Table 25. RF transmitter BLE characteristics (continued) Symbol Rgfsk PLLres Parameter Test conditions Min Typ Max Unit On Air data rate - - 1 2 Mbps RF channel spacing - - 2 - MHz Table 26. RF transmitter BLE characteristics (1 Mbps)(1) Symbol Parameter Test conditions Maximum output power Prf Pband BW6dB IBSE fd Min Typ Max SMPS Bypass or  ON (VFBSMPS = 1.7 V and VDD > 1.95 V)(2) - 6.0 - SMPS Bypass (VDD > 1.71 V) or ON (VFBSMPS = 1.4 V and VDD > 1.95 V), Code 29(2) - 3.7 - - - 0 - Minimum output power - - -20 - -0.5 - 0.4 dB kHz Output power variation over the band Tx = 0 dBm - Typical Tx = maximum output power 6 dB signal bandwidth In band spurious emission - 670 - ® - -50 - ® Bluetooth Low Energy: -30 dBm - -53 - Bluetooth® Low Energy: ±50 kHz -50 - +50 kHz kHz/ 50 µs Bluetooth Low Energy: -20 dBm 2 MHz ≥ 3 MHz Frequency drift Maximum drift rate Bluetooth Low Energy: ±20 kHz / 50 µs -20 - +20 Frequency offset Bluetooth® Low Energy:  ±150 kHz -150 - +150 ∆f1 Frequency deviation average Bluetooth® Low Energy:  between 225 and 275 kHz 225 - 275 ∆fa Frequency deviation ∆f2 (average) / ∆f1 (average) Bluetooth® Low Energy:> 0.80 0.80 - - fo OBSE(3) dBm 0 dBm output power ® maxdr Unit Out of band spurious emission dBm kHz < 1 GHz - - -61 - ≥ 1 GHz - - -46 - dBm 1. Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and impedance matching networks to interface with a 50 Ω antenna. 2. VFBSMPS and VDD must be set to different voltage levels, depending upon the desired TX signal (see AN5246 Usage of SMPS on STM32WB Series microcontrollers, available on www.st.com). 3. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan). DS11929 Rev 11 89/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 27. RF transmitter BLE characteristics (2 Mbps)(1) Symbol Parameter Test conditions Maximum output power Prf Pband BW6dB maxdr fo SMPS Bypass or ON (VFBSMPS = 1.7 V and VDD > 1.95 V)(2) - 6.0 - SMPS Bypass or ON (VFBSMPS = 1.4 V and VDD > 1.71 V), Code 29(2) - 3.7 - Unit dBm - 0 - Minimum output power - - -20 - -0.5 - 0.4 dB kHz Output power variation over the band Tx = 0 dBm - Typical 6 dB signal bandwidth Tx = maximum output power - 670 - Bluetooth® Low Energy: -20 dBm - -56 - - -57 - dBm In band spurious emission 5 MHz ® Bluetooth Low Energy: -20 dBm ® Bluetooth Low Energy: -30 dBm -58 Frequency drift Bluetooth® Low Energy: ±50 kHz -50 - 50 kHz Maximum drift rate Bluetooth® Low Energy: ±20 kHz / 50 µs -20 - 20 kHz/ 50 µs Frequency offset Bluetooth® Low Energy: ±150 kHz -150 - 150 ∆f1 Frequency deviation average ∆fa Frequency deviation ∆f2 (average) / ∆f1 (average) OBSE(3) Max - ≥ 6 MHz fd Typ 0 dBm output power 4 MHz IBSE Min Out of band spurious emission Bluetooth® Low Energy:  between 450 and 550 kHz 450 - 550 Bluetooth® Low Energy:> 0.80 0.80 - - < 1 GHz - - -61 - ≥ 1 GHz - - -46 - kHz dBm 1. Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and impedance matching networks to interface with a 50 Ω antenna. 2. VFBSMPS and VDD must be set to different voltage levels, depending upon the desired TX signal (see AN5246 Usage of SMPS on STM32WB Series microcontrollers, available on www.st.com). 3. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan). 90/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Table 28. RF receiver BLE characteristics (1 Mbps) Symbol Prx_max Psens(1) Parameter Test conditions Maximum input signal PER 3.5 MHz - -35 - dB Maximum output power(1) Prf Pband Output power variation over the band Tx = 0 dBm - Typical EVMrms EVM rms Txpd Transmit power density Unit dBm 1. Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and impedance matching networks to interface with a 50 Ω antenna. Table 32. RF receiver 802.15.4 characteristics Symbol Parameter Prx_max Maximum input signal Sensitivity (SMPS Bypass) Rsens Conditions Typ Min: -20 dBm and PER < 1% -10 Max: -85 dBm and PER < 1% Sensitivity (SMPS ON) -100 Unit dBm -98 C/adj Adjacent channel rejection - 35 C/alt Alternate channel rejection - 46 dB Figure 19. Typical link quality indicator code vs. Rx level 240 220 TEST_NAME TP/154/PHY24/RECEIVERͲ06/Ch11(2405MHz) 200 180 LQI 160 TP/154/PHY24/RECEIVERͲ06/Ch19(2445MHz) TP/154/PHY24/RECEIVERͲ06/Ch26(2480MHz) 140 120 100 80 60 40 20 0 -120 -115-110 -105-100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 Pin (dBm) PARAM2 94/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Figure 20. Typical energy detection (T = 27°C, VDD = 3.3 V) 240 224 208 192 176 160 128 ED 144 112 96 80 64 48 32 16 0 Input power Table 33. RF 802.15.4 power consumption for VDD = 3.3 V(1) Symbol Itxmax Itx0dbm Irxlo Parameter Typ TX maximum output power consumption (SMPS Bypass) 11.7 TX maximum output power consumption (SMPS On, VFBSMPS = 1.7 V) 6.5 TX 0 dBm output power consumption (SMPS Bypass) 9.1 TX 0 dBm output power consumption (SMPS On, VFBSMPS = 1.4 V) 4.5 Rx consumption (SMPS Bypass) 9.2 Rx consumption (SMPS On) 4.5 Unit mA 1. Power consumption including RF subsystem and digital processing. DS11929 Rev 11 95/193 169 Electrical characteristics 6.3.5 STM32WB55xx STM32WB35xx Operating conditions at power-up / power-down The parameters given in Table 34 are derived from tests performed under the ambient temperature condition summarized in Table 24. Table 34. Operating conditions at power-up / power-down Symbol tVDD tVDDA tVDDUSB tVDDRF 6.3.6 Parameter Conditions VDD rise time rate - VDD fall time rate VDDA rise time rate - VDDA fall time rate VDDUSB rise time rate - VDDUSB fall time rate VDDRF rise time rate - VDDRF fall time rate Min Max - ∞ 10 ∞ 0 ∞ 10 ∞ 0 ∞ 10 ∞ - ∞ - ∞ Unit µs/V Embedded reset and power control block characteristics The parameters given in Table 35 are derived from tests performed under the ambient temperature conditions summarized in Table 24: General operating conditions. Table 35. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) Conditions(1) Parameter Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.70 Falling edge 1.60 1.64 1.69 Rising edge 2.06 2.10 2.14 Falling edge 1.96 2.00 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.10 2.15 2.19 Falling edge 2.00 2.05 2.10 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Reset temporization after BOR0 is detected VDD rising VBOR0(2) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 96/193 Min VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 DS11929 Rev 11 V STM32WB55xx STM32WB35xx Electrical characteristics Table 35. Embedded reset and power control block characteristics (continued) Symbol VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_BORH0 Conditions(1) Parameter Hysteresis voltage of BORH0 Min Typ Max Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous mode - 20 - Hysteresis in other mode - 30 - Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - BOR(3) (except BOR0) and PVD consumption from VDD - - 1.1 1.6 VPVM1 VDDUSB peripheral voltage monitoring - 1.18 1.22 1.26 VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 Vhyst_BOR_PVD IDD (BOR_PVD)(2) Vhyst_PVM3 PVM3 hysteresis - - 10 - Vhyst_PVM1 PVM1 hysteresis - - 10 - IDD (PVM1)(2) PVM1 consumption from VDD - - 0.2 - (PVM3)(2) PVM3 consumption from VDD - - 2 - IDD Unit V mV µA V mV µA 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. DS11929 Rev 11 97/193 169 Electrical characteristics 6.3.7 STM32WB55xx STM32WB35xx Embedded voltage reference The parameters given in Table 36 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 36. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +125 °C 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - tstart_vrefint Start time of reference voltage buffer when ADC is enabled - - 8 12(2) IDD(VREFINTBUF) VREFINT buffer consumption from VDD when converted by ADC - - 12.5 20(2) µA ∆VREFINT Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV –40 °C < TA < +125 °C - 30 50(2) ppm/°C 300 1000(2) ppm - 250 1200(2) ppm/V 24 25 26 49 50 51 74 75 76 TCoeff ACoeff VDDCoeff Temperature coefficient Long term stability µs 1000 hours, T = 25 °C Voltage coefficient VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage 3.0 V < VDD < 3.6 V - - % VREFINT 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Figure 21. VREFINT vs. temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 98/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 6.3.8 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 18: Current consumption measurement scheme. Typical and maximum current consumption The MCU is put under the following conditions:  All I/O pins are in analog input mode  All peripherals are disabled except when explicitly mentioned  The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the reference manual).  When the peripherals are enabled fPCLK = fHCLK  For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS The parameters given in Table 37 to Table 48 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. DS11929 Rev 11 99/193 169 Conditions Symbol Parameter - Voltage scaling Range 2 IDD(Run) DS11929 Rev 11 fHCLK = fHSI16 up to 16 MHz included, Supply fHCLK = fHSE = 32 MHz Range 1 current in fHSI16 + PLL ON Run mode above 32 MHz All peripherals disabled SMPS Range 1 Supply current in fHCLK = fMSI IDD(LPRun) Low-power All peripherals disabled run mode Max(1) Typ Unit fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C 16 MHz 1.90 1.90 2.00 2.20 2.40 2.52 2.96 2 MHz 0.960 0.985 1.10 1.25 1.25 1.57 2.05 64 MHz 8.15 8.25 8.40 8.60 9.30 9.60 10.02 32 MHz 4.20 4.25 4.40 4.65 4.25 4.63 5.17 16 MHz 2.25 2.30 2.40 2.65 2.65 2.91 3.52 64 MHz 5.00 5.00 5.10 5.20 - - - 32 MHz 3.15 3.15 3.25 3.35 - - - 16 MHz 2.30 2.30 2.35 2.45 - - - 2 MHz 0.335 0.360 0.470 0.670 0.480 0.910 1.47 1 MHz 0.170 0.210 0.325 0.520 0.270 0.730 1.31 400 kHz 0.0815 0.120 0.230 0.425 0.140 0.590 1.18 100 kHz 0.0415 0.076 0.190 0.385 0.070 0.550 1.14 Electrical characteristics 100/193 Table 37. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V mA 1. Guaranteed by characterization results, unless otherwise specified. STM32WB55xx STM32WB35xx Conditions Symbol Parameter - Voltage scaling Range 2 IDD(Run) fHCLK = fHSI16 up to 16 MHz included, Supply fHCLK = fHSE = 32 MHz Range 1 current in fHSI16 + PLL ON Run mode above 32 MHz All peripherals disabled SMPS Range 1 DS11929 Rev 11 Supply current in fHCLK = fMSI IDD(LPRun) Low-power All peripherals disabled run mode Max(1) Typ Unit fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C 16 MHz 2.00 2.05 2.15 2.30 2.57 3.04 3.64 2 MHz 0.970 1.00 1.10 1.25 1.62 1.90 2.55 64 MHz 8.80 8.90 9.00 9.20 10.50 10.80 11.30 32 MHz 4.50 4.55 4.70 4.90 4.63 4.89 5.62 16 MHz 2.40 2.40 2.55 2.70 2.50 2.70 3.21 64 MHz 5.25 5.30 5.35 5.45 - - - 32 MHz 3.25 3.25 3.35 3.45 - - - 16 MHz 2.35 2.35 2.40 2.45 - - - 2 MHz 0.265 0.285 0.385 0.550 0.440 0.940 1.620 1 MHz 0.135 0.170 0.270 0.430 0.290 0.760 1.480 400 kHz 0.066 0.097 0.195 0.360 0.200 0.670 1.380 100 kHz 0.031 0.0625 0.160 0.325 0.170 0.470 1.330 STM32WB55xx STM32WB35xx Table 38. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, VDD = 3.3 V mA 1. Guaranteed by characterization results, unless otherwise specified. Electrical characteristics 101/193 Electrical characteristics STM32WB55xx STM32WB35xx Table 39. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V Conditions IDD(Run) Supply current in Run mode Supply current in IDD(LPRun) Low-power run Code 25 °C Reduced code(1) 1.90 119 Coremark 1.85 116 Dhrystone 2.1 1.85 Fibonacci 1.75 109 1.60 100 Reduced code 8.15 127 Coremark 8.00 125 Dhrystone 2.1 8.10 Fibonacci 7.60 119 While(1) 6.85 107 5.00 78 Coremark 4.95 77 Dhrystone 2.1 4.95 Fibonacci 4.75 74 While(1) 4.40 69 Reduced code(1) 4.07 64 Coremark 3.99 62 Dhrystone 2.1 4.04 Fibonacci 3.79 59 While(1) 3.42 53 Reduced code(1) 320 160 Coremark 350 175 Dhrystone 2.1 350 Fibonacci 390 195 While(1) 225 113 While(1) Reduced code(1) 1. Reduced code used for characterization results provided in Table 37 and Table 38. 2. Value computed. MCU consumption when RF TX and SMPS are ON. 102/193 Unit 25 °C (1) fHCLK = fMSI = 2 MHz All peripherals disable TYP Unit Voltage scaling Range 2 fHCLK = 16 MHz fHCLK = fHSI16 up to 16 MHz included, fHSI16 + PLL ON above 32 MHz All peripherals disable - Range 1 fHCLK = 64 MHz Parameter Range 1, SMPS On fHCLK = 64 MHz, Range 1, SMPS On When RF Tx fHCLK = 64 MHz level = 0 dBm(2) Symbol TYP DS11929 Rev 11 mA mA mA mA µA 116 127 77 63 175 µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz STM32WB55xx STM32WB35xx Electrical characteristics Table 40. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V Conditions IDD(Run) IDD(LPRun) Supply current in Run mode Supply current in Low-power run fHCLK = fMSI = 2 MHz All peripherals disable TYP Unit Voltage scaling Range 2 fHCLK = 16 MHz fHCLK = fHSI16 up to 16 MHz included, fHSI16 + PLL ON above 32 MHz All peripherals disable - Range 1 fHCLK = 64 MHz Parameter Range 1, SMPS On fHCLK = 64 MHz, Range 1, SMPS On When RF Tx fHCLK = 64 MHz level = 0 dBm(2) Symbol TYP Unit Code 25 °C 25 °C Reduced code(1) 2.00 125 Coremark 1.75 109 Dhrystone 2.1 1.95 Fibonacci 1.85 116 1.85 116 8.80 138 Coremark 7.50 117 Dhrystone 2.1 8.60 Fibonacci 7.90 123 8.00 125 5.25 82 Coremark 4.65 73 Dhrystone 2.1 5.15 Fibonacci 4.85 76 While(1) 4.90 77 Reduced code(1) 4.39 69 Coremark 3.74 58 Dhrystone 2.1 4.29 Fibonacci 3.94 62 While(1) 3.99 62 Reduced code(1) 255 128 Coremark 205 103 Dhrystone 2.1 250 Fibonacci 230 115 While(1) 220 110 While(1) Reduced code(1) While(1) Reduced code(1) mA mA mA mA µA 122 134 80 67 125 µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz 1. Reduced code used for characterization results provided in Table 37 and Table 38. 2. Value computed. MCU consumption when RF TX and SMPS are ON. DS11929 Rev 11 103/193 169 Conditions Symbol Parameter - IDD(Sleep) DS11929 Rev 11 IDD(LPSleep) fHCLK = fHSI16 up to 16 MHz included, fHCLK = fHSE up to Supply 32 MHz current in + PLL ON f sleep mode, HSI16 above 32 MHz  All peripherals disabled Supply current in low-power sleep mode MAX(1) TYP Unit Voltage scaling fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C Range 2 16 MHz 0.740 0.765 0.865 1.05 0.840 1.210 1.810 64 MHz 2.65 2.70 2.80 3.00 3.00 3.33 3.91 32 MHz 1.40 1.45 1.60 1.80 1.55 1.86 2.49 16 MHz 0.845 0.875 0.990 1.20 0.970 1.40 2.02 64 MHz 2.60 2.60 2.65 2.75 - - - 32 MHz 1.90 1.95 2.00 2.10 - - - 16 MHz 1.70 1.70 1.75 1.80 - - - 2 MHz 0.090 0.125 0.235 0.430 0.130 0.600 1.19 1 MHz 0.058 0.093 0.205 0.400 0.090 0.570 1.16 400 kHz 0.044 0.0725 0.185 0.380 0.070 0.540 1.11 100 kHz 0.0315 0.0635 0.0175 0.370 0.055 0.530 1.13 Range 1 SMPS Range 1 fHCLK = fMSI All peripherals disabled Electrical characteristics 104/193 Table 41. Current consumption in Sleep and Low-power sleep modes, Flash memory ON mA 1. Guaranteed by characterization results, unless otherwise specified. Table 42. Current consumption in Low-power sleep modes, Flash memory in Power down Symbol MAX(1) TYP Parameter Supply current in IDD (LPSleep) low-power sleep mode Unit - fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C fHCLK = fMSI  All peripherals disabled 2 MHz 94.0 115 200 335 135 610 1201 1 MHz 56.5 86.0 170 305 94.2 560 1171 400 kHz 40.5 66.5 150 285 68.0 540 1129 100 kHz 27.5 57.5 140 275 54.6 539 1131 1. Guaranteed by characterization results, unless otherwise specified. µA STM32WB55xx STM32WB35xx Conditions Symbol Parameter Supply current in Stop 2 IDD (Stop 2) mode, RTC disabled Conditions LCD disabled BLE disabled DS11929 Rev 11 IDD (Stop 2 with RTC) Supply current in Stop 2 mode, RTC enabled, BLE disabled VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C 1.8 V 1.00 1.85 3.15 5.95 21.5 50.0 2.4 V 1.10 1.85 3.20 6.00 22.0 51.0 3.0 V 1.10 1.85 3.25 6.10 22.0 52.0 3.6 V 1.15 1.95 3.35 6.25 23.0 53.0 2.00 3.35 6.10 22.0 50.5 2.00 3.40 6.20 22.0 51.0 - - 2.10 3.45 6.30 22.5 52.0 1.85 4.41 58.1 135.8 LCD enabled(2) 1.8 V 1.20 2.4 V 1.20 and clocked by LSI 3.0 V 1.25 BLE disabled 3.6 V 1.30 RTC clocked by LSI, LCD disabled MAX(1) TYP 1.58 4.12 56.9 132.7 - - 1.60 4.17 57.9 135.6 1.69 4.40 58.6 135.7 1.76 4.30 57.1 133.3 - - - - 2.15 3.60 6.55 23.0 53.5 1.97 4.66 59.4 136.6 1.8 V 1.30 2.10 3.45 6.25 22.0 50.5 1.91 4.50 57.2 133.0 2.4 V 1.45 2.25 3.55 6.40 22.5 51.5 - - - - 3.0 V 1.50 2.30 3.70 6.55 22.5 52.5 2.11 4.64 58.3 136.1 3.6 V 1.75 2.50 3.95 6.85 23.5 53.5 2.26 5.12 59.7 136.9 1.8 V 1.35 2.20 3.55 6.30 22.0 50.5 1.99 4.57 57.4 133.8 3.65 6.50 22.5 51.5 - - 3.85 6.65 23.0 52.5 2.17 4.87 58.4 136.3 4.05 6.95 23.5 54.0 2.41 5.11 59.9 137.1 1.91 4.29 57.1 133.5 - - RTC clocked 2.4 V 1.50 2.35 by LSI, (2) 3.0 V 1.70 2.45 LCD enabled 3.6 V 1.80 2.60 RTC clocked by 1.8 V 1.35 LSE quartz(3) 2.4 V 1.45 in low drive 3.0 V 1.55 mode 3.6 V 1.70 - - 2.20 3.50 6.25 22.0 50.5 2.25 3.65 6.40 22.5 51.5 2.45 3.80 6.65 23.0 52.5 2.01 4.31 58.0 135.9 2.55 4.05 6.95 23.5 54.0 2.16 4.40 81.6 137.0 - - Unit STM32WB55xx STM32WB35xx Table 43. Current consumption in Stop 2 mode µA Electrical characteristics 105/193 Symbol Parameter Conditions - MAX(1) TYP VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C Wakeup clock is HSI16, voltage 3.0 V Range 2. See(4). Supply current Wakeup clock is IDD MSI = 32 MHz, during (wakeup 3.0 V voltage wakeup from from (4) Stop 2 mode Range 1. See . Stop 2) bypass mode Wakeup clock is MSI = 4 MHz, 3.0 V voltage (4) Range 2. See . - 389 - - - - - - - - - 320 - - - - - - - - - 528 - - - - - - - - Unit µA Electrical characteristics 106/193 Table 43. Current consumption in Stop 2 mode (continued) 1. Guaranteed based on test during characterization, unless otherwise specified. DS11929 Rev 11 2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 4. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. STM32WB55xx STM32WB35xx Symbol Parameter Supply current in IDD Stop 1 mode, (Stop 1) RTC disabled DS11929 Rev 11 IDD (Stop 1 with RTC) Conditions - MAX(1) TYP VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 1.8 V 5.05 9.20 15.5 28.0 96.0 210 2.4 V 5.10 9.25 15.5 28.5 96.5 215 3.0 V 5.15 9.30 15.5 28.5 97.0 215 3.6 V 5.25 9.45 16.0 29.0 97.5 215 1.8 V 5.05 9.30 15.5 28.5 96.0 210 2.4 V 5.10 9.35 16.0 28.5 96.5 215 - - 3.0 V 5.20 9.65 16.0 28.5 97.0 215 7.26 29.6 345.0 747.0 3.6 V 5.55 9.85 16.0 29.0 98.5 215 7.62 29.8 349.0 750.8 1.8 V 5.30 9.35 16.0 28.5 96.5 215 7.30 29.5 343.7 739.2 RTC clocked by LSI 2.4 V 5.40 9.45 LCD disabled 3.0 V 5.70 9.55 16.0 28.5 97.0 215 16.5 29.0 98.5 220 BLE disabled LCD disabled BLE disabled LCD enabled(2), clocked by LSI Supply current in Stop 1 mode, RTC clocked by LSI LCD enabled(2) RTC enabled, BLE disabled RTC clocked by LSE quartz(3) in Low drive mode 7.00 28.4 105 °C 343.7 738.6 - - 7.07 28.5 346.8 746.0 7.30 28.8 351.0 749.4 7.10 28.7 344.4 739.0 - - - - - - 7.69 29.7 - - 347.2 746.1 3.6 V 5.85 10.0 16.5 29.5 96.5 215 8.08 29.8 349.9 751.1 1.8 V 5.25 9.60 16.0 28.5 96.5 215 7.10 29.0 344.3 739.9 2.4 V 5.30 9.75 16.0 29.0 97.0 215 - - 3.0 V 5.85 9.80 16.5 29.0 97.5 215 7.53 29.8 347.4 746.2 3.6 V 5.90 10.5 16.5 29.0 98.5 220 8.18 29.9 350.6 751.8 6.00 28.7 343.9 738.7 - - - - 1.8 V 5.35 9.55 16.0 28.5 96.5 215 2.4 V 5.40 9.70 16.0 29.0 96.5 215 3.0 V 5.75 9.70 16.0 29.0 97.5 215 7.40 28.9 346.6 743.8 3.6 V 5.90 10.0 16.5 29.5 99.0 220 7.58 29.2 349.0 749.9 - - Unit STM32WB55xx STM32WB35xx Table 44. Current consumption in Stop 1 mode µA Electrical characteristics 107/193 Symbol IDD (wakeup from Stop1) Parameter Supply current during wakeup from Stop 1 bypass mode Conditions - MAX(1) TYP VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C Wakeup clock HSI16,  voltage Range 2. See (4). 3.0 V - 129 - - - - - - - - Wakeup clock  MSI = 32 MHz, voltage Range 1. See (4). 3.0 V - 124 - - - - - - - - Wakeup clock  MSI = 4 MHz, voltage Range 2. See (4). 3.0 V - 207 - - - - - - - - Unit µA Electrical characteristics 108/193 Table 44. Current consumption in Stop 1 mode (continued) DS11929 Rev 11 1. Guaranteed based on test during characterization, unless otherwise specified. 2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. STM32WB55xx STM32WB35xx Symbol Parameter Supply current in Stop 0 mode, RTC disabled, BLE disabled, LCD disabled IDD (Stop 0) Conditions - -- MAX(1) TYP VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C 1.8 V 95.5 100 110 120 195 315 110.0 114.2 458.1 2.4 V 97.5 105 110 125 195 315 3.0 V 98.5 105 110 125 195 320 117.3 134.3 461.8 880.0 3.6 V 100 105 115 125 200 320 165.0 135.7 494.0 884.1 - - - Unit 874.8 - DS11929 Rev 11 Wakeup clock HSI16, 3.0 V voltage Range 2. (2). See - 331 - - - - - - - - Supply current Wakeup clock is during wakeup MSI = 32 MHz, 3.0 V voltage Range 1. from Stop 0 (2). See Bypass mode - 349 - - - - - - - - Wakeup clock is MSI = 4 MHz, 3.0 V voltage Range 2. (2). See - 196 - - - - - - - - STM32WB55xx STM32WB35xx Table 45. Current consumption in Stop 0 mode µA 1. Guaranteed by characterization results, unless otherwise specified. 2. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. Electrical characteristics 109/193 Symbol IDD (Standby) Parameter Conditions - BLE disabled Supply current No independent in Standby watchdog mode (backup registers and SRAM2a BLE disabled retained),  With RTC disabled independent watchdog DS11929 Rev 11 Supply current in Standby mode (backup IDD registers and (Standby with SRAM2a RTC) retained),  RTC enabled BLE disabled RTC clocked by LSI, no independent watchdog RTC clocked by LSI, with independent watchdog VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C 1.8 V 0.270 0.320 0.515 0.920 3.45 8.20 2.4 V 0.270 0.350 0.540 0.955 3.50 8.80 3.0 V 0.270 0.370 0.575 1.00 3.85 9.50 0.380 0.945 8.505 21.200 3.6 V 0.300 0.410 0.645 1.15 4.20 10.50 0.400 1.040 8.980 22.400 0.520 1.095 8.041 19.500 Unit 0.300 0.828 7.850 19.300 - - - - 1.8 V 0.265 0.525 0.710 1.10 3.90 8.40 2.4 V 0.280 0.595 0.790 1.20 4.00 9.05 3.0 V 0.290 0.670 0.855 1.35 4.15 9.80 0.730 1.253 8.774 21.400 3.6 V 0.295 0.770 0.990 1.50 4.60 11.00 0.851 1.356 9.360 22.840 1.8 V 0.500 0.600 0.780 1.20 3.70 8.45 0.680 1.165 8.143 19.660 2.4 V 0.630 0.705 0.910 1.30 3.80 9.10 3.0 V 0.725 0.825 1.050 1.50 3.95 9.90 0.930 1.463 8.977 21.440 3.6 V 0.860 0.970 1.200 1.70 4.25 11.00 1.050 1.628 9.634 23.080 1.8 V 0.565 0.655 0.830 1.25 3.75 8.55 0.734 1.196 8.187 19.710 2.4 V 0.635 0.790 0.975 1.40 4.10 9.20 3.0 V 0.725 0.915 1.100 1.55 4.50 10.00 1.028 1.573 9.072 21.810 - - - - - - - - - - - - 3.6 V 0.870 1.050 1.300 1.80 4.90 11.00 1.144 1.723 9.730 23.200 1.8 V 0.525 0.625 0.840 1.25 3.75 8.60 0.600 1.061 8.029 19.610 2.4 V 0.665 0.755 0.960 1.35 4.05 9.25 - - - µA - 3.0 V 0.775 0.880 1.100 1.55 4.40 10.00 0.600 1.100 8.719 21.570 3.6 V 0.935 1.050 1.300 1.80 5.00 11.00 0.750 1.171 9.460 23.030 STM32WB55xx STM32WB35xx RTC clocked by LSE quartz (2) in low drive mode MAX(1) TYP Electrical characteristics 110/193 Table 46. Current consumption in Standby mode Symbol Parameter Supply current to be subtracted in IDD Standby (3) (SRAM2a) mode when SRAM2a is not retained Conditions - MAX(1) TYP VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C 1.8 V 0.160 0.210 0.380 0.660 2.30 5.15 - - - - 2.4 V 0.165 0.245 0.375 0.650 2.15 5.20 - - - - 3.0 V 0.155 0.250 0.385 0.630 2.25 5.20 - - - - 3.6 V 0.155 0.235 0.375 0.670 2.20 5.20 - - - - - - - - - µA - Supply current Wakeup clock is IDD during HSI16. See (4). (wakeup from wakeup from Standby) SMPS OFF Standby mode Unit 3.0 V - 1.73 - - - STM32WB55xx STM32WB35xx Table 46. Current consumption in Standby mode (continued) mA DS11929 Rev 11 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. The supply current in Standby with SRAM2a mode is: IDD(Standby) + IDD(SRAM2a). The supply current in Standby with RTC with SRAM2a mode is: IDD(Standby + RTC) + IDD(SRAM2a). 4. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 51. Electrical characteristics 111/193 Symbol Parameter IDD (Shutdown) Supply current in Shutdown mode (backup registers retained) RTC disabled Conditions - MAX(1) TYP VDD 0 °C 25 °C 40 °C 55 °C 85 °C 1.8 V 0.039 0.013 0.030 0.100 2.4 V 0.059 0.014 0.055 3.0 V 0.064 0.037 3.6 V 0.071 1.8 V 105 °C 0 °C 25 °C 85 °C 105 °C 0.635 1.950 - - 2.099 6.200 0.120 0.785 2.350 - - - - 0.070 0.180 1.000 2.900 - 0.185 2.670 7.490 0.093 0.140 0.280 1.300 3.700 - 0.247 3.120 8.450 0.320 0.315 0.355 0.420 0.985 2.300 - 0.572 2.702 6.180 2.4 V 0.425 0.405 0.460 0.540 1.200 2.800 - - - - 3.0 V 0.535 0.535 0.595 0.700 1.500 3.450 - 0.664 2.990 7.800 3.6 V 0.695 0.720 0.790 0.940 2.000 4.350 - 0.790 3.730 9.140 Unit - Electrical characteristics 112/193 Table 47. Current consumption in Shutdown mode µA IDD (Shutdown with RTC) DS11929 Rev 11 Supply current in Shutdown mode (backup registers retained) RTC enabled RTC clocked by LSE quartz (2) in low drive mode 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Table 48. Current consumption in VBAT mode Symbol Parameter Conditions - Backup domain IDD(VBAT) supply current RTC enabled and clocked by LSE quartz(2) VBAT 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 1.8 V 1.00 2.00 4.00 10.0 52.0 145 - - - - - - 2.4 V 1.00 2.00 5.00 12.0 60.0 165 - - - - - - 3.0 V 2.00 4.00 7.00 16.0 75.0 225 - - - - - - 3.6 V 7.00 15.0 23.0 42.0 170 450 - - - - - - 1.8 V 295 305 315 325 380 480 - - - - - - 2.4 V 385 395 400 415 475 595 - - - - - - 3.0 V 495 505 515 530 600 765 - - - - - - 3.6 V 630 645 660 685 830 1150 - - - - - - 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Unit nA STM32WB55xx STM32WB35xx RTC disabled MAX(1) TYP Symbol IDD(RST) Conditions MAX(1) TYP 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 1.8 V - 410 - - - - - - - - - - 2.4 V - - - - - - - - - - - - 3.0 V - 550 - - - - - 750 - - - - 3.6 V - 750 - - - - - - - - - - 1. Guaranteed by characterization results, unless otherwise specified. Unit µA STM32WB55xx STM32WB35xx Table 49. Current under Reset condition DS11929 Rev 11 Electrical characteristics 113/193 Electrical characteristics STM32WB55xx STM32WB35xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 72: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 50: Peripheral current consumption, the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD  f SW  C where  ISW is the current sunk by a switching I/O to charge/discharge the capacitive load  VDD is the I/O supply voltage  fSW is the I/O switching frequency  C is the total capacitance seen by the I/O pin: C = CIO+ CEXT  CIO is the I/O pin capacitance  CEXT is the PCB board capacitance plus any connected external device pin capacitance. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 114/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 50. The MCU is placed under the following conditions:  All I/O pins are in Analog mode  The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off  Ambient operating temperature and supply voltage conditions summarized in Table 20: Voltage characteristics  The power consumption of the digital part of the on-chip peripherals is given in Table 50. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 50. Peripheral current consumption Range 1 Range 2 Low-power run and sleep Bus matrix(1) 2.40 2.00 1.80 TSC 1.25 1.05 1.05 CRC 0.465 0.375 0.380 DMA1 1.90 1.55 1.80 DMA2 2.00 1.65 1.80 DMAMUX 4.15 3.40 4.45 All AHB1 peripherals 12.0 10.0 11.5 AES1 4.00 3.30 3.90 ADC1 independent clock domain 2.55 2.10 2.10 ADC1 clock domain 2.25 1.90 1.90 All AHB2 peripherals 7.45 6.20 6.60 QSPI 7.60 6.25 7.10 TRNG independent clock domain 3.80 N/A N/A TRNG clock domain 2.00 N/A N/A SRAM2 1.70 1.35 1.35 AHB Shared FLASH 8.35 6.90 8.45 AES2 6.95 5.75 7.00 PKA 4.40 3.65 4.25 All AHB shared peripherals 17.5 14.5 16.0 Peripheral AHB1 AHB2(2) AHB3 DS11929 Rev 11 Unit µA/MHz 115/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 50. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep RTCA 1.10 0.88 1.25 CRS 0.24 0.20 0.20 USB FS independent clock domain 3.20 N/A N/A USB FS clock domain 2.05 N/A N/A I2C1 independent clock domain 2.50 4.40 4.40 I2C1 clock domain 4.80 4.00 5.50 I2C3 independent clock domain 2.10 3.50 3.55 I2C3 clock domain 3.70 3.10 3.55 LCD 1.35 1.10 2.10 SPI2 1.65 1.40 2.25 LPTIM1 independent clock domain 2.10 3.40 3.00 LPTIM1 clock domain 3.60 3.00 3.80 TIM2 5.65 4.70 4.90 LPUART1 independent clock domain 2.70 4.15 3.85 LPUART1 clock domain 4.45 3.70 5.25 LPTIM2 clock domain 3.95 3.25 4.50 LPTIM2 independent clock domain 2.20 3.70 3.80 WWDG 0.335 0.285 0.965 27.0 22.5 25.5 AHB to APB2 1.10 0.885 1.35 TIM1 8.20 6.80 7.25 TIM17 2.85 2.40 2.40 TIM16 2.75 2.30 2.55 USART1 independent clock domain 4.40 7.80 7.00 USART1 clock domain 8.80 7.30 7.75 SPI1 1.75 1.45 1.45 SAI1 independent clock domain 2.50 1.50 3.50 SAI1 clock domain 2.40 N/A N/A All APB2 on 28.0 23.0 25.5 97.5 80.5 90.0 Peripheral APB1 All APB1 peripherals (3) APB2 ALL 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. GPIOs consumption during read and write accesses. 3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2. 116/193 DS11929 Rev 11 Unit µA/MHz STM32WB55xx STM32WB35xx 6.3.9 Electrical characteristics Wakeup time from Low-power modes and voltage scaling transition times The wakeup times given in Table 51 are the latency between the event and the execution of the first user instruction. The device goes in Low-power mode after the WFE (Wait For Event) instruction. Table 51. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Wakeup time from Sleep mode to Run mode Conditions Typ Max - 9 10 Wakeup time from  Wakeup in Flash with memory in power-down tWULPSLEEP Low-power sleep mode during low-power sleep mode (FPDS = 1 in to Low-power run mode PWR_CR1) and with clock MSI = 2 MHz Wake up time from Stop 0 mode  to Run mode in Flash memory Range 1 Range 2 tWUSTOP0 Wake up time from Stop 0 mode  to Run mode in SRAM1 Range 1 Range 2 Range 1 Wake up time from Stop 1 mode  to Run in Flash memory SMPS bypassed Range 2 tWUSTOP1 Wake up time from Stop 1 mode  to Run in SRAM1 SMPS bypassed Wake up time from Stop 1 mode to  Low-power run mode in Flash memory Wake up time from Stop 1 mode to  Low-power run mode in SRAM1 Range 1 Range 2 Regulator in Low-power mode (LPR = 1 in PWR_CR1) 9 10 Wakeup clock MSI = 32 MHz 2.38 2.96 Wakeup clock HSI16 = 16 MHz 1.69 2.00 Wakeup clock HSI16 = 16 MHz 1.70 2.01 Wakeup clock MSI = 4 MHz 7.43 8.59 Wakeup clock MSI = 32 MHz 2.63 3.00 Wakeup clock HSI16 = 16 MHz 1.80 2.00 Wakeup clock HSI16 = 16 MHz 1.82 2.02 Wakeup clock MSI = 4 MHz 7.58 8.70 Wakeup clock MSI = 32 MHz 4.67 5.56 Wakeup clock HSI16 = 16 MHz 5.09 6.03 Wakeup clock HSI16 = 16 MHz 5.08 6.00 Wakeup clock MSI = 4 MHz 8.36 9.28 Wakeup clock MSI = 32 MHz 4.88 5.55 Wakeup clock HSI16 = 16 MHz 5.29 5.95 Wakeup clock HSI16 = 16 MHz 5.28 5.96 Wakeup clock MSI = 4 MHz 8.49 9.30 7.96 9.59 8.00 9.47 Unit No. of CPU cycles µs Wakeup clock MSI = 4 MHz DS11929 Rev 11 117/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 51. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Wake up time from Stop 2 mode  to Run mode in Flash memory SMPS bypassed Range 1 Range 2 tWUSTOP2 Wake up time from Stop 2 mode to Run mode in SRAM1 SMPS bypassed tWUSTBY Wakeup time from Standby mode to Run mode SMPS Bypassed Range 1 Range 2 Range 1 Typ Max Wakeup clock MSI = 32 MHz 5.27 6.07 Wakeup clock HSI16 = 16 MHz 5.71 6.52 Wakeup clock HSI16 = 16 MHz 5.72 6.52 Wakeup clock MSI = 4 MHz 9.10 9.93 Wakeup clock MSI = 32 MHz 5.20 5.94 Wakeup clock HSI16 = 16 MHz 5.64 6.42 Wakeup clock HSI16 = 16 MHz 5.64 6.43 Wakeup clock MSI = 4 MHz 9.05 9.85 Wakeup clock HSI16 = 16 MHz 51.0 58.1 Unit µs µs 1. Guaranteed by characterization results (VDD = 3 V, .T = 25 °C). Table 52. Regulator modes transition times(1) Symbol tWULPRUN tVOST Parameter Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 15.33 16.30 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 21.4 28.9 Code run with HSI16 Unit µs 1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C). 2. Time until REGLPF flag is cleared in PWR_SR2. 3. Time until VOSF flag is cleared in PWR_SR2. Table 53. Wakeup time using USART/LPUART(1) Symbol tWUUSART tWULPUART Parameter Conditions Wakeup time needed to calculate the maximum Stop mode 0 USART/LPUART baud rate allowing to wakeup from Stop modes when USART/LPUART clock source is Stop mode 1/2 HSI16 1. Guaranteed by design. 118/193 DS11929 Rev 11 Typ Max - 1.7 - 8.5 Unit µs STM32WB55xx STM32WB35xx 6.3.10 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The high-speed external (HSE) clock is supplied with a 32 MHz crystal oscillator or a sine or a square wave. The devices include internal programmable capacitances that can be used to tune the crystal frequency in order to compensate the PCB parasitic one. The characteristics in Table 54 and Table 55 are measured over recommended operating conditions, unless otherwise specified. Typical values are referred to TA = 25 °C and  VDD = 3.0 V. Table 54. HSE crystal requirements(1) Symbol Parameter fNOM Oscillator frequency fTOL Frequency tolerance CL ESR Conditions Min Typ Max Unit - - 32 - MHz - - (2) ppm Includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance. Load capacitance - 6 - 8 pF Equivalent series resistance - - - 100 Ω 1. 32 MHz XTAL is specified for two specific references: NX2016SA and NX1612SA. 2. Refer to the standard specification: 50 ppm for BLE, 40 ppm for 802.15.4 and when both BLE and 802.15.4 are used. Table 55. HSE clock source requirements(1) Symbol Parameter Conditions Min Typ Max Unit fHSE_ext User external clock source frequency - - 32 - MHz - - (2) ppm fTOL Frequency tolerance Includes initial accuracy, stability over temperature and aging. VHSE Clock input voltage limits Sine or square wave, AC-coupled(3) 0.4 - 1.6 VPP - 45 50 55 % 10% - 90% square wave - - 15 * VPP ns Offset = 10 kHz - - -127 Offset = 100 kHz - - -135 Offset = 1 MHz - - -138 DuCy(HSE) Duty cycle tr, tf φn(HSE) Rise and fall times Phase noise for 32 MHz dBc/Hz 1. Guaranteed by design. 2. Refer to the standard specification: 50 ppm for BLE, 40 ppm for 802.15.4 and when both BLE and 802.15.4 are used. 3. Only AC coupled is supported (capacitor 470 pF to 100 nF). DS11929 Rev 11 119/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 56. HSE oscillator characteristics Symbol Parameter tSUA(HSE) Startup time for 80% amplitude stabilization tSUR(HSE) Startup time for XOREADY signal IDDRF(HSE) HSE current consumption Conditions Min Typ Max VDDRF stabilized,  XOTUNE=000000,  -40 to +125 °C range - 1000 - - 250 - HSEGMC=000, XOTUNE=000000 - 50 - - 1 5 ±20 ±40 - - 6 - bit - - 0.1 ms µs XOTg(HSE) XOTUNE granularity XOTfp(HSE) XOTUNE frequency pulling XOTnb(HSE) XOTUNE number of tuning bits Capacitor bank XOTst(HSE) XOTUNE setting time Note: Unit µA ppm For information about oscillator trimming refer to AN5165 “Development of RF hardware using STM32WB microcontrollers”, available from www.st.com. Low-speed external user clock generated from an external source The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. The information provided in this section is based on design simulation results obtained with typical external components specified in Table 57. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 57. Low-speed external user clock characteristics(1) Symbol IDD(LSE) Gmcritmax tSU(LSE)(2) 120/193 Parameter LSE current consumption Maximum critical crystal gm Startup time Conditions Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.50 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.70 LSEDRV[1:0] = 11 High drive capability - - 2.70 VDD stabilized - 2 - DS11929 Rev 11 Unit nA µA/V s STM32WB55xx STM32WB35xx Electrical characteristics 1. Guaranteed by design. 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stable 32 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal refer to application note AN2867 “Oscillator design guide for STM8S, STM8A and STM32 microcontrollers” available from www.st.com. Figure 22. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden to add one. In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics detailed in Section 6.3.17. The recommend clock input waveform is shown in Figure 23. Figure 23. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 DS11929 Rev 11 121/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 58. Low-speed external user clock characteristics(1) – Bypass mode Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - 21.2 32.768 44.4 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDx - VDDx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDx OSC32_IN high or low time - 250 - - ns -500 - +500 ppm tw(LSEH) tw(LSEL) ftolLSE V Includes initial accuracy, stability over Frequency tolerance temperature, aging and frequency pulling 1. Guaranteed by design. 6.3.11 Internal clock source characteristics The parameters given in Table 59 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 59. HSI16 oscillator characteristics(1) Symbol fHSI16 TRIM Parameter HSI16 Frequency HSI16 user trimming step Conditions Min Typ Max Unit VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz Trimming code is not a multiple of 64 0.2 0.3 0.4 Trimming code is a multiple of 64 -4 -6 -8 45 - 55 DuCy(HSI16)(2) Duty Cycle - ∆Temp(HSI16) HSI16 oscillator frequency drift over temperature TA= 0 to 85 °C -1 - 1 TA= -40 to 125 °C -2 - 1.5 ∆VDD(HSI16) HSI16 oscillator frequency drift over VDD VDD=1.62 V to 3.6 V -0.1 - 0.05 tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 1. Guaranteed by characterization results. 2. Guaranteed by design. 122/193 DS11929 Rev 11 % μs μA STM32WB55xx STM32WB35xx Electrical characteristics Figure 24. HSI16 frequency vs. temperature MHz 16.4 +2% 16.3 +1.5% 16.2 +1% 16.1 16 15.9 -1% 15.8 -1.5% 15.7 -2% 15.6 -40 -20 0 20 40 min mean 60 80 100 120 °C max MSv39299V1 DS11929 Rev 11 123/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Multi-speed internal (MSI) RC oscillator Table 60. MSI oscillator characteristics(1) Symbol Parameter Conditions MSI mode fMSI ∆TEMP(MSI)(2) 124/193 MSI frequency after factory calibration, done at VDD=3 V and TA=30 °C MSI oscillator frequency drift over temperature Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.304 - Range 1 - 196.608 - Range 2 - 393.216 - Range 3 - 786.432 - Range 4 - 1.016 - PLL mode Range 5 XTAL= 32.768 kHz Range 6 - 1.999 - - 3.998 - Range 7 - 7.995 - Range 8 - 15.991 - Range 9 - 23.986 - Range 10 - 32.014 - Range 11 - 48.005 - -3.5 - 3 -8 - 6 MSI mode TA= -0 to 85 °C TA= -40 to 125 °C DS11929 Rev 11 Unit kHz MHz kHz MHz % STM32WB55xx STM32WB35xx Electrical characteristics Table 60. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD =  1.62 to 3.6 V -1.2 - VDD =  2.4 to 3.6 V -0.5 - VDD =  1.62 to 3.6 V -2.5 - VDD =  2.4 to 3.6 V -0.8 - VDD =  1.62 to 3.6 V -5 - VDD =  2.4 to 3.6 V -1.6 - TA= -40 to 85 °C - 1 2 TA= -40 to 125 °C - 2 4 Range 0 to 3 ∆VDD(MSI)(2) MSI oscillator frequency drift MSI mode over VDD (reference is 3 V) Range 4 to 7 Range 8 to 11 ∆FSAMPLING (MSI)(2)(6) P_USB Jitter(MSI)(6) MT_USB Jitter(MSI)(6) CC jitter(MSI)(6) P jitter(MSI)(6) tSU(MSI)(6) tSTAB(MSI)(6) Frequency MSI mode variation in sampling mode(3) Period jitter for USB clock(4) PLL mode Range 11 Medium term jitter PLL mode for USB clock(5) Range 11 Max 0.5 0.7 % 1 For next transition - - - 3.458 For paired transition - - - 3.916 For next transition - - - 2 For paired transition - - - 1 ns RMS cycle-tocycle jitter PLL mode Range 11 - - 60 - RMS period jitter PLL mode Range 11 - - 50 - Range 0 - - 10 20 Range 1 - - 5 10 Range 2 - - 4 8 Range 3 - - 3 7 Range 4 to 7 - - 3 6 Range 8 to 11 - - 2.5 6 10 % of final frequency - - 0.25 0.5 5 % of final frequency - - 0.5 1.25 1 % of final frequency - - - 2.5 MSI oscillator start-up time MSI oscillator stabilization time PLL mode Range 11 DS11929 Rev 11 Unit ps μs ms 125/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 60. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1. Guaranteed by characterization results. 2. This is a deviation for an individual part once the initial frequency has been measured. 3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable. 4. Average period of MSI at 48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI at 48 MHz clock. 5. Only accumulated jitter of MSI at 48 MHz is extracted over 28 cycles. For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI at 48 MHz, for 1000 captures over  28 cycles. For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI at 48 MHz, for 1000 captures over 56 cycles. 6. Guaranteed by design. 126/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Figure 25. Typical current consumption vs. MSI frequency High-speed internal 48 MHz (HSI48) RC oscillator Table 61. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM USER TRIM COVERAGE Parameter HSI48 frequency Min Typ Max Unit VDD = 3.0 V, TA = 30 °C - 48 - MHz - 0.11(2) 0.18(2) ±3(3) ±3.5(3) - 45(2) - 55(2) VDD = 3.0 V to 3.6 V, TA = –15 to 85 °C - - ±3(3) VDD = 1.65 V to 3.6 V, TA = –40 to 125 °C - - ±4.5(3) VDD = 3 V to 3.6 V - 0.025(3) 0.05(3) VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3) HSI48 user trimming step - HSI48 user trimming coverage ±32 steps DuCy(HSI48) Duty cycle - Accuracy of the HSI48 oscillator ACCHSI48_REL over temperature (factory calibrated) DVDD(HSI48) Conditions HSI48 oscillator frequency drift with VDD % tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA DS11929 Rev 11 127/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 61. HSI48 oscillator characteristics(1) (continued) Symbol Parameter NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) Conditions Min Typ Max - - ±0.15(2) - - (2) Unit ns - ±0.25 - 1. VDD = 3 V, TA = –40 to 125 °C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Jitter measurement are performed without clock source activated in parallel. Figure 26. HSI48 frequency vs. temperature % 6 4 2 0 -2 -4 -6 -50 -30 -10 10 30 50 Avg 70 min 90 110 130 °C max MSv40989V1 Low-speed internal (LSI) RC oscillator Table 62. LSI1 oscillator characteristics(1) Symbol fLSI tSU(LSI1)(2) Parameter LSI1 frequency Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - - 80 130 - 125 180 - 110 180 LSI1 oscillator start-up time tSTAB(LSI1)(2) LSI1 oscillator stabilization time 5% of final frequency IDD(LSI1)(2) LSI1 oscillator power consumption - 1. Guaranteed by characterization results. 2. Guaranteed by design. 128/193 DS11929 Rev 11 Unit kHz μs nA STM32WB55xx STM32WB35xx Electrical characteristics Table 63. LSI2 oscillator characteristics(1) Symbol fLSI2 Parameter LSI2 frequency Conditions Min Typ Max Unit VDD = 3.0 V, TA = 30 °C 21.6 - 44.2 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 21.2 - 44.4 kHz tSU(LSI2)(2) LSI2 oscillator start-up time - 0.7 - 3.5 ms IDD(LSI2)(2) LSI2 oscillator power consumption - - 500 1180 nA 1. Guaranteed by characterization results. 2. Guaranteed by design. 6.3.12 PLL characteristics The parameters given in Table 64 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions. Table 64. PLL, PLLSAI1 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 2.66 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 2 - 64 Voltage scaling Range 2 2 - 16 Voltage scaling Range 1 8 - 64 Voltage scaling Range 2 8 - 16 Voltage scaling Range 1 8 - 64 Voltage scaling Range 2 8 - 16 Voltage scaling Range 1 96 - 344 Voltage scaling Range 2 64 - 128 - 15 40 - 40 - - 30 - VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) System clock 64 MHz MHz μs ps μA 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the two PLLs. DS11929 Rev 11 129/193 169 Electrical characteristics 6.3.13 STM32WB55xx STM32WB35xx Flash memory characteristics Table 65. Flash memory characteristics(1) Symbol tprog Parameter Conditions Typ Max Unit - 81.7 90.8 µs Normal programming 5.2 5.5 Fast programming 3.8 4.0 Normal programming 41.8 43.0 Fast programming 30.4 31.0 64-bit programming time tprog_row One row (64 double word) programming time tprog_page One page (4 Kbytes) programming time Page (4 Kbytes) erase time - 22.0 24.5 tME Mass erase time - 22.1 25.0 IDD Average consumption from VDD Write mode 3.4 - Erase mode 3.4 - tERASE ms mA 1. Guaranteed by design. Table 66. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = –40 to +105 °C 1 tRET Data retention kcycle(2) Unit 10 kcycles at TA = 85 °C 30 1 kcycle (2) at TA = 105 °C 15 1 kcycle (2) at TA = 125 °C 7 10 kcycles(2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 10 kcycles (2) at TA = 105 °C 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 130/193 Min(1) DS11929 Rev 11 10 Years STM32WB55xx STM32WB35xx 6.3.14 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:  Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.  FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operation to be resumed. The test results are given in Table 67. They are based on the EMS levels and classes defined in AN1709 “EMC design guide for STM8, STM32 and Legacy MCUs”, available on www.st.com. Table 67. EMS characteristics Symbol Parameter Conditions Level/Class VFESD VDD = 3.3 V, TA = +25 °C,  Voltage limits to be applied on any I/O pin fHCLK = 64 MHz, to induce a functional disturbance conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C,  fHCLK = 64 MHz, conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. Good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for the application. Software recommendations The software flow must include the management of runaway conditions such as:  corrupted program counter  unexpected reset  critical data corruption (e.g. control registers) DS11929 Rev 11 131/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling two LEDs through the I/O ports). This emission test is compliant with the IEC 61967-2 standard, which specifies the test board and the pin loading. Table 68. EMI characteristics Symbol Parameter Monitored frequency band Conditions Peripheral ON SMPS OFF or ON [fHSE / fCPUM4, fCPUM0] Unit 32 MHz / 64 MHz, 32 MHz SEMI Peak level VDD = 3.6 V, TA = 25 °C, WLCSP100 package compliant with IEC 61967-2 0.1 MHz to 30 MHz 1 30 MHz to 130 MHz 4 130 MHz to 1 GHz -1 1 GHz to 2 GHz 7 EMI level 6.3.15 dBµV 1.5 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 69. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C, conforming to ANSI/ESD STM5.3.1 JS-002 1. Guaranteed by characterization results. 2. UFQFPN48, VFQPN68 and WLCSP100 packages. 3. UFBGA129 package. 132/193 DS11929 Rev 11 Class Maximum value(1) 2 2000 C2a(2) 500(2) C1(3) 250(3) Unit V STM32WB55xx STM32WB35xx Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance:  a supply overvoltage is applied to each power supply pin  a current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 70. Electrical sensitivity Symbol LU 6.3.16 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA / 0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 71. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 71. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on all pins except PB0, PB1 -5 N/A(2) Injected current on PB0, PB1 pins -5 0 Unit mA 1. Guaranteed by characterization results. 2. Injection not possible. DS11929 Rev 11 133/193 169 Electrical characteristics 6.3.17 STM32WB55xx STM32WB35xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 72 are derived from tests performed under the conditions summarized in Table 24: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 72. I/O static characteristics Symbol VIL VIH Vhys Parameter Conditions I/O input low level voltage(1) Typ Max - - 0.3 x VDD I/O input low level voltage(2) I/O input high level voltage(1) V 0.7 x VDD - - 0.49 x VDD + 0.26 - - - 200 - - - ±100 - - 650 - - 200(7) - - ±150 - - 2500 - - 250 - - ±150 - - 2000 1.62 V < VDD < 3.6 V I/O input high level voltage(2) TT_xx, FT_xxx and NRST I/O input hysteresis Max(VDDXXX) ≤ VIN ≤ FT_xx Max(VDDXXX) +1 V(2)(3)(4) input leakage current Max(VDDXXX) +1 V < VIN ≤ 5.5 V(2)(3)(4)(5)(6) 0 ≤ VIN ≤ Max(VDDXXX)(3) Max(VDDXXX) ≤ VIN ≤ FT_lu, FT_u and PC3 IO Max(VDDXXX) +1 V(2)(3) input leakage current Max(VDDXXX) +1 V < VIN ≤ 5.5 V(1)(3)(4)(8) VIN ≤ Max(VDDXXX)(3) TT_xx input leakage current Max(VDDXXX) ≤ VIN < 3.6 V(3) RPU Weak pull-up equivalent resistor(1) VIN = VSS 25 40 55 RPD Weak pull-down equivalent resistor(1) VIN = VDD 25 40 55 CIO I/O pin capacitance - 5 - mV nA kΩ - 1. Tested in production. 2. Guaranteed by design, not tested in production. 3. Represents the pad leakage of the I/O itself. The total product pad leakage is given by ITotal_Ileak_max = 10 μA + number of I/Os where VIN is applied on the pad x Ilkg(Max). 4. Max(VDDXXX) is the maximum value among all the I/O supplies. 5. VIN must be lower than [Max(VDDXXX) + 3.6 V]. 6. Refer to Figure 27: I/O input characteristics. 134/193 Unit 0.39 x VDD - 0.06 0 ≤ VIN ≤ Max(VDDXXX)(3) Ilkg Min DS11929 Rev 11 pF STM32WB55xx STM32WB35xx Electrical characteristics 7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB, VLCD) + 0.3 V, the internal pull-up and pull-down resistors must be disabled. All FT_xx IO except FT_lu, FT_u and PC3. 8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS, whose contribution to the series resistance is minimal (~10%). All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 27 . Figure 27. I/O input characteristics Vil-Vih (all IO except BOOT0) 3 2.5 TTL requirement Vih min = 2V 2 Voltage cmos vil spec 30% cmos vih spec 70% ttl vil spec ttl 1.5 ttl vih spec ttl datasheet Vil_rule datasheet Vih_rule 1 TTL requirement Vil min = 0.8V 0.5 0 1.5 2 2.5 3 3.5 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed VOL / VOH). In the user application, the number of I/O pins that can drive current must be limited to respect the absolute maximum rating specified in Section 6.2.  The sum of the currents sourced by all the I/Os on VDD, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 20: Voltage characteristics).  The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 20: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT unless otherwise specified). DS11929 Rev 11 135/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 73. Output voltage characteristics(1) Symbol Parameter Conditions VOL(2) Output low level voltage for an I/O pin VOH(2) Output high level voltage for an I/O pin VOL(2) Output low level voltage for an I/O pin VOH(2) Output high level voltage for an I/O pin VOL(2) Output low level voltage for an I/O pin VOH(2) Output high level voltage for an I/O pin VOL(2) Output low level voltage for an I/O pin VOH(2) Output high level voltage for an I/O pin VOLFM+(2) Min CMOS port(3)  |IIO| = 8 mA VDD ≥ 2.7 V Max Unit - 0.4 VDD - 0.4 - - 0.4 2.4 - - 1.3 VDD - 1.3 - - 0.4 VDD - 0.45 - |IIO| = 20 mA VDD ≥ 2.7 V - 0.4 |IIO| = 10 mA Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with “f” option) VDD ≥ 1.62 V - 0.4 - 0.4 TTL port(3)  |IIO| = 8 mA VDD ≥ 2.7 V |IIO| = 20 mA VDD ≥ 2.7 V |IIO| = 4 mA VDD ≥ 1.62 V |IIO| = 2 mA 1.62 V ≥ VDD ≥ 1.08 V V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings Σ IIO. 2. Guaranteed by design. 3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 74. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 74. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf 136/193 Output rise and fall time Conditions Min Max C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5 C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 1 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10 C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 1.5 C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25 C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 52 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17 C=10 pF, 1.62 V ≤ VDD ≤ ≤2.7 V - 37 DS11929 Rev 11 Unit MHz ns STM32WB55xx STM32WB35xx Electrical characteristics Table 74. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 01 Tr/Tf Fmax Output rise and fall time Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Output rise and fall time Conditions Min Max C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25 C=50 pF, 1.62 V ≤ VDD ≤ ≤2.7 V - 10 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50 C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 15 C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 9 C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 16 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5 C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 9 C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50 C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 25 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100(3) C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 37.5 C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.8 C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 11 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.5 C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 5 C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 120(3) C=30 pF, 1.62 V ≤ VDD ≤ 2.7 V - 50 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 180(3) C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 75(3) C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.3 C=30 pF, 1.62 V ≤ VDD ≤ 2.7 V - 6 C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.7 C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 3.3 Unit MHz ns MHz ns MHz ns 1. The maximum frequency is defined with (Tr+ Tf) ≤ 2/3 T, and Duty cycle comprised between 45 and 55%. 2. The fall and rise time are defined, respectively, between 90 and 10%, and between 10 and 90% of the output waveform. 3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz. 6.3.18 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent  pull-up resistor, RPU. Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. DS11929 Rev 11 137/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 75. NRST pin characteristics(1) Symbol Parameter Conditions Min Typ Max VIL(NRST) NRST input low level voltage - - - 0.3 x VDD VIH(NRST) NRST input high level voltage - 0.7 x VDD - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ - - - 70 1.71 V ≤ VDD ≤ 3.6 V 350 - - VF(NRST) NRST input filtered pulse VNF(NRST) NRST input not filtered pulse 1. Unit V ns Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10%). Figure 28. Recommended NRST pin protection External reset circuit(1) VDD RPU NRST(2) Internal reset Filter 0.1 μF MS19878V3 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 75, otherwise the reset will not be taken into account by the device. 3. The external capacitor on NRST must be placed as close as possible to the device. 138/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 6.3.19 Electrical characteristics Analog switches booster Table 76. Analog switches booster characteristics(1) Symbol VDD tSU(BOOST) IDD(BOOST) Parameter Min Typ Max Unit 1.62 - 3.6 V Booster startup time - - 240 µs Booster consumption for 1.62 V ≤ VDD ≤ 2.0 V - - 250 Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V - - 500 Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V - - 900 Supply voltage µA 1. Guaranteed by design. DS11929 Rev 11 139/193 169 Electrical characteristics 6.3.20 STM32WB55xx STM32WB35xx Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 77 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 24: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 77. ADC characteristics(1) (2) (3) Symbol Parameter VDDA Analog supply voltage VREF+ Positive reference voltage VREF- Negative reference voltage fADC ADC clock frequency Sampling rate for FAST channels fs Sampling rate for SLOW channels fTRIG External trigger frequency Conditions Min Typ Max Unit - 1.62 - 3.6 V 2 - VDDA V VDDA ≥ 2 V VDDA < 2 V VDDA V - VSSA V Range 1 0.14 - 64 Range 2 0.14 - 16 Resolution = 12 bits - - 4.26 Resolution = 10 bits - - 4.92 Resolution = 8 bits - - 5.81 Resolution = 6 bits - - 7.11 Resolution = 12 bits - - 3.36 Resolution = 10 bits - - 4.00 Resolution = 8 bits - - 4.57 Resolution = 6 bits - - 7.11 fADC = 64 MHz Resolution = 12 bits - - 4.26 MHz Resolution = 12 bits - - 15 1/fADC (VREF++ VREF-) / 2 - 0.18 (VREF++ VREF-) / 2 (VREF++ VREF-) / 2 + 0.18 V Differential mode MHz Msps VCMIN Input common mode VAIN (4) Conversion voltage range(2) - 0 - VREF+ V RAIN External input impedance - - - 50 kΩ CADC Internal sample and hold capacitor - - 5 - pF tSTAB Power-up time - tCAL Calibration time 140/193 fADC = 64 MHz - DS11929 Rev 11 1 Conversion cycle 1.8125 µs 116 1 / fADC STM32WB55xx STM32WB35xx Electrical characteristics Table 77. ADC characteristics(1) (2) (3) (continued) Symbol tLATR tLATRINJ ts tADCVREG_STUP tCONV IDDA(ADC) IDDV_S(ADC) IDDV_D(ADC) Parameter Min Typ Max CKMODE = 00 Trigger conversion CKMODE = 01 latency Regular and injected channels CKMODE = 10 without conversion abort CKMODE = 11 1.5 2 2.5 - - 2.0 - - 2.25 - - 2.125 CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3.0 CKMODE = 10 - - 3.25 CKMODE = 11 - - 3.125 fADC = 64 MHz 0.039 - 10.0 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.234 - 1.019 µs Trigger conversion latency Injected channels aborting a regular conversion Sampling time ADC voltage regulator start-up time Conditions fADC = 64 MHz Resolution = 12 bits Total conversion time (including sampling time) Resolution = 12 bits ADC consumption from the VDDA supply ADC consumption from the VREF+ single ended mode ADC consumption from the VREF+ differential mode ts + 12.5 cycles for successive approximations = 15 to 653 fs = 4.26 Msps - 730 830 fs = 1 Msps - 160 220 fs = 10 ksps - 16 50 fs = 4.26 Msps - 130 160 fs = 1 Msps - 30 40 fs = 10 ksps - 0.6 2 fs = 4.26 Msps - 250 310 fs = 1 Msps - 60 70 fs = 10 ksps - 1.3 3 Unit 1/fADC 1/fADC 1/fADC µA µA µA 1. Guaranteed by design 2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. SMPS in bypass mode. 4. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pinouts and pin description for further details. DS11929 Rev 11 141/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 78. ADC sampling time(1)(2) Fast channel Resolution (bits) 12 10 8 142/193 RAIN (kΩ) Slow channel Minimum sampling time (ns) Sampling cycles Minimum sampling time (ns) Sampling cycles 0 33 6.5 57 6.5 0.05 37 6.5 62 6.5 0.1 42 6.5 67 6.5 0.2 51 6.5 76 6.5 0.5 78 6.5 104 12.5 1 123 12.5 151 12.5 5 482 47.5 526 47.5 10 931 92.5 994 92.5 20 1830 247.5 1932 247.5 50 4527 640.5 4744 640.5 100 9021 640.5 9430 640.5 0 27 2.5 47 6.5 0.05 30 2.5 51 6.5 0.1 34 6.5 55 6.5 0.2 41 6.5 62 6.5 0.5 64 6.5 85 6.5 1 100 12.5 124 12.5 5 395 47.5 431 47.5 10 763 92.5 816 92.5 20 1500 247.5 1584 247.5 50 3709 640.5 3891 640.5 100 7391 640.5 7734 640.5 0 21 2.5 37 2.5 0.05 24 2.5 40 6.5 0.1 27 2.5 43 6.5 0.2 32 6.5 49 6.5 0.5 50 6.5 67 6.5 1 78 6.5 97 6.5 5 308 47.5 337 24.5 10 595 92.5 637 47.5 20 1169 247.5 1237 92.5 50 2891 247.5 3037 247.5 100 5762 640.5 6038 640.5 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Table 78. ADC sampling time(1)(2) (continued) Fast channel Resolution (bits) 6 RAIN (kΩ) Slow channel Minimum sampling time (ns) Sampling cycles Minimum sampling time (ns) Sampling cycles 0 15 2.5 26 2.5 0.05 17 2.5 28 2.5 0.1 19 2.5 31 2.5 0.2 23 2.5 35 2.5 0.5 36 6.5 48 6.5 1 56 6.5 69 6.5 5 221 24.5 242 24.5 10 427 47.5 458 47.5 20 839 92.5 890 92.5 50 2074 247.5 2184 247.5 100 4133 640.5 4342 640.5 1. Guaranteed by design. 2. VDD = 1.62 V, Cpcb = 4.7 pF, 125 °C, booster enabled. DS11929 Rev 11 143/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 79. ADC accuracy - Limited test conditions 1(1)(2)(3) Symbol ET Conditions(4) Parameter Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error ED EL ENOB SINAD SNR Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Signal-tonoise ratio ADC clock frequency ≤ 64 MHz, Sampling rate ≤ 4.26 Msps, VDDA = VREF+ = 3 V, TA = 25 °C Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 144/193 Min Typ Max Fast channel (max speed) - 4 5 Slow channel (max speed) - 4 5 Fast channel (max speed) - 3.5 4.5 Slow channel (max speed) - 3.5 4.5 Fast channel (max speed) - 1 2.5 Slow channel (max speed) - 1 2.5 Fast channel (max speed) - 1.5 2.5 Slow channel (max speed) - 1.5 2.5 Fast channel (max speed) - 2.5 4.5 Slow channel (max speed) - 2.5 4.5 Fast channel (max speed) - 2.5 3.5 Slow channel (max speed) - 2.5 3.5 Fast channel (max speed) - 1 1.5 Slow channel (max speed) - 1 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 1.5 2.5 Slow channel (max speed) - 1.5 2.5 Fast channel (max speed) - 1 2 Slow channel (max speed) - 1 2 Fast channel (max speed) 10.4 10.5 - Slow channel (max speed) 10.4 10.5 - Fast channel (max speed) 10.8 10.9 - Slow channel (max speed) 10.8 10.9 - Fast channel (max speed) 64.4 65 - Slow channel (max speed) 64.4 65 - Fast channel (max speed) 66.8 67.4 - Slow channel (max speed) 66.8 67.4 - Fast channel (max speed) 65 66 - Slow channel (max speed) 65 66 - Fast channel (max speed) 67 68 - Slow channel (max speed) 67 68 - DS11929 Rev 11 Unit LSB bits dB STM32WB55xx STM32WB35xx Electrical characteristics Table 79. ADC accuracy - Limited test conditions 1(1)(2)(3) (continued) THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ 64 MHz, Sampling rate ≤ 4.26 Msps, VDDA = VREF+ = 3 V, TA = 25 °C Symbol Min Typ Max Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Unit Single ended dB Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 Differential 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling. DS11929 Rev 11 145/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 80. ADC accuracy - Limited test conditions 2(1)(2)(3) Symbol ET Conditions(4) Parameter Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error ED EL ENOB SINAD SNR Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Signal-tonoise ratio ADC clock frequency ≤ 64 MHz, Sampling rate ≤ 4.26 Msps, VDDA ≥ 2 V TA = 25 °C Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 146/193 Min Typ Max Fast channel (max speed) - 4 6.5 Slow channel (max speed) - 4 6.5 Fast channel (max speed) - 3.5 5.5 Slow channel (max speed) - 3.5 5.5 Fast channel (max speed) - 1 4.5 Slow channel (max speed) - 1 5 Fast channel (max speed) - 1.5 3 Slow channel (max speed) - 1.5 3 Fast channel (max speed) - 2.5 6 Slow channel (max speed) - 2.5 6 Fast channel (max speed) - 2.5 3.5 Slow channel (max speed) - 2.5 3.5 Fast channel (max speed) - 1 1.5 Slow channel (max speed) - 1 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 1.5 3.5 Slow channel (max speed) - 1.5 3.5 Fast channel (max speed) - 1 3 Slow channel (max speed) - 1 2.5 Fast channel (max speed) 10 10.5 - Slow channel (max speed) 10 10.5 - Fast channel (max speed) 10.7 10.9 - Slow channel (max speed) 10.7 10.9 - Fast channel (max speed) 62 65 - Slow channel (max speed) 62 65 - Fast channel (max speed) 66 67.4 - Slow channel (max speed) 66 67.4 - Fast channel (max speed) 64 66 - Slow channel (max speed) 64 66 - Fast channel (max speed) 66.5 68 - Slow channel (max speed) 66.5 68 - DS11929 Rev 11 Unit LSB bits dB STM32WB55xx STM32WB35xx Electrical characteristics Table 80. ADC accuracy - Limited test conditions 2(1)(2)(3) (continued) THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ 64 MHz, Sampling rate ≤ 4.26 Msps, VDDA ≥ 2 V TA = 25 °C Symbol Min Typ Max Fast channel (max speed) - -74 -65 Slow channel (max speed) - -74 -67 Unit Single ended dB Fast channel (max speed) - -79 -70 Slow channel (max speed) - -79 -71 Differential 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling. DS11929 Rev 11 147/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 81. ADC accuracy - Limited test conditions 3(1)(2)(3) Symbol ET Conditions(4) Parameter Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error ED EL ENOB SINAD SNR Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Signal-tonoise ratio ADC clock frequency ≤ 64 MHz, Sampling rate ≤ 4.26 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 1 Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 148/193 Min Typ Max Fast channel (max speed) - 5.5 7.5 Slow channel (max speed) - 4.5 6.5 Fast channel (max speed) - 4.5 7.5 Slow channel (max speed) - 4.5 5.5 Fast channel (max speed) - 2 5 Slow channel (max speed) - 2.5 5 Fast channel (max speed) - 2 3.5 Slow channel (max speed) - 2.5 3 Fast channel (max speed) - 4.5 7 Slow channel (max speed) - 3.5 6 Fast channel (max speed) - 3.5 4 Slow channel (max speed) - 3.5 5 Fast channel (max speed) - 1.2 1.5 Slow channel (max speed) - 1.2 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 3 3.5 Slow channel (max speed) - 2.5 3.5 Fast channel (max speed) - 2 2.5 Slow channel (max speed) - 2 2.5 Fast channel (max speed) 10 10.4 - Slow channel (max speed) 10 10.4 - Fast channel (max speed) 10.6 10.7 - Slow channel (max speed) 10.6 10.7 - Fast channel (max speed) 62 64 - Slow channel (max speed) 62 64 - Fast channel (max speed) 65 66 - Slow channel (max speed) 65 66 - Fast channel (max speed) 63 65 - Slow channel (max speed) 63 65 - Fast channel (max speed) 66 67 - Slow channel (max speed) 66 67 - DS11929 Rev 11 Unit LSB bits dB STM32WB55xx STM32WB35xx Electrical characteristics Table 81. ADC accuracy - Limited test conditions 3(1)(2)(3) (continued) THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ 64 MHz, Sampling rate ≤ 4.26 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 1 Symbol Min Typ Max Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Unit Single ended dB Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 Differential 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling. DS11929 Rev 11 149/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 82. ADC accuracy - Limited test conditions 4(1)(2)(3) Symbol ET Conditions(4) Parameter Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error ED EL ENOB SINAD SNR Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Signal-tonoise ratio ADC clock frequency ≤ 16 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 150/193 Min Typ Max Fast channel (max speed) - 5 5.4 Slow channel (max speed) - 4 5 Fast channel (max speed) - 4 5 Slow channel (max speed) - 3.5 4.5 Fast channel (max speed) - 2 4 Slow channel (max speed) - 2 4 Fast channel (max speed) - 2 3.5 Slow channel (max speed) - 2 3.5 Fast channel (max speed) - 4 4.5 Slow channel (max speed) - 4 4.5 Fast channel (max speed) - 3 4 Slow channel (max speed) - 3 4 Fast channel (max speed) - 1 1.5 Slow channel (max speed) - 1 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 2.5 3 Slow channel (max speed) - 2.5 3 Fast channel (max speed) - 2 2.5 Slow channel (max speed) - 2 2.5 Fast channel (max speed) 10.2 10.5 - Slow channel (max speed) 10.2 10.5 - Fast channel (max speed) 10.6 10.7 - Slow channel (max speed) 10.6 10.7 - Fast channel (max speed) 63 65 - Slow channel (max speed) 63 65 - Fast channel (max speed) 65 66 - Slow channel (max speed) 65 66 - Fast channel (max speed) 64 65 - Slow channel (max speed) 64 65 - Fast channel (max speed) 66 67 - Slow channel (max speed) 66 67 - DS11929 Rev 11 Unit LSB bits dB STM32WB55xx STM32WB35xx Electrical characteristics Table 82. ADC accuracy - Limited test conditions 4(1)(2)(3) (continued) Conditions(4) Parameter ADC clock frequency ≤ 16 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Symbol Total harmonic distortion THD Min Typ Max Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Unit Single ended dB Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 Differential 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins that may potentially inject negative current. 4. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disabled when VDDA ≥ 2.4 V. No oversampling. Figure 29. ADC accuracy characteristics Output code EG (1) Example of an actual transfer curve (2) Ideal transfer curve (3) End-point correlation line 2n-1 2n-2 2n-3 n = ADC resolution ET = total unajusted error: maximum deviation between the actual and ideal transfer curves EO = offset error: maximum deviation between the first actual transition and the first ideal one EG = gain error: deviation between the last ideal transition and the last actual one ED = differential linearity error: maximum deviation between actual steps and the ideal one EL = integral linearity error: maximum deviation between any actual transition and the end point correlation line (2) ET (3) 7 (1) 6 5 EO EL 4 3 ED 2 1 LSB IDEAL 1 0 1 2 3 4 5 6 7 2n-3 2n-2 2n-1 2n VREF+ (or VDDA) MS19880V4 DS11929 Rev 11 151/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Figure 30. Typical connection diagram using the ADC VDDA VT RAIN(1) VAIN Sample and hold ADC converter RADC AINx Cparasitic(2) Ilkg (3) VT 12-bit converter CADC MS33900V5 1. Refer to Table 77: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 72: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Table 72: I/O static characteristics for the values of Ilkg. General PCB design guidelines Power supply decoupling has to be performed as shown in Figure 16: Power supply scheme (all packages except UFBGA129 and WLCSP100). The 10 nF capacitor needs to be ceramic (good quality), placed as close as possible to the chip. 6.3.21 Voltage reference buffer characteristics Table 83. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode(2) Normal mode VREFBUF_ OUT Voltage reference output Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 VRS = 0 2.046 2.048 2.049 VRS = 1 2.498 2.5 2.502 VRS = 0 VDDA-150 mV - VDDA VRS = 1 VDDA-150 mV - VDDA Unit V Trim step resolution - - - ±0.05 ±0.1 % CL Load capacitor - - 0.5 1 1.5 µF esr Equivalent series resistor of Cload - - - - 2 Ω Iload Static load current - - - - 4 mA TRIM 152/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Table 83. VREFBUF characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Iload = 500 µA - 200 1000 Iload = 4 mA - 100 500 500 Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V Iload_reg Load regulation 500 μA ≤ Iload ≤4 mA Normal mode - 50 -40 °C < TJ < +125 °C - - vrefint - - Tcoeff_ vrefint + 50 DC 40 60 - 100 kHz 25 40 - CL = 0.5 µF(3) - 300 350 µF(3) - 500 650 CL = 1.5 µF(3) - 650 800 - 8 - Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 TCoeff Temperature coefficient 0 °C < TJ < +50 °C PSRR tSTART IINRUSH Power supply rejection Start-up time Control of maximum DC current drive on VREFBUF_OUT during start-up phase (4) VREFBUF IDDA consumption (VREFBUF) from VDDA CL = 1.1 - - Tcoeff_ + 50 Unit ppm/V ppm/mA ppm/ °C dB µs mA µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode the voltage reference buffer cannot maintain accurately the output voltage that will follow (VDDA - drop voltage). 3. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise. 4. To correctly control the VREFBUF in-rush current during start-up phase and scaling change, the VDDA voltage must be in the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1. DS11929 Rev 11 153/193 169 Electrical characteristics 6.3.22 STM32WB55xx STM32WB35xx Comparator characteristics Table 84. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 VIN Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA IDDA(SCALER) Parameter ±5 ±10 mV - 200 300 nA - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.7 V - - 7 VDDA ≥ 2.7 V - - 15 VDDA < 2.7 V - - 25 - - 40 VDDA ≥ 2.7 V - 55 80 VDDA < 2.7 V - 55 100 Medium mode - 0.55 0.9 Ultra-low-power mode - 4 7 Full common mode range - ±5 ±20 No hysteresis - 0 - Low hysteresis - 8 - Medium hysteresis - 15 - High hysteresis - 27 - Static - 400 600 With 50 kHz ±100 mV overdrive square signal - 1200 - Static - 5 7 With 50 kHz ±100 mV overdrive square signal - 6 - Static - 70 100 With 50 kHz ±100 mV overdrive square signal - 75 - tSTART_SCALER Scaler startup time tSTART High-speed mode Medium mode Ultra-low-power mode tD (3) Voffset Vhys Propagation delay with 100 mV overdrive Comparator offset error Comparator hysteresis High-speed mode Ultra-lowpower mode IDDA(COMP) Comparator consumption from VDDA Medium mode High-speed mode 1. Guaranteed by design, unless otherwise specified. 2. Refer to Table 36: Embedded internal voltage reference. 3. Guaranteed by characterization results. 154/193 VREFINT - Scaler static consumption BRG_EN=0 (bridge disable) from VDDA BRG_EN=1 (bridge enable) Comparator startup time to reach propagation delay specification Unit DS11929 Rev 11 µs ns µs mV mV nA µA STM32WB55xx STM32WB35xx 6.3.23 Electrical characteristics Temperature sensor characteristics Table 85. TS characteristics Symbol Parameter TL(1) VTS linearity with temperature (2) Avg_Slope Average slope Voltage at 30 °C (±5 °C)(3) V30 Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV / °C 0.742 0.76 0.785 V tSTART (TS_BUF)(1) Sensor buffer start-up time in continuous mode(4) - 8 15 µs tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs tS_temp(1) ADC sampling time when reading the temperature 5 - - µs IDD(TS)(1) Temperature sensor consumption from VDD, when selected by ADC - 4.7 7 µA 1. Guaranteed by design. 2. Guaranteed by characterization results. 3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 11: Temperature sensor calibration values. 4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 6.3.24 VBAT monitoring characteristics Table 86. VBAT monitoring characteristics(1) Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 3 x 39 - kΩ Q Ratio on VBAT measurement - 3 - - Error on Q -10 - 10 % ADC sampling time when reading VBAT 12 - - µs Er (2) tS_vbat(2) 1. 1.55 < VBAT < 3.6 V. 2. Guaranteed by design. Table 87. VBAT charging characteristics Symbol RBC Parameter Conditions Battery charging resistor Min Typ Max VBRS = 0 - 5 - VBRS = 1 - 1.5 - DS11929 Rev 11 Unit kΩ 155/193 169 Electrical characteristics 6.3.25 STM32WB55xx STM32WB35xx SMPS step-down converter characteristics The SMPS step-down converter characteristic are given at 4 MHz clock, with a 20 mA load (unless otherwise specified), using a 10 µH inductor and a 4.7 µF capacitor. 6.3.26 LCD controller characteristics The STM32WB55xx devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 88. LCD controller characteristics(1) Symbol Parameter Conditions Min Typ Max VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.62 - VLCD1 LCD internal reference voltage 1 - 2.76 - VLCD2 LCD internal reference voltage 2 - 2.89 - VLCD3 LCD internal reference voltage 3 - 3.04 - VLCD4 LCD internal reference voltage 4 - 3.19 - VLCD5 LCD internal reference voltage 5 - 3.32 - VLCD6 LCD internal reference voltage 6 - 3.46 - VLCD7 LCD internal reference voltage 7 - 3.62 - Buffer OFF  (BUFEN=0 is LCD_CR register) 0.2 - 2 Buffer ON  (BUFEN=1 is LCD_CR register) 1 - 2 Supply current from VDD at VDD = 2.2 V Buffer OFF  (BUFEN=0 is LCD_CR register) - 3 - Supply current from VDD at VDD = 3.0 V Buffer OFF  (BUFEN=0 is LCD_CR register) - 1.5 - Buffer OFF (BUFFEN = 0, PON = 0) - 0.5 - Buffer ON (BUFFEN = 1, 1/2 Bias) - 0.6 - Buffer ON (BUFFEN = 1, 1/3 Bias) - 0.8 - Buffer ON (BUFFEN = 1, 1/4 Bias) - 1 - Cext ILCD(2) IVLCD VLCD external capacitance Supply current from VLCD (VLCD = 3 V) Unit V μF μA μA RHN Total High resistor value for Low drive resistive network - 5.5 - MΩ RLN Total Low resistor value for High drive resistive network - 240 - kΩ 156/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Table 88. LCD controller characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max V44 Segment/Common highest level voltage - VLCD - V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V23 Segment/Common 2/3 level voltage - 2/3 VLCD - V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V13 Segment/Common 1/3 level voltage - 1/3 VLCD - V14 Segment/Common 1/4 level voltage - 1/4 VLCD - V0 Segment/Common lowest level voltage - 0 - Unit V 1. Guaranteed by design. 2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio = 64, all pixels active, no LCD connected. 6.3.27 Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.17 for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 89. TIMx(1) characteristics Symbol Parameter tres(TIM) Timer resolution time fEXT ResTIM tCOUNTER tMAX_COUNT Conditions Min Max Unit - 1 - tTIMxCLK 15.625 - ns 0 fTIMxCLK/2 0 40 TIM1, TIM16, TIM17 - 16 TIM2 - 32 1 65536 tTIMxCLK 0.015625 1024 µs - 65536 × 65536 tTIMxCLK - 67.10 s fTIMxCLK = 64 MHz Timer external clock frequency on CH1 to CH4 fTIMxCLK = 64 MHz Timer resolution 16-bit counter clock period Maximum possible count with 32-bit counter fTIMxCLK = 64 MHz fTIMxCLK = 64 MHz MHz bit 1. TIMx, is used as a general term where x stands for 1, 2, 16 or 17. DS11929 Rev 11 157/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 90. IWDG min/max timeout period at 32 kHz (LSI1)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF /4 0 0.125 512 /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 Unit ms 1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC period of uncertainty. 6.3.28 Clock recovery system (CRS) The devices embed a special block for the automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which can be derived from USB Sart Of Frame (SOF) signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 6.3.29 Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for:  Standard-mode (Sm): bit rate up to 100 kbit/s  Fast-mode (Fm): bit rate up to 400 kbit/s  Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s. Table 91. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Standard-mode f(I2CCLK) I2CCLK frequency Fast-mode Fast-mode Plus Min - 2 Analog filter ON, DNF = 0 9 Analog filter OFF, DNF = 1 9 Analog filter ON, DNF = 0 19 Analog filter OFF, DNF = 1 16 Unit MHz The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (see the reference manual). 158/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The 20 mA output drive requirement in Fast-mode Plus is supported partially. This limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:  tr(SDA/SCL) = 0.8473 x Rp x Cload  Rp(min) = [VDD - VOL(max)] / IOL(max) where Rp is the I2C lines pull-up. Refer to Section 6.3.17 for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter, refer to Table 92 for its characteristics. Table 92. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 110(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered SPI characteristics Unless otherwise specified, the parameters given in Table 93 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 24: General operating conditions.  Output speed is set to OSPEEDRy[1:0] = 11  Capacitive load C = 30 pF  Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.17 for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). DS11929 Rev 11 159/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 93. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master mode 1.65 < VDD < 3.6 V Voltage Range 1 32 Master transmitter mode 1.65 < VDD < 3.6 V Voltage Range 1 32 Slave receiver mode 1.65 < VDD < 3.6 V Voltage Range 1 - - 32 Slave mode transmitter/full duplex 2.7 < VDD < 3.6 V Voltage Range 1 32(2) Slave mode transmitter/full duplex 1.65 < VDD < 3.6 V Voltage Range 1 20.5(2) Voltage Range 2 Slave mode, SPI prescaler = 2 4xTPCLK - - th(NSS) Slave mode, SPI prescaler = 2 2xTPCLK - - Master mode TPCLK - 1.5 TPCLK TPCLK + 1 Master mode 1.5 - - Slave mode 1 - - Master mode 5 - - Slave mode 1 - - 9 - 34 9 - 16 Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 14.5 15.5 Slave mode 1.65 < VDD < 3.6 V Voltage Range 1 - 15.5 24 Slave mode 1.65 < VDD < 3.6 V Voltage Range 2 - 19.5 26 Master mode (after enable edge) - 2.5 3 Slave mode (after enable edge) 8 - - Master mode (after enable edge) 1 - - tw(SCKH) SCK high and low time tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time ta(SO) Data output access time tdis(SO) Data output disable time tv(SO) Data output valid time tv(MO) th(SO) th(MO) Data output hold time Slave mode MHz 8 tsu(NSS) NSS setup time NSS hold time Unit - ns ns 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50 %. 160/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Figure 31. SPI timing diagram - slave mode and CPHA = 0 SCK input NSS input MISO OUTPUT MSB OUT BIT6 OUT MSB IN BIT1 IN LSB OUT (SI) MOSI INPUT LSB IN (SI) Figure 32. SPI timing diagram - slave mode and CPHA = 1 NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. DS11929 Rev 11 161/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Figure 33. SPI timing diagram - master mode High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. 162/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Electrical characteristics Quad-SPI characteristics Unless otherwise specified, the parameters given in Table 94 and Table 95 for Quad-SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:  Output speed is set to OSPEEDRy[1:0] = 11  Capacitive load C = 15 or 20 pF  Measurement points are set at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.17 for more details on the input/output alternate function characteristics. Table 94. Quad-SPI characteristics in SDR mode(1) Symbol FCK 1/t(CK) tw(CKH) tw(CKL) Parameter Quad-SPI clock frequency Quad-SPI clock high and low time ts(IN) Data input setup time th(IN) Data input hold time tv(OUT) Data output valid time th(OUT) Data output hold time Conditions Min Typ Max 1.65 < VDD< 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 1.65 < VDD< 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 2.7 < VDD< 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 60 1.65 < VDD < 3.6 V CLOAD = 20 pF Voltage Range 2 - - 16 t(CK)/2 - 0.5 - t(CK)/2 + 1 t(CK)/2 - 1 - t(CK)/2 + 0.5 Voltage Range 1 2 - - Voltage Range 2 3.5 - - Voltage Range 1 4.5 - - Voltage Range 2 6 - - Voltage Range 1 - 1 1.5 Voltage Range 2 - 1 1.5 Voltage Range 1 0 - - Voltage Range 2 0 - - fAHBCLK= 48 MHz, presc=1 Unit MHz ns 1. Guaranteed by characterization results. DS11929 Rev 11 163/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 95. Quad-SPI characteristics in DDR mode(1) Symbol FCK 1/t(CK) Parameter Quad-SPI clock frequency tw(CKH) Quad-SPI clock high and low time t Conditions Min Typ Max 1.65 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2.0 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 50 1.65 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 1.65 < VDD < 3.6 V CLOAD = 20 pF Voltage Range 2 - - 16 t(CK)/2 - t(CK)/2 + 1 t(CK)/2 - 1 - t(CK)/2 - - - - - - - - 4 5.5 fAHBCLK = 48 MHz, presc=0 w(CKL) MHz tsr(IN) Voltage Range 1 Data input setup time on rising edge Voltage Range 2 2.5 tsf(IN) Voltage Range 1 Data input setup time on falling edge Voltage Range 2 2.5 thr(IN) Voltage Range 1 Data input hold time on rising edge Voltage Range 2 5.5 thf(IN) Voltage Range 1 Data input hold time on falling edge Voltage Range 2 5 Voltage Range 1 Data output valid tvr(OUT) time on rising edge Voltage Range 2 Voltage Range 1 Data output valid tvf(OUT) time on falling edge Voltage Range 2 Voltage Range 1 Data output hold thr(OUT) time on rising edge Voltage Range 2 Voltage Range 1 Data output hold thf(OUT) time on falling edge Voltage Range 2 3.5 1.5 6.5 6 DHHC=0 DHHC=1 DHHC=0 DHHC=0 7 4 6 t(CK)/2 + 1 t(CK)/2 + 2 6 7.5 - - - - 3.5 - - 3 - - - - - - - 2 DHHC=1 t(CK)/2 + 0.5 5 DS11929 Rev 11 t(CK)/2 + 1 t(CK)/2 + 1.5 4.5 DHHC=1 t(CK)/2 + 0.5 1. Guaranteed by characterization results. 164/193 - DHHC=0 DHHC=1 Unit ns STM32WB55xx STM32WB35xx Electrical characteristics Figure 34. Quad-SPI timing diagram - SDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tv(OUT) th(OUT) Data output D1 D0 ts(IN) Data input D0 D2 th(IN) D1 D2 MSv36878V1 Figure 35. Quad-SPI timing diagram - DDR mode tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK) Clock tvf(OUT) Data output thr(OUT) IO0 tvr(OUT) IO1 IO2 thf(OUT) IO3 tsf(IN) thf(IN) Data input IO0 IO1 IO4 IO5 tsr(IN) thr(IN) IO2 IO3 IO4 IO5 MSv36879V3 SAI characteristics Unless otherwise specified, the parameters given in Table 96 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 24: General operating conditions, with the following configuration:  Output speed is set to OSPEEDRy[1:0] = 10  Capacitive load C = 30 pF  Measurement are performed at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.17 for more details on the input/output alternate function characteristics (CK,SD,FS). DS11929 Rev 11 165/193 169 Electrical characteristics STM32WB55xx STM32WB35xx Table 96. SAI characteristics(1) Symbol Parameter Conditions Min Max fMCLK SAI main clock output - - 50 Master transmitter 2.7 V ≤ VDD ≤ 3.6 V Voltage Range 1 - 23.5 Master transmitter 1.65 V ≤ VDD ≤ 3.6 V Voltage Range 1 - 16 Master receiver Voltage Range 1 - 16 fCK tv(FS) SAI clock frequency(2) Slave transmitter 2.7 V ≤ VDD ≤ 3.6 V Voltage Range 1 FS valid time - 26 Slave transmitter 1.65 V ≤ VDD ≤ 3.6 V Voltage Range 1 - 20 Slave receiver Voltage Range 1 - 32 Voltage Range 2 - 8 Master mode 2.7 V ≤ VDD ≤ 3.6 V - 21 Master mode 1.65 V ≤ VDD ≤ 3.6 V - 30 FS hold time Master mode 10 - tsu(FS) FS setup time Slave mode 1.5 - th(FS) FS hold time Slave mode 2.5 - Master receiver 1 - Slave receiver 1.5 - Master receiver 6.5 - Slave receiver 2.5 - Slave transmitter (after enable edge) 2.7 V ≤ VDD ≤ 3.6 V - 19 Slave transmitter (after enable edge) 1.65 V ≤ VDD ≤ 3.6 V - 25 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 V ≤ VDD ≤ 3.6 V - 18.5 Master transmitter (after enable edge) 1.65 V ≤ VDD ≤ 3.6 V - 25 Master transmitter (after enable edge) 10 - tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Data input setup time Data input hold time Data output valid time Data output hold time Data output valid time Data output hold time 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. 166/193 MHz th(FS) tsu(SD_A_MR) DS11929 Rev 11 Unit ns STM32WB55xx STM32WB35xx Electrical characteristics Figure 36. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) th(SD_MT) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) SAI_SD_X (receive) Slot n+2 th(SD_MR) Slot n MS32771V1 Figure 37. SAI slave timing waveforms 1/fSCK SAI_SCK_X tw(CKH_X) SAI_FS_X (input) tw(CKL_X) tsu(FS) th(FS) th(SD_ST) tv(SD_ST) SAI_SD_X (transmit) Slot n tsu(SD_SR) SAI_SD_X (receive) Slot n+2 th(SD_SR) Slot n MS32772V1 DS11929 Rev 11 167/193 169 Electrical characteristics STM32WB55xx STM32WB35xx USB characteristics The STM32WB55xx and STM32WB35xx USB interface is fully compliant with the USB specification version 2.0, and is USB-IF certified (for Full-speed device operation). Table 97. USB electrical characteristics(1) Symbol VDDUSB Parameter Conditions Min Max Unit - 3.6 V °C USB transceiver operating voltage - USB crystal-less operation temperature - -15 - 85 RPUI Embedded USB_DP pull-up value during idle - 900 1250 1600 RPUR Embedded USB_DP pull-up value during reception - 1400 2300 3200 Driving high and low 28 36 44 Tcrystal_less ZDRV(3) Output driver impedance(4) 3.0 Typ (2) Ω 1. TA = -40 to 125 °C unless otherwise specified. 2. The STM32WB55xx and STM32WB35xx USB functionality is ensured down to 2.7 V, but the full USB electrical characteristics are degraded in the 2.7 to 3.0 V voltage range. 3. Guaranteed by design. 4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver. JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 98 and Table 99 are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:  Capacitive load C = 30 pF  Measurement points are done at CMOS levels: 0.5 ₓ VDD Table 98. JTAG characteristics Symbol 168/193 Parameter Conditions Min Typ Max 2.7 < VDD < 3.6 V - - 29 1.65 < VDD < 3.6 V - - 21 1/tc(TCK) TCK clock frequency tisu(TMS) TMS input setup time - 2.5 - - tih(TMS) TMS input hold time - 2 - - tisu(TDI) TDI input setup time - 1.5 - - tih(TDI) TDI input hold time - 2 - - 2.7 < VDD < 3.6 V - 13.5 16.5 1.65 < VDD < 3.6 V - 13.5 23 - 11 - - tov(TDO) TDO output valid time toh(TDO) TDO output hold time DS11929 Rev 11 Unit MHz ns STM32WB55xx STM32WB35xx Electrical characteristics Table 99. SWD characteristics Symbol Parameter 1/tc(SWCLK) SWCLK clock frequency Conditions Min Typ Max 2.7 < VDD < 3.6 V - - 55 1.65 < VDD < 3.6 V - - 35 tisu(TMS) SWDIO input setup time - 2.5 - - tih(TMS) SWDIO input hold time - 2 - - tov(TDO) SWDIO output valid time 2.7 < VDD < 3.6 V - 16 18 1.65 < VDD < 3.6 V - 16 28 toh(TDO) SWDIO output hold time - 13 - - Unit MHz ns Refer to Section 6.3.17 for more details on the input/output alternate function characteristics (CK, SD, WS). DS11929 Rev 11 169/193 169 Package information 7 STM32WB55xx STM32WB35xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 UFBGA129 package information This UFBGA is a 129-ball, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array package. Figure 38. UFBGA129 package outline C A4 A1 corner index area B A b (129 balls) A B fff M C A2 B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 eee M C SEATING PLANE b e E1 e F E F A1 A A D1 D ddd BOTTOM VIEW B09R_UFBGA129_ME_V2 1. Drawing is not to scale. 2. - The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug. - A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. Table 100. UFBGA129 mechanical data inches(1) millimeters Symbol 170/193 Min Typ Max Min Typ Max A(2) - - 0.60 - - 0.024 A1 - - 0.11 - - 0.004 A2 - 0.13 - - 0.005 - A4 - 0.32 - - 0.013 - b(3) 0.24 0.29 0.34 0.009 0.011 0.013 DS11929 Rev 11 C STM32WB55xx STM32WB35xx Package information Table 100. UFBGA129 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 6.85 7.00 7.15 0.270 0.276 0.281 E 6.85 7.00 7.15 0.270 0.276 0.281 D1 - 6.00 - - 0.236 - E1 - 6.00 - - 0.236 - e - 0.50 - - 0.020 - F - 0.50 - - 0.020 - - - 0.08 - - 0.003 - - 0.15 - - 0.006 - - 0.05 - - 0.002 ddd eee (4) fff(5) 1. Values in inches are converted from mm and rounded to four decimal digits. 2. - UFBGA stands for Ultra Thin Profile Fine Pitch Ball Grid Array. - Ultra thin profile: 0.50 < A ≤ 0.65mm / Fine pitch: e < 1.00mm pitch. - The total profile height (Dim A) is measured from the seating plane to the top of the component - The maximum total package height is calculated by the following methodology: A Max = A1 Typ + A2 Typ + A4 Typ + √ (A1²+A2²+A4² tolerance values). 3. The typical balls diameters before mounting is 0.20 mm. 4. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datum A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones. Figure 39. UFBGA129 recommended footprint Dpad Dsm BGA_WLCSP_FT_V1 DS11929 Rev 11 171/193 185 Package information STM32WB55xx STM32WB35xx Table 101. UFBGA129 recommended PCB design rules Dimension Recommended values Pitch 0.5 mm Dpad 0,360 mm Dsm 0.460 mm typ. (depends on soldermask registration tolerance) Stencil opening 0.360 mm Stencil thickness 0.100 mm Device marking for UFBGA129 Figure 40 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 40. UFBGA129 marking example (package top view) STM32WB Product identification(1) 55V Y WW Y Additional information Pin 1 identifier Date code MS53511V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 172/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 7.2 Package information WLCSP100 package information WLCSP100 is a 100-ball, 4.390 x 4.371 mm, 0.4 mm pitch, wafer level chip scale package. Figure 41. WLCSP100 outline e1 A1 A1 BALL LOCATION F 10 1 G A DETAIL A e4 e2 E E e K K e e3 H A3 A D D BOTTOM VIEW A2 TOP VIEW SIDE VIEW A2 BUMP FRONT VIEW A1 DETAIL A ROTATED 90 SEATING PLANE A08S_WLCSP100_ME_V1 DS11929 Rev 11 173/193 185 Package information STM32WB55xx STM32WB35xx Table 102. WLCSP100 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 0.59 - - 0.023 A1 - 0.18 - - 0.007 - A2 - 0.38 - - 0.015 - - - 0.001 - A3 - b 0.22 0.25 0.28 0.009 0.010 0.0110 D 4.38 4.40 4.42 0.1715 0.1728 0.1742 E 4.36 4.38 4.40 0.1707 0.1721 0.1735 e - 0.40 - - 0.0157 - e1 - 3.60 - - 0.1417 - e2 - 3.60 - - 0.1417 - e3 - 0.08 - - 0.0031 - e4 - 0.08 F - 0.025 (2) - - 0.0033 - 0.480 (3) - - 0.0187 - (3) - - 0.0119 - G - 0.306 H - 0.32 - - 0.0124 - K - 0.47 - - 0.0185 - aaa - - 0.10 - - 0.0039 bbb - - 0.10 - - 0.0039 ccc - - 0.10 - - 0.0039 ddd - - 0.05 - - 0.0020 eee - - 0.05 - - 0.0020 1. Values in inches are converted from mm and rounded to the third decimal place. 2. Nominal dimension rounded to the third decimal place results from process capability. 3. Calculated dimensions are rounded to third decimal place. 174/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Package information Figure 42. WLCSP100 recommended footprint Dpad Dsm A08S_WLCSP100_FP_V1 1. Dimensions are expressed in millimeters. Table 103. WLCSP100 recommended PCB design rules Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking for WLCSP100 Figure 43 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. DS11929 Rev 11 175/193 185 Package information STM32WB55xx STM32WB35xx Figure 43. WLCSP100 marking example (package top view) Pin 1 identifier WB55V Product identification(1) Y ww Y Date code MS53512V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 176/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 7.3 Package information VFQFPN68 package information VFQFPN68 is a 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat package. Figure 44. VFQFPN68 package outline PIN 1 IDENTIFIER LASER MARKING ddd C D A A1 A2 68 67 1 2 E (2X) E 0.10 C SEATING PLANE C SIDE VIEW TOP VIEW L D2 E2 2 1 PIN 1 ID C 0.30 X 45' 68 67 e b EXPOSED PAD AREA BOTTOM VIEW B029_VFQFPN68_ME_V1 1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed version. Very thin profile: 0.80 < A ≤ 1.00 mm. 2. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. Exact shape and size of this feature is optional. Table 104. VFQFPN68 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0 0.02 0.05 0 0.0008 0.0020 A3 - 0.20 - - 0.0008 - b 0.15 0.20 0.25 0.0059 0.0079 0.0098 D 7.85 8.00 8.15 0.3091 0.3150 0.3209 D2 6.30 6.40 6.50 0.2480 0.2520 0.2559 DS11929 Rev 11 177/193 185 Package information STM32WB55xx STM32WB35xx Table 104. VFQFPN68 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 7.85 8.00 8.15 0.3091 0.3150 0.3209 E2 6.30 6.40 6.50 0.2480 0.2520 0.2559 e - 0.40 - - 0.0157 - L 0.40 0.50 0.60 0.0157 0.0197 0.0236 ddd - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 45. VFQFPN68 recommended footprint 8.30 7.00 6.65 6.40 0.15 8.30 7.00 6.65 6.40 0.25 0.82 0.65 0.40 B029_VFQFPN68_FP_V2 1. Dimensions are expressed in millimeters. Device marking for VFQFPN68 Figure 45 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. 178/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Package information Figure 46. VFQFPN68 marking example (package top view) Product identification(1) STM32WB55 R Y Pin 1 identifier MS53514V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS11929 Rev 11 179/193 185 Package information 7.4 STM32WB55xx STM32WB35xx UFQFPN48 package information UFQFPN48 is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package. Figure 47. UFQFPN48 outline Pin 1 identifier laser marking area D A E E T ddd A1 Seating plane b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45° pin1 corner E2 R 0.125 typ. Detail Z 1 Z 48 A0B9_ME_V3 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package, it must be electrically connected to the PCB ground. 180/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Package information Table 105. UFQFPN48 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 48. UFQFPN48 recommended footprint 7.30 6.20 48 37 1 36 5.60 0.20 7.30 5.80 6.20 5.60 0.30 12 25 13 24 0.50 0.55 5.80 0.75 A0B9_FP_V2 1. Dimensions are expressed in millimeters. DS11929 Rev 11 181/193 185 Package information STM32WB55xx STM32WB35xx Device marking for UFQFPN48 Figure 49 and Figure 50 give examples of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 49. STM32WB55xx UFQFPN48 marking example (package top view) Product identification(1) STM32WB55 CGU6 Y Date code WW Y Pin 1 identifier Revision code MS51581V2 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. Figure 50. STM32WB35xx UFQFPN48 marking example (package top view) Product identification(1) STM32WB35 CCU6 Y WW A Pin 1 identifier Date code Revision code MS53143V2 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 182/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 7.5 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 24: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated using the equation: TJ max = TA max + (PD max x ΘJA) where:  TA max is the maximum ambient temperature in °C,  ΘJA is the package junction-to-ambient thermal resistance, in °C / W,  PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max),  PINT max is the product of IDD and VDD, expressed in Watt. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins:  PI/O max = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH) taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Note: When the SMPS is used, a portion of the power consumption is dissipated into the external inductor, therefore reducing the chip power dissipation. This portion depends mainly on the inductor ESR characteristics. Note: As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the chip power consumption. Note: RF characteristics (such as sensitivity, Tx power, consumption) are provided up to 85 °C. Table 106. Package thermal characteristics Symbol ΘJA ΘJB Parameter Value Thermal resistance junction-ambient UFQFPN48 - 7 mm x 7 mm 24.9 Thermal resistance junction-ambient VFQFPN68 - 8 mm x 8 mm 47.0 Thermal resistance junction-ambient WLCSP100 - 0.4 mm pitch 35.8 Thermal resistance junction-ambient UFBGA129 - 0.5 mm pitch 41.5 Thermal resistance junction-board UFQFPN48 - 7 mm x 7 mm 13.0 Thermal resistance junction-board VFQFPN68 - 8 mm x 8 mm 36.1 Thermal resistance junction-board WLCSP100 - 0.4 mm pitch N/A Thermal resistance junction-board UFBGA129 - 0.5 mm pitch 16.2 DS11929 Rev 11 Unit °C/W °C/W 183/193 185 Package information STM32WB55xx STM32WB35xx Table 106. Package thermal characteristics (continued) Symbol ΘJC 7.5.1 Parameter Value Thermal resistance junction-case UFQFPN48 - 7 mm x 7 mm 1.3 Thermal resistance junction-case VFQFPN68 - 8 mm x 8 mm 13.7 Thermal resistance junction-case WLCSP100 - 0.4 mm pitch N/A Thermal resistance junction-case UFBGA129 - 0.5 mm pitch 34.9 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.5.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the device at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range is best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TA max = 82 °C (measured according to JESD51-2), IDD max = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL = 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINT max = 50 mA × 3.5 V = 175 mW PIO max = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINT max = 175 mW and PIO max = 272 mW PD max = 175 + 272 = 447 mW Using the values obtained in Table 106 TJ max is calculated as follows: – For VFQFPN68, 47 °C / W TJ max = 82 °C + (47 °C / W × 447 mW) = 82 °C + 21 °C = 103 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C), see Section 8. In this case, parts must be ordered at least with the temperature range suffix 6. 184/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx Note: Package information With this given PD max user can find the TA max allowed for a given device temperature range (order code suffix 7). Suffix 7: TA max = TJ max - (47 °C / W × 447 mW) = 125 °C - 21 °C = 103 °C Example 2: High-temperature application Using the same rules, it is possible to address applications running at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TA max = 100 °C (measured according to JESD51-2), IDD max = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINT max = 50 mA × 3.5 V = 175 mW PIO max = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 175 mW and PIO max = 64 mW PD max = 175 + 64 = 239 mW Thus: PD max = 239 mW Using the values obtained in Table 106 TJ max is calculated as follows: – For UFQFPN48, 24.9 °C / W TJ max = 100 °C + (24.9 °C / W × 239 mW) = 100 °C + 6 °C = 106 °C This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8), unless user reduces the power dissipation to be able to use suffix 6 parts. DS11929 Rev 11 185/193 185 Ordering information 8 STM32WB55xx STM32WB35xx Ordering information Example: STM32 WB 55 V G V 6 A TR Device family STM32 = Arm® based 32-bit microcontroller Product type WB = Wireless Bluetooth® Device subfamily 55 = Die 5, full set of features 35 = Die 3, full set of features(1) Pin count C = 48 pins R = 68 pins V = 100 or 129 pins Flash memory size C = 256 Kbytes E = 512 Kbytes Y(2) = 640 Kbytes G = 1 Mbyte Package U = UFQFPN48 7 x 7 mm V = VFQFPN68 8 x 8 mm Y = WLCSP100 0.4 mm pitch Q = UFBGA129 0.5 mm pitch Temperature range 6 = Industrial temperature range, -40 to 85 °C (105 °C junction) 7 = Industrial temperature range, -40 to 105 °C (125 °C junction) Identification code A = Proprietary identification code blank = Non-proprietary identification code Packing TR = tape and reel xxx = programmed parts 1. STM32WB35xx only available with 48-pin UFQFPN48 package, 256 or 512 Kbytes Flash memory. 2. Only STM32WB55VY, WLCSP100 package, temperature range -40 to 85 °C (105 °C junction). 186/193 DS11929 Rev 11 STM32WB55xx STM32WB35xx 9 Revision history Revision history Table 107. Document revision history Date Revision 25-Jul-2017 1 Initial release. 2 Updated document title, Features, Section 1: Introduction, Section 2: Description, Section 3.1: Architecture, Section 3.3.2: Memory protection unit, Section 3.3.3: Embedded Flash memory, Section 3.4: Security and safety, Section 3.6: RF subsystem, Section 3.6.1: RF front-end block diagram, Section 3.6.2: BLE general description, Section 3.7.1: Power supply distribution, Section 3.7.2: Power supply schemes, Section 3.7.4: Power supply supervisor, Section 3.10: Clocks and startup, Section 3.14: Analog to digital converter (ADC), Section 3.19: True random number generator (RNG), Section 5: Memory mapping, Section 6.3.25: SMPS step-down converter characteristics and Section 7.5.2: Selecting the product temperature range. Updated Table 2: STM32WB55xx devices features and peripheral counts, Table 6: Power supply typical components, Table 7: Features over all modes, Table 8: STM32WB55xx modes overview, Table 13: Timer features, Table 15: Legend/abbreviations used in the pinout table, Table 16: STM32WB55xx pin and ball definitions, Table 17: Alternate functions, Table 23: RF transmitter BLE characteristics, Table 26: RF receiver BLE characteristics (1 Mbps) and added footnote to it, Table 28: RF BLE power consumption for VDD = 3.3 V, Table 31: RF 802.15.4 power consumption for VDD = 3.3 V, Table 37: Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V, Table 38: Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V, Table 40: Current consumption in Low-power sleep modes, Flash memory in Power down, Table 41: Current consumption in Stop 2 mode, Table 42: Current consumption in Stop 1 mode, Table 43: Current consumption in Stop 0 mode, Table 44: Current consumption in Standby mode, Table 45: Current consumption in Shutdown mode, Table 48: Peripheral current consumption, Table 104: Package thermal characteristics and Table 97: STM32WB55xx ordering information scheme. Added Table 47: Current under Reset condition. Updated Figure 1: STM32WB55xx block diagram, Figure 2: STM32WB55xx RF front-end block diagram, Figure 4: Power distribution, Figure 6: Power supply overview, Figure 7: Clock tree, Figure 8: STM32WB55Cx UFQFPN48 pinout(1)(2), Figure 9: STM32WB55Rx VFQFPN68 pinout(1)(2), Figure 10: STM32WB55Vx WLCSP100 ballout(1) and Figure 14: Power supply scheme (all packages except UFBGA129). 04-Apr-2018 Changes DS11929 Rev 11 187/193 192 Revision history STM32WB55xx STM32WB35xx Table 107. Document revision history (continued) Date 08-Oct-2018 188/193 Revision Changes 3 Changed document classification to Public. Updated Features, Section 3.6.2: BLE general description, Section 3.7.2: Power supply schemes, Section 3.7.3: Linear voltage regulator, Section 3.10: Clocks and startup, Section 6.3.10: External clock source characteristics, Section 6.3.20: Analog-to-Digital converter characteristics, Section 6.3.29: Communication interfaces characteristics, Section 7.2: WLCSP100 package information and Section 7.5: Thermal characteristics. Replaced VDDIOx with VDD throughout the whole document. Updated Table 5: Typical external components, footnote 2 of Table 7: Features over all modes, Table 8: STM32WB55xx modes overview and its footnote 5, Table 12: Internal voltage reference calibration values, Table 16: STM32WB55xx pin and ball definitions and its footnote 6, Table 17: Alternate functions, Table 20: Thermal characteristics, Table 21: Main performance at VDD = 3.3 V, Table 21: Main performance at VDD = 3.3 V, Table 22: General operating conditions, Table 23: RF transmitter BLE characteristics and its footnote, Table 26: RF receiver BLE characteristics (1 Mbps), Table 28: RF BLE power consumption for VDD = 3.3 V, Table 29: RF transmitter 802.15.4 characteristics and its footnote 1, Table 30: RF receiver 802.15.4 characteristics, Table 31: RF 802.15.4 power consumption for VDD = 3.3 V, Table 34: Embedded internal voltage reference, Table 35: Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V, Table 36: Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, VDD = 3.3 V, Table 37: Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V, Table 38: Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V, Table 39: Current consumption in Sleep and Low-power sleep modes, Flash memory ON, Table 40: Current consumption in Low-power sleep modes, Flash memory in Power down, Table 41: Current consumption in Stop 2 mode, Table 42: Current consumption in Stop 1 mode, Table 43: Current consumption in Stop 0 mode, Table 44: Current consumption in Standby mode, Table 45: Current consumption in Shutdown mode, Table 46: Current consumption in VBAT mode, Table 47: Current under Reset condition, Table 48: Peripheral current consumption, Table 49: Lowpower mode wakeup timings, Table 50: Regulator modes transition times, Table 51: Wakeup time using LPUART, Table 53: HSE clock source requirements and added footnote to it, Table 61: LSI2 oscillator characteristics, Table 63: Flash memory characteristics, Table 65: EMS characteristics, Table 67: ESD absolute maximum ratings, Table 69: I/O current injection susceptibility, Table 70: I/O static characteristics and its footnotes, Table 71: Output voltage characteristics, Table 72: I/O AC characteristics and its footnotes 1 and 2, Table 73: NRST pin characteristics, Table 77: ADC accuracy - Limited test conditions 1, Table 78: ADC accuracy - Limited test conditions 2, Table 79: ADC accuracy - Limited test conditions 3, Table 80: ADC accuracy - Limited test conditions 4, Table 82: COMP characteristics, Table 90: I2C analog filter characteristics, Table 91: SPI characteristics, Table 92: Quad-SPI characteristics in SDR mode, Table 93: Quad-SPI characteristics in DDR mode and Table 94: SAI characteristics. DS11929 Rev 11 STM32WB55xx STM32WB35xx Revision history Table 107. Document revision history (continued) Date 08-Oct-2018 20-Feb-2019 Revision Changes 3 (cont’d) Updated Figure 2: STM32WB55xx RF front-end block diagram, Figure 14: Power supply scheme (all packages except UFBGA129), Figure 18: Typical energy detection (T = 27°C, VDD = 3.3 V) and Figure 25: I/O input characteristics. Added Figure 5: Power-up/down sequence, Figure 17: Typical link quality indicator code vs. Rx level and Figure 18: Typical energy detection (T = 27°C, VDD = 3.3 V). Added Table 24: RF transmitter BLE characteristics (1 Mbps), Table 25: RF transmitter BLE characteristics (2 Mbps), Table 27: RF receiver BLE characteristics (2 Mbps), Table 52: HSE crystal requirements and Table 89: Minimum I2CCLK frequency in all I2C modes. Added Device marking for UFQFPN48. Removed former Figure 22: I/O AC characteristics definition(1) and Figure 27: SMPS efficiency - VDDSMPS = 3.6 V. 4 Updated document title. Product status moved to Production data. Introduced BGA129 package, hence updated image on cover page, Table 16: STM32WB55xx pin and ball definitions and Section 8: Ordering information, and added Figure 11: STM32WB55Vx UFBGA129 ballout(1) and Section 7.1: UFBGA129 package information. Updated Features, Section 3.3.4: Embedded SRAM, Section 3.17: Touch sensing controller (TSC) and Section 3.24: Low-power universal asynchronous receiver transmitter (LPUART). Added Section 6.3.28: Clock recovery system (CRS). Added Table 76: ADC sampling time. Removed former Table 75: Maximum ADC RAIN and Table 84: SMPS step-down converter characteristics. Updated captions of figures 8, 9 and 10. Updated Figure 43: VFQFPN68 recommended footprint. DS11929 Rev 11 189/193 192 Revision history STM32WB55xx STM32WB35xx Table 107. Document revision history (continued) Date 20-Feb-2019 04-Oct-2019 190/193 Revision Changes 4 (cont’d) Updated Table 2: STM32WB55xx devices features and peripheral counts, Table 8: STM32WB55xx modes overview and its footnotes, Table 21: Main performance at VDD = 3.3 V, Table 22: General operating conditions, Table 23: RF transmitter BLE characteristics, Table 24: RF transmitter BLE characteristics (1 Mbps), Table 25: RF transmitter BLE characteristics (2 Mbps), Table 26: RF receiver BLE characteristics (1 Mbps), Table 27: RF receiver BLE characteristics (2 Mbps), Table 28: RF BLE power consumption for VDD = 3.3 V, Table 29: RF transmitter 802.15.4 characteristics, Table 31: RF 802.15.4 power consumption for VDD = 3.3 V, Table 35: Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V, Table 36: Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, VDD = 3.3 V, Table 37: Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V, Table 38: Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V, Table 39: Current consumption in Sleep and Low-power sleep modes, Flash memory ON, Table 40: Current consumption in Low-power sleep modes, Flash memory in Power down, Table 41: Current consumption in Stop 2 mode, Table 42: Current consumption in Stop 1 mode, Table 43: Current consumption in Stop 0 mode, Table 44: Current consumption in Standby mode, Table 45: Current consumption in Shutdown mode, Table 46: Current consumption in VBAT mode, Table 47: Current under Reset condition, Table 48: Peripheral current consumption and its footnotes, Table 49: Low-power mode wakeup timings, Table 50: Regulator modes transition times and its footnote 1, Table 65: EMS characteristics, Table 66: EMI characteristics, Table 67: ESD absolute maximum ratings, Table 69: I/O current injection susceptibility, Table 75: ADC characteristics, Table 77: ADC accuracy Limited test conditions 1, Table 78: ADC accuracy - Limited test conditions 2, Table 79: ADC accuracy - Limited test conditions 3, Table 80: ADC accuracy - Limited test conditions 4 and Table 104: Package thermal characteristics. 5 Updated Features, Section 2: Description, Section 6.1.6: Power supply scheme, Section 6.2: Absolute maximum ratings and Section 7.2: WLCSP100 package information. Updated Table 6: Power supply typical components, Table 7: Features over all modes, Table 11: Temperature sensor calibration values, Table 16: STM32WB55xx pin and ball definitions, Table 17: Alternate functions, Table 21: Main performance at VDD = 3.3 V, Table 26: RF receiver BLE characteristics (1 Mbps), Table 34: Embedded internal voltage reference, Table 62: PLL, PLLSAI1 characteristics and Table 67: ESD absolute maximum ratings. Updated Figure 6: Power supply overview and Figure 33: Quad-SPI timing diagram - DDR mode. Added Figure 15: Power supply scheme (UFBGA129 package) and Figure 21: Low-speed external clock source AC timing diagram. Added Table 56: Low-speed external user clock characteristics – Bypass mode. DS11929 Rev 11 STM32WB55xx STM32WB35xx Revision history Table 107. Document revision history (continued) Date 19-Feb-2020 10-Apr-2020 17-Jun-2020 Revision Changes 6 Updated Features, Section 2: Description, I/O system current consumption, Section 3.17: Touch sensing controller (TSC), Section 7.1: UFBGA129 package information, Section 7.2: WLCSP100 package information, Section 7.3: VFQFPN68 package information, Section 7.4: UFQFPN48 package information, Section 7.5: Thermal characteristics and Section 8: Ordering information. Added JTAG/SWD interface characteristics, Device marking for UFBGA129, Device marking for WLCSP100 and Device marking for VFQFPN68. Updated Table 2: STM32WB55xx devices features and peripheral counts, Table 7: Features over all modes, Table 16: STM32WB55xx pin and ball definitions, Table 17: Alternate functions, Table 18: Voltage characteristics, Table 22: General operating conditions, Table 26: RF receiver BLE characteristics (1 Mbps), Table 27: RF receiver BLE characteristics (2 Mbps), Table 30: RF receiver 802.15.4 characteristics, Table 47: Current under Reset condition, Table 61: LSI2 oscillator characteristics and Table 104: Package thermal characteristics. Added footnote 5 to Table 15: Legend/abbreviations used in the pinout table. Updated Figure 2: STM32WB55xx RF front-end block diagram, Figure 6: Power supply overview, Figure 7: Clock tree, Figure 11: STM32WB55Vx UFBGA129 ballout(1), Figure 14: Power supply scheme (all packages except UFBGA129), Figure 36: UFBGA129 package outline and Figure 47: UFQFPN48 marking example (package top view). 7 Updated Section 3.6.5: Typical RF application schematic and Section 6.3.10: External clock source characteristics. Updated Table 16: STM32WB55xx pin and ball definitions and Table 54: HSE crystal requirements. Updated Figure 11: STM32WB55Vx UFBGA129 ballout(1) and Figure 14: Power supply scheme (all packages except UFBGA129). Minor text edits across the whole document. 8 Introduced STM32WB55VY. Updated Section 3.3.4: Embedded SRAM, Section 3.4: Security and safety, Section 3.14: Analog to digital converter (ADC), Section 6.3.10: External clock source characteristics and Section 8: Ordering information. Updated Table 1: Device summary, Table 2: STM32WB55xx and STM32WB35xx devices features and peripheral counts, Table 26: RF transmitter BLE characteristics (1 Mbps), Table 27: RF transmitter BLE characteristics (2 Mbps), Table 65: Flash memory characteristics and Table 77: ADC characteristics. Updated Figure 10: STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout(1)(2), Figure 11: STM32WB55Rx VFQFPN68 pinout(1)(2) and Figure 17: Power supply scheme (UFBGA129 and WLCSP100 packages). Updated footnote 5 of Table 15: Legend/abbreviations used in the pinout table and footnote 8 of Table 16: STM32WB55xx pin and ball definitions. Added footnote 3 to Table 16, footnote 2 to Figure 16, footnote 1 to Table 86 and footnotes to tables 23, 30 and 33. Added Table 55: HSE clock source requirements. DS11929 Rev 11 191/193 192 Revision history STM32WB55xx STM32WB35xx Table 107. Document revision history (continued) Date 02-Jul-2020 23-Nov-2020 07-Apr-2021 192/193 Revision Changes 9 Added STM32WB35xx devices. Updated Section 2: Description, Section 3.3.4: Embedded SRAM and Section 8: Ordering information. Updated Table 1: Device summary, Table 2: STM32WB55xx and STM32WB35xx devices features and peripheral counts, Table 7: Features over all modes and Table 106: Package thermal characteristics. Added Table 17: STM32WB35xx pin and ball definitions and Table 19: Alternate functions (STM32WB35xx). Added Figure 2: STM32WB35xx block diagram, Figure 8: STM32WB35xx - Power supply overview and Figure 50: STM32WB35xx UFQFPN48 marking example (package top view), Updated Figure 1: STM32WB55xx block diagram, Figure 4: External components for the RF part, Figure 16: Power supply scheme (all packages except UFBGA129 and WLCSP100), Figure 17: Power supply scheme (UFBGA129 and WLCSP100 packages) and added footnote to Figure 9: Clock tree. Added footnote 1 to Table 8: STM32WB55xx and STM32WB35xx modes overview. 10 Updated Features, Section 3.15: Voltage reference buffer (VREFBUF) and Section 3.28.2: Embedded Trace Macrocell™. Updated Table 9: STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix, Table 17: STM32WB35xx pin and ball definitions, Table 26: RF transmitter BLE characteristics (1 Mbps), Table 27: RF transmitter BLE characteristics (2 Mbps), Table 31: RF transmitter 802.15.4 characteristics, Table 50: Peripheral current consumption, Table 54: HSE crystal requirements, Table 55: HSE clock source requirements, footnote 2 of Table 57: Low-speed external user clock characteristics and Table 86: VBAT monitoring characteristics. Added footnote 2 to Table 24, footnote 2 to Table 26 and footnote 2 to Table 27. Updated Figure 9: Clock tree and Figure 13: STM32WB55Vx UFBGA129 ballout(1). Minor text edits across the whole document. 11 Updated document title, Features, Section 1: Introduction, Section 2: Description, Section 3.3.4: Embedded SRAM, Section 3.6: RF subsystem, Section 3.6.2: BLE general description and Section 6.1.2: Typical values, Section 6.3.10: External clock source characteristics. Updated Table 2: STM32WB55xx and STM32WB35xx devices features and peripheral counts, Table 16: STM32WB55xx pin and ball definitions, Table 17: STM32WB35xx pin and ball definitions, Table 18: Alternate functions (STM32WB55xx), Table 19: Alternate functions (STM32WB35xx), Table 23: Main performance at VDD = 3.3 V, Table 50: Peripheral current consumption, Table 53: Wakeup time using USART/LPUART and Table 55: HSE clock source requirements. Updated Figure 3: STM32WB55xx and STM32WB35xx RF front-end block diagram, Figure 9: Clock tree, Figure 16: Power supply scheme (all packages except UFBGA129 and WLCSP100), Figure 17: Power supply scheme (UFBGA129 and WLCSP100 packages) and Figure 29: ADC accuracy characteristics. Removed former footnote 3 from Table 83: VREFBUF characteristics. DS11929 Rev 11 STM32WB55xx STM32WB35xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS11929 Rev 11 193/193 193