STM6522

STM6522 Smart Reset Features ■ ™ Dual push-button with capacitor-adjustable setup delay Dual Smart Reset™ push-button inputs with capacitor-adjustable extended reset setup delay (tSRC) No power-on reset Dual RST output, active-low, open-drain Fixed Smart Reset™ input logic voltage levels Broad operating voltage range 1.65 V to 5.5 V, inactive reset output levels valid down to 1.0 V Low supply current (1.5 µA) Operating temperature: industrial grade –40 °C to +85 °C TDFN8 package: 2 mm x 2 mm x 0.75 mm RoHS compliant TDFN8 (DG) 2 mm x 2 mm ■ ■ ■ ■ ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ ■ Mobile phones, smartphones e-books MP3 players Games Portable navigation devices Any application that requires delayed reset push-button(s) response for improved system stability May 2010 Doc ID 17045 Rev 2 1/25 www.st.com 1 Contents STM6522 Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Primary Smart Reset™ input (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Secondary Smart Reset™ input (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Adjustable delay of Smart Reset™ (SRC pin) . . . . . . . . . . . . . . . . . . . . . 10 Reset output (RST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset output (RST2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 4 5 6 7 8 9 10 11 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 Doc ID 17045 Rev 2 STM6522 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 tSRC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 17 Parameters for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . 18 Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Doc ID 17045 Rev 2 3/25 STM6522 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Single-button Smart Reset™ typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Dual-button Smart Reset™ typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STM6522 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply current (ICC) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Smart Reset delay (tSRC) vs. temperature, CSRC = 0.6 µF. . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset timeout period (tREC) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Smart Reset™ input voltage threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . 17 Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 18 Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package marking, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 17045 Rev 2 4/25 STM6522 Description 1 Description The Smart Reset™ devices provide a useful feature that ensures that inadvertent short reset push-button closures do not cause system resets as the extended Smart Reset™ delay setup periods are implemented. Once the valid Smart Reset™ input levels and setup delay are met, the device generates an output reset pulse for a fixed timeout period (tREC). The typical application hookup shows that either a single Smart Reset™ input, or both reset inputs can be connected to the applications interrupt and control both the interrupt pin and the hard reset functions. If the push-button is closed for a short time, the processor is only interrupted. If the system still does not respond properly, holding the push-button(s) for the extended setup time (tSRC) causes a hard reset of the processor. The Smart Reset™ feature helps significantly increase system stability and eliminates the need for a dedicated reset button. The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset circuits targeted at applications such as MP3 players, portable navigation or mobile phones, generally any application that requires delayed reset push-button(s) response for improved system stability. The devices in the STM65xx Smart Reset™ family include various combinations of useful features for the targeted applications. The STM6522 has two combined Smart Reset™ inputs (SR0 and SR1) with delayed reset setup time (tSRC) programmed by an external capacitor on the SRC pin. Figure 1. Logic diagram VCC SR0 RST1 SR1 SRC STM6522 RST2 VSS AM04867v2 Doc ID 17045 Rev 2 5/25 Description Table 1. Symbol RST1 RST2 SR0 STM6522 Signal names Input/ output Output Output Input Description Open-drain reset output, active-low, no internal pull-up resistor. Open-drain reset output, active-low, no internal pull-up resistor. Primary push-button Smart Reset™ input, active-low, fixed voltage input logic levels, no internal pull-up. Secondary push-button Smart Reset™ input - combines with the primary pushbutton reset to provide setup delay time, active-low, fixed voltage input logic levels, no internal pull-up. Smart Reset™ input delay setup control: connect to an external capacitor to adjust the delay setup time (tSRC). Supply voltage input. Power supply for the device. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between VCC and VSS pins. Supply ground. No connect (not bonded); should be connected to VSS. SR1 Input SRC VCC VSS NC Input Supply Supply Figure 2. Pin connections RST2 VSS SR1 RST1 1 2 3 4 8 VCC SR0 NC SRC AM04868v2 STM6522 7 6 5 Figure 3. SR1 Block diagram tSRC generator SR0 SRC tREC generator RST1 RST2 AM04869v2 6/25 Doc ID 17045 Rev 2 STM6522 Figure 4. Single-button Smart Reset™ typical hookup VCC Description VCC RST1 SRC RESET VCC STM6522 SR1 SR0 VSS CSRC MCU INT/ NMI VSS PUSH-BUTTON SWITCH AM04870v2 Figure 5. Dual-button Smart Reset™ typical hookup VCC VCC RST1 SRC CSRC RESET VCC STM6522 SR1 MCU SR0 VSS INT/ NMI VSS PUSH-BUTTON SWITCH PUSH-BUTTON SWITCH AM004871v2 Doc ID 17045 Rev 2 7/25 Description Figure 6. Timing waveforms 1.65 V VCC STM6522 1.65 V tREC SR0 Glitch immunity tSRC SR1 RST1, RST2 AM04872v2 8/25 Doc ID 17045 Rev 2 STM6522 Pin descriptions 2 2.1 Pin descriptions Power supply (VCC) This pin is used to provide the power to the device. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between VCC and VSS pins. 2.2 Ground (VSS) This is the supply ground for the device. 2.3 Primary Smart Reset™ input (SR0) The primary push-button Smart Reset™ input, active-low pin is connected to the pushbutton switch. The input logic voltage levels are set to a fixed voltage level and have no internal pull-up resistor. 2.4 Secondary Smart Reset™ input (SR1) The secondary push-button Smart Reset™ input, active-low pin is connected to the second push-button switch. The input logic voltage levels are set to a fixed voltage level and have no internal pull-up resistor. Keeping both Smart Reset™ inputs SR0 and SR1 active for longer than tSRC activates the reset output pulse. Figure 7. STM6522 timing tSRC SR0 tREC SR1 RST1, RST2 AM04873v2 Reset is asserted “low” right after the Smart Reset™ setup delay (tSRC) has been met and returns to high after the tREC period. Doc ID 17045 Rev 2 9/25 Pin descriptions STM6522 2.5 Adjustable delay of Smart Reset™ (SRC pin) This pin controls the setup time before the push-button action is validated by the reset output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the desired value of setup time (tSRC). Selected calculated tSRC and CSRC examples are given in Table 2. Refer also to Table 5. Table 2. tSRC programmed by an ideal external capacitor Setup delay tSRC [s](1)(2) Min. 2 3 6 10 Typ. 2.5 3.75 7.5 12.5 Max. 3.0 4.5 9 15 Closest common CSRC value [µF] 0.22 0.33 0.56 1 Calculated CSRC value [µF] 0.2 0.3 0.6 1 1. At 25 ° C. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tSRC programming capacitor (CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be used and placed as close as possible to the SRC pin. Also an adequate low-leakage PCB environment should be ensured to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC is 0.1 µF. 2. In case of quickly repeated activations of tSRC counter, an interval of 10 ms min. is needed between the activations to fully discharge C SRC, so that the next tSRC is as specified. 2.6 Reset output (RST1) This output is active-low, open-drain with no internal pull-up resistor. 2.7 Reset output (RST2) This output is active-low, open-drain with no internal pull-up resistor. 10/25 Doc ID 17045 Rev 2 STM6522 Typical operating characteristics 3 Typical operating characteristics Figure 8. Supply current (ICC) vs. temperature 3 2.5 2 ICC [µA] 1.5 1 0.5 0 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V 2V AM07328 Figure 9. Smart Reset delay (tSRC) vs. temperature, CSRC = 0.6 µF 9 8.5 8 t SRC [s] 7.5 7 6.5 6 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V 2V AM07329 Doc ID 17045 Rev 2 11/25 Typical operating characteristics Figure 10. Reset timeout period (tREC) vs. temperature 280 260 240 t REC [ms] STM6522 220 200 180 160 140 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V 2V AM07330 Figure 11. Smart Reset™ input voltage threshold vs. temperature 0.8 0.7 V ITH(SR) [V] 0.6 0.5 0.4 0.3 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V 2V AM07331 12/25 Doc ID 17045 Rev 2 STM6522 Maximum ratings 4 Maximum ratings Stressing the device above the ratings listed in Table 3: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Symbol TSTG TSLD(1) Absolute maximum ratings Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Thermal resistance (junction to ambient) Input or output voltage Supply voltage TDFN8 Value –55 to +150 260 149.0 –0.3 to VCC +0.3 –0.3 to 7 Unit °C °C °C/W V V θ JA VIO VCC 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. Doc ID 17045 Rev 2 13/25 DC and AC parameters STM6522 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 4: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and measurement conditions Parameter VCC supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Value 1.65 to 5.5 –40 to +85 ≤5 0.2 to 0.8 V CC 0.3 to 0.7 V CC Unit V °C ns V V Figure 12. AC testing input/output waveforms 0.8 VCC 0.2 VCC 0.7 VCC 0.3 VCC AM00478 14/25 Doc ID 17045 Rev 2 STM6522 Table 5. Symbol VCC ICC DC and AC parameters DC and AC characteristics Parameter Supply voltage range Supply current VCC = 5.0 V VCC = 3.0 V VCC ≥ 4.5 V, sinking 3.2 mA Reset output voltage low (active-low reset asserted) Test conditions(1) Min. 1.65 2 1.5 0.3 0.3 0.3 140 210 280 Typ.(2) Max. 5.5 3 Unit V µA µA V V V ms VOL VCC ≥ 3.3 V, sinking 2.5 mA VCC ≥ 1.65 V, sinking 1 mA tREC Reset timeout delay, factory programmed Smart Reset™ inputs VIL VIH ILI(SR) SR0, SR1 input voltage low SR0, SR1 input voltage high Input leakage current, SRx input VSS – 0.3 0.85 –1 0.3 5.5 +1 V V µA Smart Reset™ delay tSRC(3) Delayed Smart Reset™ T = 25 °C setup time. Refer to Table 2. A 10 x CSRC 12.5 x CSRC (µF) (µF) 15 x CSRC (µF) s 1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.65 to 5.5 V (except where noted). 2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted. 3. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite). Doc ID 17045 Rev 2 15/25 Package mechanical data STM6522 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 16/25 Doc ID 17045 Rev 2 STM6522 Package mechanical data Figure 13. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline D A B PIN 1 INDEX AREA E 0.10 C 2x 0.10 C 2x TOP VIEW 0.10 C A A1 SEAT ING PLANE SIDE VIEW C 0.08 C e PIN 1 INDEX AREA b 1 4 0.10 CAB Pin#1 ID L 8 BOTTOM VIEW 5 8070540_A Table 6. Symbol TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data Dimension (mm) Min. Nom. 0.75 0.02 0.20 2.00 2.00 0.50 0.45 0.55 0.65 0.018 Max. 0.80 0.05 0.25 2.1 2.1 Min. 0.028 0.000 0.006 0.075 0.075 Dimension (inches) Nom. 0.030 0.001 0.008 0.079 0.079 0.020 0.022 0.026 Max. 0.031 0.002 0.010 0.083 0.083 A A1 b D BSC E BSC e L 0.70 0.00 0.15 1.9 1.9 Doc ID 17045 Rev 2 17/25 Package footprint STM6522 7 Package footprint Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad D P E E1 L b AM00441 Table 7. Parameter L b E E1 D P Parameters for landing pattern - TDFN – 8-lead 2 x 2 mm package Dimension (mm) Description Min. Contact length Contact width Max. land pattern Y-direction Contact gap spacing Max. land pattern X-direction Contact pitch 1.05 0.25 Nom. Max. 1.15 0.30 — — 2.85 0.65 1.75 0.5 — — — — — — — — 18/25 Doc ID 17045 Rev 2 STM6522 Tape and reel information 8 Tape and reel information Figure 15. Carrier tape P0 D T A0 Top cover tape B0 P2 E F W K0 Center lines of cavity User direction of feed P1 AM03073v2 Table 8. Package Carrier tape dimensions W 8.00 +0.30 –0.10 D 1.50 +0.10/ –0.00 E P0 P2 F A0 2.30 ±0.05 B0 2.30 ±0.05 K0 1.00 ±0.05 P1 4.00 ±0.10 T 0.250 ±0.05 Unit Bulk qty. TDFN8 1.75 4.00 2.00 3.50 ±0.10 ±0.10 ±0.10 ±0.05 mm 3000 Doc ID 17045 Rev 2 19/25 Tape and reel information Figure 16. Reel dimensions STM6522 T 40 mm min. acces hole at slot location B D A C N Full radius Tape slot in core for tape start 25 mm min width G measured at hub AM00443 Table 9. Tape sizes 8 mm Reel dimensions A max. 180 (7 inches) B min. 1.50 C 13.0 +/– 0.20 D min. 20.20 N min. 60 G 8.4 +2/–0 T max. 14.40 20/25 Doc ID 17045 Rev 2 STM6522 Figure 17. Tape trailer/leader End Tape and reel information Start Top cover tape No components T RA IL ER 160 mm min. Components 100 mm min. No components L EA D ER 400 mm min. Sealed with cover tape User direction of feed AM00444 Figure 18. Pin 1 orientation User direction of feed AM00442 Note: 1 2 Drawings are not to scale. All dimensions are in mm, unless otherwise noted. Doc ID 17045 Rev 2 21/25 Part numbering STM6522 9 Table 10. Example: Part numbering Ordering information scheme STM6522 A A A A DG 6 F Device type STM6522 VCC monitoring, power-on reset A = no V CC monitoring, no power-on reset Smart Reset™ setup delay (tSRC); presence of internal input pull-up on all Smart Reset™ inputs (SRx) A = user-programmed (external capacitor); no input pull-up Output type A = both RST1 and RST2 open-drain, no pull-up, active-low Reset timeout period (tREC) A = 140 ms min. Package DG = TDFN8 2 x 2 x 0.75 mm, 0.5 mm pitch Temperature range 6 = –40 °C to +85 °C Shipping method F = ECOPACK® package, tape and reel For device options currently available refer to Table 11. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 22/25 Doc ID 17045 Rev 2 STM6522 Package marking 10 Package marking Table 11. Package marking Smart tSRC delay Reset™ control inputs(1) CSRC AL Power-on reset, VCC monitoring — RST1 RST2 tREC Topmark output(1) output(1) option AL, OD AL, OD A AAL Part number STM6522AAAADG6F 1. AL = active-low, AH = active-high, PU = with internal pull-up resistor, OD = open-drain. Figure 19. Package marking, top view A B C D E Topmark A = dot (pin 1 reference) B = assembly plant (P) C = assembly year (Y, 0-9): 9 = 2009 etc. D = assembly work week (WW, 01 to 52): 20 = WW20 etc. E = marking area (topmark) AM00479 Doc ID 17045 Rev 2 23/25 Revision history STM6522 11 Revision history Table 12. Date 03-Feb-2010 Document revision history Revision 1 Initial release. Updated title, Features, Applications, Section 1, Figure 1, Table 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Section 2.4, Figure 7, note 1 below Table 2, Section 2.6, added Section 2.7, Section 3, Table 5, Table 6, Table 7, Table 10, Section 8, Table 11. Changes 10-May-2010 2 24/25 Doc ID 17045 Rev 2 STM6522 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 17045 Rev 2 25/25