STM6823

STM6321/6322 STM6821/6822/6823/6824/6825 5-pin supervisor with watchdog timer and push-button reset Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Precision VCC monitoring of 5, 3.3, 3, or 2.5 V power supplies RST outputs (active-low, push-pull or open drain) RST outputs (active-high, push-pull) Reset pulse width of 1.4 ms, 200 ms and 240 ms (typ)(a) Watchdog timeout period of 1.6 s (typ)(a) Manual reset input (MR) Low supply current - 3 µA (typ) Guaranteed RST (RST) assertion down to VCC = 1.0 V Operating temperature: –40 to +85°C (industrial grade) RoHS compliance Lead-free components are compliant with the RoHS directive Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability. Device summary Reset output Part number Watchdog input Manual reset input Active-low (push-pull) Active-high (push-pull) ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ Active-low (open drain) ✔ ✔ SOT23-5 (WY) a. Table 1. STM6321 STM6322 STM6821 STM6822 STM6823 STM6824 STM6825 ✔ June 2008 Rev 8 1/28 www.st.com 1 Contents STM6321/6322STM6821/6822/6823/6824/6825 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825 . . 7 Active-low, open drain reset output (RST) - STM6321/6322/6822 . . . . . 7 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Active-high reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 2.5 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Open drain RST output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Push-button reset input (STM6322/6821/6822/6823/6825) . . . . . . . . . . . 11 Watchdog input (STM6321/6821/6822/6823/6824) . . . . . . . . . . . . . . . . . 11 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5.1 2.5.2 Watchdog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . 11 2.6 Interfacing to microprocessors with bidirectional reset pins . . . . . . . . . . . 12 3 4 5 6 7 8 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/28 STM6321/6322STM6821/6822/6823/6824/6825 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC and AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/28 List of figures STM6321/6322STM6821/6822/6823/6824/6825 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic diagram (STM6321/6322/6824/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 STM6822/6823 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6821 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6322/6825 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6321/6824 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram (STM6321/6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM6321/6322/6822 open drain RST output with multiple supplies . . . . . . . . . . . . . . . . . 10 Ensuring RST valid to VCC = 0, (active-low push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 12 Ensuring RST valid to VCC = 0, (active-high, push-pull outputs) . . . . . . . . . . . . . . . . . . . . 12 Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MR-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized reset threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Normalized power-up watchdog time-out period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage output low vs. ISINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage output high vs. ISOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23 4/28 STM6321/6322STM6821/6822/6823/6824/6825 Description 1 Description The STM6xxx supervisors are self-contained devices which provide microprocessor supervisory functions. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM6322/6825) and/or a push-button (MR) reset input. These devices are available in a standard 5-pin SOT23 package. Figure 1. Logic diagram (STM6821/6822/6823) VCC WDI STM6XXX MR RST (RST)(1) VSS AI09128 1. For STM6821 only. Figure 2. Logic diagram (STM6321/6322/6824/6825) VCC RST (WDI) (1) MR STM6XXX RST VSS AI09129 1. For STM6321/6824. Table 2. MR WDI RST RST VCC VSS Signal names Push-button reset input Watchdog input Active-low reset output Active-high reset output Supply voltage Ground 5/28 Description Figure 3. STM6321/6322STM6821/6822/6823/6824/6825 STM6822/6823 SOT23-5 connections SOT23-5 RST(1) VSS MR 1 2 3 5 4 VCC WDI AI09130a 1. Open drain for STM6822. Figure 4. STM6821 SOT23-5 connections SOT23-5 RST(1) VSS MR 1 2 3 5 4 VCC WDI AI12285 1. Push-pull only. Figure 5. STM6322/6825 SOT23-5 connections SOT23-5 RST(1) VSS RST(2) 1 2 3 5 4 VCC MR AI09131a 1. Open drain for STM6322. 2. Push-pull only. Figure 6. STM6321/6824 SOT23-5 connections SOT23-5 RST(1) VSS RST(2) 1 2 3 5 4 VCC WDI AI12286 1. Open drain for STM6321. 2. Push-pull only. 6/28 STM6321/6322STM6821/6822/6823/6824/6825 Description 1.1 1.1.1 Pin descriptions Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825 Pulses low when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. 1.1.2 Active-low, open drain reset output (RST) - STM6321/6322/6822 Pulses low when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. Connect a pull-up resistor to supply voltage. 1.1.3 Push-button reset input (MR) A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal 52 kΩ pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused. 1.1.4 Watchdog input (WDI) If WDI remains high or low for at least 1.6s, the internal watchdog timer expires and reset is asserted. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function CAN be disabled if WDI is left unconnected or is connected to a tri-state buffer output. 1.1.5 Active-high reset output (RST) Active-high, push-pull reset output; inverse of RST. Table 3. Pin functions Pin STM6822 STM6823 1 3 4 — 5 2 STM6821 — 3 4 1 5 2 STM6321 STM6824 1 — 4 3 5 2 STM6322 STM6825 1 4 — 3 5 2 RST MR WDI RST VCC VSS Active-low reset output Push-button reset input Watchdog Input Active-high reset output Supply voltage Ground Name Function 7/28 Description STM6321/6322STM6821/6822/6823/6824/6825 Figure 7. Block diagram (STM6821/6822/6823) WDI Transitional Detector WATCHDOG TIMER trec Generator WDI VCC VCC VRST COMPARE RST (RST) (1,2) MR AI09132a 1. Push-pull for STM6823, open drain for STM6822. 2. Active-high (push-pull) for STM6821. Figure 8. Block diagram (STM6321/6824) WDI Transitional Detector WATCHDOG TIMER trec Generator RST(1) RST(2) A12287 WDI VCC VRST COMPARE 3. Active-low (open drain) for STM6321, active-low (push-pull) for STM6824. 4. Push-pull only. Figure 9. Block diagram (STM6322/6825) VCC VCC VRST COMPARE RST(1) RST(2) trec Generator MR AI12288 1. Active-low (open drain) for STM6322, active-low (push-pull) for STM6825. 2. Push-pull only. 8/28 STM6321/6322STM6821/6822/6823/6824/6825 Description Figure 10. Hardware hookup VCC VCC 0.1μF STM6XXX From Microprocessor WDI (1) Push-button MR (2) RST (RST) RST (3) (4) To Microprocessor Reset To Microprocessor Reset AI09133 1. For STM6321/6821/6822/6823/6824 2. For STM6322/6821/6822/6823/6825 3. For STM6821/ (RST output only) 4. For STM6321/6322/6824/6825 (both RST and RST outputs) 9/28 Operation STM6321/6322STM6821/6822/6823/6824/6825 2 2.1 Operation Reset output The STM6xxx Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1 V for TA = 0°C to 85°C. During power-up, once VCC exceeds the reset threshold an internal timer keeps reset low for the reset time-out period, trec. After this interval reset is de-asserted. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. 2.2 Open drain RST output The STM6321/6322/6822 have an active-low, open drain reset output. This output structure will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply voltage up to 6 V (see Figure 11). Select a resistor value large enough to register a logic low, and small enough to register a logic high while supplying all input current and leakage paths connected to the reset output line. A 10 kΩ pull-up resistor is sufficient in most applications. Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies 3.3V 5.0V VCC STM6XXX MR(1) WDI(2) RST(3) RST GND AI09137 10k 5V System 1. STM6322/6822 2. STM6321/6822 3. STM6321/6322 10/28 STM6321/6322STM6821/6822/6823/6824/6825 Operation 2.3 Push-button reset input (STM6322/6821/6822/6823/6825) A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 25 on page 19) after it returns high. The MR input has an internal 52 kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used. 2.4 Watchdog input (STM6321/6821/6822/6823/6824) The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6 sec), the reset is asserted. The internal watchdog timer is cleared by either: 1. 2. a reset pulse, or by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns. The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting. Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and the maximum allowable load capacitance is 200 pF. 2.5 2.5.1 Applications information Watchdog input current The WDI input is internally driven through a buffer and series resistor from the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period. When high, WDI can draw as much as 160µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog time-out period by a low-high-low pulse from the counter chain. 2.5.2 Ensuring a valid reset output down to VCC = 0 V The STM6xxx supervisors are guaranteed to operate properly down to VCC = 1 V. In applications that require valid reset levels down to VCC = 0, a pull-down resistor to activelow outputs (push/pull only, see Figure 12 on page 12) and a pull-up resistor to active-high outputs (push/pull only, see Figure 13 on page 12) will ensure that the reset line is valid while the reset output can no longer sink or source current. This scheme does not work with the open drain outputs of the STM6321/6322/6822. The resistor value used is not critical, but it must be large enough not to load the reset output when VCC is above the reset threshold. For most applications, 100 kΩ is adequate. 11/28 Operation STM6321/6322STM6821/6822/6823/6824/6825 Figure 12. Ensuring RST valid to VCC = 0, (active-low push-pull outputs) STM6XXX VCC GND RST R1 AI09138 VCC Figure 13. Ensuring RST valid to VCC = 0, (active-high, push-pull outputs) STM6XXX VCC GND RST VCC R1 AI09139 1. This configuration does not work on open drain outputs of the STM6321/6322/6822. 2.6 Interfacing to microprocessors with bidirectional reset pins Microprocessors with bidirectional reset pins can contend with the STM6321 / 6322 / 6821 / 6822 / 6823 / 6824 / 6825 reset output. For example, if the reset output is driven high and the microprocessor wants to pull it low, signal contention will result. To prevent this from occurring, connect a 4.7 kΩ resistor between the reset output and the microprocessor’s reset I/O as in Figure 14. Figure 14. Interfacing to microprocessors with bidirectional reset I/O Buffered Reset to other System Components VCC STM6XXX 4.7k RST RST VCC Microprocessor GND GND AI09135 12/28 STM6321/6322STM6821/6822/6823/6824/6825 Typical operating characteristics 3 Typical operating characteristics Figure 15. VCC-to-reset output delay vs. temperature 35 30 Reset Output Delay (µs) 25 20 15 10 5 0 –40 –20 0 20 40 60 80 AI09627a Temperature (˚C) Figure 16. Supply current vs. temperature 7 6 Supply Current (µA) 5 4 3 2 1 0 –40 VCC = 3V VCC = 5V –20 0 20 40 60 80 AI09628a Temperature (˚C) 13/28 Typical operating characteristics STM6321/6322STM6821/6822/6823/6824/6825 Figure 17. MR-to-reset output delay vs. temperature 600 Reset Output Delay (ns) 500 400 300 200 100 0 –40 –20 0 20 40 60 80 AI09669 Temperature (˚C) Figure 18. Normalized power-up trec vs. temperature 1.05 Normalized Power-up trec 1.04 1.03 1.02 1.01 1.00 0.99 –40 –20 0 20 40 60 80 AI09670 Temperature (˚C) 14/28 STM6321/6322STM6821/6822/6823/6824/6825 Typical operating characteristics Figure 19. Normalized reset threshold voltage vs. temperature 1.05 1.04 Normalized Reset Threshold Voltage 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 –40 –20 0 20 40 60 80 AI09631a Temperature (˚C) Figure 20. Normalized power-up watchdog time-out period Normalized Watchdog Time-out Period 1.05 1.04 1.03 1.02 1.01 1.00 0.99 –40 –20 0 20 40 60 80 AI09671 Temperature (˚C) 15/28 Typical operating characteristics Figure 21. Voltage output low vs. ISINK 0.35 STM6321/6322STM6821/6822/6823/6824/6825 0.30 0.25 VOUT (V) 0.20 VCC = 2.9V 0.15 0.10 0.05 0.00 0 1 2 3 4 5 6 AI09634a ISINK (mA) Figure 22. Voltage output high vs. ISOURCE 2.92 2.90 2.88 2.86 VOUT (V) 2.84 VCC = 2.9V 2.82 2.80 2.78 2.76 2.74 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 AI09635a ISOURCE (mA) 16/28 STM6321/6322STM6821/6822/6823/6824/6825 Typical operating characteristics Figure 23. Maximum transient duration vs. reset threshold overdrive 35 30 Transient Duration (µs) 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 180 200 AI09637a S Z L Reset Threshold Overdrive (mV) 17/28 Maximum ratings STM6321/6322STM6821/6822/6823/6824/6825 4 Maximum ratings Stressing the device above the rating listed in Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Symbol TSTG TSLD (1) Absolute maximum ratings Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation Value –55 to 150 260 –0.3 to VCC + 0.3 –0.3 to 7.0 20 320 Unit °C °C V V mA mW VIO VCC IO PD 1. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds). 18/28 STM6321/6322STM6821/6822/6823/6824/6825 DC and AC parameters 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement conditions Parameter VCC supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages STM6xxx 1.0 to 5.5 –40 to 85 ≤5 0.2 to 0.8VCC 0.3 to 0.7VCC Unit V °C ns V V Figure 24. AC testing input/output waveforms 0.8VCC 0.7VCC 0.3VCC AI02568 0.2VCC Figure 25. MR timing waveform MR tMLRL RST (1) tMLMH trec AI07837a 1. RST for STM6322/6821/6825. Figure 26. Watchdog timing VCC RST trec WDI tWD AI09136 19/28 DC and AC parameters Table 6. Sym VCC STM6321/6322STM6821/6822/6823/6824/6825 DC and AC characteristic Alternative Description Operating voltage VCC supply current (MR and WDI unconnected) T/S/R/Z/Y (VCC < 3.6 V) L/M (VCC < 5.5 V) T/S/R/Z/Y (VCC < 3.6 V) L/M (VCC < 5.5 V) 0V = VIN = VCC WDI = VCC, time average WDI = GND, time average VCC > VRST, Reset not asserted VRST > 4.0 V VRST < 4.0 V Input high voltage (WDI) (4) Input low voltage (MR) Input low voltage (WDI) (4) Test condition (1) Min 1.2 (2) Typ Max 5.5 Unit V µA µA µA µA µA µA µA 4 6 3 3 –1 120 –20 –1 2.0 0.7VCC 0.7VCC –15 12 17 8 12 +1 160 ICC VCC supply current (MR unconnected; STM6322/6825) Input leakage current ILI Input leakage current (WDI)(3) Open drain reset output leakage current Input high voltage (MR) ILO VIH VIH VIL VIL +1 µA V V V VRST (max) < VCC < 5.5 V VRST > 4.0 V VRST < 4.0 V VRST (max) < VCC < 5.5 V VCC ≥ 1.0 V, ISINK = 50 µA, Reset asserted VCC ≥ 1.2 V, ISINK = 100 µA, Reset asserted VCC ≥ 2.7 V, ISINK = 1.2 mA, Reset asserted VCC ≥ 4.5 V, ISINK = 3.2 mA, Reset asserted VCC ≥ 2.7 V, ISINK = 1.2 mA, Reset not asserted VCC ≥ 4.5 V, ISINK = 3.2 mA, Reset not asserted 0.8 0.3VCC 0.3VCC 0.3 0.3 0.3 0.4 0.3 0.4 V V V V V V V V V Output low voltage (RST; push-pull or open drain) VOL Output low voltage (RST; push-pull only) 20/28 STM6321/6322STM6821/6822/6823/6824/6825 Table 6. Sym DC and AC parameters DC and AC characteristic (continued) Alternative Description Test condition (1) VCC ≥ 2.7 V, ISOURCE = 500 µA, Reset not asserted Output high voltage (RST) VCC ≥ 4.5 V, ISOURCE = 800 µA , Reset not asserted VCC ≥ 1.0 V, ISOURCE = 1 µA, Reset asserted (0°C to 85°C) VCC ≥ 1.5 V, ISOURCE = 100 µA, Reset asserted Min Typ Max Unit 0.8VCC 0.8VCC 0.8VCC 0.8VCC V V V V V V VOH Output high voltage (RST) VCC ≥ 2.55 V, ISOURCE = 500 µA, 0.8VCC Reset asserted VCC ≥ 4.25 V, ISOURCE = 800 µA, 0.8VCC Reset asserted Reset Thresholds 25°C STM6xxxL –40 to 85°C 25°C STM6xxxM –40 to 85°C 25°C STM6xxxT –40 to 85°C VRST(5) 25°C Reset threshold STM6xxxS –40 to 85°C 25°C STM6xxxR –40 to 85°C 25°C STM6xxxZ –40 to 85°C 25°C STM6xxxY –40 to 85°C L/M versions Reset threshold hysteresis T/S/R/Z/Y versions VCC to RST delay (VRST – VCC = 100 mV, VCC falling at 1 mV/µs) A trec (6) Reset pulse width Blank J 1 140 240 5 20 1.4 200 360 2 280 480 1.950 10 2.050 2.243 1.970 2.000 2.358 2.030 2.564 2.266 2.300 2.696 2.335 2.857 2.590 2.630 3.000 2.660 3.000 2.890 2.930 3.150 2.960 4.270 3.040 3.080 4.490 3.110 4.514 4.314 4.390 4.746 4.446 4.561 4.630 4.699 V V V V V V V V V V V V V V mV mV µs ms ms ms 21/28 DC and AC parameters Table 6. Sym STM6321/6322STM6821/6822/6823/6824/6825 DC and AC characteristic (continued) Alternative Description Reset threshold temperature coefficient Test condition (1) Min Typ 40 Max Unit ppm/C Push-button Reset Input tMLMH tMLRL tMR tMRD MR pulse width MR to RST output delay MR glitch immunity MR pull-up resistor Watchdog Timer tWD (6) Watchdog timeout period WDI pulse width(7) VCC ≥ 3.0 V 1.12 50 1.60 2.24 s ns 35 1 500 100 52 75 µs ns ns kΩ 1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5 V for “L/M” versions; VCC = 2.7 to 3.6 V for “T/S/R” versions; and VCC = 1.2 to 2.75 V for “Z/Y” version (except where noted). 2. VCC (min) = 1.0 V for TA = 0 to +85°C. 3. WDI input is designed to be driven by a three-state output device. To float WDI, the “high-impedance mode” of the output device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device must also be able to source and sink at least 200 µA when active. 4. WDI is internally serviced within the watchdog period if WDI is left unconnected. 5. The leakage current measured on the RST pin is tested with the reset asserted (output high impedance). 6. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability. 7. For VCC < 3.0 V, tWD(min) = 100 ns. 22/28 STM6321/6322STM6821/6822/6823/6824/6825 Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing SOT23-5L 1. Drawing is not to scale. 23/28 Package mechanical data Table 7. Symb Typ A A1 A2 B C D D1 E e F K L 0.35 1.05 0.40 0.15 2.90 1.90 2.80 0.95 1.60 1.50 0° 0.10 2.60 0.90 0.35 0.09 2.80 1.20 Min 0.90 STM6321/6322STM6821/6822/6823/6824/6825 SOT23-5 – 5-lead small outline transistor package mechanical data mm Max 1.45 0.15 1.30 0.50 0.20 3.00 0.041 0.016 0.006 0.114 0.075 3.00 0.110 0.037 1.75 10° 0.60 0.014 0.063 0.059 0° 0.004 0.069 10° 0.024 0.102 0.118 0.035 0.014 0.004 0.110 Typ 0.047 inches Min 0.035 Max 0.057 0.006 0.051 0.020 0.008 0.118 24/28 STM6321/6322STM6821/6822/6823/6824/6825 Part numbering 7 Part numbering Table 8. Example: Device type STM6xxx Reset threshold voltage L: VRST = 4.514 to 4.746 V M: VRST = 4.270 to 4.490 V T: VRST = 3.000 to 3.150 V S: VRST = 2.850 to 3.000 V R: VRST = 2.564 to 2.696 V Z: VRST = 2.243 to 2.358 V Y: VRST = 1.950 to 2.050 V Reset pulse width (1) A: trec = 1 to 2 ms Blank: trec = 140 to 280 ms J: trec = 240 to 480 ms Package WY = SOT23-5 Temperature range 6 = –40 to 85°C Shipping method E = ECOPACK® package, tubes F = ECOPACK® package, tape & reel Ordering information scheme STM6xxx L WY 6 E 1. Contact local sales office for availability. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 25/28 Part numbering Table 9. Marking description STM6321/6322STM6821/6822/6823/6824/6825 Part number STM6321LWY6F STM6321MAWY6F STM6321MWY6F STM6321TWY6F STM6321SWY6F STM6321RWY6F STM6322LWY6F STM6322MWY6F STM6322TWY6F STM6322SWY6F STM6322RWY6F STM6821LWY6F STM6821MWY6F STM6821TWY6F STM6821SWY6F STM6821RWY6F STM6822LWY6F STM6822MWY6F STM6822TWY6F STM6822SWY6F STM6822RWY6F STM6822ZWY6F STM6822YWY6F STM6823LWY6F STM6823MWY6F STM6823TJWY6F STM6823TWY6F STM6823SJWY6F STM6823SWY6F STM6823RJWY6F STM6823RWY6F STM6824LWY6F STM6824MWY6F STM6824TWY6F STM6824SWY6F STM6824RWY6F STM6825LWY6F STM6825MWY6F STM6825TWY6F STM6825SWY6F STM6825RWY6F Reset threshold (V) 4.630 4.390 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 2.300 2.000 4.630 4.390 3.080 3.080 2.930 2.930 2.630 2.630 4.630 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 Reset pulse width (ms) 200 1.4 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 280 200 280 200 280 200 200 200 200 200 200 200 200 200 200 200 Topside marking 5AUx 5CRx 5AVx 5AWx 5AXx 5AYx 5BAx 5BBx 5BCx 5BDx 5BEx 5BGx 5BHx 5BJx 5BKx 5BLx 5BNx 5BPx 5BQx 5BRx 5BSx 5BTx 5CTx 5BUx 5BVx 5CMx 5BWx 5CNx 5BXx 5CPx 5BYx 5CAx 5CBx 5CCx 5CDx 5CEx 5CGx 5CHx 5CJx 5CKx 5CLx Note: Where “x” = assembly work week (A to Z), such that “A” = WW01-02, “B” = WW03-04, and so forth. 26/28 STM6321/6322STM6821/6822/6823/6824/6825 Revision history 8 Revision history Table 10. Date 25-Aug-2004 15-Dec-2004 10-Mar-2005 17-Jun-2005 11-Apr-2006 11-Aug-2006 25-May-2007 03-Jun-2008 Document revision history Revision 1 2 3 4 5 6 7 8 First draft Update characteristics (Figure 15, 16, 17; Table 6, and 8) Document promoted to Datasheet status Package marking update (Table 9) Update characteristics, Lead-free text, availability (Figure 3, 4, 5, 6, 7, 8, and 9; Table 1, 6, 8, and 9) Update Description, Table 8, and 9. Formatting changes, updated Table 9. Updated cover page; updated reset threshold values in Table 6, 8, and 9; addition of text to Section 6; updated Figure 27 and Table 6 and 7; minor text changes. Changes 27/28 STM6321/6322STM6821/6822/6823/6824/6825 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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