STM706PDS6E

STM706T/S/R, STM706P, STM708T/S/R 3 V supervisor Datasheet - production data Features • Precision VCC monitor – T: 3.00 V ≤ VRST ≤ 3.15 V – S: 2.88 V ≤ VRST ≤ 3.00 V – R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V  • RST and RST outputs • 200 ms (typ.) trec  • Watchdog timer - 1.6 s (typ.) 620 • Manual reset input (MR) • Power-fail comparator (PFI/PFO) • Low supply current - 40 µA (typ.) • Guaranteed RST (RST) assertion down to VCC = 1.0 V • Operating temperature: –40 °C to 85 °C (industrial grade) • RoHS compliance – Lead-free components are compliant with the RoHS directive 76623['6 &RQWDFWORFDO67VDOHVRIILFHIRUDYDLODELOLW\ Applications • Computers • Controllers • Intelligent instruments Table 1. Device summary STM706T/S/R STM706P (2) Watchdog input Watchdog output(1) Active low RST (1) ✓ ✓ ✓ ✓ ✓ STM708T/S/R ✓ Active high RST(1) Manual reset input Power-fail comparator ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 1. Push-pull output. 2. The STM706P device is identical to the STM706R device, except its reset output is active high. December 2015 This is information on a product in full production. DocID10518 Rev 13 1/32 www.st.com Contents STM706T/S/R, STM706P, STM708T/S/R Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 2.1 MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 WDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 Watchdog input (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . .11 3.4 Watchdog output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . .11 3.5 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . . 12 3.7 Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 13 4 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 SO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 TSSOP8 3x3 (DS) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO8 - 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . . . 27 TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID10518 Rev 13 3/32 3 List of figures STM706T/S/R, STM706P, STM708T/S/R List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. 4/32 Logic diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 STM706T/S/R and STM706P SO8 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM706T/S/R and STM706P TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM708T/S/R SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM708T/S/R TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Watchdog timeout period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output voltage vs. load current (VCC = 5 V; TA = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Watchdog timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO8 - 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . . . 27 TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, package outline . . . . . . . 28 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R 1 Description Description The STM70x supervisors are self-contained devices which provide microprocessor supervisory functions. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM708T/S/R) as well as a power-fail comparator to provide the system with an early warning of impending power failure. The STM706P device is identical to the STM706R device, except its reset output is active high. These devices are available in a standard 8-pin SOIC package or a space-saving 8pin TSSOP package. Figure 1. Logic diagram (STM706T/S/R and STM706P) VCC WDI MR WDO STM706T/S/R, STM706P RST (RST)(1) PFO PFI VSS AI08841 1. For STM706P only. Figure 2. Logic diagram (STM708T/S/R) VCC RST MR STM708T/S/R RST PFI PFO VSS DocID10518 Rev 13 AI08842 5/32 31 Description STM706T/S/R, STM706P, STM708T/S/R Table 2. Signal names Symbol Name MR Push-button reset input WDI Watchdog input WDO Watchdog output RST Active low reset output RST (1) Active high reset output VCC Supply voltage PFI Power-fail input PFO Power-fail output VSS Ground NC No connect 1. For STM706P and STM708T/S/R only. Figure 3. STM706T/S/R and STM706P SO8 connections SO8 MR 1 8 VCC VSS 2 7 3 6 WDI PFI 4 5 PFO WDO RST(RST)(1) AI08837 1. For STM706P reset output is active high. Figure 4. STM706T/S/R and STM706P TSSOP8 connections TSSOP8 (1) RST(RST) 1 8 WDI WDO 2 7 PFO MR 3 6 PFI VCC 4 5 VSS AI08838 1. For STM706P reset output is active high. Figure 5. STM708T/S/R SO8 connections SO8 MR 1 8 RST VCC VSS 2 7 RST 3 6 NC PFI 4 5 PFO AI08839 6/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R Description Figure 6. STM708T/S/R TSSOP8 connections TSSOP8 RST 1 8 NC RST 2 7 PFO MR 3 6 PFI VCC 4 5 VSS AI08840 DocID10518 Rev 13 7/32 31 Pin descriptions 2 Pin descriptions 2.1 MR STM706T/S/R, STM706P, STM708T/S/R A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused. 2.2 WDI If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset (or WDO) is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function can be disabled by allowing the WDI pin to float. This feature is available for the “D” version only (see Section 8: Part numbering). 2.3 WDO WDO goes low when a transition does not occur on WDI within 1.6 s, and remains low until a transition occurs on WDI (indicating the watchdog interrupt has been serviced) or MR input is asserted (goes low). WDO also goes low when VCC falls below the reset threshold; however, unlike the reset output, WDO goes high as soon as VCC exceeds the reset threshold. Output type is push-pull. Note: For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO is connected to MR. 2.4 RST Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. 2.5 RST Pulses high for trec when triggered, and stays high whenever VCC is above the reset threshold or when MR is a logic high. It remains high for trec after either VCC falls below the reset threshold, the watchdog triggers a reset, or MR goes from high to low. 2.6 PFI When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Connect to ground if unused. 8/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R 2.7 Pin descriptions PFO When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Output type is push-pull. PFO pin is not supposed to be forced low by a processor. MR input is gated off during the period PFO is forced low. Leave open if unused. Table 3. Pin description Pin STM706P STM706T/S/R STM708T/S/R Name Function SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 1 3 1 3 1 3 MR Push-button reset input 6 8 6 8 — — WDI Watchdog input 8 2 8 2 — — WDO Watchdog output (push-pull) — — 7 1 7 1 RST Active low reset output 7 1 — — 8 2 RST Active high reset output 2 4 2 4 2 4 VCC Supply voltage 4 6 4 6 4 6 PFI Power-fail input 5 7 5 7 5 7 PFO Power-fail output (push-pull) 3 5 3 5 3 5 VSS Ground — — — — 6 8 NC No connect Figure 7. Block diagram (STM706T/S/R and STM706P) WDI transitional detector WDI VCC WATCHDOG TIMER VRST WDO COMPARE VCC trec generator MR RST (RST)(1) PFI VPFI COMPARE PFO AI08829 1. For STM706P only DocID10518 Rev 13 9/32 31 Pin descriptions STM706T/S/R, STM706P, STM708T/S/R Figure 8. Block diagram (STM708T/S/R) VCC COMPARE VRST RST VCC trec generator MR PFI COMPARE VPFI RST PFO AI08830 Figure 9. Hardware hookup Regulator Unregulated voltage VIN VCC VCC STM706T/S/R; STM706P; STM708T/S/R 0.1 μF WDI(1) R1 WDO(1) To microprocessor IRQ PFI PFO To microprocessor NMI MR RST RST(2) From microprocessor R2 Push-button To microprocessor reset AI08843 1. For STM706T/S/R and STM706P devices 2. For STM706P and STM708T/S/R devices 10/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R 3 Operation 3.1 Reset output Operation The STM70x supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog timeout occurs (if WDO is connected to MR), or when the push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM706P and STM708T/S/R) for VCC < VRST down to VCC =1 V for TA = 0 °C to 85 °C. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset timeout period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset timeout period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. 3.2 Push-button reset input A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 27) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain / collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used. 3.3 Watchdog input (STM706T/S/R and STM706P) The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the watchdog input (WDI) within tWD (1.6 s), the watchdog output pin (WDO) is asserted. The internal 1.6s timer is cleared by either: 1. a reset pulse, or 2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns. See Figure 28 for STM706T/S/R and STM706P. The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting. Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and the maximum allowable load capacitance is 200 pF. 3.4 Watchdog output (STM706T/S/R and STM706P) When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it to the MR input. DocID10518 Rev 13 11/32 31 Operation 3.5 STM706T/S/R, STM706P, STM708T/S/R Power-fail input/output The power-fail input (PFI) is compared to an internal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM70x or the microprocessor drops below the minimum operating voltage. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. PFO may be connected to MR on the STM70x so that a low voltage on PFI will generate a reset output. 3.6 Ensuring a valid reset output down to VCC = 0 V When VCC falls below 1 V, the state of the RST output can no longer be guaranteed, and becomes essentially an open circuit. If a high value pulldown resistor is added to the RST pin, the output will be held low during this condition. A resistor value of approximately 100 kΩ will be large enough to not load the output under operating conditions, but still sufficient to pull RST to ground during this low voltage condition (see Figure 10). Figure 10. Reset output valid to ground circuit STM70x RST R1 AI08844 12/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R 3.7 Operation Interfacing to microprocessors with bi-directional reset pins Microprocessors with bi-directional reset pins can contend with the STM70x reset output. For example, if the reset output is driven high and the micro wants to pull it low, signal contention will result. To prevent this from occurring, connect a 4.7kΩ resistor between the reset output and the micro's reset I/O as in Figure 11. Figure 11. Interfacing to microprocessors with bi-directional reset I/O Buffered reset to other system components VCC VCC STM70x Microprocessor 4.7 kΩ RST GND RST GND AI08845 DocID10518 Rev 13 13/32 31 Typical operating characteristics 4 STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics Typical values are at TA = 25 °C. Figure 12. Supply current vs. temperature (no load) 30 25 Supply current (µA) 20 15 VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.5 V VCC = 5.5 V 10 5 0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09141b 14/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics Figure 13. VPFI threshold vs. temperature 1.270 1.265 V PFI threshold (V) 1.260 1.255 VCC = 2.5 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V 1.250 1.245 1.240 1.235 1.230 1.225 –40 –20 0 20 40 Temperature (°C) 60 80 100 120 AI09142b Figure 14. Reset comparator propagation delay vs. temperature 30 28 Propagation delay (µs) 26 24 22 20 18 16 14 12 10 –40 –20 0 20 40 60 Temperature (°C) DocID10518 Rev 13 80 100 120 AI09143b 15/32 31 Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R Figure 15. Power-up trec vs. temperature 240 235 t rec (ms) 230 VCC = 3.0 V 225 VCC = 4.5 V VCC = 5.5 V 220 215 210 –40 –20 0 20 40 60 Temperature (°C) 80 100 120 AI09144b Figure 16. Normalized reset threshold vs. temperature Normalized reset threshold 1.004 1.002 1.000 0.998 0.996 –40 –20 0 20 40 60 Temperature (°C) 16/32 DocID10518 Rev 13 80 100 120 AI09145b STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics Figure 17. Watchdog timeout period vs. temperature 1.90 Watchdog timeout period (s) 1.85 1.80 1.75 VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V 1.70 1.65 1.60 –40 –20 0 20 40 60 80 100 120 Temperature (˚ C) AI09146b Figure 18. PFI to PFO propagation delay vs. temperature 4.0 VCC = 3.0 V VCC = 3.6 V PFI to PFO propagation dela 3.0 VCC = 4.5 V VCC = 5.5 V 2.0 1.0 0.0 –40 –20 0 20 40 60 Temperature (˚C) DocID10518 Rev 13 80 100 120 AI09148b 17/32 31 Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R Figure 19. Output voltage vs. load current (VCC = 5 V; TA = 25 °C) 5.00 V OUT (V) 4.98 4.96 4.94 0 10 20 30 40 50 I OUT (mA) AI10496 Figure 20. RST output voltage vs. supply voltage 5 5 V RST (V) VRST VCC 4 4 3 3 2 2 1 1 0 0 V CC (V) 500 ms / div 18/32 DocID10518 Rev 13 AI09149b STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics Figure 21. RST output voltage vs. supply voltage 5 5 V RST VCC V RST (V) 4 4 3 3 V CC (V) 2 2 1 1 0 0 500 ms / div AI09150b Figure 22. Power-fail comparator response time (assertion) 9  9  GLY 3)2 9  9 3),  P9  GLY 9  QV  GLY DocID10518 Rev 13 19/32 31 Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R Figure 23. Power-fail comparator response time (de-assertion) 9  9  GLY 3)2 9  9 3),  P9  GLY 9  QV  GLY Figure 24. Maximum transient duration vs. reset threshold overdrive 6000 Transient duration (µs) 5000 4000 Reset occurs above the curve 3000 2000 1000 0 0.001 0.01 0.1 Reset comparator overdrive, V RST – V CC (V) 20/32 DocID10518 Rev 13 1 10 AI09156b STM706T/S/R, STM706P, STM708T/S/R 5 Maximum ratings Maximum ratings Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 5: Operating and AC measurement conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings Symbol TSTG TSLD(1) VIO(2) Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Input or output voltage Value Unit –55 to 150 °C 260 °C –0.3 to VCC +0.3 V VCC Supply voltage –0.3 to 7.0 V IO Output current 20 mA PD Power dissipation 320 mW 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. 2. Negative undershoot of –1.5 V for up to 10 ns or positive overshoot of VCC + 1.5 V for up to 10 ns is allowable on the WDI and MR input pins. DocID10518 Rev 13 21/32 31 DC and AC parameters 6 STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in Table 6: DC and AC characteristics are derived from tests performed under the measurement conditions summarized in Table 5: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement conditions Parameter STM70x Unit VCC supply voltage 1.0 to 5.5 V Ambient operating temperature (TA) –40 to 85 °C ≤5 ns Input pulse voltages 0.2 to 0.8 VCC V Input and output timing ref. voltages 0.3 to 0.7 VCC V Input rise and fall times Figure 25. AC testing input/output waveforms 0.8 V CC 0.7 V CC 0.3 V CC 0.2 V CC AI02568 Figure 26. Power-fail comparator waveform VCC VRST trec PFO RST AI08860a 22/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters Figure 27. MR timing waveform MR RST (1) tMLRL tMLMH trec AI07837a 1. RST for STM706P and STM708T/S/R. Figure 28. Watchdog timing (STM706T/S/R and STM706P) VCC RST trec tWD WDI WDO AI08833 DocID10518 Rev 13 23/32 31 DC and AC parameters STM706T/S/R, STM706P, STM708T/S/R Table 6. DC and AC characteristics Symbol Description VCC Operating voltage ICC VCC supply current ILI Typ. 1.2(2) Max. Unit 5.5 V VCC < 3.6 V 35 50 µA VCC < 5.5 V 40 60 µA 0 V < VIN < VCC –1 +1 µA Input leakage current (WDI) with watchdog disable feature (“D” version) 0 V < VIN < VCC -110 110 µA Input leakage current (PFI) 0 V < VIN < VCC –25 2 +25 nA VRST (max.) < VCC < 3.6 V 25 80 250 µA 4.5 V < VCC < 5.5 V 75 125 300 µA 4.5 V < VCC < 5.5 V 2.0 V VRST (max.) < VCC < 3.6 V 0.7 VCC V VRST (max.) < VCC < 5.5 V 0.7 VCC V VIH Input high voltage (MR) VIH Input high voltage (WDI) VIL Input low voltage (MR) VIL Input low voltage (WDI) VOL Output low voltage (PFO, RST, RST, WDO) VOH Min. Input leakage current (WDI) Input leakage current (MR) VOL Test condition(1) Output low voltage (RST) 4.5 V < VCC < 5.5 V 0.8 V VRST (max.) < VCC < 3.6 V 0.6 V VRST (max.) < VCC < 5.5 V 0.3 VCC V VCC = VRST (max.), ISINK = 3.2 mA 0.3 V ISINK = 50 µA, VCC = 1.0 V, TA = 0 °C to 85 °C 0.3 V ISINK = 100 µA, VCC = 1.2 V 0.3 V Output high voltage (RST, RST, WDO) ISOURCE = 1 mA, VCC = VRST (max.) 2.4 V Output high voltage (PFO) ISOURCE = 75 µA, VCC = VRST (max.) 0.8 VCC V PFI falling (STM70xP/R, VCC = 3.0 V; STM70xS/T, VCC = 3.3 V) 1.20 Power-fail comparator VPFI PFI input threshold tPFD PFI to PFO propagation delay 24/32 1.25 2 DocID10518 Rev 13 1.30 V µs STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters Table 6. DC and AC characteristics (continued) Symbol Description Test condition(1) Min. Typ. Max. Unit STM706P/70xR 2.55 2.63 2.70 V STM70xS 2.85 2.93 3.00 V STM70xT 3.00 3.08 3.15 V Reset thresholds VRST Reset threshold(3) Reset threshold hysteresis trec 20 RST pulse width mV Blank (see Table 9) 140 200 280 A(4) (see Table 9) 160 200 280 VRST (max.) < VCC < 3.6 V 500 ns 4.5 V < VCC < 5.5 V 150 ns ms Push-button reset input tMLMH (or tMR) MR pulse width tMLRL MR to RST output delay (or tMRD) VRST (max.) < VCC < 3.6 V 750 ns 4.5 V < VCC < 5.5 V 250 ns 2.24 s Watchdog timer (STM706T/S/R and STM706P) tWD Watchdog timeout period WDI pulse width STM706P/70xR, VCC = 3.0 V 1.12 1.60 STM70xS/70XT, VCC = 3.3 V 4.5 V < VCC < 5.5 V 50 ns VRST (max.) < VCC < 3.6 V 100 ns 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = VRST (max.) to 5.5 V (except where noted). 2. VCC (min) = 1.0 V for TA = 0 °C to +85 °C. 3. For VCC falling. 4. STM706P/STM70xR device, VCC = 3 V; STM706xS/STM70xT device, VCC = 3.3 V. DocID10518 Rev 13 25/32 31 Package information 7 STM706T/S/R, STM706P, STM708T/S/R Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 26/32 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R 7.1 Package information SO8 package information Figure 29. SO8 - 8-lead plastic small outline, 150 mils body width, package outline A2 A C B ddd e D 8 E H 1 A1 L SO-A Note: Drawing is not to scale. Table 7. SO8 - 8-lead plastic small outline, 150 mils body width, mechanical data Dimensions Symbol mm inches Typ. Min. Max. Typ. Min. Max. A — 1.35 1.75 — 0.053 0.069 A1 — 0.10 0.25 — 0.004 0.010 B — 0.33 0.51 — 0.013 0.020 C — 0.19 0.25 — 0.007 0.010 D — 4.80 5.00 — 0.189 0.197 ddd — — 0.10 — — 0.004 E — 3.80 4.00 — 0.150 0.157 e 1.27 — — 0.050 — — H — 5.80 6.20 — 0.228 0.244 h — 0.25 0.50 — 0.010 0.020 L — 0.40 0.90 — 0.016 0.035 α — 0° 8° — 0° 8° N 8 8 DocID10518 Rev 13 27/32 31 Package information 7.2 STM706T/S/R, STM706P, STM708T/S/R TSSOP8 3x3 (DS) package information Figure 30. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, package outline D 8 5 c E1 1 E 4 A1 A L A2 L1 CP b e TSSOP8BM Note: Drawing is not to scale. Table 8. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data Dimensions Symbol 28/32 mm inches Typ. Min. Max. Typ. Min. Max. A — — 1.10 — — 0.043 A1 — 0.05 0.15 — 0.002 0.006 A2 0.85 0.75 0.95 0.034 0.030 0.037 b — 0.25 0.40 — 0.010 0.016 c — 0.13 0.23 — 0.005 0.009 CP — — 0.10 — — 0.004 D 3.00 2.90 3.10 0.118 0.114 0.122 e 0.65 — — 0.026 — — E 4.90 4.65 5.15 0.193 0.183 0.203 E1 3.00 2.90 3.10 0.118 0.114 0.122 L 0.55 0.40 0.70 0.022 0.016 0.030 L1 0.95 — — 0.037 — — α — 0° 6° — 0° 6° N 8 8 DocID10518 Rev 13 STM706T/S/R, STM706P, STM708T/S/R 8 Part numbering Part numbering Table 9. Ordering information scheme Example: STM706 T D M 6 F Device type STM706 STM708 Reset threshold voltage T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V Watchdog disable Blank = not activated D = activated RST pulse width Blank = 140 to 280 ms A(1) = 160 to 280 ms Package M = SO8 DS(2) = TSSOP8 Temperature range 6 = –40 to 85 °C Shipping method F = ECOPACK® packages, tape and reel 1. Available in SO8 (M) package only 2. Contact local ST sales office for availability For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. DocID10518 Rev 13 29/32 31 Part numbering STM706T/S/R, STM706P, STM708T/S/R Table 10. Marking description 30/32 Part number Reset threshold STM706P 2.63 V STM706T 3.08 V STM706S 2.93 V STM706R 2.63 V STM706RD 2.63 V STM708T 3.08 V STM708S 2.93 V STM708R 2.63 V DocID10518 Rev 13 Package SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 Topside marking 706P 706T 706S 706R 706RD 708T 708S 708R STM706T/S/R, STM706P, STM708T/S/R 9 Revision history Revision history Table 11. Document revision history Date Revision Oct-2003 1 Initial release. 12-Dec-2003 2 Reformatted; update characteristics (Figure 2, 3, 8 to 10, 27 to 29; Table 6 to 9). 16-Jan-2004 2.1 Add Typical operating characteristics (Figure 13, to 19, 21, to 25). 09-Apr-2004 3 Reformatted; update characteristics (Figure 15, 19, 21, 22, 25; Table 8). 25-May-2004 4 Update characteristics (Table 3, Table 6). 02-Jul-2004 5 Datasheet promoted; waveform corrected (Table 27). 21-Sep-2004 6 Clarify root part numbers; (Figure 2, to 10, 29; Table 1, 3, 6, 9). 25-Feb-2005 7 Update typical characteristics (Figure 13 to 25). 02-Nov-2009 8 Updated Table 1, Table 3, Table 4, Table 6, Table 9, Section 2.3, Section 2.7, text in Section 7; reformatted document. 30-Apr-2010 9 Updated Table 4, corrected typo in Table 2, Section 2.3, Section 3, Section 5 and Section 6, Figure 17, Table 7 and Table 8. 06-Aug-2010 10 Updated Features, Section 4: Typical operating characteristics; Table 9. 06-Sep-2011 11 Updated Section 2.7, Section 5 and Disclaimer, minor typo modifications throughout the document. 21-Aug-2012 12 Added Applications, updated Section 2.2 and Section 2.3, added note to Section 3.3, added cross-references in Section 5 and Section 6, minor text corrections throughout document. 13 Updated layout of cover page and Section 7: Package information. Added information about the watchdog disable function to Section 2.2: WDI, Table 6, Table 9, and Table 10. Table 9: removed the “E” option (tubes) from shipping method 15-Dec-2015 Changes DocID10518 Rev 13 31/32 31 STM706T/S/R, STM706P, STM708T/S/R IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 32/32 DocID10518 Rev 13