STM8AF5286UAX

STM8AF526x/8x/Ax STM8AF6269/8x/Ax Automotive 8-bit MCU, with up to 128 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V Datasheet - production data Features • AEC-Q10x qualified • Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Program memory: 32 to 128 Kbyte Flash program; data retention 20 years at 55 °C – Data memory: up to 2 Kbyte true data EEPROM; endurance 300 kcycle – RAM: 6 Kbyte • Clock management – Low-power crystal resonator oscillator with external clock input – Internal, user-trimmable 16 MHz RC and low-power 128 kHz RC oscillators – Clock security system with clock monitor • Reset and supply management – Wait/auto-wakeup/Halt low-power modes with user definable clock gating – Low consumption power-on and powerdown reset • Interrupt management – Nested interrupt controller with 32 vectors – Up to 37 external interrupts on 5 vectors • Timers – 2 general purpose 16-bit timers with up to 3 CAPCOM channels each (IC, OC, PWM) – Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization – 8-bit AR basic timer with 8-bit prescaler – Auto-wakeup timer – Window and independent watchdog timers • I/Os – Up to 68 user pins (11 high sink I/Os) November 2016 This is information on a product in full production. LQFP80 14x14 mm LQFP64 10x10 mm LQFP32 7x7 mm LQFP48 7x7 mm VFQFP32 5x5 mm – Highly robust I/O design, immune against current injection • Communication interfaces – High speed 1 Mbit/s CAN 2.0B interface – USART with clock output for synchronous operation - LIN master mode – LINUART LIN 2.2 compliant, master/slave modes with automatic resynchronization – SPI interface up to 10 Mbit/s or fMASTER/2 – I2C interface up to 400 Kbit/s • Analog to digital converter (ADC) – 10-bit resolution, 2 LSB TUE, 1 LSB linearity and up to 16 multiplexed channels • Operating temperature up to 150 °C • Qualification conforms to AEC-Q100 grade 0 Table 1. Device summary(1) Reference Part number STM8AF5268, STM8AF5269, STM8AF526x/8x/Ax STM8AF5286, STM8AF5288, STM8AF5289, STM8AF528A, (with CAN) STM8AF52A6, STM8AF52A8, STM8AF52A9, STM8AF52AA STM8AF6269, STM8AF6286, STM8AF6288, STM8AF6289, STM8AF6269/8x/Ax STM8AF628A, STM8AF62A6, STM8AF62A8, STM8AF62A9, STM8AF62AA 1. In the order code, ‘F’ applies to devices with Flash program memory and data EEPROM. ‘F’ is replaced by ‘P’ for devices with FASTROM (see Table 2, Table 3 and Figure 60). DocID14395 Rev 15 1/125 www.st.com Contents STM8AF526x/8x/Ax STM8AF6269/8x/Ax Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 5.2 5.1.1 Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.3 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 15 5.2.1 SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 2/125 STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4.2 Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.3 Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.4 Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5.2 16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 17 5.5.3 128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 18 5.5.4 24 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . . 18 5.5.5 External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.6 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.1 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.2 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.3 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 7 5.7.4 Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 20 5.7.5 Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10 6 Contents 5.9.1 Universal synchronous/asynchronous receiver transmitter (USART) . . 22 5.9.2 Universal asynchronous receiver/transmitter with LIN support (LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.9.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9.4 Inter integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9.5 Controller area network interface (beCAN) . . . . . . . . . . . . . . . . . . . . . . 26 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 68 10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 70 DocID14395 Rev 15 3/125 4 Contents STM8AF526x/8x/Ax STM8AF6269/8x/Ax 10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.8 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 80 10.3.9 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.3.10 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.1 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.5 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.6.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 110 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .112 13.1.1 13.2 13.3 14 4/125 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 13.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8AF526x/8x/Ax product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STM8AF6269/8x/Ax product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Peripheral clock gating bits (CLK_PCKENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Peripheral clock gating bits (CLK_PCKENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Legend/abbreviation for the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description . . . . . . . . . . . . . . . . . . . . . . 34 Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Temporary memory unprotection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Total current consumption in Run, Wait and Slow mode. General conditions for VDD apply, TA = -40 °C to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Total current consumption in Halt and Active-halt modes. General conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical peripheral current consumption VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC accuracy for VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DocID14395 Rev 15 5/125 6 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. 6/125 STM8AF526x/8x/Ax STM8AF6269/8x/Ax ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block diagram . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STM8AF62xx LQFP/VFQFPN 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM8AF52x6 VFQFPN32 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67 Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 67 Typ. IDD(RUN)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67 Typ. IDD(WFI)HSE vs. VDD @ fCPU = 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67 Typ. IDD(WFI)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 67 Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical HSI frequency vs VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical LSI frequency vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical pull-up resistance RPU vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 75 Typical pull-up current Ipu vs VDD @ four temperatures(1) . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD - VOH @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typical NRST VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typical NRST pull-up resistance RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical NRST pull-up current Ipu vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI timing diagram in slave mode and with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SPI timing diagram in slave mode and with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 90 LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 LQFP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DocID14395 Rev 15 7/125 8 List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. 8/125 STM8AF526x/8x/Ax STM8AF6269/8x/Ax LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 94 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 97 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 101 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 VFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1 . . . . . . . . . 111 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 1 Introduction Introduction This datasheet refers to the STM8AF526x/8x/Ax and STM8AF6269/8x/Ax products with 32 to 128 Kbyte of program memory. In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM and ‘P’ to product versions with FASTROM. The identifiers ‘F’ and ‘P’ do not coexist in a given order code. The datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8A microcontroller memory, registers and peripherals, please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016). • For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S and STM8A Flash programming manual (PM0051). • For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). • For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). DocID14395 Rev 15 9/125 114 Description 2 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Description The STM8AF526x/8x/Ax and STM8AF6269/8x/Ax automotive 8-bit microcontrollers described in this datasheet offer from 32 Kbyte to 128 Kbyte of non volatile memory and integrated true data EEPROM. They are referred to as high density STM8A devices in STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016). The STM8AF52 series features a CAN interface. All devices of the STM8A product line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity. The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, wtachdog, and brown-out reset. Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system. Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map, and modular peripherals. Full documentation is offered with a wide choice of development tools. Product longevity is ensured in the STM8A family thanks to their advanced core which is made in a state-of-the art technology for automotive applications with 3.3 V to 5.5 V operating supply. All STM8A and ST7 microcontrollers are supported by the same tools including STVD/STVP development environment, the STice emulator and a low-cost, third party incircuit debugging tool. 10/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 3 Product line-up Product line-up .. Table 2. STM8AF526x/8x/Ax product line-up with CAN Order code Package STM8AF/P52AA LQFP80 (14x14) STM8AF/P528A STM8AF/P52A9 STM8AF/P5289 LQFP64 (10x10) STM8AF/P5268 2K 16 64 K 1K 6K 64 K 32 K STM8AF/P5286 2K Serial interfaces 1x8-bit: TIM4 CAN, 3x16-bit: TIM1, LIN(UART), TIM2, TIM3 SPI, (9/9/9) USART, I²C 10 I/0 wakeup pins 52/36 38/35 1K 64 K VFQFPN32 (5x5) Timers (IC/OC/PWM) 68/37 64 K 128 K LQFP48 (7x7) 10-bit A/D chan. 128 K 32 K STM8AF/P52A8 STM8AF/P52A6 Data RAM EEPROM (bytes) (bytes) 128 K STM8AF/P5269 STM8AF/P5288 High density Flash program memory (bytes) 2K 128 K 6 1x8-bit: TIM4 CAN, 3x16-bit: TIM1, LIN(UART), TIM2, TIM3 I²C (8/8/8) 25/24 Table 3. STM8AF6269/8x/Ax product line-up without CAN Order code Package STM8AF/P62AA LQFP80 (14x14) STM8AF/P628A STM8AF/P62A9 STM8AF/P6289 10-bit A/D chan. Timers (IC/OC/PWM) Serial interfaces 128 K 64 K 16 2K 32 K 128 K STM8AF/P6286 LQFP32 (7x7) 64 K STM8AF/P62A6 VFQFPN32 (5x5) I/0 wakeup pins 68/37 2K 64 K LQFP48 (7x7) STM8AF/P6288 Data RAM EEPROM (bytes) (bytes) 128 K LQFP64 (10x10) STM8AF/P6269 STM8AF/P62A8 High density Flash program memory (bytes) 1K 1x8-bit: TIM4 LIN(UART), 3x16-bit: TIM1, SPI, TIM2, TIM3 USART, I²C (9/9/9) 52/36 6K 10 2K 7 128 K 38/35 1x8-bit: TIM4 3x16-bit: TIM1, LIN(UART), TIM2, TIM3 SPI, I²C (8/8/8) 25/23 . DocID14395 Rev 15 11/125 114 Block diagram 4 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Block diagram Figure 1. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block diagram 5HVHWEORFN ;7$/0+] &ORFNFRQWUROOHU 5HVHW 5HVHW 5&LQW0+] 'HWHFWRU 325 %25 5&LQWN+] &ORFNWRSHULSKHUDOVDQGFRUH :LQGRZ:'* 670$FRUH ,QGHSHQGHQW:'* 0DVWHUVODYH DXWRPDWLF UHV\QFKURQL]DWLRQ 86$57 .ELWV ,& 0ELWV 63, /,1PDVWHU 63,HPXO 0ELWV 8SWR.E\WH KLJKGHQVLW\ SURJUDP)ODVK 'HEXJ6:,0 $GGUHVVDQGGDWDEXV 6LQJOHZLUH GHEXJLQWHUIDFH 8SWR.E\WH GDWD((3520 8SWR.E\WH5$0 %RRW520 ELWDGYDQFHGFRQWURO WLPHU7,0 /,18$57 ELWJHQHUDOSXUSRVH WLPHUV7,07,0 EH&$1 8SWR &$3&20 FKDQQHOV ELW$5WLPHU 7,0 8SWRFKDQQHOV ELW$'& $:8WLPHU 069 12/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Block diagram 1. Legend: ADC: Analog-to-digital converter beCAN: Controller area network BOR: Brownout reset I²C: Inter-integrated circuit multimaster interface IWDG: Independent window watchdog LINUART: Local interconnect network universal asynchronous receiver transmitter POR: Power on reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter Window WDG: Window watchdog DocID14395 Rev 15 13/125 114 Product overview 5 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Product overview This section is intended to describe the family features that are actually implemented in the products covered by this datasheet. For more detailed information on each feature please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016). 5.1 STM8A central processing unit (CPU) The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency and performance. It contains 21 internal registers (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions. 5.1.1 5.1.2 5.1.3 14/125 Architecture and registers • Harvard architecture • 3-stage pipeline • 32-bit wide program memory bus with single cycle fetching for most instructions • X and Y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations • 8-bit accumulator • 24-bit program counter with 16-Mbyte linear memory space • 16-bit stack pointer with access to a 64 Kbyte stack • 8-bit condition code register with seven condition flags for the result of the last instruction. Addressing • 20 addressing modes • Indexed indirect addressing mode for look-up tables located anywhere in the address space • Stack pointer relative addressing mode for efficient implementation of local variables and parameter passing Instruction set • 80 instructions with 2-byte average instruction size • Standard data movement and logic/arithmetic functions • 8-bit by 8-bit multiplication • 16-bit by 8-bit and 16-bit by 16-bit division • Bit manipulation • Data transfer between stack and accumulator (push/pop) with direct stack access • Data transfer using the X and Y registers or direct memory-to-memory transfers DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Product overview 5.2 Single wire interface module (SWIM) and debug module (DM) 5.2.1 SWIM The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. The interface can be activated in all device operation modes and can be connected to a running device (hot plugging).The maximum data transmission speed is 145 bytes/ms. 5.2.2 Debug module The non-intrusive debugging module features a performance close to a full-flavored emulator. Besides memory and peripheral operation, CPU operation can also be monitored in real-time by means of shadow registers. 5.3 5.4 • R/W of RAM and peripheral registers in real-time • R/W for all resources when the application is stopped • Breakpoints on all program-memory instructions (software breakpoints), except the interrupt vector table • Two advanced breakpoints and 23 predefined breakpoint configurations Interrupt controller • Nested interrupts with three software priority levels • 24 interrupt vectors with hardware priority • Five vectors for external interrupts (up to 37 depending on the package) • Trap and reset interrupts Flash program and data EEPROM • 32 Kbytes to 128 Kbytes of high density single voltage Flash program memory • Up to 2 Kbytes true (not emulated) data EEPROM • Read while write: writing in the data memory is possible while executing code in the Flash program memory. The whole Flash program memory and data EEPROM are factory programmed with 0x00. 5.4.1 Architecture • The memory is organized in blocks of 128 bytes each • Read granularity: 1 word = 4 bytes • Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel • Writing, erasing, word and block management is handled automatically by the memory interface. DocID14395 Rev 15 15/125 114 Product overview 5.4.2 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Write protection (WP) Write protection in application mode is intended to avoid unintentional overwriting of the memory. The write protection can be removed temporarily by executing a specific sequence in the user software. 5.4.3 Protection of user boot code (UBC) If the user chooses to update the Flash program memory using a specific boot code to perform in application programming (IAP), this boot code needs to be protected against unwanted modification. In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user option level. Other than the standard write protection, the UBC protection can exclusively be modified via the debug interface, the user software cannot modify the UBC protection status. The UBC memory area contains the reset and interrupt vectors and its size can be adjusted in increments of 512 bytes by programming the UBC and NUBC option bytes (see Section 9: Option bytes on page 54). Figure 2. Flash memory organization of STM8A products 'DWDPHPRU\DUHD 'DWD ((3520 PHPRU\ 2SWLRQE\WHV 8%&DUHD 5HPDLQVZULWHSURWHFWHGGXULQJ,$3 3URJUDPPDEOH DUHDIURP.E\WH ILUVWWZRSDJHVXSWR SURJUDPPHPRU\HQG PD[LPXP.E\WH )ODVKSURJUDP PHPRU\  )ODVKSURJUDPPHPRU\DUHD :ULWHDFFHVVSRVVLEOHIRU,$3 069 5.4.4 Read-out protection (ROP) The STM8A provides a read-out protection of the code and data memory which can be activated by an option byte setting (see the ROP option byte in section 10). The read-out protection prevents reading and writing Flash program memory, data memory and option bytes via the debug module and SWIM interface. This protection is active in all device operation modes. Any attempt to remove the protection by overwriting the ROP option byte triggers a global erase of the program and data memory. 16/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Product overview The ROP circuit may provide a temporary access for debugging or failure analysis. The temporary read access is protected by a user defined, 8-byte keyword stored in the option byte area. This keyword must be entered via the SWIM interface to temporarily unlock the device. If desired, the temporary unlock mechanism can be permanently disabled by the user through OPT6/NOPT6 option bytes. 5.5 Clock controller The clock controller distributes the system clock coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. 5.5.1 Features • 5.5.2 Clock sources – 16 MHz high-speed internal RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI) – 1-24 MHz high-speed external crystal (HSE) – Up to 24 MHz high-speed user-external clock (HSE user-ext) • Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock (16 MHz/8). The clock source and speed can be changed by the application program as soon as the code execution starts. • Safe clock switching: Clock sources can be changed safely on the fly in Run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. • Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • Wakeup: In case the device wakes up from low-power modes, the internal RC oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device switches to the clock source that was selected before Halt mode was entered. • Clock security system (CSS): The CSS permits monitoring of external clock sources and automatic switching to the internal RC (16 MHz/8) in case of a clock failure. • Configurable main clock output (CCO): This feature permits to output a clock signal for use by the application. 16 MHz high-speed internal RC oscillator (HSI) • Default clock after reset 2 MHz (16 MHz/8) • Fast wakeup time User trimming The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign permits frequency tuning by the application program. The adjustment range covers all possible frequency variations versus supply voltage and temperature. This trimming does not change the initial production setting. DocID14395 Rev 15 17/125 114 Product overview 5.5.3 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 128 kHz low-speed internal RC oscillator (LSI) The frequency of this clock is 128 kHz and it is independent from the main clock. It drives the independent watchdog or the AWU wakeup timer. In systems which do not need independent clock sources for the watchdog counters, the 128 kHz signal can be used as the system clock. This configuration has to be enabled by setting an option byte (OPT3/OPT3N, bit LSI_EN). 5.5.4 24 MHz high-speed external crystal oscillator (HSE) The external high-speed crystal oscillator can be selected to deliver the main clock in normal Run mode. It operates with quartz crystals and ceramic resonators. 5.5.5 • Frequency range: 1 MHz to 24 MHz • Crystal oscillation mode: preferred fundamental • I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT External clock input An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The frequency range is 0 to 24 MHz. 5.5.6 Clock security system (CSS) The clock security system protects against a system stall in case of an external crystal clock failure. In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is automatically selected with a frequency of 2 MHz (16 MHz/8). Table 4. Peripheral clock gating bits (CLK_PCKENR1) 18/125 Control bit Peripheral PCKEN17 TIM1 PCKEN16 TIM3 PCKEN15 TIM2 PCKEN14 TIM4 PCKEN13 LINUART PCKEN12 USART PCKEN11 SPI PCKEN10 I 2C DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Product overview Table 5. Peripheral clock gating bits (CLK_PCKENR2) 5.6 Control bit Peripheral PCKEN27 CAN PCKEN26 Reserved PCKEN25 Reserved PCKEN24 Reserved PCKEN23 ADC PCKEN22 AWU PCKEN21 Reserved PCKEN20 Reserved Low-power operating modes For efficient power management, the application can be put in one of four different lowpower modes. Users can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. • Wait mode In this mode, the CPU is stopped but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. • Active-halt mode with regulator on In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in Activehalt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. • Active-halt mode with regulator off This mode is the same as Active-halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. • Halt mode CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. In all modes the CPU and peripherals remain permanently powered on, the system clock is applied only to selected modules. The RAM content is preserved and the brown-out reset circuit remains activated. DocID14395 Rev 15 19/125 114 Product overview 5.7 Timers 5.7.1 Watchdog timers STM8AF526x/8x/Ax STM8AF6269/8x/Ax The watchdog system is based on two independent timers providing maximum security to the applications. The watchdog timer activity is controlled by the application program or option bytes. Once the watchdog is activated, it cannot be disabled by the user program without going through reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application timing perfectly. The application software must refresh the counter before time-out and during a limited time window. If the counter is refreshed outside this time window, a reset is issued. Independent watchdog timer The independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. If the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. 5.7.2 Auto-wakeup counter This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked by the internal 128 kHz internal low-frequency RC oscillator or external clock. LSI clock can be internally connected to TIM3 input capture channel 1 for calibration. 5.7.3 Beeper This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be output on a pin. This is useful when audible sounds without interference need to be generated for use in the application. 5.7.4 Advanced control and general purpose timers STM8A devices described in this datasheet, contain up to three 16-bit advanced control and general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can be used either as input compare, output compare or PWM channel. These timers are named TIM1, TIM2 and TIM3. 20/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Product overview Table 6. Advanced control and general purpose timers Timer Counter width TIM1 16-bit Counter type Prescaler Channels factor Up/down 1 to 65536 TIM2 16-bit Up TIM3 16-bit Up 2n n = 0 to 15 2n n = 0 to 15 Inverted Repetition outputs counter trigger unit External trigger Break input 4 3 Yes Yes Yes Yes 3 None No No No No 2 None No No No No TIM1 - advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and bridge driver. • 16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler. • Four independent CAPCOM channels configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output • Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In the present implementation it is possible to trigger the ADC upon a timer event. • External trigger to change the timer behavior depending on external signals • Break input to force the timer outputs into a defined state • Three complementary outputs with adjustable dead time • Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break TIM2, TIM3 - 16-bit general purpose timers 5.7.5 • 16-bit auto-reload up-counter • 15-bit prescaler adjustable to fixed power of two ratios 1…32768 • Timers with three or two individually configurable CAPCOM channels • Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update Basic timer The typical usage of this timer (TIM4) is the generation of a clock tick. Table 7. TIM4 Timer Counter width Counter type TIM4 8-bit Up Prescaler Channels factor 2n n = 0 to 7 Inverted Repetition outputs counter 0 None No trigger unit External trigger Break input No No No • 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128 • Clock source: master clock • Interrupt source: 1 x overflow/update DocID14395 Rev 15 21/125 114 Product overview 5.8 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Analog to digital converter (ADC) The STM8A products described in this datasheet contain a 10-bit successive approximation ADC with up to 16 multiplexed input channels, depending on the package. The ADC name differs between the datasheet and the STM8A/S reference manual (see Table 8). Table 8. ADC naming Peripheral name in datasheet Peripheral name in reference manual (RM0016) ADC ADC2 ADC features 5.9 • 10-bit resolution • Single and continuous conversion modes • Programmable prescaler: fMASTER divided by 2 to 18 • Conversion trigger on timer events, and external events • Interrupt generation at end of conversion • Selectable alignment of 10-bit data in 2 x 8 bit result registers • Shadow registers for data consistency • ADC input range: VSSA ≤VIN ≤VDDA • Schmitt-trigger on analog inputs can be disabled to reduce power consumption Communication interfaces The following sections give a brief overview of the communication peripheral. Some peripheral names differ between the datasheet and STM8S series and STM8AF series 8-bit microcontrollers reference manual (see Table 9). Table 9. Communication peripheral naming correspondence 5.9.1 Peripheral name in datasheet Peripheral name in reference manual (RM0016) USART UART1 LINUART UART3 Universal synchronous/asynchronous receiver transmitter (USART) The devices covered by this datasheet contain one USART interface. The USART can operate in standard SCI mode (serial communication interface, asynchronous) or in SPI emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master support. 22/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Product overview Detailed feature list: • Full duplex, asynchronous communications • NRZ standard format (mark/space) • High-precision baud rate generator system – Common programmable transmit and receive baud rates up to fMASTER/16 • Programmable data word length (8 or 9 bits) • Configurable stop bits: Support for 1 or 2 stop bits • LIN master mode: – LIN break and delimiter generation – LIN break and delimiter detection with separate flag and interrupt source for readback checking. • Transmitter clock output for synchronous communication • Separate enable bits for transmitter and receiver • Transfer detection flags: • • • • – Receive buffer full – Transmit buffer empty – End of transmission flags Parity control: – Transmits parity bit – Checks parity of received data byte Four error detection flags: – Overrun error – Noise error – Frame error – Parity error Six interrupt sources with flags: – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Parity error – LIN break and delimiter detection Two interrupt vectors: – Transmitter interrupt – Receiver interrupt • Reduced power consumption mode • Wakeup from mute mode (by idle line detection or address mark detection) • Two receiver wakeup modes: – Address bit (MSB) – Idle line DocID14395 Rev 15 23/125 114 Product overview 5.9.2 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Universal asynchronous receiver/transmitter with LIN support (LINUART) The devices covered by this datasheet contain one LINUART interface. The interface is available on all the supported packages. The LINUART is an asynchronous serial communication interface which supports extensive LIN functions tailored for LIN slave applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.2. Detailed feature list: LIN mode Master mode • LIN break and delimiter generation • LIN break and delimiter detection with separate flag and interrupt source for read back checking. Slave mode • Autonomous header handling – one single interrupt per valid header • Mute mode to filter responses • Identifier parity error checking • LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI) clock source • Break detection at any time, even during a byte reception • Header errors detection: – Delimiter too short – Synch field error – Deviation error (if automatic resynchronization is enabled) – Framing error in synch field or identifier field – Header time-out UART mode • Full duplex, asynchronous communications - NRZ standard format (mark/space) • High-precision baud rate generator – 24/125 A common programmable transmit and receive baud rates up to fMASTER/16 • Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control • Separate enable bits for transmitter and receiver • Error detection flags • Reduced power consumption mode • Multi-processor communication - enter mute mode if address match does not occur • Wakeup from mute mode (by idle line detection or address mark detection) • Two receiver wakeup modes: – Address bit (MSB) – Idle line DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 5.9.3 Product overview Serial peripheral interface (SPI) The devices covered by this datasheet contain one SPI. The SPI is available on all the supported packages. 5.9.4 • Maximum speed: 10 Mbit/s or fMASTER/2 for master, 8 Mbit/s or fMASTER /2 for slave • Full duplex synchronous transfers • Simplex synchronous transfers on two lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • CRC calculation • 1 byte Tx and Rx buffer • Slave mode/master mode management by hardware or software for both master and slave • Programmable clock polarity and phase • Programmable data order with MSB-first or LSB-first shifting • Dedicated transmission and reception flags with interrupt capability • SPI bus busy status flag • Hardware CRC feature for reliable communication: – CRC value can be transmitted as last byte in Tx mode – CRC error checking for last received byte Inter integrated circuit (I2C) interface The devices covered by this datasheet contain one I2C interface. The interface is available on all the supported packages. • • I2C master features: – Clock generation – Start and stop generation 2 I C slave features: – Programmable I2C address detection – Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds: • • – Standard speed (up to 100 kHz), – Fast speed (up to 400 kHz) Status flags: – Transmitter/receiver mode flag – End-of-byte transmission flag – I2C busy flag Error flags: – Arbitration lost condition for master mode – Acknowledgement failure after address/data transmission – Detection of misplaced start or stop condition – Overrun/underrun if clock stretching is disabled DocID14395 Rev 15 25/125 114 Product overview • • 5.9.5 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Interrupt: – Successful address/data communication – Error condition – Wakeup from Halt Wakeup from Halt on address detection in slave mode Controller area network interface (beCAN) The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the CAN protocol version 2.0A and B. It is equipped with a receive FIFO and a very versatile filter bank. Together with a filter match index, this allows a very efficient message handling in today’s car network architectures. The CPU is significantly unloaded. The maximum transmission speed is 1 Mbit/s. Transmission • Three transmit mailboxes • Configurable transmit priority by identifier or order request Reception • 11- and 29-bit ID • 1 receive FIFO (3 messages deep) • Software-efficient mailbox mapping at a unique address space • FMI (filter match index) stored with message for quick message association • Configurable FIFO overrun • Time stamp on SOF reception • 6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID. • Filtering modes (mixable): – Mask mode permitting ID range filtering – ID list mode Interrupt management 26/125 • Maskable interrupt • Software-efficient mailbox mapping at a unique address space DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 5.10 Product overview Input/output specifications The product features four I/O types: • Standard I/O 2 MHz • Fast I/O up to 10 MHz • High sink 8 mA, 2 MHz • True open drain (I2C interface) To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum slew rate. The rise and fall times are similar to those of standard I/Os. The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitttrigger input stage on the analog I/Os can be disabled in order to reduce the device standby consumption. STM8A I/Os are designed to withstand current injection. For a negative injection current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to this feature, external protection diodes against current injection are no longer required. Caution: In STM8AF5286UC device, the following I/O ports are not automatically configured by hardware: PA3, PA4, PA5, PA6, PF4, PB6, PB7, PE0, PE1, PE2, PE3, PE6, PE7. As a consequence, they must be put into one of the following configurations by software: - configured as input with internal pull-up/down resistor, - configured as output push-pull low. DocID14395 Rev 15 27/125 114 Pinouts and pin description STM8AF526x/8x/Ax STM8AF6269/8x/Ax 6 Pinouts and pin description 6.1 Package pinouts 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/BEEP PD3 (HS)/TIM2_CH2 PD2 (HS)/TIM3_CH1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 PI7 PI6 PE0/CLK_CCO PE1/I2C_SCL PE2/I 2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 PI5 PI4 Figure 3. LQFP 80-pin pinout 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 AIN3/PB3 AIN2/PB2 AIN1/PB1 AIN0/PB0 TIM1_ETR/PH4 TIM1_CH3N/PH5 TIM1_CH2N/PH6 TIM1_CH1N/PH7 AIN8/PE7 AIN9/PE6 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 TIM2_CH3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 (HS) PH0 (HS) PH1 PH2 PH3 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 1. The CAN interface is only available on STM8AF52xx product lines. 2. (HS) stands for high sink capability. 28/125 DocID14395 Rev 15 PI3 PI2 PI1 PI0 PG4 PG3 PG2 PG1/CAN_RX(1) PG0/CAN_TX(1) PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PC0/ADC_ETR PE5/SPI_NSS STM8AF526x/8x/Ax STM8AF6269/8x/Ax Pinouts and pin description PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/ BEEP PD3 (HS)/TIM2_CH2/ADC_ETR PD2 (HS)/TIM3_CH1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 Figure 4. LQFP 64-pin pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PI0 PG4 PG3 PG2 PG1/CAN_RX(1) PG0/CAN_TX(1) PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_CH3N/AIN2/PB2 TIM1_CH2N/AIN1/PB1 TIM1_CH1N/AIN0/PB0 AIN8/PE7 AIN9/PE6 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 TIM2_CH3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 1. The CAN interface is only available on STM8AF52xx product lines. 2. HS stands for high sink capability. DocID14395 Rev 15 29/125 114 Pinouts and pin description STM8AF526x/8x/Ax STM8AF6269/8x/Ax PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/BEEP PD3 (HS)/TIM2_CH2/ADC_ETR PD2 (HS)/TIM3_CH1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PE3/TIM1_BKIN Figure 5. LQFP 48-pin pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 2223 24 VDDA VSSA AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_CH3N/AIN2/PB2 TIM1_CH2N/AIN1/PB1 TIM1_CH1N/AIN0/PB0 AIN8/PE7 AIN9/PE6 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 TIM2_CH3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 1. The CAN interface is only available on STM8AF52xx product lines. 2. HS stands for high sink capability. 30/125 DocID14395 Rev 15 PG1/CAN_RX PG0/CAN_TX PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS STM8AF526x/8x/Ax STM8AF6269/8x/Ax Pinouts and pin description PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/BEEP PD3 (HS)/TIM2_CH2/ADC_ETR PD2 (HS)/TIM3_CH1/TIM2_CH3 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2/CLK_CCO/TIM1_BRK Figure 6. STM8AF62xx LQFP/VFQFPN 32-pin pinout 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 1516 PC7/SPI_MISO PC6/SPI_MOSI PC5/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS VDDA VSSA I2C_SDA/AIN5/PB5 I2C_SCL/AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_CH3N/AIN2/PB2 TIM1_CH2N/AIN1/PB1 TIM1_CH1N/AIN0/PB0 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 1. HS stands for high sink capability. DocID14395 Rev 15 31/125 114 Pinouts and pin description STM8AF526x/8x/Ax STM8AF6269/8x/Ax 3'+67,0B&+%((3 3'+67,0B&+$'&B(75 3'+67,0B&+7,0B&+ 3'+66:,0        3'+67,0B&+&/.B&&27,0B%5. '/,18$57B7;  1%-*/6"35@39 1567 3'7/, Figure 7. STM8AF52x6 VFQFPN32 32-pin pinout   3*&$1B5; 26&,13$   3*&$1B7; 26&2873$   3&   3&+67,0B&+ 966  3&+67,0B&+ 3$   3(        7,0B&+1$,13%  7,0B&+1$,13%  7,0B&+1$,13% 3&+67,0B&+ 7,0B(75$,13%  ,&B6&/$,13%  9'',2 ,&B6'$$,13% 3&+67,0B&+ 9 66$  9''$  9'' 9&$3 069 1. The following I/O ports are not automatically configured by hardware: PA3, PA4, PA5, PA6, PF4, PB6, PB7, PE0, PE1, PE2, PE3, PE6, PE7. As a consequence, they must be put into one of the following configurations by software: - configured as input with internal pull-up/down resistor, - configured as output push-pull low. 2. HS stands for high sink capability. 32/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Pinouts and pin description Table 10. Legend/abbreviation for the pin description table Type Level Output speed Port and control configuration Reset state I= input, O = output, S = power supply Input CM = CMOS (standard for all I/Os) Output HS = high sink (8 mA) O1 = Standard (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Input float = floating, wpu = weak pull-up Output T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state). DocID14395 Rev 15 33/125 114 Pinouts and pin description STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description 2 2 2 2 2 3 3 3 3 4 4 4 5 5 5 6 6 6 7 7 8 9 PP NRST OD 1 Speed 1 Ext. interrupt High sink STM8AF52x6 VFQFPN32 1 Alternate function after remap [option bit] Wpu STM8AF62xx LQFP32/VFQFPN32 1 Main function (after reset) Floating LQFP48 1 Output Type LQFP64 Input LQFP80 Pin number I/O - X - - - - - PA1/OSCIN(1) I/O X X - - O1 X X Port A1 Resonator/ crystal in - 3 PA2/OSCOUT I/O X X X - O1 X X Port A2 Resonator/ crystal out - - - VSSIO_1 S - - - - - - - I/O ground - 4 4 VSS S - - - - - - - Digital ground - 5 5 VCAP S - - - - - - - 1.8 V regulator capacitor - 7 6 6 VDD S - - - - - - - Digital power supply - 8 8 7 7 VDDIO_1 S - - - - - - - I/O power supply - 9 9 - - PA3/TIM2_CH3 I/O X X X - O1 X X Port A3 Timer 2 channel 3 TIM3_CH1 [AFR1] 10 10 10 - - PA4/USART_RX I/O X X X - O3 X X Port A4 USART receive - 11 11 11 - - PA5/USART_TX I/O X X X - O3 X X Port A5 USART transmit - 12 12 12 - 8 (2) I/O X X X - O3 X X Port A6 USART synchro nous clock - 13 - - PH0 I/O X X - HS O3 X X Port H0 - - - - Pin name PA6/USART_CK Default alternate function Reset - 14 - - - - PH1 I/O X X - HS O3 X X Port H1 - - 15 - - - - PH2 I/O X X - - O1 X X Port H2 - - 16 - - - - PH3 I/O X X - - O1 X X Port H3 - - 17 13 - - - PF7/AIN15 I/O X X - - O1 X X Port F7 Analog input 15 - 18 14 - - - PF6/AIN14 I/O X X - - O1 X X Port F6 Analog input 14 - 19 15 - - - PF5/AIN13 I/O X X - - O1 X X Port F5 Analog input 13 - 20 16 - 8 - PF4/AIN12 I/O X X - - O1 X X Port F4 Analog input 12 - 21 17 - - - PF3/AIN11 I/O X X - - O1 X X Port F3 Analog input 11 - 34/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Pinouts and pin description Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued) Floating Wpu Speed OD PP - VREF+ S - - - - - - - ADC positive reference voltage - 23 19 13 9 9 VDDA S - - - - - - - Analog power supply - 24 20 14 10 10 VSSA S - - - - - - - Analog ground - S - - - - - - - ADC negative reference voltage - 22 18 Pin name Ext. interrupt High sink Type - LQFP64 - LQFP80 STM8AF52x6 VFQFPN32 Output STM8AF62xx LQFP32/VFQFPN32 Input LQFP48 Pin number Main function (after reset) Default alternate function Alternate function after remap [option bit] 25 21 - - - VREF- 26 22 - - - PF0/AIN10 I/O X X - - O1 X X Port F0 Analog input 10 - 27 23 15 - - PB7/AIN7 I/O X X X - O1 X X Port B7 Analog input 7 - 28 24 16 - - PB6/AIN6 I/O X X X - O1 X X Port B6 Analog input 6 - 29 25 17 11 11 PB5/AIN5 I/O X X X - O1 X X Port B5 Analog input 5 I2C_SDA [AFR6] 30 26 18 12 12 PB4/AIN4 I/O X X X - O1 X X Port B4 Analog input 4 I2C_SCL [AFR6] 31 27 19 13 13 PB3/AIN3 I/O X X X - O1 X X Port B3 Analog input 3 TIM1_ETR [AFR5] 32 28 20 14 14 PB2/AIN2 I/O X X X - O1 X X Port B2 Analog input TIM1_CH3N [AFR5] 33 29 21 15 15 PB1/AIN1 I/O X X X - O1 X X Port B1 Analog input 1 TIM1_CH2N [AFR5] 34 30 22 16 16 PB0/AIN0 I/O X X X - O1 X X Port B0 Analog input 0 TIM1_CH1N [AFR5] X - - O1 X X Port H4 Timer 1 trigger input - 35 - - - - PH4/TIM1_ETR I/O X 36 - - - - PH5/ TIM1_CH3N I/O X X - - O1 X X Port H5 Timer 1 inverted channel 3 - 37 - - - - PH6/ TIM1_CH2N I/O X X - - O1 X X Port H6 Timer 1 inverted channel 2 - DocID14395 Rev 15 35/125 114 Pinouts and pin description STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued) 39 31 23 Main function (after reset) PH7/ TIM1_CH1N I/O X X - - O1 X X Port H7 Timer 1 inverted channel 2 - - - PE7/AIN8 I/O X X - - O1 X X Port E7 Analog input 8 - PE6/AIN9 I/O X X X - O1 X X Port E6 Analog input 9 - - 40 32 24 41 33 25 42 - Pin name Default alternate function Alternate function after remap [option bit] (2) I/O X X X - O1 X X Port E5 SPI master/ slave select PC0/ADC_ETR I/O X X X - O1 X X Port C0 ADC trigger input - 17 PE5/SPI_NSS - - 43 34 26 18 18 PC1/TIM1_CH1 I/O X X X HS O3 X X Port C1 Timer 1 channel 1 - 44 35 27 19 19 PC2/TIM1_CH2 I/O X X X HS O3 X X Port C2 Timer 1channel 2 - 45 36 28 20 20 PC3/TIM1_CH3 I/O X X X HS O3 X X Port C3 Timer 1 channel 3 - 46 37 29 21 21 PC4/TIM1_CH4 I/O X X X HS O3 X X Port C4 Timer 1 channel 4 - 47 38 30 22 22 PC5/SPI_SCK(2) I/O X X X - O3 X X Port C5 SPI clock - 48 39 31 - - VSSIO_2 S - - - - - - - I/O ground - 49 40 32 - - VDDIO_2 S - - - - - - - I/O power supply - 50 41 33 23 - I/O X X X - O3 X X Port C6 SPI master out/ slave in - 51 42 34 24 - (2) I/O X X X - O3 X X Port C7 SPI master in/ slave out - 52 43 35 - 23 PG0/CAN_TX I/O X X - - O1 X X Port G0 CAN transmit - 53 44 36 - 24 PG1/CAN_RX I/O X X - - O1 X X Port G1 CAN receive - 54 45 - - PG2 I/O X X - - O1 X X Port G2 - - 36/125 - 17 Type PP - OD - Speed STM8AF52x6 VFQFPN32 - Ext. interrupt High sink STM8AF62xx LQFP32/VFQFPN32 - Wpu LQFP48 38 Output Floating LQFP64 Input LQFP80 Pin number - PC6/SPI_MOSI (2) PC7/SPI_MISO DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Pinouts and pin description Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued) Floating Wpu Ext. interrupt High sink Speed OD PP - - - PG3 I/O X X - - O1 X X Port G3 - - 56 47 - - - PG4 I/O X X - - O1 X X Port G4 - - 57 48 - - - PI0 I/O X X - - O1 X X Port I0 - - 58 - - - - PI1 I/O X X - - O1 X X Port I1 - - 59 - - - - PI2 I/O X X - - O1 X X Port I2 - - 60 - - - - PI3 I/O X X - - O1 X X Port I3 - - 61 - - - - PI4 I/O X X - - O1 X X Port I4 - - 62 - Pin name Type 55 46 LQFP64 Main function (after reset) LQFP80 STM8AF52x6 VFQFPN32 Output STM8AF62xx LQFP32/VFQFPN32 Input LQFP48 Pin number Default alternate function Alternate function after remap [option bit] - - - PI5 I/O X X - - O1 X X Port I5 - - 63 49 - - - PG5 I/O X X - - O1 X X Port G5 - - 64 50 - - - PG6 I/O X X - - O1 X X Port G6 - - 65 51 - - - PG7 I/O X X - - O1 X X Port G7 - - 66 52 - - - PE4 I/O X X X - O1 X X Port E4 - - 67 53 37 - - 68 54 38 - - PE2/I2C_SDA 2C_SCL 69 55 39 - - 70 56 40 - - X X - O1 X Port E3 Timer 1 break input I/O X - X - O1 T(3) - Port E2 I2C data - I/O X - X - O1 T(3) - Port E1 I2C clock - I/O X X X - O3 X X Port E0 Configurab le clock output - PE3/TIM1_BKIN I/O X PE1/I PE0/CLK_CCO X 71 - - - - PI6 I/O X X - - O1 X X Port I6 - - 72 - - - - PI7 I/O X X - - O1 X X Port I7 - TIM1_BKIN [AFR3]/ CLK_CCO [AFR2] X X HS O3 X X Port D0 Timer 3 channel 2 I/O X X X HS O4 X X Port D1 SWIM data interface - 27 PD2/TIM3_CH1 I/O X X X HS O3 X X Port D2 Timer 3 channel 1 TIM2_CH3 [AFR1] 28 28 PD3/TIM2_CH2 I/O X X X HS O3 X X Port D3 Timer 2 channel 2 ADC_ETR [AFR0] 29 29 PD4/TIM2_CH1/ I/O X BEEP X X HS O3 X X Port D4 Timer 2 channel 1 BEEP output [AFR7] 73 57 41 25 25 74 58 42 26 26 75 59 43 27 76 60 44 77 61 45 PD0/TIM3_CH2 I/O X PD1/SWIM(4) DocID14395 Rev 15 37/125 114 Pinouts and pin description STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued) OD PP X X - O1 X X Port D5 LINUART data transmit - 79 63 47 31 31 PD6/ LINUART_RX I/O X X X - O1 X X Port D6 LINUART data receive - 80 64 48 32 32 PD7/TLI(5) I/O X X X - O1 X X Port D7 Top level interrupt - Ext. interrupt High sink I/O X Wpu PD5/ LINUART_TX Floating 30 Pin name Type 30 LQFP48 78 62 46 LQFP64 Main function (after reset) LQFP80 Speed Output STM8AF52x6 VFQFPN32 Input STM8AF62xx LQFP32/VFQFPN32 Pin number Default alternate function Alternate function after remap [option bit] 1. In Halt/Active-halt mode, this pin behaves as follows: - The input/output path is disabled. - If the HSE clock is used for wakeup, the internal weak pull-up is disabled. - If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in Halt/Active-halt mode. 2. SPI and USTART are not available in STM8AF5286UC, refer to Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout for the pin names. 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to VDD are not implemented) 4. The PD1 pin is in input pull-up during the reset phase and after reset release. 5. If this pin is configured as interrupt pin, it will trigger the TLI. 38/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 6.2 Pinouts and pin description Alternate function remapping As shown in the rightmost column of Table 11, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 9: Option bytes on page 54. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of STM8S series and STM8AF series 8-bit microcontrollers reference manual, RM0016). DocID14395 Rev 15 39/125 114 Memory and register map STM8AF526x/8x/Ax STM8AF6269/8x/Ax 7 Memory and register map 7.1 Memory map Figure 8. Register and memory map [ .E\WH5$0 [ [)) VWDFN 5HVHUYHG [ [ XSWR.E\WHGDWD((3520 2SWLRQE\WHV [ 5HVHUYHG [ +DUGZDUHUHJLVWHUV [ 5HVHUYHG [ .E\WHRI%RRW520 [ 5HVHUYHG [) &386:,0GHEXJ,7& UHJLVWHUV [ ,QWHUUXSWYHFWRUV [ 8SWR.E\WHRI)ODVK SURJUDPPHPRU\ )ODVKSURJUDPPHPRU\HQGDGGUHVV 069 40/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Memory and register map Table 12. Memory model 128K 7.2 Flash program memory size Flash program memory end address 128 K 0x00 27FFF 64 K 0x00 17FFF 32 K 0x00 0FFFF RAM size RAM end address Stack roll-over address 6K 0x00 17FF 0x00 1400 Register map In this section the memory and register map of the devices covered by this datasheet is described. For a detailed description of the functionality of the registers, refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual, RM0016. Table 13. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX(1) PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX(1) PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0xXX(1) PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX(1) PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 Block Port A Port B Port C Port D DocID14395 Rev 15 41/125 114 Memory and register map STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 13. I/O port hardware register map (continued) Register label Register name Reset status 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xXX(1) PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xXX(1) PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX(1) PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 PH_ODR Port H data output latch register 0x00 0x00 5024 PH_IDR Port H input pin value register 0xXX(1) PH_DDR Port H data direction register 0x00 0x00 5026 PH_CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 PI_ODR Port I data output latch register 0x00 0x00 5029 PI_IDR Port I input pin value register 0xXX(1) PI_DDR Port I data direction register 0x00 0x00 502B PI_CR1 Port I control register 1 0x00 0x00 502C PI_CR2 Port I control register 2 0x00 Address 0x00 5016 0x00 501B 0x00 5020 0x00 5025 0x00 502A Block Port E Port F Port G Port H Port I 1. Depends on the external circuitry. 42/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Memory and register map Table 14. General hardware register map Register label Register name Reset status 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF FLASH_FPR Flash protection register 0x00 0x00 505E FLASH_NFPR Flash complementary protection register 0xFF 0x00 505F FLASH_IAPSR Flash in-application programming status register 0x40 Address 0x00 505D Block Flash 0x00 5060 to 0x005061 0x00 5062 Reserved area (2 bytes) Flash FLASH_PUKR 0x00 5063 0x00 5064 0x00 50A1 Flash FLASH_DUKR ITC 0x00 50C1 0x00 50C2 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reserved area (17 bytes) RST RST_SR 0x00 50B4 to 0x00 50BF 0x00 50C0 Data EEPROM unprotection register Reserved area (59 bytes) 0x00 50A2 to 0x00 50B2 0x00 50B3 0x00 Reserved area (1 byte) 0x00 5065 to 0x00 509F 0x00 50A0 Flash Program memory unprotection register Reset status register 0xXX(1) Reserved area (12 bytes) CLK CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 Reserved area (1 byte) DocID14395 Rev 15 43/125 114 Memory and register map STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 14. General hardware register map (continued) Register label Register name Reset status 0x00 50C3 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF Address 0x00 50C8 Block CLK 0x00 50CB Reserved area (1 byte) 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 0x00 50CE to 0x00 50D0 0x00 50D1 0x00 50D2 Reserved area (3 bytes) WWDG WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F 0x00 50D3 to 0x00 50DF Reserved area (13 bytes) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0xXX(2) IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 50FF 44/125 BEEP AWU_CSR1 AWU control/status register 1 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F Reserved area (12 bytes) DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Memory and register map Table 14. General hardware register map (continued) Register label Register name Reset status 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 SPI_SR SPI status register 0x02 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF Address 0x00 5203 0x00 5204 Block SPI 0x00 5208 to 0x00 520F Reserved area (8 bytes) 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 I2C_DR I2C data register 0x00 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C clock control register low 0x00 0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 5215 0x00 5216 0x00 5217 0x00 521E to 0x00 522F I2C Reserved area (18 bytes) DocID14395 Rev 15 45/125 114 Memory and register map STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 14. General hardware register map (continued) Register label Register name Reset status 0x00 5230 UART1_SR USART status register 0xC0 0x00 5231 UART1_DR USART data register 0xXX 0x00 5232 UART1_BRR1 USART baud rate register 1 0x00 0x00 5233 UART1_BRR2 USART baud rate register 2 0x00 0x00 5234 UART1_CR1 USART control register 1 0x00 UART1_CR2 USART control register 2 0x00 0x00 5236 UART1_CR3 USART control register 3 0x00 0x00 5237 UART1_CR4 USART control register 4 0x00 0x00 5238 UART1_CR5 USART control register 5 0x00 0x00 5239 UART1_GTR USART guard time register 0x00 0x00 523A UART1_PSCR USART prescaler register 0x00 Address 0x00 5235 Block USART 0x00 523B to 0x00 523F Reserved area (5 bytes) 0x00 5240 UART3_SR LINUART status register 0xC0 0x00 5241 UART3_DR LINUART data register 0xXX 0x00 5242 UART3_BRR1 LINUART baud rate register 1 0x00 0x00 5243 UART3_BRR2 LINUART baud rate register 2 0x00 UART3_CR1 LINUART control register 1 0x00 UART3_CR2 LINUART control register 2 0x00 0x00 5246 UART3_CR3 LINUART control register 3 0x00 0x00 5247 UART3_CR4 LINUART control register 4 0x00 0x00 5244 0x00 5245 LINUART 0x00 5248 0x00 5249 0x00 524A to 0x00 524F 46/125 Reserved UART3_CR6 LINUART control register 6 Reserved area (6 bytes) DocID14395 Rev 15 0x00 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Memory and register map Table 14. General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 Address 0x00 525F 0x00 5260 0x00 5270 to 0x00 52FF Block TIM1 Reserved area (147 bytes) DocID14395 Rev 15 47/125 114 Memory and register map STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 14. General hardware register map (continued) Register label Register name Reset status 0x00 5300 TIM2_CR1 TIM2 control register 1 0x00 0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00 0x00 5308 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 5309 TIM2_CCER2 TIM2 capture/compare enable register 2 0x00 TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00 00 530C0x TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00 0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00 0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00 Address 0x00 530A 0x00 5315 to 0x00 531F 48/125 Block TIM2 Reserved area (11 bytes) DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Memory and register map Table 14. General hardware register map (continued) Register label Register name Reset status 0x00 5320 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 0x00 5327 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 Address 0x00 5328 Block TIM3 0x00 5331 to 0x00 533F Reserved area (15 bytes) 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF 0x00 5343 0x00 5347 to 0x00 53FF TIM4 Reserved area (185 bytes) DocID14395 Rev 15 49/125 114 Memory and register map STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 14. General hardware register map (continued) Register label Register name Reset status 0x00 5400 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 ADC_CR3 ADC configuration register 3 0x00 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 Address 0x00 5403 0x00 5404 Block ADC 0x00 5408 to 0x00 541F 0x00 5420 CAN_MCR CAN master control register 0x02 0x00 5421 CAN_MSR CAN master status register 0x02 0x00 5422 CAN_TSR CAN transmit status register 0x00 0x00 5423 CAN_TPR CAN transmit priority register 0x0C 0x00 5424 CAN_RFR CAN receive FIFO register 0x00 0x00 5425 CAN_IER CAN interrupt enable register 0x00 0x00 5426 CAN_DGR CAN diagnosis register 0x0C 0x00 5427 CAN_FPSR CAN page selection register 0x00 0x00 5428 CAN_P0 CAN paged register 0 0xXX(3) 0x00 5429 CAN_P1 CAN paged register 1 0xXX(3) 0x00 542A CAN_P2 CAN paged register 2 0xXX(3) CAN_P3 CAN paged register 3 0xXX(3) 0x00 542C CAN_P4 CAN paged register 4 0xXX(3) 0x00 542D CAN_P5 CAN paged register 5 0xXX(3) 0x00 542E CAN_P6 CAN paged register 6 0xXX(3) 0x00 542F CAN_P7 CAN paged register 7 0xXX(3) 0x00 5430 CAN_P8 CAN paged register 8 0xXX(3) 0x00 5431 CAN_P9 CAN paged register 9 0xXX(3) 0x00 5432 CAN_PA CAN paged register A 0xXX(3) 0x00 5433 CAN_PB CAN paged register B 0xXX(3) 0x00 5434 CAN_PC CAN paged register C 0xXX(3) 0x00 5435 CAN_PD CAN paged register D 0xXX(3) 0x00 5436 CAN_PE CAN paged register E 0xXX(3) 0x00 542B 50/125 Reserved area (24 bytes) beCAN DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Memory and register map Table 14. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 5437 beCAN CAN_PF CAN paged register F 0xXX(3) 0x00 5438 to 0x00 57FF Reserved area (968 bytes) 1. Depends on the previous reset source. 2. Write only register. 3. If the bootloader is enabled, it is initialized to 0x00. Table 15. CPU/SWIM/debug module/interrupt controller registers Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x80 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17(2) 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CC Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 CPU(1) 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 bytes) CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF ITC_SPR4 Interrupt software priority register 4 0xFF ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F73 0x00 7F74 CPU ITC 0x00 7F78 to 0x00 7F79 0x00 7F80 Reserved area (2 bytes) SWIM SWIM_CSR SWIM control status register DocID14395 Rev 15 0x00 51/125 114 Memory and register map STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 15. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register label 0x00 7F81 to 0x00 7F8F Register name Reset status Reserved area (15 bytes) 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF 0x00 7F95 DM 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) 1. Accessible by debug module only 2. Product dependent value, see Figure 8: Register and memory map. Table 16. Temporary memory unprotection registers Register label Register name Reset status 0x00 5800 TMU_K1 Temporary memory unprotection key register 1 0x00 0x00 5801 TMU_K2 Temporary memory unprotection key register 2 0x00 0x00 5802 TMU_K3 Temporary memory unprotection key register 3 0x00 0x00 5803 TMU_K4 Temporary memory unprotection key register 4 0x00 TMU_K5 Temporary memory unprotection key register 5 0x00 0x00 5805 TMU_K6 Temporary memory unprotection key register 6 0x00 0x00 5806 TMU_K7 Temporary memory unprotection key register 7 0x00 0x00 5807 TMU_K8 Temporary memory unprotection key register 8 0x00 0x00 5808 TMU_CSR Temporary memory unprotection control and status register 0x00 Address 0x00 5804 52/125 Block TMU DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 8 Interrupt table Interrupt table Table 17. STM8A interrupt table(1) Priority Source block Description Interrupt vector address Wakeup from Halt Comments - Reset Reset 0x00 8000 Yes - - TRAP SW interrupt 0x00 8004 - - 0 TLI External top level interrupt 0x00 8008 - - 1 AWU Auto-wakeup from Halt 0x00 800C Yes - 2 Clock controller Main clock controller 0x00 8010 - - 3 MISC External interrupt E0 0x00 8014 Yes Port A interrupts 4 MISC External interrupt E1 0x00 8018 Yes Port B interrupts 5 MISC External interrupt E2 0x00 801C Yes Port C interrupts 6 MISC External interrupt E3 0x00 8020 Yes Port D interrupts 7 MISC External interrupt E4 0x00 8024 Yes Port E interrupts 8 CAN CAN interrupt Rx 0x00 8028 Yes - 9 CAN CAN interrupt TX/ER/SC 0x00 802C - - 10 SPI End of transfer 0x00 8030 Yes - 11 Timer 1 Update/overflow/ trigger/break 0x00 8034 - - 12 Timer 1 Capture/compare 0x00 8038 - - 13 Timer 2 Update/overflow 0x00 803C - - 14 Timer 2 Capture/compare 0x00 8040 - - 15 Timer 3 Update/overflow 0x00 8044 - - 16 Timer 3 Capture/compare 0x00 8048 - - 17 USART Tx complete 0x00 804C - - 18 USART Receive data full reg. 0x00 8050 - - I C interrupts 0x00 8054 Yes - 2 2 19 I C 20 LINUART Tx complete/error 0x00 8058 - - 21 LINUART Receive data full reg. 0x00 805C - - 22 ADC End of conversion 0x00 8060 - - 23 Timer 4 Update/overflow 0x00 8064 - - 24 EEPROM End of programming/ write in not allowed area 0x00 8068 - - 1. All unused interrupts must be initialized with ‘IRET’ for robust programming. DocID14395 Rev 15 53/125 114 Option bytes 9 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 18: Option bytes below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP and UBC options that can only be changed in ICP mode (via SWIM). Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 18. Option bytes Addr. 0x00 4800 0x00 4801 0x00 4802 0x00 4803 0x00 4804 0x00 4805 0x00 4806 0x00 4807 0x00 4808 0x00 4809 0x00 480A 54/125 Option name Option byte no. Read-out protection (ROP) OPT0 ROP[7:0] 0x00 OPT1 UBC[7:0] 0x00 NOPT1 NUBC[7:0] 0xFF User boot code (UBC) Option bits 7 6 5 4 3 2 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 function remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 (AFR) Watchdog option Clock option HSE clock startup 1 0 Factory default setting AFR1 AFR0 0x00 NAFR1 NAFR0 0xFF OPT3 Reserved LSI_ EN IWDG _HW WWD G _HW WWDG _HALT 0x00 NOPT3 Reserved NLSI_ EN NIWD G_HW NWWD G_HW NWWG _HALT 0xFF OPT4 Reserved EXT CLK CKAW USEL PRSC1 PRSC0 0x00 NOPT4 Reserved NEXT CLK NCKAW NPRSC NPRSC1 USEL 0 0xFF OPT5 HSECNT[7:0] 0x00 NOPT5 NHSECNT[7:0] 0xFF DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Option bytes Table 18. Option bytes (continued) Addr. 0x00 480B 0x00 480C 0x00 480D 0x00 480E Option name Option byte no. Option bits 7 6 5 4 3 2 1 0 Factory default setting OPT6 TMU[3:0] 0x00 NOPT6 NTMU[3:0] 0xFF TMU Flash wait states OPT7 Reserved WAIT STATE 0x00 NOPT7 Reserved NWAIT STATE 0xFF 0x00 480F Reserved 0x00 4810 OPT8 TMU_KEY 1 [7:0] 0x00 0x00 4811 OPT9 TMU_KEY 2 [7:0] 0x00 0x00 4812 OPT10 TMU_KEY 3 [7:0] 0x00 0x00 4813 OPT11 TMU_KEY 4 [7:0] 0x00 OPT12 TMU_KEY 5 [7:0] 0x00 0x00 4815 OPT13 TMU_KEY 6 [7:0] 0x00 0x00 4816 OPT14 TMU_KEY 7 [7:0] 0x00 0x00 4817 OPT15 TMU_KEY 8 [7:0] 0x00 0x00 4818 OPT16 TMU_MAXATT [7:0] 0xC7 0x00 4814 TMU 0x00 4819 to 487D 0x00 487E 0x00 487F Reserved Bootloader(1) OPT17 BL [7:0] 0x00 NOPT 17 NBL [7:0] 0xFF 1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no effect on EMC reset. DocID14395 Rev 15 55/125 114 Option bytes STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 19. Option byte description 56/125 Option byte no. Description OPT0 ROP[7:0]: Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0]: User boot code area 0x00: No UBC, no write-protection 0x01: Page 0 to 1 defined as UBC, memory write-protected 0x02: Page 0 to 3 defined as UBC, memory write-protected 0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM write protection for more details. OPT2 AFR7: Alternate function remapping option 7 0: Port D4 alternate function = TIM2_CH1 1: Port D4 alternate function = BEEP AFR6: Alternate function remapping option 6 0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL. AFR5: Alternate function remapping option 5 0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0. 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N. AFR4: Alternate function remapping option 4 0: Port D7 alternate function = TLI 1: Reserved AFR3: Alternate function remapping option 3 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = TIM1_BKIN AFR2: Alternate function remapping option 2 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = CLK_CCO Note: AFR2 option has priority over AFR3 if both are activated AFR1: Alternate function remapping option 1 0: Port A3 alternate function = TIM2_CH3, port D2 alternate function TIM3_CH1. 1: Port A3 alternate function = TIM3_CH1, port D2 alternate function TIM2_CH3. AFR0: Alternate function remapping option 0 0: Port D3 alternate function = TIM2_CH2 1: Port D3 alternate function = ADC_ETR DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Option bytes Table 19. Option byte description (continued) Option byte no. Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source OPT3 IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on Halt 0: No reset generated on Halt if WWDG active 1: Reset generated on Halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN OPT4 CKAWUSEL: Auto-wakeup unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for AWU PRSC[1:0]: AWU clock prescaler 00: 24 MHz to 128 kHz prescaler 01: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilization time to 0.5, 8, 128, and 2048 HSE cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and 0x00. OPT6 TMU[3:0]: Enable temporary memory unprotection 0101: TMU disabled (permanent ROP). Any other value: TMU enabled. OPT7 WAIT STATE: Wait state configuration This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory. 0: No wait state 1: One wait state OPT8 TMU_KEY 1 [7:0]: Temporary unprotection key 0 Temporary unprotection key: Must be different from 0x00 or 0xFF OPT9 TMU_KEY 2 [7:0]: Temporary unprotection key 1 Temporary unprotection key: Must be different from 0x00 or 0xFF OPT10 TMU_KEY 3 [7:0]: Temporary unprotection key 2 Temporary unprotection key: Must be different from 0x00 or 0xFF OPT11 TMU_KEY 4 [7:0]: Temporary unprotection key 3 Temporary unprotection key: Must be different from 0x00 or 0xFF DocID14395 Rev 15 57/125 114 Option bytes STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 19. Option byte description (continued) Option byte no. 58/125 Description OPT12 TMU_KEY 5 [7:0]: Temporary unprotection key 4 Temporary unprotection key: Must be different from 0x00 or 0xFF OPT13 TMU_KEY 6 [7:0]: Temporary unprotection key 5 Temporary unprotection key: Must be different from 0x00 or 0xFF OPT14 TMU_KEY 7 [7:0]: Temporary unprotection key 6 Temporary unprotection key: Must be different from 0x00 or 0xFF OPT15 TMU_KEY 8 [7:0]: Temporary unprotection key 7 Temporary unprotection key: Must be different from 0x00 or 0xFF OPT16 TMU_MAXATT [7:0]: TMU access failure counter TMU_MAXATT can be initialized with the desired value only if TMU is disabled (TMU[3:0]=0101 in OPT6 option byte). When TMU is enabled, any attempt to temporary remove the readout protection by using wrong key values increments the counter. When the option byte value reaches 0x08, the Flash memory and data EEPROM are erased. OPT17 BL[7:0]: Bootloader enable If this option byte is set to 0x55 (complementary value 0xAA) the bootloader program is activated also in case of a programmed code memory (for more details, see the bootloader user manual, UM0560). DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = -40 °C, TA = 25 °C, and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5.0 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range. 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. Figure 9. Pin loading conditions 670$3,1 S) 06Y9 DocID14395 Rev 15 59/125 114 Electrical characteristics 10.1.5 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 10. Pin input voltage 670$3,1 9,1 06Y9 10.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device’s reliability. The device’s mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 20. Voltage characteristics Symbol Min Max -0.3 6.5 VSS - 0.3 6.5 VSS - 0.3 VDD + 0.3 |VDDx - VDD| Variations between different power pins - 50 |VSSx - VSS| Variations between all the different ground pins - 50 VDDx - VSS VIN VESD Ratings Supply voltage (including VDDA and VDDIO)(1) Input voltage on true open drain pins (PE1, PE2)(2) (2) Input voltage on any other pin Electrostatic discharge voltage Unit V mV see Absolute maximum ratings (electrical sensitivity) on page 88 1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected 60/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Table 21. Current characteristics Symbol Ratings Max. IVDDIO Total current into VDDIO power lines (source)(1)(2)(3) 100 IVSSIO (1)(2)(3) 100 IIO IINJ(PIN)(4) IINJ(TOT) Total current out of VSS IO ground lines (sink) Output current sunk by any I/O and control pin 20 Output current source by any I/Os and control pin -20 Injected current on any pin ±10 Sum of injected currents 50 Unit mA 1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. 2. The total limit applies to the sum of operation and injected currents. 3. VDDIO includes the sum of the positive injection currents. VSSIO includes the sum of the negative injection currents. 4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current allowed and the corresponding VIN maximum must always be respected. Table 22. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Value -65 to 150 Maximum junction temperature 160 Unit °C Table 23. Operating lifetime(1) Symbol OLF Ratings Conforming to AEC-Q100 rev G Value Unit −40 to 125 °C Grade 1 −40 to 150 °C Grade 0 1. For detailed mission profile analysis, please contact the nearest ST Sales Office. DocID14395 Rev 15 61/125 114 Electrical characteristics 10.3 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Operating conditions Table 24. General operating conditions Symbol Parameter fCPU Min Max 1 wait state TA = -40 °C to 150 °C 16 24 0 wait state TA = -40 °C to 150 °C 0 16 Standard operating voltage - 3.0 5.5 V CEXT: capacitance of external capacitor - 470 3300 nF - 0.3 Ω - 15 nH Internal CPU clock frequency VDD/VDDIO VCAP(1) Conditions ESR of external capacitor at 1 MHz(2) ESL of external capacitor MHz Suffix A TA TJ Ambient temperature 85 - 40 Suffix C Junction temperature range Unit 125 Suffix D 150 Suffix A 90 Suffix C - 40 Suffix D °C 130 155 1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. 2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator. Figure 11. fCPUmax versus VDD I&38>0+]@  )XQFWLRQDOLW\JXDUDQWHHG #7$WRƒ&DWZDLWVWDWH )XQFWLRQDOLW\ QRWJXDUDQWHHG  LQWKLVDUHD  )XQFWLRQDOLW\JXDUDQWHHG #7$WRƒ&DWZDLWVWDWH        6XSSO\YROWDJH>9@ 06Y9 62/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Table 25. Operating conditions at power-up/power-down tTEMP Conditions Min Typ Max - 2(1) - - (1) - 8 tVDD Parameter 8 Symbol VDD rise time rate VDD fall time rate 2 Unit µs/V Reset release delay VDD rising - 1 1.7 ms Reset generation delay VDD falling - 3 - µs VIT+ Power-on reset threshold(2) (3) - 2.65 2.8 2.95 VIT- Brown-out reset threshold - 2.58 2.73 2.88 VHYS(BOR) Brown-out reset hysteresis - - 70(1) - V mV 1. Guaranteed by design, not tested in production. 2. If VDD is below 3 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is kept. The EEPROM programming sequence must not be initiated. 3. There is inrush current into VDD present after device power on to charge CEXT capacitor. This inrush energy depends from CEXT capacitor value. For example, a CEXT of 1 μF requires Q=1 μF x 1.8 V = 1.8 μC. 10.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 24. Care should be taken to limit the series inductance to less than 15 nH. Figure 12. External capacitor CEXT & (6/ (65 5/HDN 06Y9 1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in Figure 9 on page 59 and Figure 10 on page 60. If not explicitly stated, general conditions of temperature and voltage apply. DocID14395 Rev 15 63/125 114 Electrical characteristics STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 26. Total current consumption in Run, Wait and Slow mode. General conditions for VDD apply, TA = −40 °C to 150 °C Symbol IDD(RUN) IDD(RUN) IDD(WFI) (1) (1) (1) IDD(SLOW)(1) Parameter Supply current in Run mode Supply current in Run mode Supply current in Wait mode Supply current in Slow mode Conditions All peripherals clocked, code executed from Flash program memory, HSE external clock (without resonator) All peripherals clocked, code executed from RAM, HSE external clock (without resonator) CPU stopped, all peripherals off, HSE external clock fCPU scaled down, all peripherals off, code executed from RAM Max 8.7 16.8 fCPU = 16 MHz 7.4 14 fCPU = 8 MHz 4.0 7.4(2) fCPU = 4 MHz 2.4 4.1(2) fCPU = 2 MHz 1.5 2.5 fCPU = 24 MHz 4.4 6.0(2) fCPU = 16 MHz 3.7 5.0 fCPU = 8 MHz 2.2 3.0(2) fCPU = 4 MHz 1.4 2.0(2) fCPU = 2 MHz 1.0 1.5 fCPU = 24 MHz 2.4 3.1(2) fCPU = 16 MHz 1.65 2.5 fCPU = 8 MHz 1.15 1.9(2) fCPU = 4 MHz 0.90 1.6(2) fCPU = 2 MHz 0.80 1.5 External clock 16 MHz fCPU = 125 kHz 1.50 1.95 LSI internal RC fCPU = 128 kHz 1.50 1.80(2) 2. Guaranteed by design, not tested in production. DocID14395 Rev 15 Unit (2) fCPU = 24 MHz 1 ws 1. The current due to I/O utilization is not taken into account in these values. 64/125 Typ mA STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Table 27. Total current consumption in Halt and Active-halt modes. General conditions for VDD applied. TA = −40 °C to 55 °C unless otherwise stated Conditions Symbol IDD(H) IDD(AH) tWU(AH) Main voltage regulator (MVR)(1) Flash mode(2) Supply current in Halt mode Off Powerdown Supply current in Active-halt mode with regulator on On Powerdown Parameter Supply current in Active-halt mode with regulator off Off Wakeup time from Active-halt mode with regulator on On Wakeup time from Active-halt mode with regulator off Off Typ Max Clocks stopped 5 35(3) Clocks stopped, TA = 25 °C 5 25 External clock 16 MHz fMASTER = 125 kHz 770 900(3) LSI clock 128 kHz 150 230(3) LSI clock 128 kHz 25 42(3) LSI clock 128 kHz, TA = 25 °C 25 30 10 30(3) Clock source and temperature condition Powerdown Operating mode TA =−40 to 150 °C Unit µA µs 50 80(3) 1. Configured by the REGAH bit in the CLK_ICKR register. 2. Configured by the AHALT bit in the FLASH_CR1 register. 3. Guaranteed by characterization results, not tested in production. Current consumption for on-chip peripherals Table 28. Oscillator current consumption Symbol IDD(OSC) IDD(OSC) Parameter HSE oscillator current consumption(2) HSE oscillator current consumption(2) Typ Max(1) fOSC = 24 MHz 1 2.0(3) fOSC = 16 MHz 0.6 - fOSC = 8 MHz 0.57 - fOSC = 24 MHz 0.5 1.0(3) fOSC = 16 MHz 0.25 - fOSC = 8 MHz 0.18 - Conditions Quartz or ceramic resonator, CL = 33 pF VDD = 5 V Quartz or ceramic resonator, CL = 33 pF VDD = 3.3 V Unit mA 1. During startup, the oscillator current consumption may reach 6 mA. 2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small Rm value. Refer to crystal manufacturer for more details 3. Informative data. DocID14395 Rev 15 65/125 114 Electrical characteristics STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 29. Programming current consumption Symbol IDD(PROG) Parameter Programming current Conditions Typ Max Unit VDD = 5 V, -40 °C to 150 °C, erasing and programming data or Flash program memory 1.0 1.7 mA Table 30. Typical peripheral current consumption VDD = 5.0 V(1) Symbol IDD(TIM1) Parameter TIM1 supply current(2) Typ. Typ. 0.03 0.23 0.34 0.02 0.12 0.19 IDD(TIM3) TIM3 supply current(2) 0.01 0.1 0.16 IDD(TIM4) TIM4 supply current(2) 0.004 0.03 0.05 0.03 0.09 0.15 IDD(TIM2) IDD(USART) IDD(LINUART) TIM2 supply current (2) Typ. fmaster = 2 MHz fmaster = 16 MHz fmaster =24 MHz USART supply current(2) 0.03 0.11 0.18 IDD(SPI) SPI supply current(2) 0.01 0.04 0.07 IDD(I2C) I2C supply current(2) IDD(CAN) IDD(AWU) IDD(TOT_DIG) IDD(ADC) LINUART supply current(2) 0.02 0.06 0.91 CAN supply current(3) 0.06 0.30 0.40 AWU supply current(2) 0.003 0.02 0.05 All digital peripherals on 0.22 1 2.4 ADC supply current when converting(4) 0.93 0.95 0.96 Unit 1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital supply voltage, the values are similar in the full supply voltage range. 2. Data based on a differential IDD measurement between no peripheral clocked and a single active peripheral. This measurement does not include the pad toggling consumption. 3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data transmit sequence in loopback mode at 1 MHz. This measurement does not include the pad toggling consumption. 4. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. 66/125 DocID14395 Rev 15 mA STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Current consumption curves Figure 13 to Figure 18 show typical current consumption measured with code executing in RAM. Figure 13. Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, peripherals = on 10 9 25°C 8 85°C 7 125°C 25°C 9 IDD(RUN)HSE [mA] IDD(RUN)HSE [mA] 10 Figure 14. Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on 6 5 4 3 2 1 8 85°C 7 125°C 6 5 4 3 2 1 0 0 2.5 3 3.5 4 4.5 5 5.5 0 6 5 10 VDD [V] 30 3 2 25°C 85°C 125°C 1 0 4.5 5.5 6 5 4 3 2 25°C 85°C 125°C 1 0 2.5 6.5 3.5 4.5 5.5 6.5 VDD [V] VDD [V] Figure 17. Typ. IDD(WFI)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on Figure 18. Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off 6 2.5 5 IDD(WFI)HSI [mA] IDD(WFI)HSE [mA] 25 Figure 16. Typ. IDD(WFI)HSE vs. VDD @ fCPU = 16 MHz, peripherals = on IDD(WFI)HSE [mA] IDD(RUN)HSI [mA] 4 3.5 20 fcpu [MHz] Figure 15. Typ. IDD(RUN)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off 2.5 15 4 3 25°C 2 85°C 1 2 1.5 1 25°C 85°C 0.5 125°C 125°C 0 0 0 5 10 15 20 25 30 fcpu [MHz] 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] DocID14395 Rev 15 67/125 114 Electrical characteristics 10.3.3 STM8AF526x/8x/Ax STM8AF6269/8x/Ax External clock sources and timing characteristics HSE external clock An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the OSCIN pin. Clock characteristics are subject to general operating conditions for VDD and TA. Table 31. HSE external clock characteristics Symbol Parameter Conditions Min Typ Max Unit TA = -40 °C to 150 °C 0(1) - 24 MHz fHSE_ext User external clock source frequency VHSEdHL Comparator hysteresis - 0.1 x VDD - - VHSEH OSCIN high-level input pin voltage - 0.7 x VDD - VDD VHSEL OSCIN low-level input pin voltage - VSS - 0.3 x VDD VSS < VIN < VDD -1 - +1 ILEAK_HSE OSCIN input leakage current V µA 1. If CSS is used, the external clock must have a frequency above 500 kHz. Figure 19. HSE external clock source 9 +6(+ 9 +6(/ ([WHUQDOFORFN VRXUFH I+6( 26&,1 670 069 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). 68/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Table 32. HSE oscillator characteristics Symbol RF CL1/CL2 (1) gm tSU(HSE)(2) Parameter Conditions Min Typ Max Unit Feedback resistor - - 220 - kΩ Recommended load capacitance - - - 20 pF Oscillator trans conductance - 5 - - mA/V VDD is stabilized - 2.8 - ms Startup time 1. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load capacitance (CLoad) is (CL1 * CL2)/(CL1 + CL2). If CL1 = CL2, Cload = CL1/2. Some oscillators have built-in load capacitors, CL1 and CL2. 2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is reached. It can vary with the crystal type that is used. Figure 20. HSE oscillator circuit diagram 5P /P I+6(WRFRUH &2 &P 5) &/ 26&,1 JP 5HVRQDWRU &XUUHQWFRQWURO 5HVRQDWRU 26&287 &/ 670 06Y9 HSE oscillator critical gm formula The crystal characteristics have to be checked with the following formula: Equation 1 g m » g mcrit where gmcrit can be calculated with the crystal parameters as follows: Equation 2 f 2 g mcrit = ( 2 × Π × HSE ) × R m ( 2Co + C ) 2 Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1 = CL2 = C: Grounded external capacitance DocID14395 Rev 15 69/125 114 Electrical characteristics 10.3.4 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High-speed internal RC oscillator (HSI) Table 33. HSI oscillator characteristics Symbol fHSI ACCHS tsu(HSI) Parameter Conditions Min Typ Max Unit - - 16 - MHz HSI oscillator user trimming accuracy Trimmed by the application for any VDD and TA conditions -1 - 1 HSI oscillator accuracy (factory calibrated) VDD = 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 150 °C -5 - 5 - - - 2(1) Frequency HSI oscillator wakeup time % 1. Guaranteed by characterization results, not tested in production. Figure 21. Typical HSI frequency vs VDD 3% HSI frequency variation [%] -40°C 2% 25°C 85°C 1% 125°C 0% -1% -2% -3% 2.5 3 3.5 4 4.5 VDD [V] 70/125 DocID14395 Rev 15 5 5.5 6 µs STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Low-speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 34. LSI oscillator characteristics Symbol fLSI tsu(LSI) Parameter Conditions Min Typ Max Unit Frequency - 112 128 144 kHz LSI oscillator wakeup time - - - 7(1) µs 1. Guaranteed by characterization results, not tested in production. Figure 22. Typical LSI frequency vs VDD LSI frequency variation [%] 3% 2% 1% 25°C 0% -1% -2% -3% 2.5 3 3.5 4 VDD [V] DocID14395 Rev 15 4.5 5 5.5 6 71/125 114 Electrical characteristics 10.3.5 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Memory characteristics Flash program memory/data EEPROM memory General conditions: TA = -40 °C to 150 °C. Table 35. Flash program memory/data EEPROM memory Symbol VDD VDD tprog terase Parameter Conditions Min(1) Typ Max Operating voltage (all modes, execution/write/erase) fCPU is 16 to 24 MHz with 1 ws fCPU is 0 to 16 MHz with 0 ws 3.0 Operating voltage (code execution) fCPU is 16 to 24 MHz with 1 ws fCPU is 0 to 16 MHz with 0 ws 2.6 - 5.5 Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) - - 6 6.6 Fast programming time for 1 block (128 bytes) - - 3 3.3 Erase time for 1 block (128 bytes) - - 3 3.3 - Unit 5.5 V ms 1. Guaranteed by characterization results, not tested in production. Table 36. Flash program memory Symbol Parameter Condition Min Max Unit TWE Temperature for writing and erasing - -40 150 °C NWE Flash program memory endurance (erase/write cycles)(1) TA = 25 °C 1000 - cycles tRET Data retention time TA = 25 °C 40 - TA = 55 °C 20 - years 1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. 72/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Table 37. Data memory Symbol Parameter Condition Min Max Unit TWE Temperature for writing and erasing - -40 150 °C NWE Data memory endurance(1) (erase/write cycles) TA = 25 °C 300 k tRET Data retention time - (2) 100 k - TA = 25 °C 40(2)(3) - TA = 55 °C (2)(3) - TA = -40°C to 125 °C 20 cycles years 1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. 2. More information on the relationship between data retention time and number of write/erase cycles is available in a separate technical document. 3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C. DocID14395 Rev 15 73/125 114 Electrical characteristics 10.3.6 STM8AF526x/8x/Ax STM8AF6269/8x/Ax I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 38. I/O static characteristics Symbol Parameter VIL Low-level input voltage VIH High-level input voltage Vhys Hysteresis(1) VOH VOL Rpu tR, tF High-level output voltage Low-level output voltage Pull-up resistor Rise and fall time (10% - 90%) Ilkg Digital input pad leakage current Ilkg ana Analog input pad leakage current Ilkg(inj) Leakage current in adjacent I/O(3) IDDIO Total current on either VDDIO or VSSIO Conditions - Min Typ Max -0.3 V 0.3 x VDD 0.7 x VDD VDD + 0.3 V - 0.1 x VDD V Standard I/0, VDD = 5 V, I = 3 mA VDD - 0.5 V - - Standard I/0, VDD = 3 V, I = 1.5 mA VDD - 0.4 V - - High sink and true open drain I/0, VDD = 5 V I = 8 mA - - 0.5 Standard I/0, VDD = 5 V I = 3 mA - - 0.6 Standard I/0, VDD = 3 V I = 1.5 mA - - 0.4 VDD = 5 V, VIN = VSS 35 50 65 Fast I/Os Load = 50 pF - - 35(2) Standard and high sink I/Os Load = 50 pF - - 125(2) Fast I/Os Load = 20 pF - - 20(2) Standard and high sink I/Os Load = 20 pF - - 50(2) VSS ≤ VIN ≤ VDD - - ±1 VSS ≤ VIN ≤ VDD -40 °C < TA < 125 °C - - ±250 VSS ≤ VIN ≤ VDD -40 °C < TA < 150 °C - - ±500 Injection current ±4 mA - - ±1(3) µA Including injection currents - - 60 mA DocID14395 Rev 15 V kΩ ns µA nA 1. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in production. 74/125 Unit STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics 2. Guaranteed by design. 3. Guaranteed by characterization results, not tested in production. Figure 23. Typical VIL and VIH vs VDD @ four temperatures 6 -40°C 25°C 5 85°C VIL / V IH [V] 4 125°C 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 24. Typical pull-up resistance RPU vs VDD @ four temperatures 60 Pull-Up resistance [k ohm] 55 50 45 -40°C 40 25°C 85°C 35 125°C 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] DocID14395 Rev 15 75/125 114 Electrical characteristics STM8AF526x/8x/Ax STM8AF6269/8x/Ax Figure 25. Typical pull-up current Ipu vs VDD @ four temperatures(1) 140 Pull-Up current [µA] 120 100 80 -40°C 60 25°C 40 85°C 125°C 20 0 0 1 2 3 4 5 6 VDD [V] 1. The pull-up is a pure resistor (slope goes through 0). Typical output level curves Figure 26 to Figure 35 show typical output level curves measured with output on a single pin. Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports) Figure 27. Typ. VOL @ VDD = 5.0 V (standard ports) -40°C 1.5 -40°C 1.5 25°C 25°C 85°C 1.25 85°C 1.25 125°C 125°C 1 VOL [V] VOL [V] 1 0.75 0.75 0.5 0.5 0.25 0.25 0 0 0 1 2 3 4 5 6 7 0 2 4 6 IOL [mA] Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) 25°C 1.75 85°C 125°C 1.5 125°C 1.25 VOL [V] VOL [V] 85°C 1.5 1.25 1 0.75 1 0.75 0.5 0.5 0.25 0.25 0 0 0 2 4 6 8 10 12 14 IOL [mA] 76/125 12 -40°C 2 25°C 1.75 10 Figure 29. Typ. VOL @ VDD = 5.0 V (true open drain ports) -40°C 2 8 IOL [mA] 0 5 10 15 IOL [mA] DocID14395 Rev 15 20 25 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 31. Typ. VOL @ VDD = 5.0 V (high sink ports) -40°C 1.5 25°C 85°C 1.25 -40°C 1.5 25°C 85°C 1.25 125°C 125°C 1 VOL [V] VOL [V] 1 0.75 0.75 0.5 0.5 0.25 0.25 0 0 0 2 4 6 8 10 12 14 0 5 10 IOL [mA] Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) 125°C 85°C 125°C 1.5 1.25 VDD - V OH [V] VDD - V OH [V] 25°C 1.75 85°C 1.5 1 0.75 1.25 1 0.75 0.5 0.5 0.25 0.25 0 0 0 1 2 3 4 5 6 7 0 2 4 6 IOH [mA] 25°C 1.75 85°C 125°C 1.5 12 -40°C 2 25°C 1.75 10 Figure 35. Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) -40°C 2 8 IOH [mA] Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 85°C 125°C 1.5 1.25 VDD - V OH [V] VDD - V OH [V] 25 -40°C 2 25°C 1.75 20 Figure 33. Typ. VDD - VOH @ VDD = 5.0 V (standard ports) -40°C 2 15 IOL [mA] 1 0.75 1.25 1 0.75 0.5 0.5 0.25 0.25 0 0 0 2 4 6 8 10 12 14 IOH [mA] 0 5 10 15 20 25 IOH [mA] DocID14395 Rev 15 77/125 114 Electrical characteristics 10.3.7 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 39. NRST pin characteristics Symbol VIL(NRST) VIH(NRST) Parameter Conditions Min Typ Max NRST low-level input voltage(1) - VSS - 0.3 x VDD (1) - 0.7 x VDD - VDD (1) IOL = 3 mA - - 0.6 NRST high-level input voltage VOL(NRST) NRST low-level output voltage RPU(NRST) NRST pull-up resistor - 30 40 60 NRST input filtered pulse(1) - 85 - 315 NRST Input not filtered pulse duration(2) - 500 - - tIFP tINFP(NRST) 1. Guaranteed by characterization results, not tested in production. 2. Guaranteed by design, not tested in production. Figure 36. Typical NRST VIL and VIH vs VDD @ four temperatures -40°C 6 25°C 85°C 5 125°C VIL / V IH [V] 4 3 2 1 0 2.5 3 3.5 4 4.5 VDD [V] 78/125 DocID14395 Rev 15 5 5.5 6 Unit V kΩ ns STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Figure 37. Typical NRST pull-up resistance RPU vs VDD -40°C 60 NRST Pull-Up resistance [k ohm] 25°C 55 85°C 125°C 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 38. Typical NRST pull-up current Ipu vs VDD 140 NRST Pull-Up current [µA] 120 100 80 60 -40°C 25°C 40 85°C 20 125°C 0 0 1 2 3 VDD [V] 4 5 6 The reset network shown in Figure 39 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 39: NRST pin characteristics), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF. DocID14395 Rev 15 79/125 114 Electrical characteristics STM8AF526x/8x/Ax STM8AF6269/8x/Ax Figure 39. Recommended reset pin protection 670$ 9'' 538 ([WHUQDO UHVHW FLUFXLW 1567 )LOWHU ,QWHUQDOUHVHW ȝ) 2SWLRQDO 06Y9 10.3.8 TIM 1, 2, 3, and 4 electrical specifications Subject to general operating conditions for VDD, fMASTER and TA. Table 40. TIM 1, 2, 3, and 4 electrical specifications Symbol fEXT Parameter Conditions Min Typ Max Unit - - - 24 MHz Timer external clock frequency(1) 1. Not tested in production. 80/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics SPI interface 10.3.9 Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under ambient temperature, fMASTER frequency, and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. SPI characteristics Symbol Parameter Conditions Master mode fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(3) SPI clock frequency Slave mode VDD < 4.5 V VDD = 4.5 V to 5.5 V SPI clock rise and fall time Capacitive load: C = 30 pF Min Max 0 10 0 6(1) 0 8(1) - 25(2) NSS setup time Slave mode 4 * tMASTER - NSS hold time Slave mode 70 - tSCK/2 + 15 tw(SCKH)(3) tw(SCKL)(3) Master mode 5 - Slave mode 5 - Master mode 7 - Slave mode 10 - ta(SO)(3)(4) Data output access time Slave mode - 3* tMASTER tdis(SO)(3)(5) Data output disable time Slave mode 25 tv(SO)(3) Data output valid time VDD < 4.5 V Slave mode (after enable edge) V = 4.5 V to 5.5 V DD - 75 - 53 tv(MO)(3) Data output valid time Master mode (after enable edge) - 30 Slave mode (after enable edge) 31 - Master mode (after enable edge) 12 - th(NSS) (3) tw(SCKH)(3) SCK high and low time tw(SCKL)(3) tsu(MI)(3) tsu(SI)(3) Data input setup time th(MI)(3) th(SI)(3) Data input hold time th(SO)(3) th(MO)(3) Data output hold time Master mode tSCK/2 - 15 Unit MHz ns 1. fSCK < fMASTER/2. 2. The pad has to be configured accordingly (fast mode). 3. Guaranteed by design or by characterization results, not tested in production. 4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. DocID14395 Rev 15 81/125 114 Electrical characteristics STM8AF526x/8x/Ax STM8AF6269/8x/Ax Figure 40. SPI timing diagram in slave mode and with CPHA = 0 166LQSXW 6&.,QSXW W68166 &3+$  &32/  WK166 WF6&. WZ6&.+ WZ6&./ &3+$  &32/  W962 WD62 0,62 287387 WU6&. WI6&. WK62 06%287 %,7287 06%,1 %,7,1 WGLV62 /6%287 WVX6, 026, ,1387 /6%,1 WK6, DLF 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 41. SPI timing diagram in slave mode and with CPHA = 1 166LQSXW 6&.LQSXW W68166 &3+$  &32/  &3+$  &32/  WZ6&.+ WZ6&./ WK62 WY62 WD62 0,62 287387 06%287 %,7287 WU6&. WI6&. WGLV62 /6%287 WK6, WVX6, 026, ,1387 WK166 WF6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. 82/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Figure 42. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$  &32/  6&.2XWSXW WF6&. &3+$  &32/  &3+$  &32/  &3+$  &32/  WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 % , 7287 06%287 WY02 /6%287 WK02 DLF 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. DocID14395 Rev 15 83/125 114 Electrical characteristics 10.3.10 STM8AF526x/8x/Ax STM8AF6269/8x/Ax I2C interface characteristics Table 42. I2C characteristics Standard mode I2C Symbol Parameter Fast mode I2C(1) Min(2) Max(2) Min(2) Max(2) Unit tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0(3) - 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time (VDD 3 V to 5.5 V) - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time (VDD 3 V to 5.5 V) - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - µs STOP to START condition time (bus free) 4.7 - 1.3 - µs - 400 - 400 pF tw(STO:STA) Cb Capacitive load for each bus line 1. fMASTER, must be at least 8 MHz to achieve max fast I 2C µs ns µs speed (400 kHz) 2. Data based on standard I2C protocol requirement, not tested in production 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 84/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 10.3.11 Electrical characteristics 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER and TA unless otherwise specified. Table 43. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit kHz/MHz fADC ADC clock frequency - 111 kHz - 4 MHz VDDA Analog supply - 3 - 5.5 VREF+ Positive reference voltage - 2.75 - VDDA VREF- Negative reference voltage - VSSA - 0.5 - VSSA - VDDA Devices with external VREF+/ VREF- pins VREF- - VREF+ - - - 3 fADC = 2 MHz - 1.5 - fADC = 4 MHz - 0.75 - fADC = 2 MHz - 7 - fADC = 4 MHz - 3.5 - fADC = 2 MHz - 7 - fADC = 4 MHz - 3.5 - - - - 30 Conversion voltage range(1) VAIN Csamp Internal sample and hold capacitor tS(1) Sampling time (3 x 1/fADC) tSTAB Wakeup time from standby tCONV Total conversion time including sampling time (14 x 1/fADC) Rswitch Equivalent switch resistance V pF µs kΩ 1. During the sample time, the sampling capacitance, Csamp (3 pF typ), can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Figure 43. Typical application with ADC s 9$,1 5$,1 /Edž ^dDϴ 97 9 5VZLWFK 7V &$,1 97 9 ,/ ELW$' FRQYHUVLRQ &VDPS 06Y9 1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor. DocID14395 Rev 15 85/125 114 Electrical characteristics STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 44. ADC accuracy for VDDA = 5 V Symbol Parameter Conditions Typ Max(1) |ET| Total unadjusted error(2) 1.4 3(3) |EO| Offset error(2) 0.8 3 0.1 2 0.9 1 0.7 1.5 (2) |EG| Gain error |ED| Differential linearity error(2) |EL| fADC = 2 MHz Integral linearity error (2) (2) (4) 1.9 4(4) 1.3(4) 4(4) 0.6(4) 3(4) |ET| Total unadjusted error |EO| Offset error(2) |EG| Gain error(2) |ED| Differential linearity error(2) 1.5(4) 2(4) |EL| Integral linearity error(2) 1.2(4) 1.5(4) fADC = 4 MHz Unit LSB 1. Guaranteed by characterization results, not tested in production. 2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy. 3. TUE 2LSB can be reached on specific sales types on the whole temperature range. 4. Target values. Figure 44. ADC accuracy characteristics 1023 1022 1021 EG V –V DDA SSA 1LSB = ----------------------------------------IDEAL 1024 (2) ET 7 (3) (1) 6 5 4 EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 1021102210231024 VDDA 1. Example of an actual transfer curve 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves. EO = Offset error: Deviation between the first actual transition and the first ideal one. EG = Gain error: Deviation between the last ideal transition and the last actual one. ED = Differential linearity error: Maximum deviation between actual steps and the ideal one. EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation line. 86/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 10.3.12 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). • ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 45. EMS data Symbol Parameter Conditions Level/class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA= 25 °C, fMASTER = 16 MHz (HSI clock), Conforms to IEC 1000-4-2 3/B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD= 3.3 V, TA= 25 °C, fMASTER = 16 MHz (HSI clock), Conforms to IEC 1000-4-4 4/A DocID14395 Rev 15 87/125 114 Electrical characteristics STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electromagnetic interference (EMI) Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading. Table 46. EMI data Conditions Symbol SEMI Parameter Peak level EMI level General conditions VDD = 5 V, TA = 25 °C, LQFP80 package conforming to IEC 61967-2 Monitored frequency band Max fCPU(1) Unit 8 MHz 16 MHz 24 MHz 0.1 MHz to 30 MHz 15 17 22 30 MHz to 130 MHz 18 22 16 130 MHz to 1 GHz -1 3 5 - 2 2.5 2.5 dBµV 1. Guaranteed by characterization results, not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 47. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge voltage (human body model) TA = 25 °C, conforming to JESD22-A114 3A 4000 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = 25 °C, conforming to JESD22-C101 3 500 VESD(MM) Electrostatic discharge voltage (charge device model) TA = 25 °C, conforming to JESD22-A115 B 200 1. Guaranteed by characterization results, not tested in production 88/125 DocID14395 Rev 15 Unit V STM8AF526x/8x/Ax STM8AF6269/8x/Ax Electrical characteristics Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance. • A supply overvoltage (applied to each power supply pin) and • A current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 48. Electrical sensitivities Symbol Parameter Conditions Class(1) TA = 25 °C LU TA = 85 °C Static latch-up class TA = 125 °C A TA = 150 °C 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). DocID14395 Rev 15 89/125 114 Package information 11 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 11.1 LQFP80 package information Figure 45. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'%0,!.% # ! CCC , $ K , $ $     0).  )$%.4)&)#!4)/. % % % B    E 3?-% 1. Drawing is not to scale. 90/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Package information Table 49. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data(1) millimeters inches Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.220 0.320 0.380 0.0087 0.0126 0.0150 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.350 - - 0.4862 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.350 - - 0.4862 - e - 0.650 - - 0.0256 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID14395 Rev 15 91/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package recommended footprint                4@'1 1. Dimensions are expressed in millimeters. 92/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 47. LQFP80 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ  999999 9999 'DWHFRGH 6WDQGDUG67ORJR : 88 5HYLVLRQFRGH 3LQLGHQWLILHU 069 1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. DocID14395 Rev 15 93/125 114 Package information 11.2 STM8AF526x/8x/Ax STM8AF6269/8x/Ax LQFP64 package information Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*(3/$1( F $ $ $ 6($7,1*3/$1( & $ FFF & ' ' ' . / /      3,1 ,'(17,),&$7,21 ( ( ( E    H :B0(B9 1. Drawing is not to scale. Table 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 94/125 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Package information Table 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint                 AIC 1. Dimensions are expressed in millimeters. DocID14395 Rev 15 95/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 50. LQFP64 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ  999999 9999 'DWHFRGH : 88 6WDQGDUG67ORJR 5HYLVLRQFRGH 3LQLGHQWLILHU 069 1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 96/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax LQFP48 package information Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 3%!4).' 0,!.% # C ! ! ! MM '!5'%0,!.% CCC # $ + ! $ , , $      0). )$%.4)&)#!4)/. % % B % 11.3 Package information    E "?-%?6 1. Drawing is not to scale. DocID14395 Rev 15 97/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 98/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Package information Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint                    AID 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. DocID14395 Rev 15 99/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Figure 53. LQFP48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ  999999 9999 'DWHFRGH 6WDQGDUG67ORJR : 88 5HYLVLRQFRGH 3LQLGHQWLILHU 069 1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 100/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax LQFP32 package information Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC '!5'%0,!.% # + $ ! , $ , $       0). )$%.4)&)#!4)/.  % % % B 11.4 Package information  E 7@.&@7 1. Drawing is not to scale. DocID14395 Rev 15 101/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. 102/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Package information Figure 55. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint                    6?&0?6 1. Dimensions are expressed in millimeters. DocID14395 Rev 15 103/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 56. LQFP32 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ  999999 9999 'DWHFRGH 6WDQGDUG67ORJR : 88 5HYLVLRQFRGH 3LQLGHQWLILHU 069 1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 104/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 11.5 Package information VFQFPN32 package information Figure 57. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline 6HDWLQJSODQH & GGG & $ $ $ ' H     ( ( E   3LQ,' 5  /  ' %RWWRPYLHZ / ?-%?!-+/2?6 1. Drawing is not to scale. DocID14395 Rev 15 105/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 53. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 - 0.200 - - 0.0079 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D2 3.500 3.600 3.700 0.1378 0.1417 0.1457 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E2 3.500 3.600 3.700 0.1378 0.1417 0.1457 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 106/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Package information Figure 58. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint    9DU$ 9DU%   9DU$ 9DU%     ?&0?!-+/2?6 1. Dimensions are expressed in millimeters. DocID14395 Rev 15 107/125 114 Package information STM8AF526x/8x/Ax STM8AF6269/8x/Ax Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 59. VFQFPN32 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ  999999 'DWHFRGH : 88 6WDQGDUG67ORJR 5HYLVLRQFRGH 3LQLGHQWLILHU 069 1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 108/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 11.6 Package information Thermal characteristics In case the maximum chip junction temperature (TJmax) specified in Table 24: General operating conditions is exceeded, the functionality of the device cannot be guaranteed. TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x ΘJA) where: TAmax is the maximum ambient temperature in ° C ΘJA is the package junction-to-ambient thermal resistance in ° C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins where: PI/Omax = Σ (VOL * IOL) + Σ((VDD - VOH) * IOH) taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low- and high-level in the application. Table 54. Thermal characteristics(1) Symbol ΘJA Parameter Value Thermal resistance junction-ambient LQFP 80 - 14 x 14 mm 38 Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm 46 Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm 57 Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm 59 Thermal resistance junction-ambient VFQFPN 32 - 5 x 5 mm 25 Unit °C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 11.6.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. DocID14395 Rev 15 109/125 114 Package information 11.6.2 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1 on page 111). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: – Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2) – IDDmax = 8 mA – VDD = 5 V – maximum 20 I/Os used at the same time in output at low-level with IOL = 8 mA – VOL = 0.4 V PINTmax = 8 mA x 5 V = 400 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 400 mW and PIOmax 64 mW PDmax = 400 mW + 64 mW Thus: PDmax = 464 mW. Using the values obtained in Table 54: Thermal characteristics TJmax is calculated as follows: For LQFP64 46 °C/W Tjmax = 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C This is within the range of the suffix C version parts (-40 °C < Tj < 125 ° C). Parts must be ordered at least with the temperature range suffix C. 110/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 12 Ordering information Ordering information Figure 60. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1 STM8A2 Example: F 62 A A T D XXX3 Y Product class 8-bit automotive microcontroller Program memory type F = Flash + EEPROM P = FASTROM Device family 52 = Silicon rev U and rev T, CAN/LIN 62 = Silicon rev U and rev T, LIN only Program memory size 6 = 32 Kbyte 8 = 64 Kbyte A= 128 Kbyte Pin count 6 = 32 pins 8 = 48 pins 9 = 64 pins A = 80 pins Package type T = LQFP U = VFQFPN Temperature range A = -40 to 85 °C C = -40 to 125 °C D = -40 to 150 °C Packing Y = Tray U = Tube X = Tape and reel compliant with EIA 481-C 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the nearest ST Sales Office. 2. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q002 or equivalent. 3. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed to be replaced later by the target silicon. DocID14395 Rev 15 111/125 114 STM8 development tools 13 STM8AF526x/8x/Ax STM8AF6269/8x/Ax STM8 development tools Development tools for the STM8A microcontrollers include the • STice emulation system offering tracing and code profiling • STVD high-level language debugger including assembler and visual development environment - seamless integration of third party C compilers • STVP Flash programming software In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 13.1 Emulation and in-circuit debugging tools The STM8 tool line includes the STice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8A application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers. 13.1.1 112/125 STice key features • Program and data trace recording up to 128 K records • Advanced breakpoints with up to 4 levels of conditions • Data breakpoints • Real-time read/write of all device resources during emulation • Occurrence and time profiling and code coverage analysis (new features) • In-circuit debugging/programming via SWIM protocol • 8-bit probe analyzer • 1 input and 2 output triggers • USB 2.0 high-speed interface to host PC • Power supply follower managing application voltages between 1.62 to 5.5 V • Modularity that allows users to specify the components they need to meet their development requirements and adapt to future requirements • Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 13.2 STM8 development tools Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. 13.2.1 STM8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes: ST visual develop Full-featured integrated development environment from STMicroelectronics, featuring: • Seamless integration of C and ASM toolsets • Full-featured debugger • Project management • Syntax highlighting editor • Integrated programming interface • Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer (STVP) Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A microcontroller’s Flash memory. STVP also offers project mode for saving programming configurations and automating programming sequences. 13.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of the application directly from an easy-to-use graphical interface. Available toolchains include: C compiler for STM8 All compilers are available in free version with a limited code size depending on the compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com, and www.iar.com. STM8 assembler linker Free assembly toolchain included in the STM8 toolset, which allows users to assemble and link their application source code. DocID14395 Rev 15 113/125 114 STM8 development tools 13.3 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Programming tools During the development cycle, STice provides in-circuit programming of the STM8A Flash microcontroller on the application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the STM8A. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. 114/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax 14 Revision history Revision history Table 55. Document revision history Date Revision 31-Jan-2008 1 Initial release 2 Added ‘H’ products to the datasheet (Flash no EEPROM). Section : Features on cover page: Updated Memories, Reset and supply management, Communication interfaces and I/Os; reduced wakeup pins by 1. Table 1: Device summary: Removed STM8AF6168, STM8AF6148, STM8AF6166, STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and STM8AF5166. Section 1: Introduction, Section 5: Product overview, Section 9: Option bytes, Section 6.2: Alternate function remapping, Table 21: Current characteristics: Updated reference documentation: RM0009, PM0047, and UM0470. Section 2: Description: added information about peak performance. Section 3: Product line-up: Removed STM8A common features table. Table 4: Peripheral clock gating bits (CLK_PCKENR1): Removed STM8AF5186T, STM8AF5176T, STM8AF5168T, and STM8AF5166T. Table 5: Peripheral clock gating bits (CLK_PCKENR2): Removed STM8AF6168T, STM8AF6166T, STM8AF6148T, and STM8AF6146T. Section 5: Product overview: Made minor content changes and improved readability and layout. Section 5.5.3: 128 kHz low-speed internal RC oscillator (LSI): Major modification, TMU included. Section 5.5.2: 16 MHz high-speed internal RC oscillator (HSI): User trimming updated. Section 5.5.3: 128 kHz low-speed internal RC oscillator (LSI): LSI as CPU clock added. Section 5.5.4: 24 MHz high-speed external crystal oscillator (HSE), Section 5.5.5: External clock input: Maximum frequency conditional 32 Kbyte/128 Kbyte. Section 5.8: Analog to digital converter (ADC): Scan for 128 Kbyte removed. Section 5.9: Communication interfaces, Section 5.9.3: Serial peripheral interface (SPI): SPI 10 Mb/s. Figure 3: LQFP 80-pin pinout, Figure 4: LQFP 64-pin pinout, Figure 6: STM8AF62xx LQFP/VFQFPN 32-pin pinout: Amended footnote 1. Table 12: Memory model 128K: HS output changed from 20 mA to 8 mA. Section 7: Memory and register map: Corrected Table 8: Register and memory map; removed address list; added Table 14: General hardware register map. Section 10.3.2: Supply current characteristics Note on typical/WC values added. 22-Aug-2008 Changes DocID14395 Rev 15 115/125 124 Revision history STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 55. Document revision history (continued) Date 22-Aug-2008 116/125 Revision Changes Table 18: Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off: Replaced the source blocks ‘simple USART’, ‘very low-end timer (timer 4)’, and ‘EEPROM’ with ‘LINUART’, ‘timer4’ and ‘reserved’ respectively, added TMU registers. Table 20: HSE oscillator circuit diagram: Updated OPT6 and NOPT6, added OPT7 to 17 (TMU, BL) Table 21: Typical HSI frequency vs VDD: Updated OPT1 UBC[7:0], OPT4 CKAWUSEL, OPT4 PRSC [1:0], and OPT6, added OPT7 to 16 (TMU). Table 23: Operating lifetime: Amended footnotes. Table 26: Total current consumption in Run, Wait and Slow mode. General conditions for VDD apply, TA = -40 °C to 150 °C: Added parameter ‘voltage and current operating conditions’. Table 27: Total current consumption in Halt and Active-halt modes. General conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise stated: Amended footnotes. Table 28: Oscillator current consumption: Replaced. Table 29: Programming current consumption: Amended maximum data and footnotes. Table 21: Current characteristics: Replaced. Table 22: Thermal characteristics: Added and amended IDD(RUN) data; amended IDD(WFI) data; amended footnotes. Table 32: HSE oscillator characteristics: Filled in, amended maximum data and footnotes. 2 (continued) Figure 13 to Figure 18: info on peripheral activity added. Table 33: HSI oscillator characteristics: Modified fHSE_ext data and added VHSEdhl data. Table 35: Flash program memory/data EEPROM memory: Removed ACCHSI parameters and replaced with ACCHS parameters; amended data and footnotes. Amended data of ‘RAM and hardware registers’ table. Table 37: Data memory: Updated names and data of NRW and tRET parameters. Table 40: TIM 1, 2, 3, and 4 electrical specifications: Added VOH and VOL parameters; Updated Ilkg ana parameter. Removed: Output driving current (standard ports), Output driving current (true open drain ports), and Output driving current (high sink ports). Table 46: EMI data: Updated fADC, tS, and tCONV data. Table: ADC accuracy for VDDA = 3.3 V: removed the 4-MHz condition from all parameters. Table 47: ESD absolute maximum ratings: Removed the 4-MHz condition from all parameters; updated footnote 1 and removed footnote 2. Table 51: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data: Added data for TA = 145 °C. Figure 53: Updated memory size, pin count and package type information. DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Revision history Table 55. Document revision history (continued) Date 16-Sep-2008 01-Jul-2009 Revision Changes 3 Replaced the salestype ‘STM8H61xx’ with ‘STM8AH61xx on the first page. Added ‘part numbers’ to heading rows of Table 1: Device summary. Updated the 80-pin package silhouette on cover page in line with POA 0062342-revD. Table 18: Renamed ‘TMU key registers 0-7 [7:0]’ as ‘TMU key registers 1-8 [7:0]’ Section 9: Updated introductory text concerning option bytes which do not need to be saved in a complementary form. Table 18: Renamed the option bits ‘TMU[0:3]’, ‘NTMU[0:3]’, and ‘TMU_KEY 0-7 [7:0]’ as ‘TMU[3:0]’, ‘NTMU[3:0]’, and ‘TMU_KEY 1-8 [7:0]’ respectively. Table 21: Updated values of option byte 5 (HSECNT[7:0]); inverted the description of option byte 6 (TMU[3:0]); renamed option bytes 8 to 15 ‘TMU_KEY 0-7 [7:0]’, as ‘TMU_KEY 1-8 [7:0]’. Updated 80-pin package information in line with POA 0062342-revD in Figure 45 and Table 53. 4 Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header. Updated : Features on page 1 (memories, timers, operating temperature, ADC and I/Os). Updated Table 1: Device summary Updated Kbyte value of program memory in Section: Introduction Changed the first two lines from the top in Section: Description. Updated Figure 1: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block diagram Updated Section 5: Product overview In Figure 5: LQFP 48-pin pinout, added USART function to pins 10, 11, and 12; added CAN Tx and CAN Rx functions to pins 35 and 36 respectively. Section 6: Pinouts and pin description: deleted the text below the Table 10: Legend/abbreviation for the pin description table Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description: 68th, 69th pin (LQFP80): replaced X with a dash for PP output and Added a table footnote. Updated Figure 8: Register and memory map. Table 12: Memory model 128K: updated footnote Deleted the Table: Stack and RAM partitioning Table 17: STM8A interrupt table: Updated priorities 13, 15, 17, 20 and 24 and changed table footnote Updated Section 7: Memory and register map Updated Table: Data memory, Table: I/O static characteristics, and Table 39: NRST pin characteristics. Section 10.1.1: Minimum and maximum values: added ambient temperature TA = -40 °C Updated Table 20: Voltage characteristics. Updated Table 21: Current characteristics. Updated Table 22: Thermal characteristics. Updated Table 24: General operating conditions. DocID14395 Rev 15 117/125 124 Revision history STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 55. Document revision history (continued) Date 01-Jul-2009 22-Oct-2009 118/125 Revision Changes Removed table: Total current consumption and timing in halt, fast active halt and slow active halt modes at VDD = 3.3 V. Added Table 28: Oscillator current consumption. Added Table 29: Programming current consumption. Updated Table 30: Typical peripheral current consumption VDD = 5.0 V Updated Table 31: HSE external clock characteristics. Updated Table 32: HSE oscillator characteristics. Table 20: HSE oscillator circuit diagram: changed ‘consumption control’ to ‘current control’ Section : HSE oscillator critical gm formula: clarified formula Updated Table 33: HSI oscillator characteristics. Removed ‘RAM and hardware registers’ Removed Table: RAM and hardware registers. Updated Table 35: Flash program memory/data EEPROM memory Added Table 36: Flash program memory. Added Table 37: Data memory. Updated Table 38: I/O static characteristics. Updated Table 39: NRST pin characteristics. 4 (continued) Updated Table 40: TIM 1, 2, 3, and 4 electrical specifications Section 10.3.9: SPI interface: changed title from “SPI serial peripheral interface“. Updated Table 41: SPI characteristics. Figure 40: SPI timing diagram in slave mode and with CPHA = 0: Changed title and added footnote. Figure 41: SPI timing diagram in slave mode and with CPHA = 1: changed the title. Updated Table 43: ADC characteristics. Updated Figure 43: Typical application with ADC. Removed Table: ADC accuracy for VDDA = 3.3 V. Updated Table 44: ADC accuracy for VDDA = 5 V. Updated Table 46: EMI data. Updated Table 48: Electrical sensitivities. Added text about Ecopack in the Section 11: Package information. Figure 48: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline: deleted footnote. Updated Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1. Added Section 13: STM8 development tools. 5 Updated Table 1: Device summary: added STM8AF5178, STM8AF519A and STM8AF619A. DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Revision history Table 55. Document revision history (continued) Date 13-Apr-2010 08-Jul-2010 Revision Changes 6 Updated title on cover page. Modified cover page header to clarify the part numbers covered by the datasheets. Updated footnote on Table 1: Device summary to add ‘P’ order codes. Changed definition of ‘P’ order codes. ‘Q’ order codes (FASTROM and EEPROM) removed. Reorganized the content of Section 5: Product overview. Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description updated PD7/TLI alternate function, removed caution note for PD6/ LINUART_RX, and added note to PA1/OSCIN. Renamed Section 7: Memory and register map, and merged content with Section: Register map. Updated Figure 8: Register and memory map. Renamed BL_EN and NBL_EN, BL and NBL, respectively, in Table 18: Option bytes. Updated AFR4 definition in Table 19: Option byte description. Added CEXT in Table 24: General operating conditions, and Section 10.3.1: VCAP external capacitor. Updated tVDD in Table 25: Operating conditions at power-up/powerdown. Moved Table 30: Typical peripheral current consumption VDD = 5.0 V to Section : Current consumption for on-chip peripherals. Removed VESD(MM) from Table 47: ESD absolute maximum ratings. Updated Section 12: Ordering information to the devices supported by the datasheet. Updated Section 13: STM8 development tools. 7 Added STM8AF5168 and STM8AF518A part number in Figure 4, and STM8AF618A in Figure 5. Added STM8AF52xx, STM8AF6269, STM8AF628x, and STM8AF62Ax. Updated D temperature range to -40 to 150°C. Updated number of I/Os on cover page. Added Table 23: Operating lifetime. Restored VESD(MM) from Table 47: ESD absolute maximum ratings. Table 24: General operating conditions: updated VCAP information. ESL parameter, and range D maximum junction temperature (TJ). Added STM8AF52xx and STM8AF62xx, and footnote in Section 12: Ordering information. Updated Section 13: STM8 development tools: added Table: Product evolution summary, and split the beCAN time triggered communication mode limitation in two sections. DocID14395 Rev 15 119/125 124 Revision history STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 55. Document revision history (continued) Date Revision Changes Modified references to reference manual, and Flash programming manual in the whole document. Added reference to AEC Q100 standard on cover page. Renamed timer types as follows: – Auto-reload timer to general purpose timer – Multipurpose timer to advanced control timer – System timer to basic timer Introduced concept of high density Flash program memory. Updated the number of I/Os for devices in 80-, 64-, and 48-pin packages in Table: STM8AF52xx product line-up with CAN, Table: STM8AF62xx product line-up without CAN, Table: STM8AF/H/P51xx product line-up with CAN, and Table: STM8AF/H/P61xx product lineup without CAN. Added TMU brief description in Section 5.4: Flash program and data EEPROM, updated TMU_MAXATT description in Table 19: Option byte description, and TMU_MAWATT reset value in Table 18: Option bytes. 30-Jan-2011 8 Updated clock sources in Section 5.5.1: Features. Added Table 4: Peripheral clock gating bits (CLK_PCKENR1). Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter. Added Table 8: ADC naming and Table 9: Communication peripheral naming correspondence. Updated SPI data rate to fMASTER/2 in Section 5.9.3: Serial peripheral interface (SPI). Added reset state in Table 10: Legend/abbreviation for the pin description table. Table: STM8A microcontroller family pin description: modified footnotes related to PD1/SWIM, corrected wpu input for PE1 and PE2, and renamed TIMn_CCx and TIMn_NCCx to TIMn_CHx and TIMn_CHxN, respectively. Section: Register map: Removed CAN register CLK_CANCCR. Removed I2C_PECR register. Added footnote for Px_IDR registers in Table 13: I/O port hardware register map. Updated register reset values for Px_IDR and PD_CR1 registers. Replaced tables describing register maps and reset values for nonvolatile memory, global configuration, reset status, TMU, clock controller, interrupt controller, timers, communication interfaces, and ADC, by TTable 14: General hardware register map. Added debug module register map Renamed Fast Active Halt mode to Active-halt mode with regulator on, and Slow Active Halt mode to Active-halt mode with regulator off, updated Section 5.6: Low-power operating modes, and Table 27: Total current consumption in Halt and Active-halt modes. General conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise stated. IDD(FAH) and IDD(SAH) renamed IDD(AH); tWU(FAH) and tWU(SAH) renamed tWU(AH). 120/125 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Revision history Table 55. Document revision history (continued) Date Revision Changes 30-Jan-2011 Removed note 1 in Table 24: General operating conditions and note 1 below Figure 11: fCPUmax versus VDD. Removed note 3 in Table 26: Total current consumption in Run, Wait and Slow mode. General conditions for VDD apply, TA = -40 °C to 150 °C. Removed note 2 in Table 31: HSE external clock characteristics and Table 35: Flash program memory/data EEPROM memory Removed note 1 in Table 37: Data memory. Modified TWE maximum value in Table 36: Flash program memory and Table 37: Data memory. Added tIFP(NRST) and renamed VF(NRST) tIFP in Table 39: NRST pin characteristics. 8 Added recommendation concerning NRST pin level, and power (continued) consumption sensitive applications, above Figure 39: Recommended reset pin protection, and updated external capacitor value. Updated Note 1 in Table 40: TIM 1, 2, 3, and 4 electrical specifications. Updated Note 1 in Table 41: SPI characteristics. Moved know limitations to separate errata sheet. Added “not recommended for new design” note to device family 51, memory size 7 and 9, and temperature range B, in Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1. Added Raisonance compiler in Section 13.2: Software tools. 18-Jul-2012 Updated wildcards of document part numbers. Added VFQFPN package. Added STM8AF62A6 part number. Table 1: Device summary updated footnote 1 and added footnote 2. Table: STM8AF52xx product line-up with CAN and Table: STM8AF62xx product line-up without CAN: added “P” version for all order codes; updated size of data EEPROM for 64K devices to 2K instead of 1.5K; updated RAM. Figure 1: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block diagram: updated POR, BOR and WDG; removed PDR; added legend. Section 5.4: Flash program and data EEPROM: removed non relevant bullet points and added a sentence about the factory program. Added Table 4: Peripheral clock gating bits (CLK_PCKENR1) and updated Table 5: Peripheral clock gating bits (CLK_PCKENR2) Section : ADC features: updated ADC input range. Table 12: Memory model 128K: updated RAM size, RAM end addresses, and stack roll-over addresses; updated footnote 1 Table 18: Option bytes: updated factory default setting for NOPT17; updated footnotes. Table 20: Voltage characteristics: updated VDDX - VDD to VDDX - VSS. Table 24: General operating conditions: updated VCAP. 9 DocID14395 Rev 15 121/125 124 Revision history STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 55. Document revision history (continued) Date 122/125 Revision Changes 18-Jul-2012 Table 26: Total current consumption in Run, Wait and Slow mode. General conditions for VDD apply, TA = -40 °C to 150 °C: updated conditions for IDD(RUN). Table 38: I/O static characteristics: added new condition and new max values for rise and fall time; updated footnote 2. Section 10.3.7: Reset pin characteristics: updated text below Figure 38: Typical NRST pull-up current Ipu vs VDD Figure 39: Recommended reset pin protection: updated unit of capacitor. Table 41: SPI characteristics: updated SCK high and low time conditions and values. Figure 42: SPI timing diagram - master mode: replaced ‘SCK input’ signals with ‘SCK output’ signals. Updated Table 49: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data, Table 50: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data, Table 51: LQFP48 9 48-pin, 7 x 7 mm low-profile quad flat package mechanical data, (continued) Table 52: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data, Table 53: VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data Replaced Figure 48: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline, Figure 51: LQFP48 - 48-pin, 7 x 7 mm lowprofile quad flat package outline and Figure 54: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline Added Figure 49: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint, Figure 52: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint and Figure 55: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint Updated Figure 57: VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline Updated Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1 Section 13.2.2: C and assembly toolchains: added www.iar.com. 31-Mar-2014 Updated: – Table 1: Device summary, – Table: STM8AF52xx product line-up with CAN, – Table: STM8AF/H/P51xx product line-up with CAN, – Table: STM8AF/H/P61xx product line-up without CAN, – Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description, – The maximum speed in Section 5.9.3: Serial peripheral interface (SPI), – tTEMP Reset release delay /VDD rising typical and max values in Table 25: Operating conditions at power-up/power-down, – The symbol tIFP(NRST) with tINFP(NRST) in Table 39: NRST pin characteristics, – The address and comment for Reset in Table 17: STM8A interrupt table. 10 DocID14395 Rev 15 STM8AF526x/8x/Ax STM8AF6269/8x/Ax Revision history Table 55. Document revision history (continued) Date 31-Mar-2014 13-Jun-2014 Revision Changes Added: – Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout; – the caution in Section 5.10: Input/output specifications, – The table footnote “Not recommended for new designs” to Table: 10 STM8AF/H/P51xx product line-up with CAN and Table: (continued) STM8AF/H/P61xx product line-up without CAN. – The figure footnotes to Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout and Figure: VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5) 11 Added STM8AF52A6 part number. 09-Jun-2015 12 Added: – the third table footnote to Table 25: Operating conditions at powerup/power-down, – Figure 47: LQFP80 marking example (package top view), – Figure 50: LQFP64 marking example (package top view), – Figure 53: LQFP48 marking example (package top view), – Figure 56: LQFP32 marking example (package top view), – Figure 59: VFQFPN32 marking example (package top view), – the footnote about the device marking to Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1. Removed STM8AF51xx and STM8AF61xx obsolete root part numbers, and consequently “H” products: – Table 1: Device summary, – Section 1: Introduction, – Section 2: Description, – Section 3: Product line-up, – Table 12: Memory model 128K, – Section 10.3: Operating conditions, – Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1. Moved Section 11.6: Thermal characteristics to Section 11: Package information. Updated: – the product naming in the document headers and captions, – the standard reference for EMI characteristics in Table 46: EMI data. 13-Jun-2016 13 Updated Table 53: VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data DocID14395 Rev 15 123/125 124 Revision history STM8AF526x/8x/Ax STM8AF6269/8x/Ax Table 55. Document revision history (continued) Date 124/125 Revision Changes 13-Oct-2016 14 Updated: – Title of Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout, (previously STM8AF5286UC VFQFPN32 32-pin pinout) – Footnotes of Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1 – Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description replaced “STM8AF5286UC VQFPN32” with “STM8AF52x6 VQFPN32” at header row – Section 10.2: Absolute maximum ratings – Section : Device marking on page 93 – Section : Device marking on page 96 – Section : Device marking on page 99 – Section : Device marking on page 104 – Section : Device marking on page 108 Added: – Footnote on Figure 47: LQFP80 marking example (package top view), Figure 50: LQFP64 marking example (package top view), Figure 56: LQFP32 marking example (package top view), Figure 59: VFQFPN32 marking example (package top view). 10-Nov-2016 15 Updated header row and PA6/USART_CK pin row on Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID14395 Rev 15 125/125 125