STM8AF6223PCU

STM8AF6213/13A STM8AF6223/23A STM8AF6226 Automotive 8-bit MCU, with up to 8-Kbyte Flash memory, data EEPROM, 10-bit ADC, timers, LIN, SPI, I²C, 3 to 5.5 V Datasheet - production data Features • AEC-Q100 qualified • Core – Max fCPU: 16 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Extended instruction set TSSOP20 (6.4x4.4 mm) LQFP32 7x7 mm • Memories – Program memory: 4 to 8 Kbyte Flash program; data retention 20 years at 55 °C after 1 kcycle – Data memory: 640 byte true data EEPROM; endurance 300 kcycle – RAM: 1 Kbyte • Clock management – Low-power crystal resonator oscillator with external clock input – Internal, user-trimmable 16 MHz RC and low-power 128 kHz RC oscillators – Clock security system with clock monitor • Reset and supply management – Wait/auto-wakeup/Halt low-power modes with user definable clock gating – Low-consumption power-on and powerdown reset VFQFPN32 (5x5 mm) • I/Os – Up to 28 I/Os on a 32-pin package including 21 high sink outputs – Highly robust I/O design, immune against current injection • Communication interfaces – LINUART LIN 2.2 compliant, master/slave modes with automatic resynchronization – SPI interface up to 8 Mbit/s or fMASTER/2 – I2C interface up to 400 Kbit/s • Analog to digital converter (ADC) – 10-bit, ± 1 LSB ADC with up to 7 muxed channels + 1 internal channel, scan mode and analog watchdog – Internal reference voltage measurement • Operating temperature up to 150 °C • Interrupt management – Nested interrupt controller with 32 interrupts – Up to 28 external interrupts on 7 vectors • Timers – Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization – 16-bit general purpose timer with 3 CAPCOM channels each (IC, OC, PWM) – 8-bit AR basic timer with 8-bit prescaler – Auto-wakeup timer – Window and independent watchdog timers April 2020 This is information on a product in full production. DS9884 Rev 9 1/112 www.st.com Contents STM8AF6213/13A/23/23A/26 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 4.2 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.1 Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.3 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13 4.2.1 SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.2 Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 4.4.1 Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4.2 Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5.1 2/112 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.11 TIM5 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.12 TIM6 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14.1 LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.2 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14.3 Inter integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 5 6 Contents Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 TSSOP20 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 LQFP32/VFQPN32 pinout and pin description . . . . . . . . . . . . . . . . . . . . . 28 5.3 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.1 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.2 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 42 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.2 STM8AF6213/13A/23/23A/26 alternate function remapping bits . . . . . . . 48 9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67 10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69 10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DS9884 Rev 9 3/112 4 Contents STM8AF6213/13A/23/23A/26 10.3.9 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.1 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 103 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . 106 13.1.1 13.2 13.3 14 4/112 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 13.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 13.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. STM8AF6213/13A/23/23A/26 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15 TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Legend/abbreviations for pinout tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM8AF6213/STM8AF6223 TSSOP20 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM8AF6213A and STM8AF6223A TSSOP20 pin description . . . . . . . . . . . . . . . . . . . . . 25 STM8AF6226 LQFP32/VFQPN32 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory model for the devices covered in this datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . 34 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM8AF6226 alternate function remapping bits [7:2] for 32-pin packages . . . . . . . . . . . . 48 STM8AF6213 and STM8AF6223 alternate function remapping bits [7:2] for 20-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM8AF6213A and STM8AF6223A alternate function remapping bits [7:2] for 20-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM8AF6226 alternate function remapping bits [1:0] for 32-pin packages . . . . . . . . . . . . 50 STM8AF6213/STM8AF6223 alternate function remapping bits [1:0] for 20-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM8AF6223A alternate function remapping bits [1:0] for 20-pin packages . . . . . . . . . . . 51 Unique ID bit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Operating lifetime (OLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 58 Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 59 Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DS9884 Rev 9 5/112 6 List of tables Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. 6/112 STM8AF6213/13A/23/23A/26 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADC accuracy with RAIN < 10 kΩ, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ADC accuracy with RAIN < 10 kΩ, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 STM8AF6213/13A/23/23A/26 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . 105 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. STM8AF6213/13A/23/23A/26 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM8AF6213/STM8AF6223 TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM8AF6213A and STM8AF6223A TSSOP20 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM8AF6226 LQFP32/VFQPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 64 Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 64 Typ IDD(RUN) vs. VDD HSEI RC osc., fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 65 Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ IDD(WFI) vs. VDD HSI RC osc., fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typical pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typical pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD- VOH @ VDD = 5 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD- VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD- VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typ. VDD- VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 80 Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 96 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package DS9884 Rev 9 7/112 8 List of figures Figure 47. Figure 48. Figure 49. Figure 50. 8/112 STM8AF6213/13A/23/23A/26 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 VFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 1 Introduction Introduction The datasheet contains the description of STM8AF6213, STM8AF6213A, STM8AF6223, STM8AF6223A and STM8AF6226 features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8A microcontroller memory, registers and peripherals, please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016). • For information on programming, erasing and protection of the internal Flash memory please refer to the STM8 Flash programming manual (PM0051). • For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). • For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). DS9884 Rev 9 9/112 108 Description 2 STM8AF6213/13A/23/23A/26 Description The STM8AF6213, STM8AF6213A, STM8AF6223, STM8AF6223A and STM8AF6226 automotive 8-bit microcontrollers offer 4 to 8 Kbytes of Flash program memory, plus integrated true data EEPROM. The STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness and reduced system cost. Device performance and robustness are ensured by advanced core and peripherals made in a state-of-the-art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system. The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. Full documentation is offered as well as a wide choice of development tools. ² Table 1. STM8AF6213/13A/23/23A/26 features Device STM8AF6226 Pin count 32 20 Max. number of GPIOs 28 including 21 high-sink I/Os 16 including 12 high-sink I/Os Ext. interrupt pins 28 16 Timer CAPCOM channels 6 7 6 7 6 Timer complementary outputs 3 1 2 1 2 A/D converter channels 7 5 7 5 7 Low-density Flash program memory (byte) STM8AF6223 STM8AF6223A 8K STM8AF6213 STM8AF6213A 4K Data EEPROM (byte) 640(1) RAM (byte) 1K Peripheral set Multipurpose timer (TIM1), SPI, I2C, LINUART, window WDG, independent WDG, ADC, PWM timer (TIM5), 8-bit timer (TIM6) 1. No read-while-write (RWW) capability. 10/112 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 3 Block diagram Block diagram Figure 1. STM8AF6213/13A/23/23A/26 block diagram Reset block XTAL 1- 16 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Debug/SWIM 400 Kbit/s I2C 8 Mbit/s SPI LIN SPI emul. Up to 7 channels Up to 8 Kbyte program Flash Address and data bus Single wire debug interface LINUART 640 byte data EEPROM 1 Kbyte RAM 16-bit advanced control timer (TIM1) Up to 4 CAPCOM channels + 3 complementary outputs 16-bit general purpose timers (TIM5) Up to 3 CAPCOM channels ADC1 8-bit basic timer (TIM6) 1/2/4 kHz beep Beeper AWU timer MS38343V1 1. Legend: ADC (Analog-to-digital converter), beCAN (Controller area network), BOR (Brownout reset), I²C (Inter-integrated circuit multimaster interface),IWDG (Independent window watchdog), LINUART (Local interconnect network universal asynchronous receiver transmitter), POR (Power on reset), SPI (Serial peripheral interface), SWIM (Single wire interface module), USART (Universal synchronous asynchronous receiver transmitter), Window WDG (Window watchdog). DS9884 Rev 9 11/112 108 Product overview 4 STM8AF6213/13A/23/23A/26 Product overview The following section intends to give an overview of the basic features of the products covered by this datasheet. For more detailed information on each feature please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016). 4.1 Central processing unit (CPU) The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. 4.1.1 4.1.2 4.1.3 12/112 Architecture and registers • Harvard architecture • 3-stage pipeline • 32-bit wide program memory bus - single cycle fetching for most instructions • X and Y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations • 8-bit accumulator • 24-bit program counter - 16-Mbyte linear memory space • 16-bit stack pointer - access to a 64 Kbyte level stack • 8-bit condition code register - 7 condition flags for the result of the last instruction. Addressing • 20 addressing modes • Indexed indirect addressing mode for look-up tables located anywhere in the address space • Stack pointer relative addressing mode for local variables and parameter passing Instruction set • 80 instructions with 2-byte average instruction size • Standard data movement and logic/arithmetic functions • 8-bit by 8-bit multiplication • 16-bit by 8-bit and 16-bit by 16-bit division • Bit manipulation • Data transfer between stack and accumulator (push/pop) with direct stack access • Data transfer using the X and Y registers or direct memory-to-memory transfers DS9884 Rev 9 STM8AF6213/13A/23/23A/26 4.2 Product overview Single wire interface module (SWIM) and debug module (DM) The single wire interface module together with an integrated debug module permit nonintrusive, real-time in-circuit debugging and fast memory programming. 4.2.1 SWIM Single wire interface module for direct access to the debug mode and memory programming. The interface can be activated in all device operation modes.The maximum data transmission speed is 145 byte/ms. 4.2.2 Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Besides memory and peripheral operation, CPU operation can also be monitored in real-time by means of shadow registers. 4.3 4.4 4.4.1 • R/W to RAM and peripheral registers in real-time • R/W access to all resources by stalling the CPU • Breakpoints on all program-memory instructions (software breakpoints) • Two advanced breakpoints, 23 predefined breakpoint configurations Interrupt controller • Nested interrupts with three software priority levels • 32 interrupt vectors with hardware priority • Up to 28 external interrupts on 7 vectors including TLI • Trap and reset interrupts Flash program and data EEPROM memory • Up to 8 Kbytes of Flash program single voltage Flash memory • 640 byte true data EEPROM • User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option byte. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option byte. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below. DS9884 Rev 9 13/112 108 Product overview STM8AF6213/13A/23/23A/26 The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: • Main program memory: up to 8 Kbyte minus UBC • User-specific boot code (UBC): configurable up to 8 Kbyte The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2. Flash memory organization Data EEPROM memory Data memory area ( 640 byte) Option bytes UBC area Remains write protected during IAP Low-density Flash program memory (up to 8Kbyte) Programmable area (from 64 byte (1 page) to up to 8 Kbyte (in 1 page steps) Flash program memory area Write access possible for IAP MS38344V1 4.4.2 Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 14/112 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 4.5 Product overview Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. 4.5.1 Features • Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Safe clock switching: Clock sources can be changed safely on the fly in Run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. • Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • Master clock sources: four different clock sources can be used to drive the master clock: – 1-16 MHz high-speed external crystal (HSE) – Up to 16 MHz high-speed user-external clock (HSE user-ext) – 16 MHz high-speed internal RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI) • Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. • Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Bit Periphera l clock Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock PCKEN17 TIM1 PCKEN13 LINUART PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM5 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved PCKEN14 TIM6 DS9884 Rev 9 15/112 108 Product overview 4.6 STM8AF6213/13A/23/23A/26 Power management For efficient power management, the application can be put in one of four different lowpower modes. Users can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. 4.7 • Wait mode: in this mode, the CPU is stopped but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. • Active-halt mode with regulator on: in this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in Active-halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. • Active-halt mode with regulator off: this mode is the same as Active-halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. • Halt mode: in this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application timing perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 16/112 1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. 2. Refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register. DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Product overview Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. The IWDG time base spans from 60 µs to 1 s 4.8 4.9 Auto wakeup counter • Used for auto wakeup from active halt mode • Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock • LSI clock can be internally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. The beeper output port is only available through the alternate function remap option bit AFR7. 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver. • 16-bit up, down and up/down auto-reload counter with 16-bit fractional prescaler. • Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output. • Synchronization module to control the timer with external signals or to synchronise with TIM5 or TIM6 • Break input to force the timer outputs into a defined state • Three complementary outputs with adjustable dead time • Encoder mode • Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break DS9884 Rev 9 17/112 108 Product overview 4.11 4.12 STM8AF6213/13A/23/23A/26 TIM5 - 16-bit general purpose timer • 16-bit autoreload (AR) up-counter • 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 • 3 individually configurable capture/compare channels • PWM mode • Interrupt sources: 3 x input capture/output compare, 1 x overflow/update • Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM6 TIM6 - 8-bit basic timer • 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 • Clock source: CPU clock • Interrupt source: 1 x overflow/update • Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM5. Table 3. TIM timer features Timer Counter size (bits) Prescaler Counting mode CAPCOM channels TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes TIM5 16 Any power of 2 from 1 to 32768 Up 3 0 No TIM6 8 Any power of 2 from 1 to 128 Up 0 0 No 18/112 DS9884 Rev 9 Complemen Ext. trigger tary outputs Timer synchroniz ation/ chaining Yes STM8AF6213/13A/23/23A/26 4.13 Product overview Analog-to-digital converter (ADC1) The STM8AF6213, STM8AF6213A, STM8AF6223, STM8AF6223A and STM8AF6226 products contain a 10-bit successive approximation A/D converter (ADC1) with up to 7 external and 1 internal multiplexed input channels and the following main features: Note: • Input voltage range: 0 to VDD • Input voltage range: 0 to VDDA • Conversion time: 14 clock cycles • Single and continuous and buffered continuous conversion modes • Buffer size (n x 10 bits) where n = number of input channels • Scan mode for single and continuous conversion of a sequence of channels • Analog watchdog capability with programmable upper and lower thresholds • Internal reference voltage on channel AIN7 • Analog watchdog interrupt • External trigger input • Trigger from TIM1 TRGO • End of conversion (EOC) interrupt Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers. Internal bandgap reference voltage Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal bandgap reference is constant and can be used, for example, to monitor VDD. It is independent of variations in VDD and ambient temperature TA. 4.14 Communication interfaces The following communication interfaces are implemented: • LINUART: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.2 capability • SPI: full and half-duplex, 8 Mbit/s • I²C: up to 400 Kbit/s Some peripheral names differ between the datasheet and STM8S series and STM8AF series 8-bit microcontrollers reference manual, RM0016 (see Table 4). Table 4. Communication peripheral naming correspondence Peripheral name in datasheet Peripheral name in reference manual (RM0016) LINUART UART4 DS9884 Rev 9 19/112 108 Product overview 4.14.1 STM8AF6213/13A/23/23A/26 LINUART Main features • 1 Mbit/s full duplex SCI • SPI emulation • High precision baud rate generator • Smartcard emulation • IrDA SIR encoder decoder • LIN mode • Single wire half duplex mode LIN mode Master mode: • LIN break and delimiter generation • LIN break and delimiter detection with separate flag and interrupt source for read back checking. Slave mode: 20/112 • Autonomous header handling – one single interrupt per valid header • Mute mode to filter responses • Identifier parity error checking • LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI) clock source • Break detection at any time, even during a byte reception • Header errors detection: – Delimiter too short – Synch field error – Deviation error (if automatic resynchronization is enabled) – Framing error in synch field or identifier field – Header time-out DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Product overview Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver • Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt) • Transmission error detection with interrupt generation • Parity control Synchronous communication 4.14.2 4.14.3 • Full duplex synchronous transfers • SPI master operation • 8-bit data communication • Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16) Serial peripheral interface (SPI) • Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave • Full duplex synchronous transfers • Simplex synchronous transfers on two lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • CRC calculation • 1 byte Tx and Rx buffer • Slave /master selection input pin Inter integrated circuit (I2C) interface • • I2C master features: – Clock generation – Start and stop generation I2C slave features: – Programmable I2C address detection – Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds: – Standard speed (up to 100 kHz), – Fast speed (up to 400 kHz) DS9884 Rev 9 21/112 108 Pinout and pin description 5 STM8AF6213/13A/23/23A/26 Pinout and pin description The following table presents the meaning of the abbreviations in use in the pin description tables in this section. Table 5. Legend/abbreviations for pinout tables Type I= input, O = output, S = power supply Level Input CM = CMOS (standard for all I/Os) Output HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control configuration Input float = floating, wpu = weak pull-up Output T = true open drain, OD = open drain, PP = push pull Reset state 5.1 Bold X (pin state after internal reset release). Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. TSSOP20 pinouts and pin descriptions Figure 3. STM8AF6213/STM8AF6223 TSSOP20 pinout [LINUART_CK] TIM5_CH1/BEEP/(HS) PD4 1 20 PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR AIN5/LINUART_TX/(HS) PD5 2 19 PD2 (HS)/AIN3 [TIM5_CH3] AIN6/LINUART_RX/(HS) PD6 3 18 PD1 (HS)/SWIM NRST 4 17 PC7 (HS)/SPI_MISO [TIM1_CH2] OSCIN/PA1 5 16 PC6 (HS)/SPI_MOSI [TIM1_CH1] OSCOUT/PA2 6 15 PC5 (HS)/SPI_SCK [TIM5_CH1] VSS 7 14 PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N] VCAP VDD 8 13 PC3 (HS)/TIM1_CH3 [TLI][TIM1_CH1N] 9 12 PB4 (T)/I2C_SCL [ADC_ETR] 10 11 PB5 (T)/I2C_SDA [TIM1_BKIN] [SPI_NSS] TIM5_CH3/(HS) PA3 MS38345V1 1. (HS) high sink capability. 2. (T) true open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 22/112 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Pinout and pin description Figure 4. STM8AF6213A and STM8AF6223A TSSOP20 pinout [LINUART_CK] TIM5_CH1/BEEP/(HS) PD4 1 20 PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR AIN5/LINUART_TX/(HS) PD5 2 19 PD2 (HS)/AIN3 [TIM5_CH3] AIN6/LINUART_RX/(HS) PD6 3 18 PD1 (HS)/SWIM NRST 4 17 PC7 (HS)/SPI_MISO [TIM1_CH2] OSCIN/PA1 5 16 PC6 (HS)/SPI_MOSI [TIM1_CH1] OSCOUT/PA2 6 15 PC5 (HS)/SPI_SCK [TIM5_CH1] VSS 7 14 PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N] VCAP VDD 8 13 PB0 (HS)/TIM1_CH1N/AIN0 9 12 PB1 (HS)/TIM1_CH2N/AIN1 10 11 PB4 (T)/I2C_SCL [ADC_ETR] [TIM5_BKIN] I2C_SDA/(T) PB5 MS38346V1 1. (HS) high sink capability. 2. (T) true open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 6. STM8AF6213/STM8AF6223 TSSOP20 pin description I/O X X X HS O3 X PP OD Speed High sink(1) Output Ext. interrupt 1 PD4/ TIM5_CH1/ BEEP [LINUART_CK] Type wpu Pin name floating TSSOP Input X Main function (after reset) Default alternate function Alternate function after remap [option bit] Port D4 Timer 5 channel 1/BEEP output LINUART clock [AFR2] Port D5 Analog input 5/ LINUART data transmit - Port D6 Analog input 6/ LINUART data receive - 2 PD5/ AIN5/ LINUART_TX 3 PD6/ AIN6/ LINUART_RX I/O X X X HS O3 X X 4 NRST I/O - X - - - - - 5 PA1/ OSCIN(2) I/O X X X - O1 X X 6 PA2/ OSCOUT I/O X X X O1 X X 7 VSS S - - - - - - - Digital ground 8 VCAP S - - - - - - - 1.8 V regulator capacitor 9 VDD S - - - - - - - Digital power supply I/O X X X HS O3 DS9884 Rev 9 X X Reset Port A1 Resonator/ crystal in - Port A2 Resonator/ crystal out - 23/112 108 Pinout and pin description STM8AF6213/13A/23/23A/26 Table 6. STM8AF6213/STM8AF6223 TSSOP20 pin description (continued) Output Timer 1 break input [AFR4] I2C clock ADC external trigger [AFR4] Timer 1 channel 3 Top level interrupt [AFR3] Timer 1 inverted channel 1 [AFR7] PP I2C data OD Port B5 Speed - High sink(1) SPI master/ slave select [AFR1] Type Ext. interrupt Timer 5 channel 3 Pin name wpu Alternate function after remap [option bit] floating Default alternate function TSSOP Input Main function (after reset) 10 PA3/ TIM5_CH3 [SPI_NSS] I/O X X X HS O3 X X Port A3 11 PB5/ I2C_SDA [TIM1_BKIN] I/O X - X - O1 T(3) 12 PB4/ I2C_SCL [ADC_ETR] - T(3) 13 PC3/ TIM1_CH3/[TLI]/[ TIM1_CH1N] I/O I/O X X - X X X HS O1 O3 X - X Port B4 Port C3 Analog Timer 1 input 2 channel 4 [AFR2]Time /configurabl r 1 inverted e clock channel 2 output [AFR7] 14 PC4/ TIM1_CH4/ CLK_CCO/AIN2/[ TIM1_CH2N] I/O X X X HS O3 X X Port C4 15 PC5/SPI_SCK [TIM5_CH1] I/O X X X HS O3 X X Port C5 SPI clock Timer 5 channel 1 [AFR0] 16 PC6/ SPI_MOSI [TIM1_CH1] I/O X X X HS O3 X X Port C6 PI master out/slave in Timer 1 channel 1 [AFR0] 17 PC7/ SPI_MISO [TIM1_CH2] I/O X X X HS O3 X X Port C7 SPI master in/ slave out Timer 1 channel 2[AFR0] 18 PD1/ SWIM(4) I/O X X X HS O4 X X Port D1 SWIM data interface - 24/112 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Pinout and pin description Table 6. STM8AF6213/STM8AF6223 TSSOP20 pin description (continued) 19 20 PD2/AIN3 [TIM5_CH3] PD3/ AIN4/ TIM5_CH2/ ADC_ETR I/O I/O X X X X X X HS HS O3 X O3 X PP OD Speed High sink(1) Output Ext. interrupt Type wpu Pin name floating TSSOP Input X X Default alternate function Alternate function after remap [option bit] Port D2 - Analog input 3 [AFR2] Timer 52 channel 3 [AFR1] Port D3 Analog input 4 Timer 52 channel 2/ADC external trigger - Main function (after reset) 1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings (see Section 10.2: Absolute maximum ratings). 2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application. 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented) 4. The PD1 pin is in input pull-up during the reset phase and after internal reset release. Table 7. STM8AF6213A and STM8AF6223A TSSOP20 pin description 2 PD5/ AIN5/ LINUART_TX I/O I/O X X X X X X HS HS O3 O3 DS9884 Rev 9 X X PP OD Speed High sink(1) Output Ext. interrupt 1 PD4/ TIM5_CH1/ BEEP/SPI_NSS [LINUART_CK] Type wpu Pin name floating TSSOP Input X X Main function (after reset) Default alternate function Alternate function after remap [option bit] Port D4 Timer 5 channel 1/BEEP output LINUART clock [AFR2] Port D5 Analog input 5/ LINUART data transmit - 25/112 108 Pinout and pin description STM8AF6213/13A/23/23A/26 Table 7. STM8AF6213A and STM8AF6223A TSSOP20 pin description (continued) Main function (after reset) Default alternate function Alternate function after remap [option bit] Port D6 Analog input 6/ LINUART data receive - X X HS O3 X X 4 NRST I/O - X - - - - - 5 PA1/ OSCIN(2) I/O X X X - O1 X X Port A1 Resonator/ crystal in - 6 PA2/ OSCOUT I/O X X X - O1 X X Port A2 Resonator/ crystal out - 7 VSS S - - - - - - - Digital ground - 8 VCAP S - - - - - - - 1.8 V regulator capacitor - 9 VDD S - - - - - - - Digital power supply - 10 PB5/ I2C_SDA [TIM1_BKIN] I/O X - X - - Port B5 11 PB4/ I2C_SCL [ADC_ETR] 12 PB1/ TIM1_CH2N/ AIN1 I/O I/O X X - X X X - HS O1 T(3) O1 T(3) O3 X PP X OD I/O Speed 3 PD6/ AIN6/ LINUART_RX Type wpu Pin name floating TSSOP High sink(1) Output Ext. interrupt Input - X Reset I2C data Timer 1 break input [AFR4] Port B4 I2C clock ADC external trigger [AFR4] Port B1 Timer 1 inverted channel 2/Analog input 1 - Port B0 Timer 1 inverted channel 1/Analog input 0 - 13 PB0/ TIM1_CH1N/AIN0 14 PC4/ TIM1_CH4/ CLK_CCO/AIN2/[ TIM1_CH2] I/O X X X HS O3 X X Port C4 15 PC5/SPI_SCK [TIM5_CH1] I/O X X X HS O3 X X Port C5 26/112 I/O X X X HS O3 DS9884 Rev 9 X X - Timer 1 Analog channel 4 input 2 /configurabl [AFR2]Time e clock r 1 channel output 2 [AFR7] SPI clock Timer 5 channel 1 [AFR0] STM8AF6213/13A/23/23A/26 Pinout and pin description Table 7. STM8AF6213A and STM8AF6223A TSSOP20 pin description (continued) Output Pin name Type wpu Ext. interrupt High sink(1) Speed OD PP Alternate function after remap [option bit] floating Default alternate function TSSOP Input Main function (after reset) 16 PC6/ SPI_MOSI [TIM1_CH1] I/O X X X HS O3 X X Port C6 PI master out/slave in Timer 1 channel 1 [AFR0] 17 PC7/ SPI_MISO [TIM1_CH2] I/O X X X HS O3 X X Port C7 SPI master in/ slave out Timer 1 channel 2[AFR0] 18 PD1/ SWIM(4) I/O X X X HS O4 X X Port D1 SWIM data interface - Port D2 - Analog input 3 [AFR2] Timer 5 channel 3 [AFR1] Port D3 Analog input 4 Timer 52 channel 2/ADC external trigger - 19 20 PD2/AIN3/ TLI[TIM5_CH3] PD3/ AIN4/ TIM5_CH2/ ADC_ETR I/O I/O X X X X X X HS HS O3 O3 X X X X 1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings (see Section 10.2: Absolute maximum ratings). 2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application. 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). 4. The PD1 pin is in input pull-up during the reset phase and after internal reset release. DS9884 Rev 9 27/112 108 Pinout and pin description 5.2 STM8AF6213/13A/23/23A/26 LQFP32/VFQPN32 pinout and pin description PD7 (HS)/TLI [TIM1_CH4] PD6 (HS)/AIN6/LINUART_RX PD5 (HS)/AIN5/LINUART_TX PD4 (HS)/BEEP/TIM5_CH1[LINUART_CK] PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR PD2 (HS)[AIN3] [TIM5_CH3] PD1 (HS)/SWIM PD0 (HS)/ TIM1_BKIN [CLK_CCO] Figure 5. STM8AF6226 LQFP32/VFQPN32 pinout 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 1516 PC7 (HS)/SPI_MISO [TIM1_CH2] PC6 (HS)/SPI_MOSI [TIM1_CH1] PC5 (HS)/SPI_SCK [TIM5_CH1] PC4(HS)TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N] PC3(HS)/TIM1_CH3 [TLI] [TIM1_CH1N] PC2(HS)/TIM1_CH2 [TIM1_CH3N] PC1(HS)/TIM1_CH1/LINUART_CK[TIM1_CH2N] PE5/SPI_NSS [TIM1_CH1N] PB7 PB6 [TIM1_BKIN]I2C_SDA/(T)PB5 [ADC_ETR] IC_SCL/(T)PB4 TIM1_ETR/AIN3/(HS) PB3 TIM1_CH3N/AIN2/(HS)PB2 TIM1_CH2N/AIN1/(HS) PB1 TIM1_CH1N/AIN0/(HS) PB0 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD [LINUART_TX][SPI_NSS] TIM5_CH3/(HS) PA3 [LINUART_RX] PF4 MS38347V1 1. (HS) high sink capability. 2. (T) true open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 8. STM8AF6226 LQFP32/VFQPN32 pin description Output Pin name Type floating wpu Ext. interrupt High sink(1) Speed OD PP Alternate function after remap [option bit] LQFP32 VFQPN32 Input 1 NRST I/O - X - - - - - 2 PA1/ OSCIN(2) I/O X X X - O1 X X Port A1 Resonator/ crystal in - 3 PA2/ OSCOUT I/O X X X - O1 X X Port A2 Resonator/ crystal out - 28/112 DS9884 Rev 9 Main function (after reset) Default alternate function Reset - STM8AF6213/13A/23/23A/26 Pinout and pin description Table 8. STM8AF6226 LQFP32/VFQPN32 pin description (continued) Output Pin name Type floating wpu Ext. interrupt High sink(1) Speed OD PP Alternate function after remap [option bit] LQFP32 VFQPN32 Input 4 VSS S - - - - - - - Digital ground - 5 VCAP S - - - - - - - 1.8 V regulator capacitor - 6 VDD S - - - - - - - Digital power supply - 7 PA3/ TIM5_CH3 [SPI_NSS] [LINUART_TX] I/O X X X 8 PF4 [LINUART_RX] I/O X X - - 9 PB7 I/O X X X - 10 PB6 I/O X X X - 11 PB5/ I2C_SDA [TIM1_BKIN] I/O X - X - 12 PB4/ I2C_SCL [ADC_ETR] 13 PB3/ AIN3/TIM1_ET R 14 PB2/ AIN2/ TIM1_CH3N 15 PB1/ AIN1/ TIM1_CH2N 16 PB0/ AIN0/ TIM1_CH1N I/O I/O I/O I/O I/O X X X X X - X X X X X X X X X Default alternate function X X Port A3 Timer 52 channel 3 SPI master/ slave select [AFR1]/ LINUART data transmit [AFR1:0] O1 X X Port F4 LINUART data receive [AFR1:0] - O1 X X Port B7 - - X X Port B6 - - O1 T(3) - Port B5 I2C data Timer 1 break input [AFR4] O1 T(3) Port B4 I2C clock ADC external trigger [AFR4] Port B3 Analog input 3/ Timer 1 external trigger - Port B2 Analog input 2/ Timer 1 inverted channel 3 - Port B1 Analog input 1/ Timer 1 inverted channel 2 - Port B0 Analog input 0/ Timer 1 inverted channel 1 - HS O3 - Main function (after reset) O1 HS O3 HS O3 HS O3 HS O3 X X X X DS9884 Rev 9 - X X X X 29/112 108 Pinout and pin description STM8AF6213/13A/23/23A/26 Table 8. STM8AF6226 LQFP32/VFQPN32 pin description (continued) I/O X X X X X X X X HS O3 HS O3 HS O3 X X X PP OD Speed 19 PC2/ TIM1_CH2 [TIM1_CH3N] I/O X High sink(1) 18 PC1/ TIM1_CH1/ LINUART_CK [TIM1_CH2N] I/O Output Ext. interrupt 17 PE5/ SPI_NSS [TIM1_CH1N] Type wpu Pin name floating LQFP32 VFQPN32 Input X X X Main function (after reset) Default alternate function Alternate function after remap [option bit] Port E5 SPI master/ slave select Timer 1 inverted channel 1 [AFR1:0] Port C1 Timer 1 channel 1 LINUART clock Timer 1 inverted channel 2 [AFR1:0] Port C2 Timer 1 channel 2 Timer 1 inverted channel 3 [AFR1:0] Timer 1 channel 3 Top level interrupt [AFR3] Timer 1 inverted channel 1 [AFR7] 20 PC3/ TIM1_CH3/[TLI] [TIM1_CH1N] 21 PC4/ TIM1_CH4/ CLK_CCO/[AIN 2][TIM1_CH2N] I/O X X X HS O3 X X Port C4 22 PC5/SPI_SCK [TIM5_CH1] I/O X X X HS O3 X X Port C5 SPI clock Timer 5 channel 1 [AFR0] 23 PC6/ SPI_MOSI [TIM1_CH1] I/O X X X HS O3 X X Port C6 PI master out/slave in Timer 1 channel 1 [AFR0] 24 PC7/ SPI_MISO [TIM1_CH2] I/O X X X HS O3 X X Port C7 SPI master in/ slave out Timer 1 channel 2[AFR0] 25 PD0/ TIM1_BKIN [CLK_CCO] I/O X X X HS O3 X X Port D0 Timer 1 break input Configurable clock output [AFR5] 26 PD1/ SWIM(4) I/O X X X HS O4 X X Port D1 SWIM data interface - 30/112 I/O X X X HS O3 X DS9884 Rev 9 X Port C3 Analog input Timer 1 2 channel 4 [AFR2]Timer /configurable 1 inverted clock output channel 2 [AFR7] STM8AF6213/13A/23/23A/26 Pinout and pin description Table 8. STM8AF6226 LQFP32/VFQPN32 pin description (continued) 27 PD2/[AIN3] [TIM5_CH3] I/O X X X HS O3 X PP OD Speed High sink(1) Output Ext. interrupt Type wpu Pin name floating LQFP32 VFQPN32 Input X Default alternate function Alternate function after remap [option bit] Port D2 - Analog input 3 [AFR2] Timer 52 channel 3 [AFR1] Port D3 Analog input 4 Timer 52 channel 2/ADC external trigger - LINUART clock [AFR2] Main function (after reset) 28 PD3/ AIN4/ TIM5_CH2/ ADC_ETR 29 PD4/ TIM5_CH1/ BEEP [LINUART_CK] I/O X X X HS O3 X X Port D4 Timer 5 channel 1/BEEP output 30 PD5/ AIN5/ LINUART_TX I/O X X X HS O3 X X Port D5 Analog input 5/ LINUART data transmit - 31 PD6/ AIN6/ LINUART_RX I/O X X X HS O3 X X Port D6 Analog input 6/ LINUART data receive - 32 PD7/ TLI [TIM1_CH4] I/O X X X HS O3 X X Port D7 Top level interrupt Timer 1 channel 4 [AFR6] I/O X X X HS O3 X X 1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings (see Section 10.2: Absolute maximum ratings). 2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application. 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). 4. The PD1 pin is in input pull-up during the reset phase and after internal reset release. DS9884 Rev 9 31/112 108 Pinout and pin description 5.3 STM8AF6213/13A/23/23A/26 Alternate function remapping As shown in the rightmost column of Table 6, Table 7 and Table 8 some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes on page 46. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of STM8S series and STM8AF series 8-bit microcontrollers reference manual, RM0016). 32/112 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Memory and register map 6 Memory and register map 6.1 Memory map Figure 6. Memory map 0x00 0000 RAM (1 Kbyte) 0x00 03FF 0x00 0800 513 byte stack Reserved 0x00 3FFF 0x00 4000 0x00 427F 0x00 4280 0x00 47FF 0x00 4800 0x00 480A 0x00 480B 0x00 4864 0x00 4865 0x00 4870 0x00 4871 640 byte data EEPROM Reserved Option bytes Reserved Unique ID Reserved 0x00 4FFF 0x00 5000 GPIO and peripheral registers 0x00 57FF 0x00 5800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 0x00 9FFF 0x00 A000 CPU/SWIM/debug/ITC registers 32 interrupt vectors Flash program memory (8 Kbyte) Reserved 0x02 7FFF MS38348V1 DS9884 Rev 9 33/112 108 Memory and register map STM8AF6213/13A/23/23A/26 Table 9. Memory model for the devices covered in this datasheet Flash program memory size Flash program memory end address 8K 0x00 9FFF 4K 0x00 8FFF 6.2 Register map 6.2.1 I/O port hardware register map RAM size RAM end address Stack roll-over address 1K 0x00 03FF 0x00 0200 Table 10. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX(1) PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX(1) PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0xXX(1) PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX(1) PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 34/112 Block Port A Port B Port C Port D DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Memory and register map Table 10. I/O port hardware register map (continued) Register label Register name Reset status 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xXX(1) PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xXX(1) PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 Address 0x00 5016 0x00 501B Block Port E Port F 1. Depends on the external circuitry. Table 11. General hardware register map Address Block Register label 0x00 501E to 0x00 5069 Register name Reset status Reserved area (60 byte) 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF FLASH_FPR Flash protection register 0x00 0x00 505E FLASH_NFPR Flash complementary protection register 0xFF 0x00 505F FLASH_IAPSR Flash in-application programming status register 0x40 0x00 505D Flash 0x00 5060 to 0x00 5061 0x00 5062 Reserved area (2 byte) Flash Flash Program memory unprotection register FLASH_PUKR 0x00 5063 0x00 5064 Reserved area (1 byte) Flash FLASH_DUKR 0x00 5065 to 0x00 509F 0x00 50A0 0x00 50A1 0x00 50A2 to 0x00 50B2 0x00 Data EEPROM unprotection register 0x00 Reserved area (59 byte) ITC EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reserved area (17 byte) DS9884 Rev 9 35/112 108 Memory and register map STM8AF6213/13A/23/23A/26 Table 11. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 50B3 RST RST_SR Reset status register 0xXX(1) 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 Reserved area (12 byte) CLK CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX CLK_CKDIVR Clock divider register 0x18 CLK_PCKENR1 Peripheral clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50C6 0x00 50C7 CLK 0x00 50CB Reserved area (1 byte) 0x00 50CC 0x00 50CD CLK CLK_HSITRIMR HSI clock calibration trimming register 0x00 CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 0x00 50CE to 0x00 50D0 0x00 50D1 0x00 50D2 Reserved area (3 byte) WWDG WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F 0x00 50D3 to 0x00 50DF Reserved area (13 byte) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0xXX(2) IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 byte) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 50FF 36/112 BEEP AWU_CSR1 AWU control/status register 1 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F Reserved area (12 byte) DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Memory and register map Table 11. General hardware register map (continued) Register label Register name Reset status 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 SPI_SR SPI status register 0x02 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF Address 0x00 5203 0x00 5204 Block SPI 0x00 5208 to 0x00 520F Reserved area (8 byte) 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 0x00 5215 Reserved area (1 byte) 0x00 5216 I2C_DR I2C data register 0x00 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C clock control register low 0x00 0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 521E I2C_PECR I2C packet error checking register 0x00 0x00 5217 0x00 521F to 0x00 522F I2C Reserved area (17 byte) DS9884 Rev 9 37/112 108 Memory and register map STM8AF6213/13A/23/23A/26 Table 11. General hardware register map (continued) Register label Register name Reset status 0x00 5230 UART4_SR LINUART status register 0xC0 0x00 5231 UART4_DR LINUART data register 0xXX 0x00 5232 UART4_BRR1 LINUART baud rate register 1 0x00 0x00 5233 UART4_BRR2 LINUART baud rate register 2 0x00 0x00 5234 UART4_CR1 LINUART control register 1 0x00 UART4_CR2 LINUART control register 2 0x00 UART4_CR3 LINUART control register 3 0x00 UART4_CR4 LINUART control register 4 0x00 Address 0x00 5235 0x00 5236 0x00 5237 Block LINUART 0x00 5238 0x00 5239 UART4_CR6 LINUART control register 6 0x00 0x00 523A UART4_GTR LINUART guard time register 0x00 0x00 523B UART4_PSCR LINUART prescaler 0x00 0x00 523C to 0x00 523F 38/112 Reserved Reserved area (20 byte) DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Memory and register map Table 11. General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 Address 0x00 525F 0x00 5260 0x00 5270 to 0x00 52FF Block TIM1 Reserved area (147 byte) DS9884 Rev 9 39/112 108 Memory and register map STM8AF6213/13A/23/23A/26 Table 11. General hardware register map (continued) Register label Register name Reset status 0x00 5300 TIM5_CR1 TIM5 control register 1 0x00 0x00 5301 TIM5_CR2 TIM5 control register 2 0x00 0x00 5302 TIM5_SMCR TIM5 slave mode control register 0x00 0x00 5303 TIM5_IER TIM5 interrupt enable register 0x00 0x00 5304 TIM5_SR1 TIM5 status register 1 0x00 0x00 5305 TIM5_SR2 TIM5 status register 2 0x00 0x00 5306 TIM5_EGR TIM5 event generation register 0x00 0x00 5307 TIM5_CCMR1 TIM5 capture/compare mode register 1 0x00 0x00 5308 TIM5_CCMR2 TIM5 capture/compare mode register 2 0x00 0x00 5309 TIM5_CCMR3 TIM5 capture/compare mode register 3 0x00 0x00 530A TIM5_CCER1 TIM5 capture/compare enable register 1 0x00 TIM5_CCER2 TIM5 capture/compare enable register 2 0x00 00 530C0x TIM5_CNTRH TIM5 counter high 0x00 0x00 530D TIM5_CNTRL TIM5 counter low 0x00 0x00 530E TIM5_PSCR TIM5 prescaler register 0x00 0x00 530F TIM5_ARRH TIM5 auto-reload register high 0xFF 0x00 5310 TIM5_ARRL TIM5 auto-reload register low 0xFF 0x00 5311 TIM5_CCR1H TIM5 capture/compare register 1 high 0x00 0x00 5312 TIM5_CCR1L TIM5 capture/compare register 1 low 0x00 0x00 5313 TIM5_CCR2H TIM5 capture/compare reg. 2 high 0x00 0x00 5314 TIM5_CCR2L TIM5 capture/compare register 2 low 0x00 0x00 5315 TIM5_CCR3H TIM5 capture/compare register 3 high 0x00 0x00 5316 TIM5_CCR3L TIM5 capture/compare register 3 low 0x00 Address 0x00 530B Block TIM5 0x00 5317 to 0x00 533F 0x00 5340 TIM6_CR1 TIM6 control register 1 0x00 0x00 5341 TIM6_CR2 TIM6 control register 2 0x00 0x00 5342 TIM6_SMCR TIM6 slave mode control register 0x00 0x00 5343 TIM6_IER TIM6 interrupt enable register 0x00 TIM6_SR TIM6 status register 0x00 0x00 5345 TIM6_EGR TIM6 event generation register 0x00 0x00 5346 TIM6_CNTR TIM6 counter 0x00 0x00 5347 TIM6_PSCR TIM6 prescaler register 0x00 0x00 5348 TIM6_ARR TIM6 auto-reload register 0xFF 0x00 5344 40/112 Reserved area (43 byte) TIM6 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Memory and register map Table 11. General hardware register map (continued) Address Block Register label 0x00 5349 to 0x00 53DF 0x00 53E0 to 0x00 53F3 Register name Reset status Reserved area (153 byte) ADC1 ADC _DBxR 0x00 53F4 to 0x00 53FF ADC data buffer registers 0x00 Reserved area (12 byte) 0x00 5400 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 ADC_TDRL ADC Schmitt trigger disable register low 0x00 ADC _HTRH ADC high threshold register high 0xFF 0x00 5409 ADC_HTRL ADC high threshold register low 0x03 0x00 540A ADC _LTRH ADC low threshold register high 0x00 0x00 540B ADC_LTRL ADC low threshold register low 0x00 0x00 540C ADC _AWSRH ADC watchdog status register high 0x00 0x00 540D ADC_AWSRL ADC watchdog status register low 0x00 0x00 540E ADC _AWCRH ADC watchdog control register high 0x00 0x00 540F ADC _AWCRL ADC watchdog control register low 0x00 0x00 5407 0x00 5408 ADC1 0x00 5410 to 0x00 57FF Reserved area (1008 byte) 1. Depends on the previous reset source. 2. Write only register. DS9884 Rev 9 41/112 108 Memory and register map 6.2.2 STM8AF6213/13A/23/23A/26 CPU/SWIM/debug module/interrupt controller registers Table 12. CPU/SWIM/debug module/interrupt controller registers Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 (1) CPU 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 byte) CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF ITC_SPR4 Interrupt software priority register 4 0xFF ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F73 0x00 7F74 CPU ITC 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F 42/112 Reserved area (2 byte) SWIM SWIM_CSR SWIM control status register Reserved area (15 byte) DS9884 Rev 9 0x00 STM8AF6213/13A/23/23A/26 Memory and register map Table 12. CPU/SWIM/debug module/interrupt controller registers (continued) Register label Register name Reset status 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF Address 0x00 7F95 Block DM 0x00 7F9B to 0x00 7F9F Reserved area (5 byte) 1. Accessible by debug module only DS9884 Rev 9 43/112 108 Interrupt vector mapping 7 STM8AF6213/13A/23/23A/26 Interrupt vector mapping Table 13. Interrupt mapping Priority 44/112 Source block Description — Reset Reset — TRAP 0 Wakeup from halt mode Wakeup from Interrupt vector active-halt address mode Yes Yes 0x00 8000 Software interrupt - - 0x00 8004 TLI External top level interrupt - - 0x00 8008 1 AWU Auto-wakeup from Halt - Yes 0x00 800C 2 Clock controller Clock controller - - 0x00 8010 3 EXTI0 Port A external interrupts Yes(1) Yes(1) 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 EXTI5 Port F - - 0x00 8028 9 Reserved - - 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIM1 TIM1 update/overflow/ underflow/trigger/break - - 0x00 8034 12 TIM1 TIM1 capture/compare - - 0x00 8038 13 TIM5 TIM5 update/overflow/trigger - - 0x00 803C 14 TIM5 TIM5 capture/compare - - 0x00 8040 15 Reserved - - - 0x00 8044 16 Reserved - - - 0x00 8048 17 LINUART Tx complete - - 0x00 804C 18 LINUART Receive register DATA FULL - - 0x00 8050 19 I2C I2C interrupts Yes Yes 0x00 8054 20 Reserved - - - 0x00 8058 21 Reserved - - - 0x00 805C 22 ADC1 - - 0x00 8060 - ADC1 end of conversion/analog watchdog interrupt DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Interrupt vector mapping Table 13. Interrupt mapping (continued) Priority Source block Description Wakeup from halt mode Wakeup from Interrupt vector active-halt address mode 23 TIM6 TIM6 update/overflow/trigger - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 1. Except PA1. DS9884 Rev 9 45/112 108 Option bytes 8 STM8AF6213/13A/23/23A/26 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 14: Option bytes below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP and UBC options that can only be modified in ICP mode (via SWIM). Refer to the STM8 Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 14. Option bytes Addr. 0x00 4800 0x00 4801 0x00 4802 0x00 4803 0x00 4804 0x00 4805 0x00 4806 0x00 4807 0x00 4808 0x00 4809 0x00 480A 46/112 Option bits Factory default setting Option name Option byte no. Read-out protection (ROP) OPT0 ROP[7:0] 0x00 OPT1 UBC[7:0] 0x00 NOPT1 NUBC[7:0] 0xFF User boot code (UBC) Alternate function remapping (AFR) Miscell. option 7 6 5 4 3 1 0 OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00 NOPT2 NAFR7 NAFR6 NAFR 5 NAFR 4 NAFR 3 NAFR 2 NAFR 1 NAFR 0 0xFF OPT3 Reserved HSI TRIM LSI _EN IWDG _HW WWDG _HW WWDG _HALT 0x00 NOPT3 Reserved NHSI TRIM NLSI _EN NIWDG _HW NWWDG _HW NWWG _HALT 0xFF OPT4 Reserved EXT CLK CKAWU SEL PRS C1 PRS C0 0x00 NOPT4 Reserved NEXT CLK NCKAWU SEL NPRS C1 NPRS C0 0xFF Clock option HSE clock startup 2 OPT5 HSECNT[7:0] 0x00 NOPT5 NHSECNT[7:0] 0xFF DS9884 Rev 9 STM8AF6213/13A/23/23A/26 8.1 Option bytes Option byte description Table 15. Option byte description Option byte no. Description OPT0 ROP[7:0]: Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0]: User boot code area 0x00: No UBC, no write-protection 0x01: Page 0 defined as UBC, memory write-protected 0x02: Page 0 to 1 defined as UBC, memory write-protected Pages 0 and 1 contain the interrupt vectors. ... 0x7F: Pages 0 to 126 defined as UBC, memory write-protected Other values: Page 0 to 127 defined as UBC, memory write-protected. Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM write protection for more details. OPT2 AFR[7:0] Refer to the following sections for the alternate function remapping descriptions of bits [7:2] and [1:0] respectively. HSITRIM: high-speed internal clock trimming register size 0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register LSI_EN: low-speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source OPT3 IWDG_HW: Independent watchdog 0: IWDG independent watchdog activated by software 1: IWDG independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on Halt 0: No reset generated on Halt if WWDG active 1: Reset generated on Halt if WWDG active DS9884 Rev 9 47/112 108 Option bytes STM8AF6213/13A/23/23A/26 Table 15. Option byte description (continued) Option byte no. Description EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN OPT4 CKAWUSEL: Auto-wakeup unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for AWU PRSC[1:0]: AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 8.2 HSECNT[7:0]: HSE crystal oscillator stabilization time 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles STM8AF6213/13A/23/23A/26 alternate function remapping bits Table 16. STM8AF6226 alternate function remapping bits [7:2] for 32-pin packages Description(1) Option byte number OPT2 AFR7: Alternate function remapping option 7 0: AFR7 remapping option inactive: default alternate function (2) 1: Port C3 alternate function = = TIM1_CH1N; port C4 alternate function = TIM1_CH2N AFR6: Alternate function remapping option 6 0: AFR6 remapping option inactive: default alternate function (2) 1: Port D7 alternate function = TIM1_CH4. AFR5: Alternate function remapping option 5 0: AFR5 remapping option inactive: default alternate function (2). 1: Port D0 alternate function = CLK_CCO. AFR4: Alternate function remapping option 4 0: AFR4 remapping option inactive: default alternate function (2). 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN. AFR3: Alternate function remapping option 3 0: AFR3 remapping option inactive: default alternate function (2) 1: Port C3 alternate function = TLI AFR2: Alternate function remapping option 2 0: AFR2 remapping option inactive: default alternate function (2) 1: Port C4 alternate function = AIN2; port D2 alternate function = AIN3; port D4 alternate function = LINUART_CK 1. Do not use more than one remapping option in the same port. 2. Refer to the pin description. 48/112 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Option bytes Table 17. STM8AF6213 and STM8AF6223 alternate function remapping bits [7:2] for 20-pin packages Description(1) Option byte number OPT2 AFR7: Alternate function remapping option 7 0: AFR7 remapping option inactive: default alternate function (2) 1: Port C3 alternate function = = TIM1_CH1N; port C4 alternate function = TIM1_CH2N AFR6: Alternate function remapping option 6 Reserved AFR5: Alternate function remapping option 5 Reserved AFR4: Alternate function remapping option 4 0: AFR4 remapping option inactive: default alternate function (2). 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN. AFR3: Alternate function remapping option 3 0: AFR3 remapping option inactive: default alternate function (2) 1: Port C3 alternate function = TLI AFR2: Alternate function remapping option 2 0: AFR2 remapping option inactive: default alternate function (2) 1: Port D4 alternate function = LINUART_CK 1. Do not use more than one remapping option in the same port. 2. Refer to the pin description. Table 18. STM8AF6213A and STM8AF6223A alternate function remapping bits [7:2] for 20-pin packages Description(1) Option byte number OPT2 AFR7: Alternate function remapping option 7 0: AFR7 remapping option inactive: default alternate function (2) 1: Port C4 alternate function = TIM1_CH2N AFR6: Alternate function remapping option 6 Reserved AFR5: Alternate function remapping option 5 Reserved AFR4: Alternate function remapping option 4 0: AFR4 remapping option inactive: default alternate function (2). 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN. AFR3: Alternate function remapping option 3 Reserved. AFR2: Alternate function remapping option 2 0: AFR2 remapping option inactive: default alternate function (2) 1: Port D4 alternate function = LINUART_CK 1. Do not use more than one remapping option in the same port. 2. Refer to the pin description. DS9884 Rev 9 49/112 108 Option bytes STM8AF6213/13A/23/23A/26 Table 19. STM8AF6226 alternate function remapping bits [1:0] for 32-pin packages AFR1 option bit value AFR0 option bit value 0 0 0 1 1 1 0 (2) 1(2) I/O port Alternate function mapping AFR1 and AFR0 remapping options inactive: Default alternate functions(1) PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PA3 SPI_NSS PD2 TIM5_CH3 PD2 TIM5_CH3 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PC2 TIM1_CH3N PC1 TIM1_CH2N PE5 TIM1_CH1N PA3 LINUART_TX PF4 LINUART_RX 1. Refer to the pin descriptions. 2. If both AFR1 and AFR0 option bits are set, the SPI hardware NSS management feature is no more available. If this remapping option is selected and the SPI is enabled, the SSM bit must be configured in the SPI_CR2 register to select software NSS management. Table 20. STM8AF6213/STM8AF6223 alternate function remapping bits [1:0] for 20-pin packages AFR1 option bit value AFR0 option bit value 0 0 0 1 50/112 1 0 DS9884 Rev 9 I/O port Alternate function mapping AFR1 and AFR0 remapping options inactive: Default alternate functions(1) PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PA3 SPI_NSS PD2 TIM5_CH3 STM8AF6213/13A/23/23A/26 Option bytes Table 20. STM8AF6213/STM8AF6223 alternate function remapping bits [1:0] for 20-pin packages (continued) AFR1 option bit value AFR0 option bit value 1 1 I/O port Alternate function mapping PD2 TIM5_CH3 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PC2 Not available PC1 Not available PE5 Not available PA3 SPI_NSS PF4 Not available 1. Refer to the pin descriptions. Table 21. STM8AF6223A alternate function remapping bits [1:0] for 20-pin packages AFR1 option bit value AFR0 option bit value 0 0 0 1 1 1(2) 0 (2) 1 I/O port Alternate function mapping AFR1 and AFR0 remapping options inactive: Default alternate functions(1) PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PA3 Not available PD2 TIM5_CH3 PD2 TIM5_CH3 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PC2 Not available PC1 Not available PE5 Not available PA3 Not available PF4 Not available 1. Refer to the pin descriptions. 2. If both AFR1 and AFR0 option bits are set, the SPI hardware NSS management feature is no more available. If this remapping option is selected and the SPI is enabled, the SSM bit must be configured in the SPI_CR2 register to select software NSS management. DS9884 Rev 9 51/112 108 Unique ID 9 STM8AF6213/13A/23/23A/26 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single byte and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: • For use as serial numbers • For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory. • To activate secure boot processes. Table 22. Unique ID bit description Address 0x4865 0x4866 0x4867 Unique ID bits 7 6 5 4 3 U_ID[7:0] X coordinate on the wafer U_ID[15:8] U_ID[23:16] 0x4868 Y coordinate on the wafer 0x4869 Wafer number U_ID[39:32] U_ID[31:24] 0x486A U_ID[47:40] 0x486B U_ID[55:48] 0x486C U_ID[63:56] 0x486D 52/112 Content description Lot number U_ID[71:64] 0x486E U_ID[79:72] 0x486F U_ID[87:80] 0x4870 U_ID[95:88] DS9884 Rev 9 2 1 0 STM8AF6213/13A/23/23A/26 Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = -40 °C, TA = 25 °C, and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5.0 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range. 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7. Figure 7. Pin loading conditions STM8 PIN 50 pF MSv37796V1 DS9884 Rev 9 53/112 108 Electrical characteristics 10.1.5 STM8AF6213/13A/23/23A/26 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8. Figure 8. Pin input voltage STM8 PIN VIN MSv37797V1 10.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 23: Voltage characteristics, Table 24: Current characteristics and Table 25: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device’s reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 23. Voltage characteristics Symbol Min Max Unit -0.3 6.5 V VSS - 0.3 6.5 VSS - 0.3 VDD + 0.3 |VDDx - VDD| Variations between different power pins - 50 |VSSx - VSS| Variations between all the different ground pins - 50 VESD Electrostatic discharge voltage VDDx - VSS VIN Ratings Supply voltage (including VDDA and VDDIO )(1) Input voltage on true open drain pins (2) Input voltage on any other pin(2) V mV see Absolute maximum ratings (electrical sensitivity) on page 90 1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected 54/112 DS9884 Rev 9 STM8AF6213/13A/23/23A/26 Electrical characteristics Table 24. Current characteristics Symbol Max.(1) Ratings IVDD Total current into VDD power lines (source)(2) 100 IVSS Total current out of VSS ground lines (sink)(2) 80 Output current sunk by any I/O and control pin 20 Output current source by any I/Os and control pin -20 Injected current on RST pin ±4 IIO IINJ(PIN)(3) (4) Injected current on OSCIN pin mA ±4 (5) Injected current on any other pin ∑IINJ(TOT)(3) Unit Total injected current (sum of all I/O and control ±4 pins)(5) ±20 1. Guaranteed by characterization results. 2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN