STM8L001J3M3TR

STM8L001J3 8-bit ultra-low-power microcontroller with up to 8-Kbyte Flash memory, multifunction timers, comparators, UART, SPI, I2C Datasheet - production data Features • Main microcontroller features – Supply voltage range 1.8 V to 3.6 V – Low power consumption (Halt: 0.3 µA, Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz) – STM8 Core with up to 16 CISC MIPS throughput – Temp. range: -40 to 125 °C SO8N 4.9x6 mm or 150 mils body width • Memories – 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM – Error correction code (ECC) – Flexible write and read protection modes – In-application and in-circuit programming – Data EEPROM capability – 1.5 Kbytes of static RAM • Clock management – Internal 16 MHz RC with fast wakeup time (typ. 4 µs) – Internal low consumption 38 kHz RC driving both the IWDG and the AWU • Reset and supply management – Ultra-low power POR/PDR – Three low-power modes: Wait, Active-halt, Halt • Peripherals – Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 1 channel (used as IC, OC, PWM) – One 8-bit timer (TIM4) with 7-bit prescaler – Infrared remote control (IR) – Independent watchdog – Auto-wakeup unit – Beeper timer with 1, 2 or 4 kHz frequencies – SPI synchronous serial interface – Fast I2C Multimaster/slave 400 kHz – UART with fractional baud rate generator – 2 comparators with 1 input each • Development support – Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging • Interrupt management – Nested interrupt controller with software priority control – Up to 6 external interrupt sources • I/Os – Up to 6 I/Os, all mappable on external interrupt vectors – I/Os with programmable input pull-ups, high sink/source capability and one LED driver infrared output September 2020 This is information on a product in full production. DS12153 Rev 4 1/58 www.st.com STM8L001J3 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . . 9 3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.7 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.8 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.9 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.10 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.11 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.13 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.14 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.15 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.16 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.17 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 2/58 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DS12153 Rev 4 STM8L001J3 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.4 9 8.1.4 8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3.2 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 34 8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3.7 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.8 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DS12153 Rev 4 3/58 3 List of tables STM8L001J3 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. 4/58 STM8L001J3 device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM8L001J3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Total current consumption and timing in Halt and Active-halt mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output driving current (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 43 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DS12153 Rev 4 STM8L001J3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. STM8L001J3 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STM8L001J3 SO8N pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IDD(RUN) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 IDD(WAIT) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 IDD(WAIT) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical LSI RC frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical VIL and VIH vs. VDD (High sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical pull-up current IPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. VOL at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typ. VOL at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typ. VOL at VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typ. VOL at VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typ. VDD - VOH at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typ. VDD - VOH at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical application with I2C bus and timing diagram (1). . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 53 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Example of SO8N marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 DS12153 Rev 4 5/58 5 Introduction 1 STM8L001J3 Introduction This datasheet provides the STM8L001J3 pinout, ordering information, mechanical and electrical device characteristics. For complete information on the STM8L001J3 microcontroller memory, registers and peripherals, please refer to the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013). The STM8L001J3 devices are members of the STM8L low-power 8-bit family. They are referred to as low-density devices in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) and in the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054). All devices of the SM8L Series provide the following benefits: • Reduced system cost – • – High system integration level with internal clock oscillators and watchdogs. – Smaller battery and cheaper power supplies. Low power consumption and advanced features – • • 6/58 8 Kbytes of low-density embedded Flash program memory including up to 2 Kbytes of data EEPROM Up to 16 MIPS at 16 MHz CPU clock frequency – Less than 150 µA/MHz, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode – Clock gated system and optimized power management Short development cycles – Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. – Full documentation and a wide choice of development tools Product longevity – Advanced core and peripherals made in a state-of-the art technology – Product family operating from 1.8 V to 3.6 V supply. DS12153 Rev 4 STM8L001J3 2 Description Description The STM8L001J3 low-power microcontroller features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultra fast Flash programming. All STM8L001J3 microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM. The STM8L001J3 low power microcontroller is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout. Table 1. STM8L001J3 device feature summary Features STM8L001J3 Flash 8 Kbytes of Flash program memory including up to 2 Kbytes of Data EEPROM RAM 1.5 Kbytes Peripheral functions Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep, Serial peripheral interface (SPI), Inter-integrated circuit (I2C), Universal synchronous / asynchronous receiver / transmitter (USART), 2 comparators, Infrared (IR) interface Timers Two 16-bit timers, one 8-bit timer Operating voltage 1.8 to 3.6 V Operating temperature -40 to +125 °C Packages SO8N DS12153 Rev 4 7/58 16 Product overview 3 STM8L001J3 Product overview Figure 1. STM8L001J3 device block diagram @ VDD 16 MHz int RC 38 kHz int RC VDD18 Clock controller Clocks to core and peripherals POR/PDR Up to 8 Kbytes Flash memory (including up to 2 Kbytes data EEPROM) Nested interrupt controller up to 6 external interrupts Infrared interface PA Port A PB Port B PC Port C PD Port D COMP1_CH3 1.5 Kbytes SRAM Address and data bus IR_TIM Debug module (SWIM) USART I²C1 multimaster SPI RX, TX SDA, SCL MOSI, MISO, SCK 16-bit Timer 2 IR_TIM 16-bit Timer 3 TIM3_CH2 8-bit Timer 4 COMP1 IWDG COMP2 Beeper COMP_REF COMP2_CH2 VDD = 1.8V to 3.6V VSS Reset STM8 Core up to 16 MHz SWIM Power Volt. reg. AWU BEEP MS32610V1 Legend: AWU: Auto-wakeup unit Int. RC: internal RC oscillator I2C: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous / asynchronous receiver / transmitter IWDG: Independent watchdog 8/58 DS12153 Rev 4 STM8L001J3 3.1 Product overview Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions. 3.2 Development tools Development tools for the STM8 microcontrollers include: • The STVD high-level language debugger including C compiler, assembler and integrated development environment • The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 3.3 Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. Recommendations for SWIM pin (pin#1) As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever. This initial delay can be removed in the final (locked) code. If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for the device debug/programming. 3.4 Interrupt controller The STM8L001J3 features a nested vectored interrupt controller: • Nested interrupts with 3 software priority levels • 26 interrupt vectors with hardware priority • Up to 6 external interrupt sources on 6 vectors • Trap and reset interrupts. DS12153 Rev 4 9/58 16 Product overview 3.5 STM8L001J3 Memory The STM8L001J3 devices have the following main features: • 1.5 Kbytes of RAM • The EEPROM is divided into two memory arrays (see the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for details on the memory mapping): – 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS). – 64 option bytes (one block) of which 5 bytes are already used for the device. Error correction code is implemented on the EEPROM. Recommendation for the device's programming: The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space). If the device's program memory is empty (0x00 content), it displays the behavior described below: • After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG (0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF). It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz HSI clock. • Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed. The reading of non-existing memory is a random content which can lead to the execution of invalid instructions. The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more. Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device. The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts). Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop. 10/58 DS12153 Rev 4 STM8L001J3 3.6 Product overview Low power modes To minimize power consumption, the product features three low power modes: 3.7 • Wait mode: CPU clock stopped, selected peripherals at full clock speed. • Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit. • Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The RAM content is preserved. Wakeup is triggered by an external interrupt. Voltage regulators The STM8L001J3 embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. 3.8 Clock control The STM8L001J3 embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler. In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU). 3.9 Independent watchdog The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. 3.10 Auto-wakeup counter The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode. 3.11 General purpose and basic timers STM8L001J3 devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). DS12153 Rev 4 11/58 16 Product overview STM8L001J3 16-bit general purpose timers The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including: • Time base generation • Measuring the pulse lengths of input signals (input capture) • Generating output waveforms (output compare, PWM and One pulse mode) • Interrupt capability on various events (capture, compare, overflow, break, trigger) 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow. 3.12 Beeper The STM8L001J3 devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz. 3.13 Infrared (IR) interface The STM8L001J3 devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.14 Comparators The STM8L001J3 features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage). Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted. 3.15 USART The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. 3.16 SPI The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration. 12/58 DS12153 Rev 4 STM8L001J3 3.17 Product overview I2C The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between the microcontroller and the serial I2Cbus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes. DS12153 Rev 4 13/58 16 Pin description 4 STM8L001J3 Pin description Figure 2. STM8L001J3 SO8N pinout PA0/SWIM/BEEP/IR_TIM/ PC3/USART_TX/ PC4/USART_CK/CCO 1 8 PC1/I2C_SCL/ PC2/USART_RX PA2/ PA4/TIM2_BKIN/ PA6/COMP_REF 2 7 PB7/SPI_MISO/ PC0/I2C_SDA VSS 3 6 PB6/SPI_MOSI VDD 4 5 STM8L PB3/TIM2_ETR/COMP2_CH2/ PB5/SPI_SCK/ PD0/TIM3_CH2/COMP1_CH3 MSv46315V1 Table 2. Legend/abbreviation for table 4 Type Level I= input, O = output, S = power supply Input CM = CMOS Output HS = high sink/source (20 mA) Port and control Input configuration Output Reset state 14/58 float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state). DS12153 Rev 4 STM8L001J3 Pin description Table 3. STM8L001J3 pin description 2 High sink / source Ext. interrupt C I/O X(1) X X PC4/USART_CK/ CCO I/O (1) X X HS X PA2 I/O X X X HS PA4/TIM2_BKIN I/O X X X PA6/COMP_REF I/O X X PA0(1)/SWIM/BEEP/ IR_TIM(2) I/O PC3/USART_TX X OD WPU X X(1) SO8N 1 Output Floating Pin name Type Input PP Pin number Main function Alternate function (after reset) (2) X X Port A0 SWIM input and output / Beep output/ Timer infrared output HS X X Port C3 USART transmit X Port C4 USART synchronous clock / Configurable clock output X X Port A2 - HS X X Port A4 Timer 2 - break input X HS X X Port A6 Comparator external reference HS 3 VSS S - - - - - - - Ground 4 VDD S - - - - - - - Power supply PD0/TIM3_CH2/ COMP1_CH3 I/O X X X HS X X Port D0 Timer 3 - Channel 2 / Comparator 1 Channel 3 PB3/TIM2_ETR/ COMP2_CH2 I/O X X X HS X X Port B3 Timer 2 - trigger / Comparator 2 Channel 2 PB5/SPI_SCK I/O X X X HS X X Port B5 SPI clock PB6/SPI_MOSI I/O X X X HS X X Port B6 SPI master out / slave in PB7/SPI_MISO I/O X X X HS X X Port B7 SPI master in / slave out PC0/I2C_SDA I/O X - X - T(3) - Port C0 I2C data - Port C1 I2C clock X Port C2 USART receive 5 6 7 8 PC1/I2C_SCL I/O X - X - T(3) PC2/USART_RX I/O X X X HS X DS12153 Rev 4 15/58 16 Pin description STM8L001J3 1. The PA0 pin is in input pull-up during the reset phase and after internal reset release. This PA0 default state influences all the GPIOs connected in parallel on pin number 1 (PC3, PC4). 2. High sink LED driver capability available on PA0. 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented). Although PC0/PC1 itself is a true open drain GPIO with its respective internal circuitry and characteristics, VIN maximum of the pin number 7 and pin number 8 is limited by the standard GPIO (PB7 or PC2) which is also bonded to the same pin number. Slope control of all GPIO pins can be programmed except true open drain pins which by default is limited to 2 MHz. Note: The PA1, PA3, PA5, PB0, PB1, PB2, PB4, PC5, PC6, PD1, PD2, PD3, PD4, PD5, PD6 and PD7 GPIOs should be configured after device reset, by user software into the in output push-pull mode with output-low state to reduce device consumption and to improve EMC immunity. Those GPIOs are not connected to pins and after device reset are in input floating mode. To configure PA1 pin in output push-pull mode refer to Section “Configuring NRST/PA1 pin as general purpose output” in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013). Note: As several pins provide a connection to multiple GPIOs, the mode selection for any of those GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PA0 is also seen on PC3 and PC4. Push-pull configuration of PA2 is also seen on PA4 and PA6, etc. 16/58 DS12153 Rev 4 STM8L001J3 5 Memory and register map Memory and register map Figure 3. Memory map 0x00 0000 0x00 05FF 0x00 0600 RAM (1.5 Kbytes) (1) including Stack (up to 513 bytes) (1) Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 48FF 0x 004900 0x 004924 0x 004925 0x 004930 0x 004931 0x00 49FF 0x00 5000 0x00 57FF 0x00 5800 Reserved Unique ID Reserved GPIO and peripheral registers(2) Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 CPU/SWIM/Debug/ITC Registers Interrupt vectors Low-density Flash program memory (up to 8 Kbytes) (1) including Data EEPROM (up to 2 Kbytes) 0x00 9FFF MS32621V1 1. Table 4 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 6 for an overview of hardware register mapping, to Table 5 for details on I/O port hardware registers, and to Table 7 for information on CPU/SWIM/debug module controller registers. DS12153 Rev 4 17/58 27 Memory and register map STM8L001J3 Table 4. Flash and RAM boundary addresses Memory area Size Start address End address RAM 1.5 Kbytes 0x00 0000 0x00 05FF Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF Table 5. I/O Port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xxx PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xxx PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xxx PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xxx PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x00 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 18/58 Block Port A Port B Port C Port D DS12153 Rev 4 STM8L001J3 Memory and register map Table 6. General hardware register map Register label Register name Reset status 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 FLASH _PUKR Flash Program memory unprotection register 0x00 0x00 5053 FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5054 FLASH _IAPSR Flash in-application programming status register 0xX0 Address 0x00 5052 Block Flash 0x00 5055 to 0x00 509F Reserved area (75 bytes) 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 EXTI_CR3 External interrupt control register 3 0x00 EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF External interrupt port select register 0x00 WFE_CR1 WFE control register 1 0x00 WFE_CR2 WFE control register 2 0x00 0x00 50A2 0x00 50A3 0x00 50A6 0x00 50A7 ITC-EXTI WFE 0x00 50A8 to 0x00 50AF 0x00 50B0 0x00 50B1 Reserved area (8 bytes) RST RST_CR Reset control register 0x00 RST_SR Reset status register 0x01 0x00 50B2 to 0x00 50BF Reserved area (14 bytes) 0x00 50C0 0x00 50C1 to 0x00 50C2 0x00 50C3 CLK_CKDIVR Clock divider register Reserved area (2 bytes) CLK CLK_PCKENR Peripheral clock gating register 0x00 50C4 0x00 50C5 0x00 50C6 to 0x00 50DF 0x03 0x00 Reserved (1 byte) CLK_CCOR Configurable clock control register 0x00 Reserved area (25 bytes) DS12153 Rev 4 19/58 27 Memory and register map STM8L001J3 Table 6. General hardware register map (continued) Address Block 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 Register label Register name Reset status IWDG_KR IWDG key register 0xXX IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 BEEP AWU_CSR AWU control/status register 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F 0x00 50F4 to 0x00 51FF Reserved area (268 bytes) 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 SPI_DR SPI data register 0x00 0x00 5202 SPI 0x00 5205 to 0x00 520F Reserved area (11 bytes) 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 0x00 5215 0x00 5216 I2C_DR I2C data register 0x00 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C Clock control register low 0x00 0x00 521C I2C_CCRH I2C Clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 5217 20/58 Reserved area (1 byte) I2C DS12153 Rev 4 STM8L001J3 Memory and register map Table 6. General hardware register map (continued) Address Block Register label 0x00 521E to 0x00 522F Register name Reset status Reserved area (18 bytes) 0x00 5230 USART_SR USART status register 0xC0 0x00 5231 USART_DR USART data register 0xXX 0x00 5232 USART_BRR1 USART baud rate register 1 0x00 USART_BRR2 USART baud rate register 2 0x00 USART_CR1 USART control register 1 0x00 0x00 5235 USART_CR2 USART control register 2 0x00 0x00 5236 USART_CR3 USART control register 3 0x00 0x00 5237 USART_CR4 USART control register 4 0x00 0x00 5233 0x00 5234 0x00 5238 to 0x00 524F USART Reserved area (18 bytes) DS12153 Rev 4 21/58 27 Memory and register map STM8L001J3 Table 6. General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM2_CR1 TIM2 control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 slave mode control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5255 TIM2_SR1 TIM2 status register 1 0x00 0x00 5256 TIM2_SR2 TIM2 status register 2 0x00 0x00 5257 TIM2_EGR TIM2 event generation register 0x00 0x00 5258 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5259 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 TIM2_CNTRH TIM2 counter high 0x00 0x00 525C TIM2_CNTRL TIM2 counter low 0x00 0x00 525D TIM2_PSCR TIM2 prescaler register 0x00 0x00 525E TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 525F TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5260 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5261 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5262 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00 0x00 5263 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5264 TIM2_BKR TIM2 break register 0x00 0x00 5265 TIM2_OISR TIM2 output idle state register 0x00 Address 0x00 525A 0x00 525B 0x00 5266 to 0x00 527F 22/58 Block TIM2 Reserved area (26 bytes) DS12153 Rev 4 STM8L001J3 Memory and register map Table 6. General hardware register map (continued) Register label Register name Reset status 0x00 5280 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5285 TIM3_SR1 TIM3 status register 1 0x00 0x00 5286 TIM3_SR2 TIM3 status register 2 0x00 0x00 5287 TIM3_EGR TIM3 event generation register 0x00 0x00 5288 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5289 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00 TIM3_CNTRH TIM3 counter high 0x00 0x00 528C TIM3_CNTRL TIM3 counter low 0x00 0x00 528D TIM3_PSCR TIM3 prescaler register 0x00 0x00 528E TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 528F TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 5290 TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 0x00 5291 TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 5292 TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5293 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 0x00 5294 TIM3_BKR TIM3 break register 0x00 0x00 5295 TIM3_OISR TIM3 output idle state register 0x00 Address 0x00 528A 0x00 528B Block TIM3 0x00 5296 to 0x00 52DF Reserved area (74 bytes) 0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4_IER TIM4 interrupt enable register 0x00 TIM4_SR1 TIM4 Status register 1 0x00 0x00 52E5 TIM4_EGR TIM4 event generation register 0x00 0x00 52E6 TIM4_CNTR TIM4 counter 0x00 0x00 52E7 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E8 TIM4_ARR TIM4 auto-reload register low 0xFF 0x00 52E4 TIM4 DS12153 Rev 4 23/58 27 Memory and register map STM8L001J3 Table 6. General hardware register map (continued) Address Block Register label 0x00 52E9 to 0x00 52FE Register name Reset status Reserved area (23 bytes) 0x00 52FF IRTIM 0x00 5300 0x00 5301 COMP 0x00 5302 IR_CR Infra-red control register 0x00 COMP_CR Comparator control register 0x00 COMP_CSR Comparator status register 0x00 COMP_CCS Comparator channel selection register 0x00 Table 7. CPU/SWIM/debug module/interrupt controller registers Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x80 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x05 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CC Condition code register 0x28 Address 0x00 7F05 Block CPU 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 bytes) CFG CFG_GCR 0x00 7F61 0x00 7F6F 0x00 Reserved area (15 bytes) 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF ITC_SPR4 Interrupt Software priority register 4 0xFF ITC_SPR5 Interrupt Software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF 0x00 7F73 0x00 7F74 24/58 Global configuration register ITC-SPR (1) DS12153 Rev 4 STM8L001J3 Memory and register map Table 7. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register label 0x00 7F78 to 0x00 7F79 0x00 7F80 Register name Reset status Reserved area (2 bytes) SWIM SWIM_CSR 0x00 7F81 to 0x00 7F8F SWIM control status register 0x00 Reserved area (15 bytes) 0x00 7F90 DM_BK1RE Breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH Breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL Breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE Breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH Breakpoint 2 register high byte 0xFF DM_BK2RL Breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 Debug module control register 1 0x00 0x00 7F97 DM_CR2 Debug module control register 2 0x00 0x00 7F98 DM_CSR1 Debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 Debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR Enable function register 0xFF 0x00 7F95 DM 1. Refer to Table 6: General hardware register map on page 19 (addresses 0x00 50A0 to 0x00 50A5) for a list of external interrupt registers. DS12153 Rev 4 25/58 27 Interrupt vector mapping 6 STM8L001J3 Interrupt vector mapping Table 8. Interrupt mapping IRQ No. Source block - RESET - TRAP 0 - 1 FLASH 2-3 - 4 AWU 5 - 6 EXTIB 7 Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode) Yes Yes Yes Yes 0x00 8000 Software interrupt - - - - 0x00 8004 Reserved - - - - Description Reset address 0x00 8008 (1) 0x00 800C EOP/WR_PG_DIS - - Yes Reserved - - - - 0x00 8010 -0x00 8017 Auto wakeup from Halt - Yes Yes Yes(1) 0x00 8018 Reserved - - - - 0x00 801C External interrupt port B Yes Yes Yes Yes 0x00 8020 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024 8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044 16 - Reserved - - - - 0x00 8048 17 - Reserved - - - - 0x00 804C -0x00 804F 18 COMP Comparators - - Yes Yes(1) 0x00 8050 19 TIM2 Update /Overflow/Trigger/Break - - Yes Yes 0x00 8054 20 TIM2 Capture/Compare - - Yes Yes 0x00 8058 Yes Yes(1) 0x00 805C (1) 0x00 8060 21 TIM3 22 TIM3 2324 - 25 TIM4 26 26/58 SPI Update /Overflow/Break - - Yes Vector Capture/Compare - - Yes Reserved - - - - 0x00 80640x00 806B Update /Trigger - - Yes Yes(1) 0x00 806C Yes Yes(1) 0x00 8070 End of Transfer Yes Yes DS12153 Rev 4 Yes STM8L001J3 Interrupt vector mapping Table 8. Interrupt mapping (continued) IRQ No. Source block 27 USART 28 USART 29 I2C Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode) Transmission complete/transmit data register empty - - Yes Yes(1) 0x00 8074 Receive Register DATA FULL/overrun/idle line detected/parity error - - Yes Yes(1) 0x00 8078 Yes Yes Yes Yes(1) 0x00 807C Description I2C interrupt(2) Vector address 1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Refer to Section Wait for event (WFE) mode in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013). 2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. DS12153 Rev 4 27/58 27 Option bytes 7 STM8L001J3 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory. All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Table 9 for details on option byte addresses. Refer to the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054) and the STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 9. Option bytes Addr. Option name Option byte No. Option bits 7 6 5 4 3 2 1 0 Factory default setting 0x4800 Read-out protection (ROP) OPT1 ROP[7:0] 0x00 0x4807 - - Reserved 0x00 0x4802 UBC (User Boot code size) OPT2 UBC[7:0] 0x00 0x4803 DATASIZE OPT3 DATASIZE[7:0] 0x00 0x4808 Independent watchdog option OPT4 [1:0] Reserved IWDG _HALT IWDG _HW 0x00 Table 10. Option byte description 28/58 OPT1 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Refer to Read-out protection section in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for details. OPT2 UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01-0x02: UBC contains only the interrupt vectors. 0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected ... 0x7F - Page 0 to 126 reserved for UBC, memory is write protected Refer to User boot area (UBC) section in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for more details. UBC[7] is forced to 0 internally by HW. DS12153 Rev 4 STM8L001J3 Option bytes Table 10. Option byte description (continued) OPT3 OPT4 Caution: DATASIZE[7:0] Size of the data EEPROM area 0x00: no data EEPROM area 0x01: 1 page reserved for data storage from 0x9FC0 to 0x9FFF 0x02: 2 pages reserved for data storage from 0x9F80 to 0x9FFF ... 0x20: 32 pages reserved for data storage from 0x9800 to 0x9FFF Refer to Data EEPROM (DATA) section in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for more details. DATASIZE[7:6] are forced to 0 internal by HW. IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware IWDG_HALT: Independent window watchdog reset on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode After a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. DS12153 Rev 4 29/58 29 Electrical parameters STM8L001J3 8 Electrical parameters 8.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 8.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3∑). 8.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given only as design guidelines and are not tested. 8.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 8.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 4. Figure 4. Pin loading conditions STM8L PIN 50 pF MS32617V1 30/58 DS12153 Rev 4 STM8L001J3 8.1.5 Electrical parameters Pin input voltage The input voltage measurement on a pin of the device is described in Figure 5. Figure 5. Pin input voltage STM8L PIN VIN MS32618V1 8.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile is compliant with the JEDEC JESD47 qualification standard; extended mission profiles are available on demand. Table 11. Voltage characteristics Symbol VDD- VSS VIN VESD Ratings External supply voltage Input voltage on any pin (1) Electrostatic discharge voltage Min Max -0.3 4.0 VSS-0.3 VDD+0.3 Unit V see Absolute maximum ratings (electrical sensitivity) on page 51 - 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN