STM8L050J3M3

STM8L050J3 Value line, 8-bit ultra-low-power MCU, 8-Kbyte Flash, 256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC, comparators Datasheet - production data Features • Operating conditions – Operating power supply: 1.8 V to 3.6 V Temperature range: −40 °C to 125 °C • Low-power features – 5 low-power modes: Wait, Low-power run (5.1 µA), Low-power wait (3 µA), Activehalt with RTC (1.3 µA), Halt (350 nA) – Ultra-low leakage per I/O: 50 nA – Fast wakeup from Halt: 5 µs • Advanced STM8 core – Harvard architecture and 3-stage pipeline – Max freq: 16 MHz, 16 CISC MIPS peak – Up to 6 external interrupt sources • Reset and supply management – Low power, ultra-safe BOR reset with 5 selectable thresholds – Ultra-low power POR/PDR – Programmable voltage detector (PVD) • Clock management – 32 kHz and 1 to 16 MHz crystal oscillators – Internal 16 MHz factory-trimmed RC – Internal 38 kHz low consumption RC – Clock security system • Low-power RTC – BCD calendar with alarm interrupt – Digital calibration with +/- 0.5 ppm accuracy – LSE security system – Auto-wakeup from Halt w/ periodic interrupt SO8N (4.9 x 6 mm or 150 mils width) • DMA – 4 channels supporting ADC, SPI, I2C, USART, timers – 1 channel for memory-to-memory • 12-bit ADC up to 1 Msps/4 channels – Internal reference voltage • Timers – Two 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder – One 8-bit timer with 7-bit prescaler – 2 watchdogs: 1 Window, 1 Independent – Beeper timer with 1, 2 or 4 kHz frequencies • Communication interfaces – Synchronous serial interface (SPI) – Fast I2C 400 kHz SMBus and PMBus – USART • Up to 6 I/Os, all mappable on interrupt vectors • Development support – Fast on-chip programming and nonintrusive debugging with SWIM – Bootloader using USART • Two ultra-low-power comparators – One with fixed threshold and another one with rail to rail • Wakeup capability • Memories – 8 Kbytes of Flash program memory and 256 bytes of data EEPROM with ECC – Flexible write and read protection modes – 1 Kbyte of RAM January 2022 This is information on a product in full production. DS12167 Rev 7 1/94 www.st.com Contents STM8L050J3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 Ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 System configuration controller and routing interface . . . . . . . . . . . . . . . 20 3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 2/94 3.2.1 3.11.1 16-bit general purpose timers (TIM2, TIM3) . . . . . . . . . . . . . . . . . . . . . 20 3.11.2 8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.2 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DS12167 Rev 7 STM8L050J3 4 3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 5 Contents System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1 9 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 51 8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.3.9 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.3.10 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DS12167 Rev 7 3/94 4 Contents STM8L050J3 9.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4/94 DS12167 Rev 7 STM8L050J3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. STM8050J3 features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM8L050J3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 51 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Total current consumption and timing in Low-power run mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Total current consumption in Low-power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 58 Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 59 Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 59 Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 60 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 72 SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DS12167 Rev 7 5/94 6 List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. 6/94 STM8L050J3 RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DS12167 Rev 7 STM8L050J3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. STM8L050J3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STM8L050J3 clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM8L050J3 SO8N package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STML050J3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical pull-up resistance RPU vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical pull-up current Ipu vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Maximum dynamic current consumption on VREF+ supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 85 SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 88 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Example of SO8N marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Low density value line STM8L050J3 ordering information scheme . . . . . . . . . . . . . . . . . . 92 DS12167 Rev 7 7/94 7 Introduction 1 STM8L050J3 Introduction This document describes the features, pinout, mechanical data and ordering information for the STM8L050J3 microcontroller with 8-Kbyte Flash memory. For further details on the STMicroelectronics low density family please refer to Section 2.2: Ultra-low-power continuum. For detailed information on device operation and registers, refer to the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). For information on to the Flash program memory and data EEPROM, refer to the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054). For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044). The low density value line devices, like STM8L050J3, provide the following benefits: • • • • Integrated system – 8 Kbytes of low-density embedded Flash program memory – 256 bytes of data EEPROM – 1 Kbyte of RAM – Internal high-speed and low-power low speed RC – Embedded reset Ultra-low-power consumption – 1 µA in Active-halt mode – Clock gated system and optimized power management – Capability to execute from RAM for Low-power wait mode and Low-power run mode Advanced features – Up to 16 MIPS at 16 MHz CPU clock frequency – Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access Short development cycles – Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals – Wide choice of development tools These features make STM8L050J3 suitable for a wide range of consumer and mass market applications. Refer to Table 1: STM8050J3 features and peripheral counts and Section 3: Functional overview for an overview of the complete range of peripherals proposed in this family. Figure 1 shows STM8L050J3 block diagram. 8/94 DS12167 Rev 7 STM8L050J3 2 Description Description STM8L050J3 is member of the STM8L ultra-low-power 8-bit family. STM8L050J3 features an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low-power operations. The STM8L050J3 MCU includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultra-fast Flash programming. It features an embedded data EEPROM and low-power, low-voltage, singlesupply program Flash memory. The device incorporates an extensive range of enhanced I/Os and peripherals, a 12-bit ADC, two comparators, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as an SPI, an I2C interface, and one USART. The modular design of the peripheral set allows this device to have the same peripherals that can be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, supported also by the use of a common set of development tools. STM8L050J3 as all the value line STM8L ultra-low-power products are based on the same architecture with the same memory mapping and a coherent pinout. DS12167 Rev 7 9/94 43 Description 2.1 STM8L050J3 Device overview Table 1. STM8050J3 features and peripheral counts Features STM8L050J3 Flash (Kbytes) 8 Data EEPROM (Bytes) 256 RAM (Kbytes) Timers 1 Basic 1 (8-bit) General purpose 2 (16-bit) SPI Communicati I2C on interfaces USART 1 1 GPIOs 6 1 12-bit synchronized ADC (number of channels) 1 (4) Comparators (COMP1/COMP2) Others 2 RTC, window watchdog, independent watchdog, 16-MHz and 32-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator CPU frequency 16 MHz Operating voltage 1.8 to 3.6 V − 40 to +125 °C Operating temperature Package 10/94 SO8N DS12167 Rev 7 STM8L050J3 2.2 Description Ultra-low-power continuum STM8L050J3 is part of STM8’s ultra-low-power value line on which all the devices are software and feature compatible. Besides the full compatibility within the STM8L family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes the STM8L001xx, STM8L101xx and STM32L15xxx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.13 µm ultra-low leakage process. Performance All the STMicroelectronics ultra-low-power families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM® 32-bit Cortex®-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs. Shared peripherals The STM8L05xxx, STM8L15xxx and STM32L15xxx devices share identical peripherals which ensure a very easy migration from one family to another: • Analog peripheral: ADC1 and comparators COMP1/COMP2 • Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L and STM32L devices use a common architecture: • Same power supply range from 1.8 to 3.6 V • Architecture optimized to reach ultra-low consumption both in low-power modes and Run mode • Fast startup strategy from low-power modes • Flexible system clock • Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on reset, power-down reset, brownout reset and programmable voltage detector. Features ST ultra-low-power continuum also lies in feature compatibility: • More than 11 packages with pin count from 8 to 100 pins and size down to 3 x 3 mm • Memory density ranging from 2 to 128 Kbytes DS12167 Rev 7 11/94 43 Functional overview 3 STM8L050J3 Functional overview Figure 1 presents the basic block diagram which includes all the functional blocks for STM8L050J3. Figure 1. STM8L050J3 block diagram OSC_IN, OSC_OUT 16 MHz internal RC OSC32_IN, OSC32_OUT @V DD 1-16 MHz oscillator 32 kHz oscillator VDD18 Clock controller and CSS Power VOLT. REG. Clocks to core and peripherals 38 kHz internal RC V DD=1.8 V to 3.6 V V SS RESET Interrupt controller POR/PDR STM8 Core SWIM BOR Debug module (SWIM) PVD 16-bit Timer 2(2) 1 channel 16-bit Timer 3(2) 8-bit Timer 4(2) IR_TIM Infrared interface DMA1 (4 channels) SCL, SDA SPI1_MOSI, SPI1_MISO, SPI1_SCK USART1_RX, USART1_TX, USART1_CK I²C1 SPI1 USART1 8-Kbyte Program memory A d d res s , c o n trol an d d ata b u s es 2 channels 256-byte Data EEPROM 1-Kbyte RAM Port A PA Port B PB Port C PC Port D PD Beeper BEEP @V /V DDA SSA ADC1_INx 12-bit ADC1 RTC ALARM IWDG (38 kHz clock) Internal reference voltage WWDG MSv47735V1 1. Legend:ADC: Analog-to-digital converter BOR: Brownout reset DMA: Direct memory access I²C: Inter-integrated circuit multimaster interface IWDG: Independent watchdog POR/PDR: Power-on reset / power-down reset RTC: Real-time clock SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog 12/94 DS12167 Rev 7 STM8L050J3 3.1 Functional overview Low-power modes STM8L050J3 as well as all the low density value line STM8L05xxx devices support five lowpower modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). • Low-power run mode: The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode. The microcontroller enters Low-power run mode by software and can exit from this mode by software or by a reset. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. • Low-power wait mode: This mode is entered when executing a Wait for event in Lowpower run mode. It is similar to Low-power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an event, the system goes back to Low-power run mode. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. • Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset. • Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The RAM content is preserved. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs. DS12167 Rev 7 13/94 43 Functional overview 3.2 STM8L050J3 Central processing unit STM8 The central processing unit represents the core of the microcontroller; it executes code and controls the peripherals. 3.2.1 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. Architecture and registers • Harvard architecture • 3-stage pipeline • 32-bit wide program memory bus - single cycle fetching most instructions • X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations • 8-bit accumulator • 24-bit program counter - 16-Mbyte linear memory space • 16-bit stack pointer - access to a 64-Kbyte level stack • 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing • 20 addressing modes • Indexed indirect addressing mode for lookup tables located anywhere in the address space • Stack pointer relative addressing mode for local variables and parameter passing Instruction set 3.2.2 • 80 instructions with 2-byte average instruction size • Standard data movement and logic/arithmetic functions • 8-bit by 8-bit multiplication • 16-bit by 8-bit and 16-bit by 16-bit division • Bit manipulation • Data transfer between stack and accumulator (push/pop) with direct stack access • Data transfer using the X and Y registers or direct memory-to-memory transfers Interrupt controller STM8L050J3 and all the low density value line STM8L05xxx feature a nested vectored interrupt controller: 14/94 • Nested interrupts with 3 software priority levels • 32 interrupt vectors with hardware priority • Up to 6 external interrupt sources on 6 vectors • Trap and reset interrupts DS12167 Rev 7 STM8L050J3 3.3 Functional overview Reset and supply management The power supplies requirements must be defined in order to have a correct microcontroller operation. The reset and supply management controls the microcontroller operation under defined conditions. 3.3.1 Power supply scheme The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: 3.3.2 • VSS1; VDD1 = 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator. Provided externally through VDD1 pins, the corresponding ground pin is VSS1. • VSSA; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals. VDDA and VSSA is internally bonded to VDD1 and VSS1, respectively. • VREF+, VREF- (for ADC1): external reference voltage for ADC1 internally bonded to VSS1 / VDD1 and externally through VREF+ and VREF- pin. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry. When the microcontroller operates between 1.8 and 3.6 V, BOR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains in reset state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator STM8L050J3 as all the low density value line STM8L05xxx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: • Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event (WFE) modes. • Low-power voltage regulator mode (LPVR) for Halt, Active-halt, Low-power run and Low-power wait modes. When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. DS12167 Rev 7 15/94 43 Functional overview 3.4 STM8L050J3 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. Features 16/94 • Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock sources: four different clock sources can be used to drive the system clock: – 1-16 MHz High speed external crystal (HSE) – 16 MHz High speed internal RC oscillator (HSI) – 32.768 Low speed external crystal (LSE) – 38 kHz Low speed internal RC (LSI) • RTC clock sources: the above four sources can be chosen to clock the RTC whatever the system clock. • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, it is automatically switched to HSI. • Configurable main clock output (CCO): This outputs an external clock for use by the application. DS12167 Rev 7 STM8L050J3 Functional overview Figure 2. STM8L050J3 clock tree diagram SWIM[3:0] OSC_OUT OSC_IN HSE OSC 1-16 MHz HSE HSI HSI RC 1-16 MHz LSI SYSCLK prescaler /1;2;4;8;16;32;64 LSE SYSCLK to core and memory PCLK to peripherals Peripheral Clock enable (13 bits) LSE BEEPCLK CLKBEEPSEL[1:0] LSI LSI RC 38 kHz IWDGCLK to BEEP to IWDG RTCSEL[3:0] OSC32_OUT OSC32_IN CCO RTC prescaler /1;2;4;8;16;32;64 LSE OSC 32.768 kHz Configurable clock output to RTC RTCCLK HSI LSI HSE LSE CCO prescaler /1;2;4;8;16;32;64 CCOSEL[3:0] MS18281V2 1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to Section HSE clock in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). 2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to Section LSE clock in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). DS12167 Rev 7 17/94 43 Functional overview 3.5 STM8L050J3 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. 3.6 • Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours • Periodic alarms based on the calendar can also be generated from every second to every year Memories STM8L050J3 as all the low density value line STM8L05xxx devices have the following main features: • Up to 1 Kbyte of RAM • The non-volatile memory is divided into three arrays: – 8 Kbytes of low-density embedded Flash program memory – 256 bytes of Data EEPROM – Option bytes The EEPROM embeds the error correction code (ECC) feature. The option byte protects part of the Flash program memory from write and readout piracy. Recommendation for the device's programming The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space). If the device's program memory is empty (0x00 content), it displays the behavior described below: • After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG (0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF). It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz HSI clock. • Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed. The reading of non-existing memory is a random content which can lead to the execution of invalid instructions. The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more. 18/94 DS12167 Rev 7 STM8L050J3 Functional overview Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device. The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts). Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that it always contains a valid code loop. 3.7 DMA A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, I2C1, SPI1, USART1, and the three timers. 3.8 Analog-to-digital converter • 12-bit analog-to-digital converter (ADC1) with 4 channels (no fast channel) and internal reference voltage • Conversion time down to 1 µs with fSYSCLK= 16 MHz • Programmable resolution • Programmable sampling time • Single and continuous mode of conversion • Scan capability: automatic conversion performed on a selected group of analog inputs • Analog watchdog • Triggered by timer Note: ADC1 can be served by DMA1. 3.9 Ultra-low-power comparators The low-density STM8L050J3xx embed two comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal or external (coming from an I/O). Each comparator has a different threshold type: • One comparator with fixed threshold (COMP1) • One comparator rail to rail with fast or slow mode (COMP2). The threshold can be of the following: – External I/O – Internal reference voltage or internal reference voltage sub multiple (1/4, 1/2, 3/4) The two comparators can be used together to offer a window function. They can wake up from Halt mode. DS12167 Rev 7 19/94 43 Functional overview 3.10 STM8L050J3 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface controls the routing of internal analog signals to ADC1 and the internal reference voltage VREFINT. 3.11 Timers STM8L050J3 contains two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). All the timers can be served by DMA1. Table 2 compares the features of the advanced control, general-purpose and basic timers. Table 2. Timer feature comparison Timer TIM2 TIM3 TIM4 3.11.1 3.11.2 Counter Counter resolution type 16-bit 8-bit up/down up Prescaler factor DMA1 request generation Any power of 2 from 1 to 128 Capture/compare channels Complementary outputs 2 Yes Any power of 2 from 1 to 32768 1 None 0 16-bit general purpose timers (TIM2, TIM3) • 16-bit autoreload (AR) up/down-counter • 7-bit prescaler adjustable to fixed power of 2 ratios (1…128) • Individually configurable capture/compare channels • PWM mode • Interrupt capability on various events (capture, compare, overflow, break, trigger) • Synchronization with other timers or external signals (external clock, reset, trigger and enable) 8-bit basic timer (TIM4) The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow. 3.12 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. 20/94 DS12167 Rev 7 STM8L050J3 3.12.1 Functional overview Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.12.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure. 3.13 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 3.14 Communication interfaces This section describes the three communication interfaces of STM8L050J3: SPI, I2C and USART. 3.14.1 SPI The serial peripheral interfaces (SPI1) provide half/ full duplex synchronous serial communication with external devices. Note: • Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave • Full duplex synchronous transfers • Simplex synchronous transfers on 2 lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • Hardware CRC calculation SPI1 can be served by the DMA1 Controller. Slave selection pin (NSS) is supported only in a slave receive-only mode. 3.14.2 I2C The I2C bus interface (I2C1) provides multi-master capability, and controls all I2C busspecific sequencing, protocol, arbitration and timing. Note: • Master, slave and multi-master capability • Standard mode up to 100 kHz and fast speed modes up to 400 kHz • 7-bit and 10-bit addressing modes • SMBus 2.0 and PMBus support • Hardware CRC calculation I2C1 can be served by the DMA1 Controller. DS12167 Rev 7 21/94 43 Functional overview 3.14.3 STM8L050J3 USART The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. • 1 Mbit/s full duplex SCI • SPI emulation • High precision baud rate generator • Smartcard emulation • IrDA SIR encoder decoder • Single wire half duplex mode Note: USART1 can be served by the DMA1 Controller. 3.15 Infrared (IR) interface The low density STM8L05xxx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.16 Development support Development tools Development tools for the STM8 microcontrollers include: • The STice emulation system offering tracing and code profiling • The STVD high-level language debugger including C compiler, assembler and integrated development environment • The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers. 22/94 DS12167 Rev 7 STM8L050J3 Functional overview Recommendations for SWIM pin (pin#1) sharing If the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it is locked forever (if the NRST pin is not available on the package). This initial delay can be removed in the final (locked) code. If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for device debug/programming. Bootloader STM8L050J3 features a built-in bootloader(which supports USART interface on pins 8 and 1: PC5 = TxD, PC6 RxD). See STM8 bootloader user manual (UM0560). The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface. DS12167 Rev 7 23/94 43 Pin description 4 STM8L050J3 Pin description This section describes the device’s pin functions (see Table 4) and package’s pinout (see Figure 3). Figure 3. STM8L050J3 SO8N package pinout PA0/[USART_CK]/SWIM/BEEP/IR_TIM/ PA2/OSC_IN/[USART_TX]/[SPI_MISO]/ PC6/OSC32_OUT/SPI_SCK/USART_RX/TIM2_CH2 1 PA3/OSC_OUT/[USART_RX]/[SPI_MOSI] 2 8 7 PC1/I2C_SCL/ PC4/USART_CK/I2C_SMB/CCO/ADC1_IN4/COMP1_INP/ COMP2_INM/ PC5/OSC32_IN/[SPI1_NSS]/USART_TX/TIM2_CH1 PB7/SPI_MISO/ADC1_IN11/COMP1_INP/ PC0/I2C_SDA STM8L VSS/VSSA/VREF- VDD/VDDA/VREF+ 3 4 6 PB6/SPI_MOSI/ADC1IN12/COMP1_INP 5 PB3/TIM2_ETR/ADC1_IN15/RTC_ALARM/COMP1_INP/ PB5/SPI_SCK/ADC1_IN13/COMP1_NP/ PD0/TIM3_CH2/[ADC1_TRIG]/ADC1_IN22/COMP1_INP/ COMP2_INP/ MSv46319V1 1. [ ] Alternative function option. If the same alternate function is shown twice, it indicates an exclusive choice and not a duplication of the function. Table 3. Legend/abbreviation for Table 4 Type Level Port and control configuration Reset state 24/94 I= input, O = output, S = power supply Output HS = high sink/source (20 mA) Input FT - five volt tolerant Input float = floating, wpu = weak pull-up Output T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state). DS12167 Rev 7 STM8L050J3 Pin description Table 4. STM8L050J3 pin description PA0(1)/[USART_CK](2)/ SWIM/BEEP/IR_TIM(3) I/O - HS X X (1) X (3) X PA2/OSC_IN/[USART_TX](2)/ [SPI_MISO] (2) (4) I/O - (1) PC6/OSC32_OUT/[SPI_SCK](2) I/O /[USART_RX]/TIM2_CH2 2 Main function (after reset) Default alternate function X Port A0 [USART1 synchronous clock](2) / SWIM input and output / Beep output / Infrared Timer output X X HS X X Port A2 HSE oscillator input / [USART transmit] / [SPI master in- slave out] (1) X X HS X X Port C6 LSE oscillator output / [SPI clock] / [USART receive]/ Timer 2 -channel 2 PA3/OSC_OUT/[USART_RX](2) I/O /[SPI_MOSI](2) X X X HS X X Port A3 HSE oscillator output / [USART receive]/ [SPI master out/slave in] 3 VSS / VREF- / VSSA - - - - - - - - Ground voltage / ADC1 negative voltage reference / Analog ground voltage 4 VDD / VDDA / VREF+ S - - - - - - - Digital supply voltage /Analog supply voltage ADC1 positive voltage reference PB3/TIM2_ETR/ ADC1_IN15/RTC_ALARM/COM I/O P1_INP X X X HS X X Port B3 Timer 2 - external trigger / ADC1_IN15 / RTC_ALARM/ Comparator1 positive input PB5/SPI_SCK/ADC1_IN13/CO I/O MP1_INP X X X HS X X Port B5 [SPI clock] / ADC1_IN13/ Comparator1 positive input 1 5 X PP High sink/source Output Ext. interrupt wpu I/O level floating SO8N Pin name Type Input OD pin n° X PD0/TIM3_CH2/[ADC1_TRIG](2 I/O - X X X HS X I/O - X X X HS X X Port B6 SPI master out/ slave in / ADC1_IN12/ Comparator1 positive input PB7/SPI_MISO/ADC1_IN11/CO I/O MP1_INP X X X HS X X Port B7 SPI1 master in- slave out/ ADC1_IN11/ Comparator1 positive input PC0/I2C_SDA X - X - T(5) - Port C0 I2C data MP2_INP 6 7 Timer 3 - channel 2 / [ADC1_Trigger] / ADC1_IN22/ Comparator1 positive input/ Comparator2 positive input Port X D0 )/ADC1_IN22/COMP1_INP/CO PB6/SPI_MOSI/ ADC1_IN12/COMP1_INP I/O - DS12167 Rev 7 25/94 43 Pin description STM8L050J3 Table 4. STM8L050J3 pin description (continued) 8 - X - T(5) - PP High sink/source X OD Ext. interrupt I/O level I/O - wpu PC1/I2C_SCL Output floating SO8N Pin name Type Input Main function (after reset) pin n° Default alternate function Port C1 I2C clock PC4/USART_CK]/ I2C_SMB/CCO/ADC1_IN4/CO MP1_INP/COMP2_INM I/O - X X X HS X X Port C4 USART synchronous clock / I2C1_SMB / Configurable clock output / ADC1_IN4/ Comparator1 positive input/ Comparator2 negative input PC5/OSC32_IN /[SPI_NSS](2)/ [USART_TX]/TIM2_CH1 I/O - X X X HS X X Port C5 LSE oscillator input / [SPI master/slave select] / [USART transmit]/Timer 2 -channel 1 1. The PA0 pin is in input pull-up during the reset phase and after reset release. The default PA0 influences all the GPIOs connected in parallel on pin number 1 (PA2, PC6). 2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 3. High Sink LED driver capability available on PA0. 4. The SPI_MISO signal on PA2 (pin1) cannot be used in application because it is shared with the SPI_SCK signal on the same pin. 5. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). Although PC0/PC1 itself is a true open drain GPIO with its respective circuitry and characteristics, the maximum VIN of the pin number 7 and pin number 8 is limited by the standard GPIO (PB7 or PC4/PC5) which is also bonded to the same pin number. Note: 26/94 1 The slope control of all GPIO pins, except true open drain pins, can be programmed. By default, the slope control is limited to 2 MHz. 2 The PA1, PB0, PB1, PB2 and PB4 should be configured after device reset by user software into the output push-pull mode with output low-state to reduce the device’s consumption and to improve its EMC immunity. The GPIOs mentioned above are not connected to pins, and they are in input-floating mode after a device reset. To configure PA1 pin in output push-pull mode refer to Section “Configuring NRST/PA1 pin as general purpose output” in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). 3 As several pins provide a connection to multiple GPIOs, the mode selection for any of those GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PA0 is also seen on PA2 and PC6. Push-pull configuration of PB3 is also seen on PB5 and PD0, etc. DS12167 Rev 7 STM8L050J3 4.1 Pin description System configuration options As shown in Table 4: STM8L050J3 pin description, some functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “Routing interface (RI) and system configuration controller” section in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). DS12167 Rev 7 27/94 43 Memory and register map 5 STM8L050J3 Memory and register map The following sections describe the mapping of the device’s memory and peripherals. 5.1 Memory mapping The memory map is shown in Figure 4. Figure 4. STML050J3 memory map 0x00 5000 GPIO ports 0x00 501E Reserved 0x00 5050 Flash 0x00 5055 Reserved 0x00 0000 0x00 03FF 0x00 0400 0x00 1FFF 0x00 1000 0x00 10FF 0x00 1100 RAM ( Up to 1 Kbyte) including Stack (512 bytes) 0x00 50A9 RST 0x00 50B2 PWR 0x00 50B4 Reserved 0x00 50C0 CLK 0x00 50D1 Reserved 0x00 50D3 WWDG Option bytes 0x00 50D5 Reserved 0x00 50E0 0x00 50E3 Reserved IWDG Reserved 0x00 50F0 0x00 50F4 BEEP Reserved 0x00 5040 0x00 5191 0x00 5200 Reserved RTC Reserved SPI1 0x00 5208 Reserved 0x00 5210 I2C1 Boot ROM (2 Kbytes) 0x00 521F Reserved 0x00 5230 0x00 523B Reserved 0x00 5250 0x00 7EFF 0x00 7F00 0x00 9FFF Reserved 0x00 50B0 Data EEPROM (256 Bytes) 0x00 5457 0x00 5458 0x00 7FFF 0x00 8000 0x00 80FF 0x00 8100 ITC-EXT1 0x00 50A6 WFE GPIO and peripheral registers 0x00 67FF 0x00 6800 0x00 50A0 ITC-EXT1 0x00 47FF 0x00 4800 0x00 5FFF 0x00 6000 DMA1 SYSCFG 0x00 50AA Reserved Reserved 0x00 487F 0x00 4880 0x00 4FFF 0x00 5000 0x00 5070 0x00 509D 0x00 5267 USART1 Reserved TIM2 Reserved CPU/SWIM/Debug/ITC Registers 0x00 5280 Reset and interrupt vectors 0x00 52EA TIM3 0x00 5297 Reserved 0x00 52E0 0x00 52FF TIM4 Reserved IRTIM 0x00 5317 Low density Flash program memory (8 Kbytes) Reserved 0x00 5340 0x00 53C8 0x00 5430 ADC1 Reserved RI 0x00 5440 0x00 5450 0x00 5457 Reserved RI MS18274V3 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. 28/94 DS12167 Rev 7 STM8L050J3 Memory and register map Table 5. Flash and RAM boundary addresses Memory area Size Start address End address RAM 1 Kbyte 0x00 0000 0x00 03FF Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF 5.2 Register map Table 6. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x01 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xXX PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x00 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 0x00 5014 to 0x00 501D Block Port A Port B Port C Port D Reserved area (0 bytes) DS12167 Rev 7 29/94 43 Memory and register map STM8L050J3 Table 7. General hardware register map Address Block Register label Register name 0x00 502E to 0x00 5049 Reset status Reserved area (44 bytes) 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 FLASH _PUKR Flash program memory unprotection key register 0x00 0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00 0x00 5054 FLASH _IAPSR Flash in-application programming status register 0x00 0x00 5052 Flash 0x00 5055 to 0x00 506F Reserved area (27 bytes) 0x00 5070 DMA1_GCSR DMA1 global configuration & status register 0xFC 0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 Reserved area (3 bytes) 0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00 0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00 0x00 5077 DMA1_C0NDTR DMA1 number of data to transfer register (channel 0) 0x00 0x00 5078 DMA1_C0PARH DMA1 peripheral address high register (channel 0) 0x52 0x00 5079 DMA1_C0PARL DMA1 peripheral address low register (channel 0) 0x00 DMA1 0x00 507A Reserved area (1 byte) 0x00 507B DMA1_C0M0ARH DMA1 memory 0 address high register (channel 0) 0x00 0x00 507C DMA1_C0M0ARL DMA1 memory 0 address low register (channel 0) 0x00 30/94 DS12167 Rev 7 STM8L050J3 Memory and register map Table 7. General hardware register map (continued) Address Block Register label Register name 0x00 507D to 0x00 507E Reset status Reserved area (2 bytes) 0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00 0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00 0x00 5081 DMA1_C1NDTR DMA1 number of data to transfer register (channel 1) 0x00 0x00 5082 DMA1_C1PARH DMA1 peripheral address high register (channel 1) 0x52 0x00 5083 DMA1_C1PARL DMA1 peripheral address low register (channel 1) 0x00 0x00 5084 Reserved area (1 byte) 0x00 5085 DMA1_C1M0ARH DMA1 memory 0 address high register (channel 1) 0x00 0x00 5086 DMA1_C1M0ARL DMA1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 Reserved area (2 bytes) 0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00 0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00 DMA1_C2NDTR DMA1 number of data to transfer register (channel 2) 0x00 0x00 508C DMA1_C2PARH DMA1 peripheral address high register (channel 2) 0x52 0x00 508D DMA1_C2PARL DMA1 peripheral address low register (channel 2) 0x00 0x00 508B DMA1 0x00 508E Reserved area (1 byte) 0x00 508F DMA1_C2M0ARH DMA1 memory 0 address high register (channel 2) 0x00 0x00 5090 DMA1_C2M0ARL DMA1 memory 0 address low register (channel 2) 0x00 0x00 5091 0x00 5092 Reserved area (2 bytes) 0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00 0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00 0x00 5095 DMA1_C3NDTR DMA1 number of data to transfer register (channel 3) 0x00 0x00 5096 DMA1_C3PARH_ C3M1ARH DMA1 peripheral address high register (channel 3) 0x40 0x00 5097 DMA1_C3PARL_ C3M1ARL DMA1 peripheral address low register (channel 3) 0x00 DS12167 Rev 7 31/94 43 Memory and register map STM8L050J3 Table 7. General hardware register map (continued) Register label Register name Reset status 0x00 5098 DMA_C3M0EAR DMA channel 3 memory 0 extended address register 0x00 0x00 5099 DMA1_C3M0ARH DMA1 memory 0 address high register (channel 3) 0x00 DMA1_C3M0ARL DMA1 memory 0 address low register (channel 3) 0x00 Address Block DMA1 0x00 509A 0x00 509B to 0x00 509C Reserved area (3 bytes) 0x00 509D SYSCFG_RMPCR3 Remapping register 3 0x00 SYSCFG_RMPCR1 Remapping register 1 0x2C 0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 EXTI_CR3 External interrupt control register 3 0x00 EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00 0x00 50A6 WFE_CR1 WFE control register 1 0x00 WFE_CR2 WFE control register 2 0x00 WFE_CR3 WFE control register 3 0x00 WFE_CR4 WFE control register 4 0x00 EXTI_CR4 External interrupt control register 4 0x00 EXTI_CONF2 External interrupt port select register 2 0x00 0x00 509E 0x00 50A2 0x00 50A3 0x00 50A7 0x00 50A8 SYSCFG ITC - EXTI WFE 0x00 50A9 0x00 50AA 0x00 50AB ITC - EXTI 0x00 50A9 to 0x00 50AF 0x00 50B0 0x00 50B1 0x00 50B2 0x00 50B3 Reserved area (7 bytes) RST PWR RST_CR Reset control register 0x00 RST_SR Reset status register 0x01 PWR_CSR1 Power control and status register 1 0x00 PWR_CSR2 Power control and status register 2 0x00 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 0x00 50C1 0x00 50C2 0x00 50C3 32/94 CLK CLK_CKDIVR CLK Clock master divider register 0x03 CLK_CRTCR CLK Clock RTC register 0x00(1) CLK_ICKCR CLK Internal clock control register 0x11 CLK_PCKENR1 CLK Peripheral clock gating register 1 0x00 DS12167 Rev 7 STM8L050J3 Memory and register map Table 7. General hardware register map (continued) Register label Register name Reset status 0x00 50C4 CLK_PCKENR2 CLK Peripheral clock gating register 2 0x00 0x00 50C5 CLK_CCOR CLK Configurable clock control register 0x00 0x00 50C6 CLK_ECKCR CLK External clock control register 0x00 0x00 50C7 CLK_SCSR CLK System clock status register 0x01 0x00 50C8 CLK_SWR CLK System clock switch register 0x01 0x00 50C9 CLK_SWCR CLK Clock switch control register 0xX0 CLK_CSSR CLK Clock security system register 0x00 0x00 50CB CLK_CBEEPR CLK Clock BEEP register 0x00 0x00 50CC CLK_HSICALR CLK HSI calibration register 0xXX 0x00 50CD CLK_HSITRIMR CLK HSI clock calibration trimming register 0x00 0x00 50CE CLK_HSIUNLCKR CLK HSI unlock register 0x00 0x00 50CF CLK_REGCSR CLK Main regulator control status register 0bxx11 1 00X 0x00 50D0 CLK_PCKENR3 CLK Peripheral clock gating register 3 0x00 Address 0x00 50CA Block CLK 0x00 50D1 to 0x00 50D2 0x00 50D3 0x00 50D4 Reserved area (2 bytes) WWDG WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F 0x00 50D5 to 00 50DF Reserved area (11 bytes) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0x01 IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 0x00 50F2 BEEP_CSR1 BEEP_CSR2 0x00 50F4 to0x00 513F 0x00 5142 BEEP control/status register 2 0x1F Reserved area (76 bytes) 0x00 5140 0x00 5141 0x00 Reserved area (2 bytes) BEEP 0x00 50F3 BEEP control/status register 1 RTC RTC_TR1 RTC Time register 1 0x00 RTC_TR2 RTC Time register 2 0x00 RTC_TR3 RTC Time register 3 0x00 DS12167 Rev 7 33/94 43 Memory and register map STM8L050J3 Table 7. General hardware register map (continued) Address Block Register label Register name 0x00 5143 Reset status Reserved area (1 byte) 0x00 5144 RTC_DR1 RTC Date register 1 0x01 0x00 5145 RTC_DR2 RTC Date register 2 0x21 0x00 5146 RTC_DR3 RTC Date register 3 0x00 0x00 5147 Reserved area (1 byte) 0x00 5148 RTC_CR1 RTC Control register 1 0x00(1) 0x00 5149 RTC_CR2 RTC Control register 2 0x00(1) 0x00 514A RTC_CR3 RTC Control register 3 0x00(1) 0x00 514B Reserved area (1 byte) 0x00 514C RTC_ISR1 RTC Initialization and status register 1 0x01 0x00 514D RTC_ISR2 RTC Initialization and Status register 2 0x00 0x00 514E 0x00 514F Reserved area (2 bytes) 0x00 5150 RTC_SPRERH RTC Synchronous prescaler register high 0x00(1) 0x00 5151 RTC_SPRERL RTC Synchronous prescaler register low 0xFF(1) 0x00 5152 RTC_APRER RTC Asynchronous prescaler register 0x7F(1) 0x00 5153 0x00 5154 0x00 5155 Reserved area (1 byte) RTC RTC_WUTRH RTC Wakeup timer register high 0xFF(1) RTC_WUTRL RTC Wakeup timer register low 0xFF(1) 0x00 5156 Reserved area (1 byte) 0x00 5157 RTC_SSRL RTC Subsecond register low 0x00 0x00 5158 RTC_SSRH RTC Subsecond register high 0x00 0x00 5159 RTC_WPR RTC Write protection register 0x00 0x00 5158 RTC_SSRH RTC Subsecond register high 0x00 0x00 5159 RTC_WPR RTC Write protection register 0x00 0x00 515A RTC_SHIFTRH RTC Shift register high 0x00 0x00 515B RTC_SHIFTRL RTC Shift register low 0x00 0x00 515C RTC_ALRMAR1 RTC Alarm A register 1 0x00(1) 0x00 515D RTC_ALRMAR2 RTC Alarm A register 2 0x00(1) 0x00 515E RTC_ALRMAR3 RTC Alarm A register 3 0x00(1) 0x00 515F RTC_ALRMAR4 RTC Alarm A register 4 0x00(1) 0x00 5160 to 0x00 5163 Reserved area (4 bytes) 0x00 5164 RTC_ALRMASSRH RTC Alarm A subsecond register high 0x00(1) 0x00 5165 RTC_ALRMASSRL RTC Alarm A subsecond register low 0x00(1) 34/94 DS12167 Rev 7 STM8L050J3 Memory and register map Table 7. General hardware register map (continued) Address Block 0x00 5166 Register label Register name Reset status RTC_ALRMASSMSKR RTC Alarm A masking register 0x00(1) 0x00 5167 to 0x00 5169 Reserved area (3 bytes) 0x00 516A 0x00 516B 0x00 516C RTC 0x00 516D RTC_CALRH RTC Calibration register high 0x00(1) RTC_CALRL RTC Calibration register low 0x00(1) RTC_TCR1 RTC Tamper control register 1 0x00(1) RTC_TCR2 RTC Tamper control register 2 0x00(1) 0x00 516E to 0x00 518A Reserved area (36 bytes) 0x00 5190 CSSLSE_CSR 0x00 519A to 0x00 51FF CSS on LSE control and status register 0x00(1) Reserved area (111 bytes) 0x00 5200 SPI1_CR1 SPI1 control register 1 0x00 0x00 5201 SPI1_CR2 SPI1 control register 2 0x00 0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00 SPI1_SR SPI1 status register 0x02 SPI1_DR SPI1 data register 0x00 0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07 0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00 0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00 0x00 5203 0x00 5204 SPI1 0x00 5208 to 0x00 520F Reserved area (8 bytes) 0x00 5210 I2C1_CR1 I2C1 control register 1 0x00 0x00 5211 I2C1_CR2 I2C1 control register 2 0x00 0x00 5212 I2C1_FREQR I2C1 frequency register 0x00 0x00 5213 I2C1_OARL I2C1 own address register low 0x00 0x00 5214 I2C1_OARH I2C1 own address register high 0x00 0x00 5215 I2C1_OAR2 I2C1 own address register for dual mode 0x00 I2C1_DR I2C1 data register 0x00 0x00 5217 I2C1_SR1 I2C1 status register 1 0x00 0x00 5218 I2C1_SR2 I2C1 status register 2 0x00 0x00 5219 I2C1_SR3 I2C1 status register 3 0x0X 0x00 521A I2C1_ITR I2C1 interrupt control register 0x00 0x00 521B I2C1_CCRL I2C1 clock control register low 0x00 0x00 521C I2C1_CCRH I2C1 clock control register high 0x00 0x00 5216 I2C1 DS12167 Rev 7 35/94 43 Memory and register map STM8L050J3 Table 7. General hardware register map (continued) Address 0x00 521D 0x00 521E Block I2C1 Register label Register name Reset status I2C1_TRISER I2C1 TRISE register 0x02 I2C1_PECR I2C1 packet error checking register 0x00 0x00 521F to 0x00 522F Reserved area (17 bytes) 0x00 5230 USART1_SR USART1 status register 0xC0 0x00 5231 USART1_DR USART1 data register 0xXX 0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00 0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00 0x00 5234 USART1_CR1 USART1 control register 1 0x00 USART1_CR2 USART1 control register 2 0x00 0x00 5236 USART1_CR3 USART1 control register 3 0x00 0x00 5237 USART1_CR4 USART1 control register 4 0x00 0x00 5238 USART1_CR5 USART1 control register 5 0x00 0x00 5239 USART1_GTR USART1 guard time register 0x00 0x00 523A USART1_PSCR USART1 prescaler register 0x00 0x00 5235 USART1 0x00 523B to 0x00 524F Reserved area (21 bytes) 0x00 5250 TIM2_CR1 TIM2 control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00 0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5256 TIM2_SR1 TIM2 status register 1 0x00 TIM2_SR2 TIM2 status register 2 0x00 TIM2_EGR TIM2 event generation register 0x00 0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 525B TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 525C TIM2_CNTRH TIM2 counter high 0x00 0x00 525D TIM2_CNTRL TIM2 counter low 0x00 0x00 525E TIM2_PSCR TIM2 prescaler register 0x00 0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 5257 0x00 5258 36/94 TIM2 DS12167 Rev 7 STM8L050J3 Memory and register map Table 7. General hardware register map (continued) Register label Register name Reset status 0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00 0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5265 TIM2_BKR TIM2 break register 0x00 0x00 5266 TIM2_OISR TIM2 output idle state register 0x00 Address 0x00 5263 Block TIM2 0x00 5267 to 0x00 527F Reserved area (25 bytes) 0x00 5280 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00 0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5286 TIM3_SR1 TIM3 status register 1 0x00 0x00 5287 TIM3_SR2 TIM3 status register 2 0x00 0x00 5288 TIM3_EGR TIM3 event generation register 0x00 0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00 0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00 TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00 0x00 528C TIM3_CNTRH TIM3 counter high 0x00 0x00 528D TIM3_CNTRL TIM3 counter low 0x00 0x00 528E TIM3_PSCR TIM3 prescaler register 0x00 0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF 0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF 0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00 0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00 0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00 0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00 0x00 5295 TIM3_BKR TIM3 break register 0x00 0x00 5296 TIM3_OISR TIM3 output idle state register 0x00 0x00 528B 0x00 5297 to 0x00 52DF TIM3 Reserved area (72 bytes) DS12167 Rev 7 37/94 43 Memory and register map STM8L050J3 Table 7. General hardware register map (continued) Register label Register name Reset status 0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00 TIM4_IER TIM4 Interrupt enable register 0x00 TIM4_SR1 TIM4 status register 1 0x00 0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00 0x00 52E7 TIM4_CNTR TIM4 counter 0x00 0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00 Address 0x00 52E4 0x00 52E5 Block TIM4 0x00 52EA to 0x00 52FE 0x00 52FF Reserved area (21 bytes) IRTIM IR_CR 0x00 5317 to 0x00 533F Infrared control register 0x00 Reserved area (41 bytes) 0x00 5340 ADC1_CR1 ADC1 configuration register 1 0x00 0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00 0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F 0x00 5343 ADC1_SR ADC1 status register 0x00 0x00 5344 ADC1_DRH ADC1 data register high 0x00 0x00 5345 ADC1_DRL ADC1 data register low 0x00 0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F 0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF ADC1_LTRH ADC1 low threshold register high 0x00 ADC1_LTRL ADC1 low threshold register low 0x00 0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00 0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00 0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00 0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00 0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00 0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00 0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00 0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00 0x00 5348 0x00 5349 38/94 ADC1 DS12167 Rev 7 STM8L050J3 Memory and register map Table 7. General hardware register map (continued) Address Block Register label 0x00 53C8 to 0x00 542F Register name Reset status Reserved area(104 bytes) 0x00 5430 Reserved area (1 byte) 0x00 0x00 5431 RI_ICR1 RI Timer input capture routing register 1 0x00 0x00 5432 RI_ICR2 RI Timer input capture routing register 2 0x00 0x00 5433 RI_IOIR1 RI I/O input register 1 0xXX 0x00 5434 RI_IOIR2 RI I/O input register 2 0xXX 0x00 5435 RI_IOIR3 RI I/O input register 3 0xXX 0x00 5436 RI_IOCMR1 RI I/O control mode register 1 0x00 RI_IOCMR2 RI I/O control mode register 2 0x00 RI_IOCMR3 RI I/O control mode register 3 0x00 0x00 5439 RI_IOSR1 RI I/O switch register 1 0x00 0x00 543A RI_IOSR2 RI I/O switch register 2 0x00 0x00 543B RI_IOSR3 RI I/O switch register 3 0x00 0x00 543C RI_IOGCR RI I/O group control register 0xFF 0x00 543D RI_ASCR1 Analog switch register 1 0x00 0x00 543E RI_ASCR2 RI Analog switch register 2 0x00 0x00 543F RI_RCR RI Resistor control register 0x00 0x00 5440 COMP_CSR1 Comparator control and status register 1 0x00 COMP_CSR2 Comparator control and status register 2 0x00 COMP_CSR3 Comparator control and status register 3 0x00 0x00 5443 COMP_CSR4 Comparator control and status register 4 0x00 0x00 5444 COMP_CSR5 Comparator control and status register 5 0x00 0x00 5437 0x00 5438 RI 0x00 5441 0x00 5442 COMP1/ COMP2 0x00 5445 to 0x00 544F Reserved area (16 bytes) 0x00 5450 RI_CR RI I/O control register 0x00 0x00 5451 RI_MASKR1 RI I/O mask register 1 0x00 0x00 5452 RI_MASKR2 RI I/O mask register 2 0x00 RI_MASKR3 RI I/O mask register 3 0x00 RI_MASKR4 RI I/O mask register 4 0x00 0x00 5455 RI_IOIR4 RI I/O input register 4 0xXX 0x00 5456 RI_IOCMR4 RI I/O control mode register 4 0x00 0x00 5457 RI_IOSR4 RI I/O switch register 4 0x00 0x00 5453 0x00 5454 RI 1. These registers are not impacted by a system reset. They are reset at power-on. DS12167 Rev 7 39/94 43 Memory and register map STM8L050J3 Table 8. CPU/SWIM/debug module/interrupt controller registers Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 0x00 7F0B to 0x00 7F5F (1) CPU Reserved area (85 bytes) CPU 0x00 7F60 CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF ITC_SPR4 Interrupt Software priority register 4 0xFF ITC_SPR5 Interrupt Software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF 0x00 7F73 0x00 7F74 ITC-SPR 0x00 7F78 to 0x00 7F79 0x00 7F80 Reserved area (2 bytes) SWIM SWIM_CSR 0x00 7F81 to 0x00 7F8F SWIM control status register 0x00 Reserved area (15 bytes) 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM Debug module control register 1 0x00 0x00 7F93 40/94 DM DS12167 Rev 7 STM8L050J3 Memory and register map Table 8. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block 0x00 7F97 0x00 7F98 0x00 7F99 DM 0x00 7F9A 0x00 7F9B to 0x00 7F9F Register label Register name Reset status DM_CR2 DM Debug module control register 2 0x00 DM_CSR1 DM Debug module control/status register 1 0x10 DM_CSR2 DM Debug module control/status register 2 0x00 DM_ENFCTR DM enable function register 0xFF Reserved area (5 bytes) 1. Accessible by debug module only DS12167 Rev 7 41/94 43 Interrupt vector mapping 6 STM8L050J3 Interrupt vector mapping The interrupt vector mapping is described in Table 9. I IRQ No. Table 9. Interrupt mapping Source block RESET Description Reset Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode)(1) Yes Yes Yes Yes 0x00 8000 Vector address TRAP Software interrupt - - - - 0x00 8004 TLI(2) External Top level Interrupt - - - - 0x00 8008 1 FLASH FLASH end of programing/ write attempted to protected page interrupt - - Yes Yes 0x00 800C 2 DMA1 0/1 DMA1 channels 0/1 half transaction/transaction complete interrupt - - Yes Yes 0x00 8010 3 DMA1 2/3 DMA1 channels 2/3 half transaction/transaction complete interrupt - - Yes Yes 0x00 8014 4 RTC RTC alarm A/wakeup/ tamper 1/tamper 2/tamper 3 Yes Yes Yes Yes 0x00 8018 5 PVD PVD interrupt Yes Yes Yes Yes 0x00 801C 6 EXTIB External interrupt port B Yes Yes Yes Yes 0x00 8020 7 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024 8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044 0 16 Reserved 17 CLK 18 ADC1 42/94 CLK system clock switch/CSS interrupt ACD1 end of conversion/ analog watchdog/ overrun interrupt 0x00 8048 - - Yes Yes 0x00 804C Yes Yes Yes Yes 0x00 8050 DS12167 Rev 7 STM8L050J3 Interrupt vector mapping Table 9. Interrupt mapping (continued) Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode)(1) TIM2 update /overflow/trigger/break interrupt - - Yes Yes 0x00 8054 TIM2 TIM2 Capture/Compare interrupt - - Yes Yes 0x00 8058 21 TIM3 TIM3 Update /Overflow/Trigger/Break interrupt - - Yes Yes 0x00 805C 22 TIM3 TIM3 Capture/Compare interrupt - - Yes Yes 0x00 8060 23 RI RI trigger interrupt - - Yes - 0x00 8064 IRQ No. Source block 19 TIM2 20 Description 24 Reserved Vector address 0x00 8068 25 TIM4 TIM4 update/overflow/ trigger interrupt - - Yes Yes 0x00 806C 26 SPI1 SPI1 TX buffer empty/ RX buffer not empty/ error/wakeup interrupt Yes Yes Yes Yes 0x00 8070 USART 1 USART1 transmit data register empty/ transmission complete interrupt - - Yes Yes 0x00 8074 28 USART 1 USART1 received data ready/overrun error/ idle line detected/parity error/global error interrupt - - Yes Yes 0x00 8078 29 I2C1 Yes Yes Yes Yes 0x00 807C 27 I2C1 interrupt(3) 1. The Low-power wait mode is entered when executing a WFE instruction in Low-power run mode. In WFE mode, the interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing. 2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts. 3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. DS12167 Rev 7 43/94 43 Option bytes 7 STM8L050J3 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for the ROP and UBCvalues which can only be taken into account when they are modified in ICP mode (with the SWIM). Refer to the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054) and the STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 10. Option byte addresses Addr. Option name Option byte No. Option bits 7 6 5 4 3 2 1 0 Factory default setting 0x00 4800 Read-out protection (ROP) OPT0 ROP[7:0] 0xAA 0x00 4802 UBC (User Boot code size) OPT1 UBC[7:0] 0x00 0x00 4807 Reserved Independent watchdog option OPT3 [3:0] Reserved Number of stabilization 0x00 4809 clock cycles for HSE and LSE oscillators OPT4 Reserved Brownout reset (BOR) OPT5 [3:0] Reserved Bootloader option bytes (OPTBL) OPTBL [15:0] 0x00 4808 0x00 480A 0x00 480B 0x00 480C 44/94 0x00 WWDG WWDG IWDG _HALT _HW _HALT LSECNT[1:0] BOR_TH IWDG _HW HSECNT[1:0] BOR_ ON 0x00 0x00 0x00 0x00 OPTBL[15:0] DS12167 Rev 7 0x00 STM8L050J3 Option bytes Table 11. Option byte description Option byte No. Option description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to the “Readout protection” section in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area 0x00: UBC is not protected. 0x01: Page 0 is write protected. 0x02: Page 0 and 1 reserved for the UBC and write protected. It covers only the interrupt vectors. 0x03: Page 0 to 2 reserved for UBC and write protected. 0x7F to 0xFF - All 128 pages reserved for UBC and write protected. The protection of the memory area not protected by the UBC is enabled through the MASS keys. Refer to the “User boot code” section in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). OPT2 Reserved IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware OPT3 IWDG_HALT: Independent window watchdog off on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode WWDG_HW: Window watchdog 0: Window watchdog activated by software 1: Window watchdog activated by hardware WWDG_HALT: Window window watchdog reset on Halt/Active-halt 0: Window watchdog stopped in Halt mode 1: Window watchdog generates a reset when MCU enters Halt mode HSECNT: Number of HSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles OPT4 LSECNT: Number of LSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles Refer to Table 29: LSE oscillator characteristics on page 64. DS12167 Rev 7 45/94 46 Option bytes STM8L050J3 Table 11. Option byte description (continued) Option byte No. OPT5 Option description BOR_ON: 0: Brownout reset off 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 20 for details on the thresholds according to the value of BOR_TH bits. OPTBL 46/94 OPTBL[15:0]: This option is checked by the boot ROM code after reset. Depending on content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 STM8 bootloader user manual for more details. DS12167 Rev 7 STM8L050J3 8 Electrical parameters Electrical parameters This section describes the quantification of the given device’s parameters. 8.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 8.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics is indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 8.1.2 Typical values Unless otherwise specified, typical data is based on TA = 25 °C, VDD = 3 V. It is given only as design guidelines and is not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 8.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 8.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 5. Figure 5. Pin loading conditions STM8 PIN 50 pF MSv37774V1 DS12167 Rev 7 47/94 87 Electrical parameters 8.1.5 STM8L050J3 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6. Figure 6. Pin input voltage STM8 PIN VIN MSv37775V1 8.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device's reliability. The device's mission profile (application conditions) is compliant with the JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 12. Voltage characteristics Symbol VDD- VSS Ratings External supply voltage (including VDDA)(1) VIN(2) Input voltage on any other pin VESD Electrostatic discharge voltage Min Max Unit - 0.3 4.0 V VSS - 0.3 VDD + 0.3 V see Absolute maximum ratings (electrical sensitivity) on page 87 - 1. All power (VDD1, VDDA) and ground (VSS1, VSSA) pins must always be connected to the external power supply. 2. VIN maximum must always be respected. Refer to Table 13: Current characteristics for maximum allowed injected current values. 48/94 DS12167 Rev 7 STM8L050J3 Electrical parameters Table 13. Current characteristics Symbol Ratings Max. IVDD Total current into VDD power line (source) 80 IVSS Total current out of VSS ground line (sink) 80 Output current sunk by IR_TIM pin (with high sink LED driver capability) 80 Output current sunk by any other I/O and control pin 25 IIO Output current sourced by any I/Os and control pin 1. IINJ(PIN) Injected current on any pin (1) ΣIINJ(PIN) Total injected current (sum of all I/O and control pins) (2) Unit mA - 25 - 5 / +5 ± 25 A positive injection is induced by VIN>VDD while a negative injection is induced by VIN> gmcrit DS12167 Rev 7 63/94 87 Electrical parameters STM8L050J3 LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 29. LSE oscillator characteristics Symbol Parameter fLSE Low speed external oscillator frequency RF Feedback resistor C(1) Recommended load capacitance (2) IDD(LSE) gm LSE oscillator power consumption Conditions Min Typ Max Unit - - 32.768 - kHz ΔV = 200 mV - 1.2 - MΩ - - 8 - pF - - - 1.4(3) µA VDD = 1.8 V - 450 - VDD = 3 V - 600 - VDD = 3.6 V - 750 - - 3(3) - - µA/V VDD is stabilized - 1 - s Oscillator transconductance tSU(LSE)(4) Startup time nA 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value. Refer to crystal manufacturer for more details. 3. Guaranteed by design. 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 13. LSE oscillator circuit diagram 64/94 DS12167 Rev 7 STM8L050J3 Electrical parameters Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 30. HSI oscillator characteristics Symbol fHSI Conditions(1) Parameter Min Typ Max Unit Frequency VDD = 3.0 V - 16 - MHz Accuracy of HSI oscillator (factory calibrated) VDD = 3.0 V, TA = 25 °C -5 - 5 % ACCHSI -7.5(2) - 7.5(2) % TRIM HSI user trimming step(3) 1.8 V ≤ VDD ≤ 3.6 V, -40 °C ≤ TA ≤ 125 °C Trimming code ≠ multiple of 16 - 0.4 0.7 % Trimming code = multiple of 16 - - ± 1.5 % tsu(HSI) HSI oscillator setup time (wakeup time) - - 3.7 6(4) µs IDD(HSI) HSI oscillator power consumption - - 100 140(4) µA 1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified. 2. Guaranteed by characterization results. 3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for more details. 4. Guaranteed by design. DS12167 Rev 7 65/94 87 Electrical parameters STM8L050J3 Low speed internal RC oscillator (LSI) In the following table, data is based on characterization results, not tested in production. Table 31. LSI oscillator characteristics Parameter (1) Symbol fLSI Conditions(1) Min Typ Max Unit - 26 38 56 kHz Frequency tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator frequency drift(3) 0 °C ≤ TA ≤ 85 °C (2) - - 200 -12 - 11 µs % 1. VDD = 1.8 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified. 2. Guaranteed by design. 3. This is a deviation for an individual part, once the initial frequency has been measured. Figure 14. Typical LSI frequency vs. VDD 45 43 LSI frequency [kHz] 41 39 37 35 33 -40°C 31 25°C 85°C 29 27 25 1.8 2.1 2.6 3.1 3.6 VDD [V] ai18219b 66/94 DS12167 Rev 7 STM8L050J3 8.3.5 Electrical parameters Memory characteristics TA = -40 to 125 °C unless otherwise specified. Table 32. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode (1) Halt mode (or Reset) 1.8 - - V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization. Flash memory Table 33. Flash program and data EEPROM memory Symbol VDD tprog Iprog tRET(2) Parameter Conditions Min Typ fSYSCLK = 16 MHz 1.8 Programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte) - Programming time for 1 to 64 bytes (block) write cycles (on erased byte) (1) Unit - 3.6 V - 6 - ms - - 3 - ms TA=+25 °C, VDD = 3.0 V - TA=+25 °C, VDD = 1.8 V - Data retention (program memory) after 100 erase/write cycles at TA= –40 to +85 °C TRET = +85 °C 30(1) - - Data retention (program memory) after 1000 erase/write cycles at TA= –40 to +125 °C TRET = +125 °C 5(1) - - Data retention (data memory) after 100000 erase/write cycles at TA= –40 to +85 °C TRET = +85 °C 30(1) - - Data retention (data memory) after 300000 erase/write cycles at TA= –40 to +125 °C TRET = +125 °C 5(1) - - - 100(1) - - cycles - - kcycles Operating voltage (all modes, read/write/erase) Programming/ erasing consumption Erase/write cycles (program memory) NRW Max (3) Erase/write cycles (data memory) TA = –40 to +85 °C 100(1) (4) 0.7 - mA years 1. Guaranteed by characterization results. 2. Conforming to JEDEC JESD22a117 3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 4. Data based on characterization performed on the whole data memory. DS12167 Rev 7 67/94 87 Electrical parameters 8.3.6 STM8L050J3 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.). The test results are given in the following table. Table 34. I/O current injection susceptibility Functional susceptibility Symbol IINJ 68/94 Description Injected current on any other pin DS12167 Rev 7 Negative injection Positive injection -5 +5 Unit mA STM8L050J3 8.3.7 Electrical parameters I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 35. I/O static characteristics Symbol VIL Conditions(1) Min Typ Max Input voltage on true open-drain pins (PC0 and PC1) VSS-0.3 - 0.3 x VDD Input voltage on any other pin VSS-0.3 - 0.3 x VDD 0.70 x VDD - VDD+0.3 Parameter (2) Input low level voltage Unit V VIH Input high level voltage (2) Input voltage on any other pin Vhys Schmitt trigger voltage hysteresis (3) I/Os - 200 - True open drain I/Os - 200 - VSS ≤ VIN ≤ VDD High sink I/Os - - 50 (5) VSS ≤ VIN ≤ VDD True open drain I/Os - - 200(5) VSS ≤ VIN ≤ VDD PA0 with high sink LED driver capability - - 200(5) 30 45 60 kΩ - 5(7) - pF Ilkg Input leakage current (4) RPU Weak pull-up equivalent resistor(2)(6) CIO I/O pin capacitance VIN = VSS - V mV nA 1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified. 2. Guaranteed by characterization results. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Not tested in production. 6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in Figure 18). 7. Capacitance per one GPIO on pin. Complete pin capacitance depends on how many GPIOs are connected on a given pin (see Table 4). The total pin capacitance is then N x CIO where N = number of GPIOs on a given pin). DS12167 Rev 7 69/94 87 Electrical parameters STM8L050J3 Figure 15. Typical VIL and VIH vs VDD (high sink I/Os) 3 -40°C 25°C 2.5 85°C VIL and VIH [V] 2 1.5 1 0.5 0 1.8 2.1 2.6 3.1 3.6 VDD [V] ai18220c Figure 16. Typical VIL and VIH vs VDD (true open drain I/Os) 3 -40°C 25°C 2.5 VIL and VIH [V] 85°C 2 1.5 1 0.5 0 1.8 2.1 2.6 VDD [V] 3.1 3.6 ai18221b 70/94 DS12167 Rev 7 STM8L050J3 Electrical parameters Figure 17. Typical pull-up resistance RPU vs VDD with VIN=VSS 60 -40°C 55 25°C Pull-up resistance [kΩ] 85°C 50 45 40 35 30 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD [V] ai18222b Figure 18. Typical pull-up current Ipu vs VDD with VIN=VSS 120 -40°C 25°C 100 Pull-up current [μA] 85°C 80 60 40 20 0 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai18223b DS12167 Rev 7 71/94 87 Electrical parameters STM8L050J3 Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 36. Output driving current (high sink ports) I/O Symbol Type Output low level voltage for an I/O pin High sink VOL (1) Parameter VOH (2) Output high level voltage for an I/O pin Conditions Min Max Unit IIO = +2 mA, VDD = 3.0 V - 0.45 V IIO = +2 mA, VDD = 1.8 V - 0.45 V IIO = +10 mA, VDD = 3.0 V - 0.7 V IIO = -2 mA, VDD = 3.0 V VDD-0.45 - V IIO = -1 mA, VDD = 1.8 V VDD-0.45 - V IIO = -10 mA, VDD = 3.0 V VDD-0.7 - V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Table 37. Output driving current (true open drain ports) Open drain I/O Symbol Type VOL (1) Parameter Output low level voltage for an I/O pin Conditions Min Max IIO = +3 mA, VDD = 3.0 V - 0.45 IIO = +1 mA, VDD = 1.8 V - Unit V 0.45 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Table 38. Output driving current (PA0 with high sink LED driver capability) IR I/O Symbol Type VOL (1) Parameter Output low level voltage for an I/O pin Conditions Min Max Unit IIO = +20 mA, VDD = 2.0 V - 0.45 V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 72/94 DS12167 Rev 7 STM8L050J3 Electrical parameters Figure 19. Typ. VOL @ VDD = 3.0 V (high sink ports) Figure 20. Typ. VOL @ VDD = 1.8 V (high sink ports) 1 0.7 -40°C 25°C 85°C 0.6 -40°C 25°C 85°C 0.5 VOL [V] VOL [V] 0.75 0.5 0.25 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 0 20 0 IOL [mA] 1 2 3 4 ai18226V2 Figure 21. Typ. VOL @ VDD = 3.0 V (true open drain ports) 5 6 7 IOL [mA] Figure 22. Typ. VOL @ VDD = 1.8 V (true open drain ports) 0.5 0.5 -40°C 25°C 85°C 0.4 0.4 -40°C 25°C 85°C 0.3 VOL [V] VOL [V] 0.3 0.2 0.2 0.1 0.1 0 0 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 ai18229V2 ai18228V2 Figure 23. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) Figure 24. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) 2 0.5 -40°C 25°C 85°C 1.75 -40°C 25°C 85°C 1.25 0.4 VDD - VOH [V] 1.5 7 IOL [mA] IOL [mA] VDD - VOH [V] 8 ai18227V2 1 0.75 0.3 0.2 0.5 0.1 0.25 0 0 0 2 4 6 8 10 12 14 16 18 20 0 IOH [mA] 1 2 3 4 5 6 7 IOH [mA] ai18231V2 ai12830V2 DS12167 Rev 7 73/94 87 Electrical parameters 8.3.8 STM8L050J3 Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 39. SPI1 characteristics Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS) (2) (2) tw(SCKH) tw(SCKL)(2) Parameter Conditions(1) Min Max Master mode 0 8 Slave mode 0 8 SPI1 clock rise and fall time Capacitive load: C = 30 pF - 30 NSS setup time Slave mode 4 x 1/fSYSCLK - NSS hold time Slave mode 80 - SCK high and low time Master mode, fMASTER = 8 MHz, fSCK= 4 MHz 105 145 Master mode 30 - Slave mode 3 - Master mode 15 - Slave mode 0 - SPI1 clock frequency tsu(MI) (2) tsu(SI)(2) Data input setup time th(MI) (2) th(SI)(2) Data input hold time ta(SO)(2)(3) Data output access time Slave mode - 3x 1/fSYSCLK tdis(SO)(2)(4) 30 - Data output disable time Slave mode (2) Data output valid time Slave mode (after enable edge) - 60 tv(MO)(2) Data output valid time Master mode (after enable edge) - 20 Slave mode (after enable edge) 15 - Master mode (after enable edge) 1 - tv(SO) th(SO)(2) th(MO)(2) Data output hold time 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z. 74/94 DS12167 Rev 7 Unit MHz ns STM8L050J3 Electrical parameters Figure 25. SPI1 timing diagram - slave mode and CPHA=0 Figure 26. SPI1 timing diagram - slave mode and CPHA=1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DS12167 Rev 7 75/94 87 Electrical parameters STM8L050J3 Figure 27. SPI1 timing diagram - master mode(1) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 76/94 DS12167 Rev 7 STM8L050J3 Electrical parameters I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 40. I2C characteristics Symbol Parameter Standard mode I2C (2) Min Fast mode I2C(1) Unit Max (2) Min (2) Max (2) tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0 - 0 900 tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - μs STOP to START condition time (bus free) 4.7 - 1.3 - μs - 400 - 400 pF tw(STO:STA) Cb Capacitive load for each bus line μs ns μs 1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz). 2. Data based on standard I2C protocol requirement, not tested in production. Note: For speeds around 200 kHz, the achieved speed can have a± 5% tolerance For other speed ranges, the achieved speed can have a± 2% tolerance The above variations depend on the accuracy of the external components used. DS12167 Rev 7 77/94 87 Electrical parameters STM8L050J3 Figure 28. Typical application with I2C bus and timing diagram 1) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 78/94 DS12167 Rev 7 STM8L050J3 8.3.9 Electrical parameters Embedded reference voltage In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 41. Reference voltage characteristics Symbol Conditions Min Typ Max. Unit Internal reference voltage consumption - - 1.4 - µA ADC sampling time when reading the internal reference voltage - - 5 10 µs Internal reference voltage buffer consumption (used for ADC) - - 13.5 25 µA Reference voltage output - 1.202(3) 1.224 1.242(3) V Internal reference voltage lowpower buffer consumption (used for comparator or output) - - 730 1200 nA IREFOUT(2) Buffer output current(4) - - - 1 µA CREFOUT Reference voltage output load - - - 50 pF tVREFINT Internal reference voltage startup time - - 2 3 ms tBUFEN(2) Internal reference voltage buffer startup time once enabled (1) - - - 10 µs Accuracy of VREFINT stored in the VREFINT_Factory_CONV byte(5) - - - ±5 mV Stability of VREFINT over temperature -40 °C ≤ TA ≤ 125 °C - 20 50 ppm/°C Stability of VREFINT over temperature 0 °C ≤ TA ≤ 50 °C - - 20 ppm/°C - - - TBD ppm IREFINT TS_VREFINT(1)(2) IBUF(2) VREFINT out ILPBUF(2) ACCVREFINT STABVREFINT STABVREFINT Parameter Stability of VREFINT after 1000 hours 1. Defined when ADC output reaches its final value ±1/2LSB 2. Data guaranteed by design. 3. Tested in production at VDD = 3 V ±10 mV. 4. To guaranty less than 1% VREFOUT deviation. 5. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy. DS12167 Rev 7 79/94 87 Electrical parameters 8.3.10 STM8L050J3 Comparator characteristics In the following table, data is guaranteed by design, not tested in production, unless otherwise specified. Table 42. Comparator 1 characteristics Min Typ Max(1) Unit Analog supply voltage 1.65 - 3.6 V Temperature range -40 - 125 °C R400K R400K value 300 400 500 R10K R10K value 7.5 10 12.5 0.6 - VDDA 1.202 1.224 1.242 - 7 10 - 3 10 Symbol VDDA TA VIN VREFINT tSTART td Parameter Comparator 1 input voltage range Internal reference voltage(2) Comparator startup time Propagation delay(3) kΩ V μs Voffset Comparator offset error - ±3 ±10 mV ICOMP1 consumption(4) - 160 260 nA Current 1. Guaranteed by characterization results. 2. Tested in production at VDD = 3 V ±10 mV. 3. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 4. Comparator consumption only. Internal reference voltage not included. Table 43. Comparator 2 characteristics Conditions Min Typ Max(1) Unit Analog supply voltage - 1.65 - 3.6 V TA Temperature range - -40 - 125 °C VIN Comparator 2 input voltage range - 0 - VDDA V Fast mode - 15 20 Slow mode - 20 20 1.65 V ≤ VDDA ≤ 2.7 V - 1.8 3.5 2.7 V ≤ VDDA ≤ 3.6 V - 2.5 6 1.65 V ≤ VDDA ≤ 2.7 V - 0.8 2 2.7 V ≤ VDDA ≤ 3.6 V - 1.2 4 - - ±4 ±20 Fast mode - 3.5 5 Slow mode - 0.5 2 Symbol VDDA tSTART td slow td fast 80/94 Parameter Comparator startup time Propagation delay in slow mode(2) Propagation delay in fast mode(2) Voffset Comparator offset error ICOMP2 Current consumption(3) DS12167 Rev 7 μs mV μA STM8L050J3 Electrical parameters 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. 8.3.11 12-bit ADC1 characteristics In the following table, data is guaranteed by design, not tested in production. Table 44. ADC1 characteristics Symbol Parameter VDDA Analog supply voltage VREF+ Reference supply voltage VREFIVDDA IVREF+ Conditions 2.4 V ≤ VDDA ≤ 3.6 V Min Typ Max Unit 1.8 - 3.6 V 2.4 - VDDA V 1.8 V ≤ VDDA ≤ 2.4 V VDDA V Lower reference voltage - VSSA V Current on the VDDA input pin - - - - Current on the VREF+ input pin 1000 400 - - 1450 µA 700 (peak)(1) µA 450 (average)(1) µA VAIN Conversion voltage range - 0(2) - VREF+ - TA Temperature range - -40 - 125 °C RAIN External resistance on VAIN on other channels - - 50(3) kΩ CADC Internal sample and hold capacitor on other channels - 16 - pF 2.4 V ≤ VDDA ≤ 3.6 V without zooming 0.320 - 16 MHz 1.8 V ≤ VDDA ≤ 2.4 V with zooming 0.320 - 8 MHz VAIN on all other channels - - 760 kHz fADC ADC sampling clock frequency fCONV 12-bit conversion rate fTRIG External trigger frequency - - - tconv 1/fADC tLAT External trigger latency - - - 3.5 1/fSYSCLK VAIN on channels VDDA < 2.4 V 0.86 - - µs VAIN on channels 2.4 V ≤ VDDA ≤ 3.6 V 0.41 - - µs tS Sampling time DS12167 Rev 7 81/94 87 Electrical parameters STM8L050J3 Table 44. ADC1 characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - 12 + tS 1/fADC 16 MHz 1 µs tconv 12-bit conversion time tWKUP Wakeup time from OFF state - - - 3 µs tIDLE Time before a new conversion - - - ∞ ms tVREFINT Internal reference voltage startup time - - - refer to Table 41 ms 1. The current consumption through VREF is composed of two parameters: - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses. So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at 1Msps 2. VREF- or VSSA must be tied to ground. 3. Guaranteed by design. 82/94 DS12167 Rev 7 STM8L050J3 Electrical parameters In the following three tables, data is guaranteed by characterization result, not tested in production. Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V Symbol Parameter Conditions Typ Max 1 1.6 Differential non linearity fADC = 8 MHz 1 1.6 fADC = 4 MHz 1 1.5 fADC = 16 MHz 1.2 2 fADC = 8 MHz 1.2 1.8 fADC = 4 MHz 1.2 1.7 fADC = 16 MHz 2.2 3.0 fADC = 8 MHz 1.8 2.5 fADC = 4 MHz 1.8 2.3 fADC = 16 MHz 1.5 2 fADC = 8 MHz 1 1.5 fADC = 4 MHz 0.7 1.2 1 1.5 fADC = 16 MHz DNL INL TUE Offset Integral non linearity Total unadjusted error Offset error fADC = 16 MHz Gain Gain error fADC = 8 MHz Unit LSB LSB fADC = 4 MHz Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V Symbol Parameter Typ Max Unit 1 2 LSB 1.7 3 LSB DNL Differential non linearity INL Integral non linearity TUE Total unadjusted error 2 4 LSB Offset Offset error 1 2 LSB Gain Gain error 1.5 3 LSB Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 LSB INL Integral non linearity 2 3 LSB TUE Total unadjusted error 3 5 LSB Offset Offset error 2 3 LSB Gain Gain error 2 3 LSB DS12167 Rev 7 83/94 87 Electrical parameters STM8L050J3 Figure 29. ADC1 accuracy characteristics Figure 30. Typical connection diagram using the ADC STM8 VDD Sample and hold ADC converter VT 0.6V (1) RAIN Cparasitic (2) VAIN RADC AINx VT 0.6V 12-bit converter CADC(1) I L± 50nA ai17090f 1. Refer to Table 48 for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value downgrades the conversion accuracy. To remedy this, fADC should be reduced. Figure 31. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700 μA 300 μA MS46324V1 84/94 DS12167 Rev 7 STM8L050J3 Electrical parameters Table 48. RAIN max for fADC = 16 MHz(1) RAIN max (kohm) Ts (cycles) Ts (µs) Slow channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 9 0.5625 0.8 Not allowed 16 1 2.0 0.8 24 1.5 3.0 1.8 48 3 6.8 4.0 96 6 15.0 10.0 192 12 32.0 25.0 384 24 50.0 50.0 1. Guaranteed by design. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 32. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip. Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA) STM8L VREF+/VDDA Supply 1 μF // 10 nF VREF-/VSSA ai17032d DS12167 Rev 7 85/94 87 Electrical parameters 8.3.12 STM8L050J3 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). • ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 49. EMS data Symbol Parameter Conditions VFESD VDD = 3.3 V, TA = +25 °C, Voltage limits to be applied on any I/O pin to induce a functional fCPU= 16 MHz, disturbance conforms to IEC 61000 VEFTB Fast transient voltage burst limits Using HSI VDD = 3.3 V, TA = +25 °C, to be applied through 100 pF on fCPU = 16 MHz, VDD and VSS pins to induce a Using HSE conforms to IEC 61000 functional disturbance Level/ Class 3B 4A 2B Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC61967-2 which specifies the board and the loading of each pin. 86/94 DS12167 Rev 7 STM8L050J3 Electrical parameters Table 50. EMI data (1) Symbol Parameter SEMI VDD = 3.6 V, TA = +25 °C, SO8N conforming to IEC61967-2 Peak level Monitored frequency band Conditions Max vs. Unit 16 MHz 0.1 MHz to 30 MHz -3 30 MHz to 130 MHz 9 130 MHz to 1 GHz 4 SAE EMI Level 2 dBμV - 1. Not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and charge device model. This test conforms to the JESD22-A114A/A115A standard. Table 51. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charge device model) Maximum value (1) Unit 2000 TA = +25 °C V 500 1. Guaranteed by characterization results. Static latch-up • LU: 3 complementary static tests are required on 6 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 52. Electrical sensitivities Symbol LU Parameter Static latch-up class DS12167 Rev 7 Class II 87/94 87 Package characteristics 9 STM8L050J3 Package characteristics Failure analysis and guarantee The small number of pins available induces limitations on failure analysis depth in case of isolated symptoms, typically with an impact lower than 0.1%. Contact your sales office for additional information for any failure analysis. STMicroelectronics makes a feasibility study for investigation based on failure rate and symptom description prior to responsibility endorsement. 9.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.2 SO8N package information Figure 33. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline h x 45˚ A A2 c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 A1 L L1 SO-A_V2 1. Drawing is not to scale. Table 53. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol 88/94 Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 DS12167 Rev 7 STM8L050J3 Package characteristics Table 53. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 34. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint 3.9 6.7 0.6 (x8) 1.27 O7_FP_V1 1. Dimensions are expressed in millimeters. DS12167 Rev 7 89/94 92 Package characteristics STM8L050J3 Device marking for SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 35. Example of SO8N marking (package top view) Product identification 8L050J3 R Y WW Date code Unmarkable surface PIN1 reference Additional information MSv46320V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 90/94 DS12167 Rev 7 STM8L050J3 9.3 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 50. The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x ΘJA) Where: • TAmax is the maximum ambient temperature in °C • ΘJA is the package junction-to-ambient thermal resistance in °C/W • PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) • PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. • PI/Omax represents the maximum power dissipation on output pins Where: PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*I OH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Table 54. Thermal characteristics(1) Symbol ΘJA Parameter Thermal resistance junction-ambient SO8N Value Unit 102 °C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. DS12167 Rev 7 91/94 92 Ordering information 10 STM8L050J3 Ordering information Figure 36. Low density value line STM8L050J3 ordering information scheme Example: STM8 L 050 J 3 M 3 Product class STM8 microcontroller Family type L = Low power Sub-family type 050 = Low density Pin count J = 8 pins Program memory size 3 = 8 Kbytes Package M = SO8N Temperature range 3 = – 40 to 125 °C For a list of available options (for example memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST sales office nearest to you. 92/94 DS12167 Rev 7 STM8L050J3 11 Revision history Revision history Table 55. Document revision history Date Revision 06-Jun-2017 1 Initial release. 04-Oct-2017 2 Updated: – Document’s classification to “Public” – Section 1: Introduction – Section 3.1: Low-power modes – Section 3.2.2: Interrupt controller – Section 3.3.3: Voltage regulator – Section 3.14.1: SPI – Section 3.14.3: USART – Table 4: STM8L050J3 pin description – Note 3 on page 26 – Section 4.1: System configuration options 04-Jul-2018 3 Updated: – Recommendations for SWIM pin (pin#1) sharing on Section 3.16: Development support 4 Updated: – Table 42: Comparator 1 characteristics – Table 43: Comparator 2 characteristics – Table 44: ADC1 characteristics 5 Updated: – Table 49: EMS data – Table 50: EMI data – Table 51: ESD absolute maximum ratings 12-Sep-2018 30-Jul-2020 Changes Deleted: – Figure Typical HSI frequency vs VDD 07-Sep-2020 6 Updated: – Table 30: HSI oscillator characteristics 31-Jan-2022 7 Updated Port C rows on Table 6: I/O port hardware register map DS12167 Rev 7 93/94 93 STM8L050J3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved 94/94 DS12167 Rev 7