STM8L052C6
Value Line, 8-bit ultra-low-power MCU, 32-KB Flash, 256-byte data
EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC
Datasheet - production data
Features
Operating conditions
– Operating power supply: 1.8 V to 3.6 V
– Temperature range: -40 °C to 85 °C
Low-power features
– Five low-power modes: Wait, Low-power
run (5.1 µA), Low-power wait (3 µA), Activehalt with full RTC (1.3 µA), Halt (350 nA)
– Consumption: 195 µA/MHz + 440 µA
– Ultra-low leakage per I/0: 50 nA
– Fast wakeup from Halt: 4.7 µs
Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq. 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
Reset and supply management
– Low-power, ultra-safe BOR reset with five
selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
Clock management
– 32 kHz and 1 to 16 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– Internal 38 kHz low consumption RC
– Clock security system
Low-power RTC
– BCD calendar with alarm interrupt
– Auto-wakeup from Halt w/ periodic interrupt
LCD: up to 4x28 segments w/ step-up
converter
Memories
– 32 KB Flash program memory and
256 bytes data EEPROM with ECC, RWW
– Flexible write and read protection modes
– 2 Kbytes of RAM
March 2015
This is information on a product in full production.
LQFP48
7 x 7 mm
DMA
– Four channels supporting ADC, SPI, I2C,
USART, timers
– One channel for memory-to-memory
12-bit ADC up to 1 Msps/25 channels
– Internal reference voltage
Timers
– Two 16-bit timers with two channels (used
as IC, OC, PWM), quadrature encoder
– One 16-bit advanced control timer with three
channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– Two watchdogs: one Window, one
Independent
– Beeper timer with 1-, 2- or 4-kHz
frequencies
Communication interfaces
– Synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– USART (ISO 7816 interface and IrDA)
Up to 41 I/Os, all mappable on interrupt vectors
Development support
– Fast on-chip programming and nonintrusive debugging with SWIM
– Bootloader using USART
DocID023331 Rev 2
1/103
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Contents
STM8L052C6
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Advanced STM8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Low-power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10
System configuration controller and routing interface . . . . . . . . . . . . . . . 19
3.11
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
2/103
3.2.1
3.11.1
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.2
16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.3
8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.1
Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.2
Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2
I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID023331 Rev 2
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Contents
3.14.3
4
3.15
Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
5
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 56
8.3.3
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.3.4
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.6
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.7
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.3.8
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.3.9
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.3.10
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.3.11
12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3.12
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DocID023331 Rev 2
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Contents
9
STM8L052C6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.1
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4/103
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Medium-density value line STM8L052C6 low-power device features and
peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Medium-density value line STM8L052C6pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56
Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption and timing in Low power run mode at VDD = 1.8 V
to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 63
Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 64
Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 65
Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 66
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 78
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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List of tables
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
6/103
STM8L052C6
ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 99
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
DocID023331 Rev 2
STM8L052C6
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Medium-density value line STM8L052C6 device block diagram . . . . . . . . . . . . . . . . . . . . 12
Medium-density value line STM8L052C6 clock tree diagram . . . . . . . . . . . . . . . . . . . . . . 17
STM8L052C6 48-pin LQFP48 package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical VIL and VIH vs. VDD (high sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 94
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 94
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 100
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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7
Introduction
1
STM8L052C6
Introduction
This document describes the features, pinout, mechanical data and ordering information of
the medium-density value line STM8L052C6 microcontroller with 32-Kbyte Flash memory
density. For further details on the whole STMicroelectronics medium-density family please
refer to Section 2.2: Ultra-low-power continuum.
For detailed information on device operation and registers, refer to the reference manual
(RM0031).
For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
Medium density value line devices provide the following benefits:
Integrated system
–
32 Kbytes of medium-density embedded Flash program memory
–
256 bytes of data EEPROM
–
2 Kbytes of RAM
–
Internal high-speed and low-power low-speed RC
–
Embedded reset
Ultra-low-power consumption
–
195 µA/MHZ + 440 µA (consumption)
–
0.9 µA with LSI in Active-halt mode
–
Clock gated system and optimized power management
–
Capability to execute from RAM for low-power wait mode and low-power-run
mode
Advanced features
–
Up to 16 MIPS at 16 MHz CPU clock frequency
–
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals
–
Wide choice of development tools
These features make the value line STM8L05xxx ultra-low-power microcontroller family
suitable for a wide range of consumer and mass market applications.
Refer to Table 1: Medium-density value line STM8L052C6 low-power device features and
peripheral counts and Section 3: Functional overview for an overview of the complete range
of peripherals proposed in this family.
Figure 1 shows the block diagram of the medium-density value line STM8L052C6 device.
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STM8L052C6
2
Description
Description
The medium-density value line STM8L052C6 devices are members of the STM8L ultra-lowpower 8-bit family.
The value line STM8L05xxx ultra-low-power family features the enhanced STM8 CPU core
providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-application debugging and ultra-fast Flash programming.
Medium-density value line STM8L052C6 microcontrollers feature embedded data EEPROM
and low-power, low-voltage, single-supply program Flash memory.
All devices offer 12-bit ADC, real-time clock, 16-bit timers, one 8-bit timer as well as
standard communication interface such as SPI, I2C, USART and 4x28-segment LCD. The
4x 28-segment LCD is available on the medium-density value line STM8L052C6.
The STM8L052C6 operates from 1.8 V to 3.6 V and is available in the -40 to +85 °C
temperature range.
The modular design of the peripheral set allows the same peripherals to be found in
different ST microcontroller families including 32-bit families. This makes any transition to a
different family very easy, and simplified even more by the use of a common set of
development tools.
All value line STM8L ultra-low-power products are based on the same architecture with the
same memory mapping and a coherent pinout.
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48
Description
2.1
STM8L052C6
Device overview
Table 1. Medium-density value line STM8L052C6 low-power device features and
peripheral counts
Features
STM8L052C6
Flash (Kbytes)
32
Data EEPROM (bytes)
256
RAM (Kbytes)
2
LCD
Timers
4x28
Basic
1
(8-bit)
General purpose
2
(16-bit)
Advanced control
1
(16-bit)
SPI
Communication
I2C
interfaces
USART
1
1
1
GPIOs
41(1)
12-bit synchronized ADC
(number of channels)
1
(25)
Others
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC,
1- to 16-MHz and 32-kHz external oscillator
CPU frequency
16 MHz
Operating voltage
1.8 V to 3.6 V
Operating temperature
-40 to +85 °C
Package
LQFP48
1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).
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STM8L052C6
2.2
Description
Ultra-low-power continuum
The ultra-low-power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software
and feature compatible. Besides the full compatibility within the STM8L family, the devices
are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.
Note:
1
The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.
2
The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM® Cortex®-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very
easy migration from one family to another:
Analog peripheral: ADC1
Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L and STM32L devices use a
common architecture:
Same power supply range from 1.8 to 3.6 V
Architecture optimized to reach ultra-low consumption both in low power modes and
Run mode
Fast startup strategy from low power modes
Flexible system clock
Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on
reset, power-down reset, brownout reset and programmable voltage detector
Features
ST ultra-low-power continuum also lies in feature compatibility:
More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
Memory density ranging from 4 to 128 Kbytes
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48
Functional overview
3
STM8L052C6
Functional overview
Figure 1. Medium-density value line STM8L052C6 device block diagram
OSC_IN,
OSC_OUT
16 MHz internal RC
OSC32_IN,
OSC32_OUT
@VDD
1-16 MHz oscillator
32 kHz oscillator
Clock
controller
and
CSS
38 kHz internal RC
VDD18
Clocks
to core and
peripherals
Interrupt controller
Debug module
(SWIM)
BOR
16-bit Timer 2
2 channels
16-bit Timer 3
3 channels
16-bit Timer 1
8-bit Timer 4
Infrared interface
DMA1
(4 channels)
SCL, SDA,
SMB
I²C1
MOSI, MISO,
SCK, NSS
SPI1
RX, TX, CK
VDDA
VSSA
ADC1_INx
VREF+
VREF-
RESET
POR/PDR
2 channels
IR_TIM
VOLT. REG.
STM8 Core
USART1
PVD
Address, control and data buses
SWIM
Power
@VDDA/VSSA
12-bit ADC1
VREFINT out
Internal reference
voltage
VLCD = 2.5 V to
3.6 V
LCD booster
VDD1 =1.8 V
to 3.6 V
VSS1
NRST
PVD_IN
32 Kbytes
program memory
256 bytes
data EEPROM
2 Kbytes RAM
Port A
PA[7:0]
Port B
PB[7:0]
Port C
PC[7:0]
Port D
PD[7:0]
Port E
PE[7:0]
Port F
PF0
Beeper
BEEP
RTC
ALARM, CALIB
IWDG
(38 kHz clock)
WWDG
LCD driver
4x28
1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
LCD: Liquid crystal display
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
IWDG: independent watchdog
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SEGx, COMx
STM8L052C6
3.1
Functional overview
Low-power modes
The medium-density value line STM8L052C6 supports five low power modes to achieve the
best compromise between low power consumption, short startup time and available wakeup
sources:
Wait mode: The CPU clock is stopped, but selected peripherals keep running. An
internal or external interrupt, event or a Reset can be used to exit the microcontroller
from Wait mode (WFE or WFI mode).
Low power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the
system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
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48
Functional overview
STM8L052C6
3.2
Central processing unit STM8
3.2.1
Advanced STM8 core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains six internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64-Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
3.2.2
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Interrupt controller
The medium-density value line STM8L052C6 features a nested vectored interrupt
controller:
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Nested interrupts with 3 software priority levels
32 interrupt vectors with hardware priority
Up to 40 external interrupt sources on 11 vectors
Trap and reset interrupts
DocID023331 Rev 2
STM8L052C6
Functional overview
3.3
Reset and supply management
3.3.1
Power supply scheme
The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
VSS1 ; VDD1 = 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.
Provided externally through VDD1 pins, the corresponding ground pin is VSS1.
3.3.2
VSSA ; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals. VDDA and
VSSA must be connected to VDD1 and VSS1, respectively.
VSS2 ; VDD2 = 1.8 to 3.6 V: external power supplies for I/Os. VDD2 and VSS2 must be
connected to VDD1 and VSS1, respectively.
VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains
under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need
for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The medium-density value line STM8L052C6 embeds an internal voltage regulator for
generating the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes
Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and
Low power wait modes
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
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48
Functional overview
3.4
STM8L052C6
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
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Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock sources: 4 different clock sources can be used to drive the system
clock:
–
1-16 MHz High speed external crystal (HSE)
–
16 MHz High speed internal RC oscillator (HSI)
–
32.768 kHz Low speed external crystal (LSE)
–
38 kHz Low speed internal RC (LSI)
RTC and LCD clock sources: The above four sources can be chosen to clock the
RTC and the LCD, whatever the system clock.
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If a HSE
clock failure occurs, the system clock is automatically switched to HSI.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
DocID023331 Rev 2
STM8L052C6
Functional overview
Figure 2. Medium-density value line STM8L052C6 clock tree diagram
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