STM8L162M8 STM8L162R8
8-bit ultra-low-power MCU, 64 KB Flash, 2 KB data EEPROM, RTC,
AES, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, COMPs
Datasheet - production data
Features
Operating conditions
– Operating power supply: 1.65 to 3.6 V
(without BOR), 1.8 to 3.6 V (with BOR)
– Temp. range: -40 to 85, 105 or 125 °C
Low-power features
– 5 low-power modes: Wait, Low-power run,
Low-power wait, Active-halt with full RTC,
Halt
– Ultra low leakage per I/0: 50 nA
– Fast wake up from Halt mode: 5 µs
Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq: 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
Reset and supply management
– Low-power, ultra safe BOR reset with five
selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
Clock management
– 32 kHz and 1-16 MHz crystal oscillators
– Internal 16 MHz factory-trimmed RC and
38 kHz low consumption RC
– Clock security system
Low-power RTC
– BCD calendar with alarm interrupt,
– Digital calibration with +/- 0.5ppm accuracy
– LSE security system
– Auto wake up from Halt w/periodic interrupt
– Advanced anti-tamper detection
LCD: 8x40 or 4x44 w/ step-up converter
DMA
– 4 ch. for ADC, AES, DACs, SPIs, I2C,
USARTs, Timers, 1 ch. for memory-tomemory
LQFP80
14 x 14 mm
LQFP64
10 x 10 mm
2x12-bit DAC (dual mode) with output buffer
12-bit ADC up to 1 Msps/28 channels
– Temp. sensor and internal ref. voltage
Memories
– Up to 64 KB of Flash memory with up to 2
KB of data EEPROM with ECC and RWW
– Flexible write/read protection modes
– Up to 4 KB of RAM
2 ultra-low-power comparators
– 1 with fixed threshold and 1 rail to rail
– Wake up capability
Timers
– Three 16-bit timers with 2 channels (IC,
OC, PWM), quadrature encoder
– One 16-bit advanced control timer with 3
channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– One window, one independent watchdog
– Beeper timer with 1, 2 or 4 kHz frequencies
Communication interfaces
– Two synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– Three USARTs (ISO 7816 interface + IrDA)
Up to 67 I/Os, all mappable on interrupt vectors
Up to 16 capacitive sensing channels
supporting touchkey, proximity, linear touch
and rotary touch sensors
Fast on-chip programming and non-intrusive
debugging with SWIM, Bootloader using
USART
96-bit unique ID
AES encryption hardware accelerator
February 2015
This is information on a product in full production.
DocID17959 Rev 4
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Contents
STM8L162M8 STM8L162R8
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
STM8L ultra-low-power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Low-power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10
Digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11
Ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
System configuration controller and routing interface . . . . . . . . . . . . . . . 20
3.13
Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16
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3.2.1
3.15.1
16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.2
16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . . 21
3.15.3
8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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3.16.1
Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16.2
Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.18
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.18.1
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.18.2
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.18.3
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.19
Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.20
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.3.2
Embedded reset and power control block characteristics
9.3.3
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3.4
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.3.6
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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9.4
10
9.3.7
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.8
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.3.9
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.3.10
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3.11
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9.3.12
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9.3.13
12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9.3.14
12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.3.15
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.1
LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.2
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
11
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
High-density STM8L162x8 low-power device features and peripheral counts . . . . . . . . . . 10
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8L162x8 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 65
Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Total current consumption and timing in Low-power run mode at VDD = 1.65 V to 3.6 V . 74
Total current consumption in Low-power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 76
Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 80
Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 81
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 94
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
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Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 110
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data. . . . . . . . . 119
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DocID17959 Rev 4
STM8L162M8 STM8L162R8
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
High-density STM8L162x8 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM8L162M8 80-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L162R8 64-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz . . . . . . . . . . . . . . . 70
Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz . . . . . . . . . . . . . . 70
Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz . . . . . . . . . . . . . . 73
Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . 73
Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 75
Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . 77
Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 81
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI1 timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 112
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 112
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 116
LQFP80 14 x 14 mm low-profile quad flat package footprint . . . . . . . . . . . . . . . . . . . . . . 117
LQFP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 119
LQFP64, 10 x 10 mm low-profile quad flat package footprint . . . . . . . . . . . . . . . . . . . . . . 120
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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7
Introduction
1
STM8L162M8 STM8L162R8
Introduction
This document describes the features, pinout, mechanical data and ordering information for
STM8L162R8 and STM8L162M8 devices.
For further details on the STMicroelectronics ultra-low-power family please refer to
Section 2.3: Ultra-low-power continuum on page 11.
For detailed information on device operation and registers, refer to the reference manual
(RM0031).
For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
2
Description
The high-density STM8L162x8 ultra-low-power devices feature an enhanced STM8 CPU
core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low-power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive in-application debugging and ultrafast Flash programming.
All high-density STM8L162x8 microcontrollers feature embedded data EEPROM and lowpower low-voltage single-supply program Flash memory.
The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit
ADC, two DACs, two comparators, a real-time clock, AES, 8x40 or 4x44-segment LCD, four
16-bit timers, one 8-bit timer, as well as standard communication interfaces such as two
SPIs, an I2C interface, and three USARTs. The modular design of the peripheral set allows
the same peripherals to be found in different ST microcontroller families including 32-bit
families. This makes any transition to a different family very easy, and simplified even more
by the use of a common set of development tools.
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STM8L162M8 STM8L162R8
2.1
Description
STM8L ultra-low-power 8-bit family benefits
High-density STM8L162x8 devices are part of the STM8L ultra-low-power family providing
the following benefits:
Integrated system
–
64 Kbytes of high-density embedded Flash program memory
–
2 Kbytes of data EEPROM
–
4 Kbytes of RAM
–
Internal high-speed and low-power low speed RC.
–
Embedded reset
ultra-low-power consumption
–
1 µA in Active-halt mode
–
Clock gated system and optimized power management
–
Capability to execute from RAM for Low-power wait mode and Low-power run
mode
Advanced features
–
Up to 16 MIPS at 16 MHz CPU clock frequency
–
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access.
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
–
Wide choice of development tools
STM8L ultra-low-power microcontrollers can operate either from 1.8 to 3.6 V (down to
1.65 V at power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40
to +125 °C temperature ranges.
These features make the STM8L ultra-low-power microcontroller families suitable for a wide
range of applications:
Medical and handheld equipment
Application control and user interface
PC peripherals, gaming, GPS and sport equipment
Alarm systems, wired and wireless sensors
Metering
The devices are offered in four different packages from 48 to 80 pins. Different sets of
peripherals are included depending on the device. Refer to Section 3 for an overview of the
complete range of peripherals proposed in this family.
All STM8L ultra-low-power products are based on the same architecture with the same
memory mapping and a coherent pinout.
Figure 1 shows the block diagram of the High-density STM8L162x8 families.
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56
Description
2.2
STM8L162M8 STM8L162R8
Device overview
Table 1. High-density STM8L162x8 low-power device features and peripheral counts
Features
STM8L162R8
STM8L162M8
Flash (Kbytes)
64
64
Data EEPROM (Kbytes)
2
2
RAM (Kbytes)
4
4
AES
1
1
LCD
8x36 or 4x40
8x40 or 4x44
Basic
1
(8-bit)
1
(8-bit)
General purpose
3
(16-bit)
3
(16-bit)
Advanced control
1
(16-bit)
1
(16-bit)
SPI
2
2
I2C
1
1
USART
3
3
GPIOs
54(1)
68(1)
12-bit synchronized ADC
(number of channels)
1
(28)
1
(28)
Number of channels
2
2
2
2
Comparators (COMP1/COMP2)
2
2
Timers
Communicatio
n interfaces
12-Bit DAC
Others
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz
external oscillator
CPU frequency
Operating voltage
Operating temperature
Packages
16 MHz
1.8 to 3.6 V (down to 1.65 V at power-down) with BOR
1.65 to 3.6 V without BOR
40 to +85 °C / 40 to +125 °C
LQFP64
LQFP80
1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).
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STM8L162M8 STM8L162R8
2.3
Description
Ultra-low-power continuum
The ultra-low-power STM8L151x6/8, STM8L152x6/8 and STM8L162x8 are fully pin-to-pin,
software and feature compatible. Besides the full compatibility within the family, the devices
are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes
STM8L101 line, STM8L151/152 lines, and STM8L162 line. The STM8L and STM32L
families allow a continuum of performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultra low-leakage process.
Note:
1
The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices.
2
The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15xx documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM® Cortex®-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L162x8 and STM32L15xxx share identical peripherals which ensure a very easy
migration from one family to another:
Analog peripherals: ADC1, DAC1/DAC2, and comparators COMP1/COMP2
Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L162x8 and STM32L1xxxx devices
use a common architecture:
Same power supply range from 1.65 to 3.6 V. For STM8L101xx and medium-density
STM8L15xxx, the power supply must be above 1.8 V at power-on, and go below 1.65 V
at power-down.
Architecture optimized to reach ultra low consumption both in low-power modes and
Run mode
Fast startup strategy from low-power modes
Flexible system clock
Ultra safe reset: same reset strategy for both STM8L162x8 and STM32L1xxxx
including power-on reset, power-down reset, brownout reset and programmable
voltage detector.
Features
STMicroelectronics ultra-low-power continuum also lies in feature compatibility:
More than 10 packages with pin counts from 20 to 100 pins and size down to 3 x 3 mm
Memory density ranging from 4 to 128 Kbytes
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56
Functional overview
3
STM8L162M8 STM8L162R8
Functional overview
Figure 1. High-density STM8L162x8 device block diagram
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1. Legend:
AF: alternate function
ADC: Analog-to-digital converter
AES: Advanced encryption standard hardware accelerator
BOR: Brownout reset
DMA: Direct memory access
DAC: Digital-to-analog converter
I²C: Inter-integrated circuit multimaster interface
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STM8L162M8 STM8L162R8
Functional overview
IWDG: Independent watchdog
LCD: Liquid crystal display
POR/PDR: Power on reset / power-down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
3.1
Low-power modes
The high-density STM8L162x8 devices support five low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal
or external interrupt or a Reset can be used to exit the microcontroller from Wait mode
(WFE or WFI mode).
Low-power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.
The microcontroller enters Low-power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
Low-power wait mode: This mode is entered when executing a Wait for event in Lowpower run mode. It is similar to Low-power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an
event, the system goes back to Low-power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
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56
Functional overview
STM8L162M8 STM8L162R8
3.2
Central processing unit STM8
3.2.1
Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16 Mbyte linear memory space
16-bit stack pointer - access to a 64 Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
3.2.2
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Interrupt controller
The high-density STM8L162x8 devices feature a nested vectored interrupt controller:
14/125
Nested interrupts with 3 software priority levels
32 interrupt vectors with hardware priority
Up to 40 external interrupt sources on 11 vectors
Trap and reset interrupts
DocID17959 Rev 4
STM8L162M8 STM8L162R8
Functional overview
3.3
Reset and supply management
3.3.1
Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
3.3.2
VSS1, VDD1, VSS2, VDD2, VSS3, VDD3, VSS4, VDD4= 1.65 to 3.6 V: external power supply
for I/Os and for the internal regulator. Provided externally through VDD pins, the
corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3/VDD4
must not be left unconnected.
VSSA, VDDA = 1.65 to 3.6 V: external power supplies for analog peripherals (minimum
voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must
be connected to VDD and VSS, respectively.
VREF+, VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
VREF+ (for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided
externally through VREF+.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR). For the device sales types without the “D” option (see Section 11: Ordering
information scheme), it is coupled with a brownout reset (BOR) circuitry. It that case the
device operates between 1.8 and 3.6 V, BOR is always active and ensures proper operation
starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading
process starts, either to confirm or modify default thresholds, or to disable BOR permanently
(in which case, the VDD min. value at power-down is 1.65 V).
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains in
reset state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for
any external reset circuit.
Note:
For device sales types with the “D” option (see Section 11: Ordering information scheme)
BOR is permanently disabled and the device operates between 1.65 and 3.6 V. In this case
it is not possible to enable BOR through the option bytes.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
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Functional overview
3.3.3
STM8L162M8 STM8L162R8
Voltage regulator
The high-density STM8L162x8 devices embed an internal voltage regulator for generating
the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
Low-power voltage regulator mode (LPVR) for Halt, Active-halt, Low-power run and
Low-power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
3.4
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness.
Features
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Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock sources: 4 different clock sources can be used to drive the system
clock:
–
1-16 MHz High speed external crystal (HSE)
–
16 MHz High speed internal RC oscillator (HSI)
–
32.768 Low speed external crystal (LSE)
–
38 kHz Low speed internal RC (LSI)
RTC and LCD clock sources: the above four sources can be chosen to clock the RTC
and the LCD, whatever the system clock.
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If a HSE
clock failure occurs, the system clock is automatically switched to HSI.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
DocID17959 Rev 4
STM8L162M8 STM8L162R8
Functional overview
Figure 2. Clock tree diagram
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LSE crystal/ceramic resonator oscillator
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 31. LSE oscillator characteristics
Symbol
Parameter
fLSE
Low speed external oscillator
frequency
RF
Feedback resistor
C(1)(2)
IDD(LSE)
(4)
Min.
V = 200 mV
Recommended load capacitance
LSE oscillator power consumption
Startup time
Typ.
Max.
Unit
32.768
kHz
1.2
M
8
pF
VDD = 1.8 V
450
VDD = 3 V
600
VDD = 3.6 V
750
nA
3(3)
Oscillator transconductance
gm
tSU(LSE)
Conditions
VDD is stabilized
µA/V
1
s
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details.
3. Guaranteed by design. Not tested in production.
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
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Electrical parameters
STM8L162M8 STM8L162R8
Figure 18. LSE oscillator circuit diagram
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Internal clock sources
Subject to general operating conditions for VDD, and TA.
High speed internal RC oscillator (HSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 32. HSI oscillator characteristics
Symbol
fHSI
ACCHSI
TRIM
Conditions(1)
Parameter
Frequency
Accuracy of HSI
oscillator (factory
calibrated)
HSI user trimming
step(3)
Min.
VDD = 3.0 V
Typ.
Max.
16
(2)
Unit
MHz
%
VDD = 3.0 V, TA = 25 °C
-1
VDD = 3.0 V, 0 °C TA 55 °C
-1.5
1.5
%
VDD = 3.0 V, -10 °C TA 70 °C
-2
2
%
VDD = 3.0 V, -10 °C TA 85 °C
-2.5
2
%
VDD = 3.0 V, -10 °C TA 125 °C
-4.5
2
%
1.65 V VDD 3.6 V,
-40 °C TA 125 °C
-4.5
3
%
0.7
%
± 1.5
%
Trimming code multiple of 16
1
(2)
0.4
Trimming code = multiple of 16
tsu(HSI)
HSI oscillator setup
time (wakeup time)
3.7
6 (4)
µs
IDD(HSI)
HSI oscillator power
consumption
100
140(4)
µA
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Tested in production.
3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.
4. Guaranteed by design, not tested in production
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Electrical parameters
Figure 19. Typical HSI frequency vs. VDD
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Low speed internal RC oscillator (LSI)
In the following table, data are based on characterization results, not tested in production.
Table 33. LSI oscillator characteristics
Symbol
fLSI
Conditions(1)
Parameter
Frequency
tsu(LSI)
LSI oscillator wakeup time
D(LSI)
LSI oscillator frequency
drift(3)
0 °C TA 85 °C
Min.
Typ.
Max.
Unit
26
38
56
kHz
200(2)
µs
11
%
-12
1. VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified.
2. Guaranteed by Design, not tested in production.
3. This is a deviation for an individual part, once the initial frequency has been measured.
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STM8L162M8 STM8L162R8
Figure 20. Typical LSI clock source frequency vs. VDD
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9.3.5
Memory characteristics
TA = -40 to 125 °C unless otherwise specified.
Table 34. RAM and hardware registers
Symbol
VRM
Parameter
Data retention mode
(1)
Conditions
Min.
Typ.
Max.
Unit
Halt mode (or Reset)
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.
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Electrical parameters
Flash memory
Table 35. Flash program and data EEPROM memory
Symbol
VDD
Parameter
Operating voltage
(all modes, read/write/erase)
Conditions
Min.
fSYSCLK = 16 MHz
1.65
-
-
Programming time for 1 or 128 bytes (block)
erase/write cycles (on programmed byte)
tprog
Iprog
tRET(2)
6
Max.
(1)
Unit
3.6
V
ms
Programming time for 1 to 128 bytes (block)
write cycles (on erased byte)
-
-
TA+25 °C, VDD = 3.0 V
-
TA+25 °C, VDD = 1.8 V
-
Data retention (program memory) after 10000
erase/write cycles at TA+85 °C
(6 suffix)
TRET+85 °C
30(1)
-
-
Data retention (program memory) after 10000
erase/write cycles at TA+125 °C
(3 suffix)
TRET+125 °C
5(1)
-
-
Programming/ erasing consumption
3
-
0.7
mA
-
years
Data retention (data memory) after 300000
erase/write cycles at TA+85 °C
(6 suffix)
TRET+85 °C
30(1)
-
-
Data retention (data memory) after 300000
erase/write cycles at TA+125 °C
(3 suffix)
TRET+125 °C
5(1)
-
-
TA+85 °C
(6 suffix),
TA+105 °C
(7 suffix) or
TA+125 °C
(3 suffix)
10(1)
-
-
-
-
Erase/write cycles (program memory)
NRW (3)
Typ.
Erase/write cycles (data memory)
300(1)
(4)
kcycles
1. Data based on characterization results, not tested in production.
2. Conforming to JEDEC JESD22a117
3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.
4. Data based on characterization performed on the whole data memory.
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9.3.6
STM8L162M8 STM8L162R8
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 36. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
9.3.7
Description
Negative
injection
Positive
injection
Injected current on true open-drain pins
-5
+0
Injected current on all 5 V tolerant (FT) pins
-5
+0
Injected current on any other pin
-5
+5
Unit
mA
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
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Electrical parameters
Table 37. I/O static characteristics
Symbol
VIL
Parameter
Input low level voltage(2)
Conditions(1)
Min.
Typ.
Max.
Input voltage on true
open-drain pins (PC0
and PC1)
VSS-0.3
-
0.3 x VDD
Input voltage on fivevolt tolerant (FT) pins
VSS-0.3
-
0.3 x VDD
Input voltage on any
other pin
VSS-0.3
-
0.3 x VDD
-
5.2
-
5.5
Input voltage on true
open-drain pins (PC0
and PC1)
with VDD < 2 V
Input voltage on true
open-drain pins (PC0
and PC1)
with VDD 2 V
VIH
Input high level voltage (2)
Input voltage on fivevolt tolerant (FT) pins
with VDD < 2 V
Ilkg
Input leakage current (4)
RPU
Weak pull-up equivalent
resistor(2)(6)
CIO
I/O pin capacitance
0.70 x VDD
V
5.2
-
5.5
0.70 x VDD
-
VDD+0.3
Standard I/Os
-
200
-
True open drain I/Os
-
200
-
VSSVIN VDD
Standard I/Os
-
-
50 (5)
VSSVIN VDD
True open drain I/Os
-
-
200(5)
VSSVIN VDD
PA0 with high sink LED
driver capability
-
-
200(5)
30
45
60
k
-
5
-
pF
Input voltage on any
other pin
Schmitt trigger voltage hysteresis (3)
V
-
Input voltage on fivevolt tolerant (FT) pins
with VDD 2 V
Vhys
Unit
0.70 x VDD
mV
VINVSS
-
nA
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
Figure 24).
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Figure 21. Typical VIL and VIH vs. VDD (standard I/Os)
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Figure 22. Typical VIL and VIH vs. VDD (true open drain I/Os)
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Figure 23. Typical pull-up resistance RPU vs. VDD with VIN=VSS
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Figure 24. Typical pull-up current Ipu vs. VDD with VIN=VSS
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Output driving current
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 38. Output driving current (high sink ports)
I/O
Symbol
Type
Output low level voltage for an I/O pin
Standard
VOL (1)
Parameter
VOH (2) Output high level voltage for an I/O pin
Conditions
Min.
Max.
IIO = +2 mA,
VDD = 3.0 V
-
0.45
IIO = +2 mA,
VDD = 1.8 V
-
0.45
IIO = +10 mA,
VDD = 3.0 V
-
0.7
Unit
V
IIO = -2 mA,
VDD = 3.0 V
VDD-0.45
-
IIO = -1 mA,
VDD = 1.8 V
VDD-0.45
-
IIO = -10 mA,
VDD = 3.0 V
VDD-0.7
-
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 15 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 15 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD.
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STM8L162M8 STM8L162R8
Table 39. Output driving current (true open drain ports)
Open drain
I/O
Symbol
Type
VOL
(1)
Parameter
Output low level voltage for an I/O pin
Conditions
Min.
Max.
IIO = +3 mA,
VDD = 3.0 V
-
0.45
IIO = +1 mA,
VDD = 1.8 V
-
Unit
V
0.45
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 15 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Table 40. Output driving current (PA0 with high sink LED driver capability)
I/O
Symbol
Type
IR
VOL (1)
Parameter
Output low level voltage for an I/O pin
Conditions
Min.
Max.
Unit
IIO = +20 mA,
VDD = 2.0 V
-
0.45
V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 15 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Figure 25. Typical VOL @ VDD = 3.0 V (high sink Figure 26. Typical VOL @ VDD = 1.8 V (high sink
ports)
ports)
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Figure 27. Typical VOL @ VDD = 3.0 V (true open Figure 28. Typical VOL @ VDD = 1.8 V (true open
drain ports)
drain ports)
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DocID17959 Rev 4
STM8L162M8 STM8L162R8
Electrical parameters
Figure 29. Typical VDD - VOH @ VDD = 3.0 V (high Figure 30. Typical VDD - VOH @ VDD = 1.8 V (high
sink ports)
sink ports)
#
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NRST pin
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 41. NRST pin characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VIL(NRST)
NRST input low level voltage (1)
-
VSS
-
0.8
VIH(NRST)
NRST input high level voltage (1)
-
1.4
-
VDD
IOL = 2 mA
2.7 V VDD 3.6 V
-
-
IOL = 1.5 mA
VDD < 2.7 V
-
-
VOL(NRST)
NRST output low level voltage (1)
Unit
V
0.4
VHYST
NRST input hysteresis(3)
-
10%VDD(2)
-
-
mV
RPU(NRST)
NRST pull-up equivalent
resistor(1)
-
30
45
60
k
VF(NRST)
NRST input filtered pulse (3)
-
-
50
VNF(NRST)
NRST input not filtered pulse (3)
-
-
-
ns
300
1. Data based on characterization results, not tested in production.
2. 200 mV min.
3. Data guaranteed by design, not tested in production.
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STM8L162M8 STM8L162R8
Figure 31. Typical NRST pull-up resistance RPU vs. VDD
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Figure 32. Typical NRST pull-up current Ipu vs. VDD
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The reset network shown in Figure 33 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 41. Otherwise the reset is not taken into account internally. For power consumptionsensitive applications, the capacity of the external reset capacitor can be reduced to limit the
charge/discharge current. If the NRST signal is used to reset the external circuitry, the user
must pay attention to the charge/discharge time of the external capacitor to meet the reset
timing conditions of the external devices. The minimum recommended capacity is 10 nF.
Figure 33. Recommended NRST pin configuration
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9.3.8
Electrical parameters
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under ambient temperature, fSYSCLK frequency and VDD supply voltage
conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 42. SPI1 characteristics
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
tsu(NSS)(2)
th(NSS)
(2)
Parameter
Min.
Max.
Master mode
0
8
Slave mode
0
8
SPI1 clock rise and fall
time
Capacitive load: C = 30 pF
-
30
NSS setup time
Slave mode
4 x 1/fSYSCLK
-
NSS hold time
Slave mode
80
-
SCK high and low time
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
105
145
Master mode
30
-
Slave mode
3
-
Master mode
15
-
Slave mode
0
-
Data output access time
Slave mode
-
3x 1/fSYSCLK
30
-
tsu(MI) (2)
tsu(SI)(2)
Data input setup time
th(MI) (2)
th(SI)(2)
Data input hold time
ta(SO)
(2)(3)
tdis(SO)(2)(4)
Data output disable time
Slave mode
(2)
Data output valid time
Slave mode (after enable edge)
-
60
tv(MO)(2)
Data output valid time
Master mode (after enable
edge)
-
20
Slave mode (after enable edge)
15
-
Master mode (after enable
edge)
1
-
tv(SO)
th(SO)(2)
th(MO)(2)
Unit
SPI1 clock frequency
(2)
tw(SCKH)
tw(SCKL)(2)
Conditions(1)
Data output hold time
MHz
ns
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.
4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.
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STM8L162M8 STM8L162R8
Figure 34. SPI1 timing diagram - slave mode and CPHA=0
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical parameters
Figure 36. SPI1 timing diagram - master mode
(IGH
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical parameters
STM8L162M8 STM8L162R8
I2C - Inter IC control interface
Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.
The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 43. I2C characteristics
Standard mode I2C
Symbol
Fast mode I2C(1)
Parameter
Unit
Min.(2)
Max. (2)
Min. (2)
Max. (2)
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
0
-
0
900
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
START condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated START condition setup
time
4.7
-
0.6
-
tsu(STO)
STOP condition setup time
4.0
-
0.6
-
s
STOP to START condition time (bus
free)
4.7
-
1.3
-
s
-
400
-
400
pF
tw(STO:STA)
Cb
Capacitive load for each bus line
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.
Note:
100/125
For speeds around 200 kHz, the achieved speed can have a 5% tolerance.
For other speed ranges, the achieved speed can have a 2% tolerance.
The above variations depend on the accuracy of the external components used.
DocID17959 Rev 4
s
ns
s
STM8L162M8 STM8L162R8
Electrical parameters
Figure 37. Typical application with I2C bus and timing diagram
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1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
9.3.9
LCD controller
In the following table, data are guaranteed by Design, not tested in production.
Table 44. LCD characteristics
Symbol
Parameter
Min.
VLCD
LCD external voltage
-
VLCD0
LCD internal reference voltage 0
-
2.6
-
VLCD1
LCD internal reference voltage 1
-
2.7
-
VLCD2
LCD internal reference voltage 2
-
2.8
-
VLCD3
LCD internal reference voltage 3
-
3.0
-
VLCD4
LCD internal reference voltage 4
-
3.1
-
VLCD5
LCD internal reference voltage 5
-
3.2
-
VLCD6
LCD internal reference voltage 6
-
3.4
-
VLCD7
LCD internal reference voltage 7
-
3.5
-
CEXT
VLCD external capacitance
0.1
1
2
-
3
-
-
3
-
Supply
IDD
current(1)
at VDD = 1.8 V
(1)
Supply current
at VDD = 3 V
Typ.
Max.
Unit
3.6
V
µF
µA
RHN(2)
High value resistive network (low drive)
-
6.6
-
M
(3)
Low value resistive network (high drive)
-
240
-
k
RLN
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Electrical parameters
STM8L162M8 STM8L162R8
Table 44. LCD characteristics (continued)
Symbol
Parameter
Min.
Typ.
Max.
V33
Segment/Common higher level voltage
-
V34
Segment/Common 3/4 level voltage
-
3/4VLCDx
-
V23
Segment/Common 2/3 level voltage
-
2/3VLCDx
-
V12
Segment/Common 1/2 level voltage
-
1/2VLCDx
-
V13
Segment/Common 1/3 level voltage
-
1/3VLCDx
-
V14
Segment/Common 1/4 level voltage
-
1/4VLCDx
-
V0
Segment/Common lowest level voltage
0
-
-
Unit
VLCDx
V
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
2. RHN is the total high value resistive network.
3. RLN is the total low value resistive network.
VLCD external capacitor
The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor CEXT to the VLCD pin. CEXT is specified in Table 44.
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STM8L162M8 STM8L162R8
9.3.10
Electrical parameters
Embedded reference voltage
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 45. Reference voltage characteristics
Symbol
Parameter
Conditions
Min.
Typ.
IREFINT
Internal reference voltage
consumption
-
-
1.4
TS_VREFINT(1)(2)
ADC sampling time when reading the
internal reference voltage
-
-
5
10
µs
IBUF(1)
Internal reference voltage buffer
consumption (used for ADC)
-
-
13.5
25
µA
VREFINT out
Reference voltage output
-
ILPBUF(1)
Internal reference voltage low-power
buffer consumption (used for
comparators or output)
IREFOUT(1)(4)
1.202
(3)
1.224
-
-
730
Buffer output current
-
CREFOUT
Reference voltage output load
tVREFINT(1)
Max.
Unit
µA
1.242
(3)
V
1200
nA
-
1
µA
-
-
50
pF
Internal reference voltage startup
time
-
-
3
ms
tBUFEN(1)(2)
Internal reference voltage buffer
startup time once enabled
-
-
10
µs
ACCVREFINT(5)
Accuracy of VREFINT stored in the
VREFINT_Factory_CONV byte
-
-
±5
mV
Stability of VREFINT over temperature
-40 °C TA 125
°C
-
20
50
ppm/°C
Stability of VREFINT over temperature
0 °C TA 50 °C
-
-
20
ppm/°C
Stability of VREFINT after 1000 hours
-
-
-
1000
ppm
STABVREFINT
STABVREFINT
2
1. Guaranteed by design, not tested in production
2. Defined when ADC output reaches its final value ±1/2LSB
3. Tested in production at VDD = 3 V ±10 mV.
4. To guarantee less than 1% VREFOUT deviation
5. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.
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Electrical parameters
9.3.11
STM8L162M8 STM8L162R8
Temperature sensor
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 46. TS characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
V90 (1)
Sensor reference voltage at 90°C ±5 °C,
0.580
0.597
0.614
V
-
±1
±2
°C
TL
VSENSOR linearity with temperature
(2)
Average slope
1.59
1.62
1.65
mV/°C
(2)
Consumption
-
3.4
6
µA
TSTART(2)(3)
Temperature sensor startup time
-
-
10
µs
TS_TEMP(2)
ADC sampling time when reading the
temperature sensor
-
5
10
µs
Avg_slope
IDD(TEMP)
1. Tested in production at VDD = 3 V ±10 mV. The 8 LSB of the V90 ADC conversion result are stored in the
TS_Factory_CONV_V90 byte.
2. Guaranteed by design, not tested in production.
3. Defined for ADC output reaching its final value ±1/2LSB.
9.3.12
Comparator characteristics
In the following tables, data are guaranteed by design, not tested in production.
Table 47. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
1.65
-
3.6
V
VDDA
Analog supply voltage
R400K
R400K value
-
-
400
-
R10K
R10K value
-
-
10
-
Comparator 1 input
voltage range
-
0.6
-
VDDA
Comparator startup time
-
-
7
10
-
-
3
10
-
-
3
10
mV
0
1.5
10
mV/1000 h
-
160
260
nA
VIN
tSTART
td
Propagation delay
Voffset
Comparator offset
dVoffset/dt
ICOMP1
k
(2)
Comparator offset
variation in worst voltage
stress conditions
Current consumption(3)
V
µs
VDDA 3.6 V
VIN+ 0 V
VIN- VREFINT
TA = 25 C
-
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
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Electrical parameters
Table 48. Comparator 2 characteristics
Symbol
VDDA
VIN
tSTART
td slow
td fast
Voffset
dThreshold/dt
ICOMP2
Conditions
Min
Typ Max(1) Unit
Analog supply voltage
-
1.65
3.6
V
Comparator 2 input voltage range
-
0
VDDA
V
Fast mode
-
15
20
Slow mode
-
20
25
1.65 V VDDA
2.7 V
-
1.8
3.5
2.7 V VDDA
3.6 V
-
2.5
6
1.65 V VDDA
2.7 V
-
0.8
2
2.7 V VDDA
3.6 V
-
1.2
4
-
-
4
20
mV
VDDA 3.3V
TA = 0 to 50 C
V- = VREF+, 3/4
VREF+,
1/2 VREF+, 1/4 VREF+.
-
15
30
ppm
/°C
Fast mode
-
3.5
5
Slow mode
-
0.5
2
Parameter
Comparator startup time
Propagation delay(2) in slow mode
Propagation delay(2) in fast mode
Comparator offset error
Threshold voltage temperature
coefficient
Current consumption(3)
µs
µA
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
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115
Electrical parameters
9.3.13
STM8L162M8 STM8L162R8
12-bit DAC characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 49. DAC characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VDDA
Analog supply voltage
-
1.8
-
3.6
VREF+
Reference supply voltage
-
1.8
-
VDDA
VREF+ = 3.3 V, no load,
middle code (0x800)
-
130
220
IVREF
Current consumption on VREF+
supply
VREF+ = 3.3 V, no load,
worst code (0x000)
-
220
350
Unit
V
µA
IVDDA
TA
RL(1) (2)
Current consumption on VDDA
supply
VDDA = 3.3 V, no load,
middle code (0x800)
-
210
320
VDDA = 3.3 V, no load,
worst code (0x000)
-
320
520
-40
-
125
°C
Temperature range
Resistive load
DACOUT buffer ON
5
-
-
k
Output impedance
DACOUT buffer OFF
-
8
10
k
-
-
50
pF
DACOUT buffer ON
0.2
-
VDDA - 0.2
V
DACOUT buffer OFF
0
-
VREF+ -1 LSB
V
Settling time (full scale: for a 12bit input code transition between
the lowest and the highest input
codes when DAC_OUT reaches
the final value ±1LSB)
RL 5 k, CL50 pF
-
7
12
µs
Max frequency for a correct
DAC_OUT (@95%) change
Update rate
when small variation of the input
code (from code i to i+1LSB).
RL 5 k, CL 50 pF
-
-
1
Msps
RO
CL(3)
DAC_OUT
(4)
tsettling
Capacitive load
DAC_OUT voltage
tWAKEUP
Wakeup time from OFF state.
Input code between lowest and
highest possible codes.
RL 5 k, CL50 pF
-
9
15
µs
PSRR+
Power supply rejection ratio (to
VDDA) (static DC measurement)
RL5 k, CL50 pF
-
-60
-35
dB
1. Resistive load between DACOUT and GNDA
2. Output on PF0 or PF1
3. Capacitive load at DACOUT pin
4. It gives the output excursion of the DAC
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STM8L162M8 STM8L162R8
Electrical parameters
In the following table, data based on characterization results, not tested in production.
Table 50. DAC accuracy
Symbol
Parameter
Conditions
Typ.
Max.
1.5
3
1.5
3
2
4
2
4
±10
±25
No load
DACOUT buffer OFF
±5
±8
DACOUT buffer OFF
±1.5
±5
RL 5 k, CL50 pF
DNL
Differential non linearity
DACOUT buffer ON(2)
(1)
No load
DACOUT buffer OFF
RL 5 k, CL50 pF
INL
Integral non linearity
DACOUT buffer ON(2)
(3)
No load
DACOUT buffer OFF
RL 5 k, CL50 pF
Offset
Offset1
DACOUT buffer ON(2)
(4)
Offset error
Offset error at Code 1 (5)
RL 5 k, CL50 pF
Gain error
DACOUT buffer ON(2)
Gain error(6)
No load
DACOUT buffer OFF
RL 5 k, CL50 pF
TUE
DACOUT buffer ON(2)
Total unadjusted error
No load -DACOUT buffer OFF
Unit
12-bit
LSB
+0.1/-0.2 +0.2/-0.5
%
+0/-0.2
+0/-0.4
12
30
8
12
12-bit
LSB
1. Difference between two consecutive codes - 1 LSB.
2. In 48-pin package devices the DAC2 output buffer must be kept off and no load must be applied on the DAC_OUT2 output.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.
4. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
5. Difference between the value measured at Code (0x001) and the ideal value.
6. Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and 0xFFF
when buffer is ON, and from Code giving 0.2 V and (VDDA -0.2) V when buffer is OFF.
In the following table, data are guaranteed by design, not tested in production.
Table 51. DAC output on PB4-PB5-PB6(1)
Symbol
Rint
Parameter
Internal resistance
between DAC output and
PB4-PB5-PB6 output
Conditions
Max
2.7 V < VDD < 3.6 V
1.4
2.4 V < VDD < 3.6 V
1.6
2.0 V < VDD < 3.6 V
3.2
1.8 V < VDD < 3.6 V
8.2
Unit
k
1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing
interface I/O switch registers.
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Electrical parameters
9.3.14
STM8L162M8 STM8L162R8
12-bit ADC1 characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 52. ADC1 characteristics
Symbol
Parameter
VDDA
Analog supply voltage
VREF+
Reference supply
voltage
VREF-
Conditions
Min.
Typ.
-
1.8
3.6
2.4 V VDDA3.6 V
2.4
VDDA
1.8 VVDDA 2.4 V
VDDA
Lower reference voltage
-
VSSA
IVDDA
Current on the VDDA
input pin
-
-
-
-
IVREF+
Current on the VREF+
input pin
1000
Max.
Unit
V
1450
700
(peak)(1)
µA
400
-
-
450
(average)(1)
VAIN
Conversion voltage
range
-
0(2)
-
VREF+
TA
Temperature range
-
-40
-
125
°C
on PF0/1/2/3 fast
channels
-
-
50(3)
k
on all other channels
-
on PF0/1/2/3 fast
channels
-
on all other channels
-
2.4 VVDDA3.6 V
without zooming
0.320
-
16
1.8 VVDDA2.4 V
with zooming
0.320
-
8
VAIN on PF0/1/2/3 fast
channels
-
-
1(3)(4)
VAIN on all other
channels
-
-
760(3)(4)
kHz
RAIN
CADC
fADC
fCONV
External resistance on
VAIN
Internal sample and hold
capacitor
ADC sampling clock
frequency
16
pF
-
MHz
12-bit conversion rate
fTRIG
External trigger
frequency
-
-
-
tconv
1/fADC
tLAT
External trigger latency
-
-
-
3.5
1/fSYSCLK
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STM8L162M8 STM8L162R8
Electrical parameters
Table 52. ADC1 characteristics (continued)
Symbol
tS
Parameter
Sampling time
Conditions
Min.
Typ.
Max.
VAIN PF0/1/2/3 fast
channels
VDDA < 2.4 V
0.43(3)(4)
-
-
VAIN PF0/1/2/3 fast
channels
2.4 V VDDA3.6 V
0.22(3)(4)
-
-
VAIN on slow channels
VDDA < 2.4 V
0.86(3)(4)
-
-
VAIN on slow channels
2.4 V VDDA3.6 V
0.41(3)(4)
-
-
Unit
µs
-
12 + tS
1/fADC
16 MHz
1(3)
µs
tconv
12-bit conversion time
tWKUP
Wakeup time from OFF
state
-
-
-
3
µs
tIDLE(5)
Time before a new
conversion
-
-
-
s
tVREFINT
Internal reference
voltage startup time
-
-
-
refer to
Table 45
ms
1. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. VREF- must be tied to ground.
3. Minimum sampling and conversion time is reached for maximum RAIN= 0.5 k
4. Value obtained for continuous conversion on fast channel.
5. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE.
DocID17959 Rev 4
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115
Electrical parameters
STM8L162M8 STM8L162R8
In the following three tables, data are guaranteed by characterization result, not tested in
production.
Table 53. ADC1 accuracy with VDDA = 3.3 V to 2.5 V
Symbol
Parameter
Conditions
Typ.
Max.
1
1.6
Differential non linearity fADC = 8 MHz
1
1.6
fADC = 4 MHz
1
1.5
fADC = 16 MHz
1.2
2
fADC = 8 MHz
1.2
1.8
fADC = 4 MHz
1.2
1.7
fADC = 16 MHz
2.2
3.0
fADC = 8 MHz
1.8
2.5
fADC = 4 MHz
1.8
2.3
fADC = 16 MHz
1.5
2
fADC = 8 MHz
1
1.5
fADC = 4 MHz
0.7
1.2
1
1.5
fADC = 16 MHz
DNL
INL
Integral non linearity
TUE
Total unadjusted error
Offset
Offset error
Unit
LSB
fADC = 16 MHz
Gain
Gain error
fADC = 8 MHz
fADC = 4 MHz
Table 54. ADC1 accuracy with VDDA = 2.4 V to 3.6 V
Symbol
Parameter
Typ.
Max.
1
2
1.7
3
DNL
Differential non linearity
INL
Integral non linearity
TUE
Total unadjusted error
2
4
Offset
Offset error
1
2
Gain
Gain error
1.5
3
Unit
LSB
Table 55. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V
Symbol
110/125
Parameter
Typ.
Max.
DNL
Differential non linearity
1
2
INL
Integral non linearity
2
3
TUE
Total unadjusted error
3
5
Offset
Offset error
2
3
Gain
Gain error
2
3
DocID17959 Rev 4
Unit
LSB
STM8L162M8 STM8L162R8
Electrical parameters
Figure 38. ADC1 accuracy characteristics
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Figure 39. Typical connection diagram using the ADC
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1. Refer to Table 52 for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 40 or Figure 41,
depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
DocID17959 Rev 4
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115
Electrical parameters
STM8L162M8 STM8L162R8
Figure 40. Power supply and reference decoupling (VREF+ not connected to VDDA)
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Figure 41. Power supply and reference decoupling (VREF+ connected to VDDA)
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112/125
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STM8L162M8 STM8L162R8
9.3.15
Electrical parameters
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 56. EMS data
Symbol
Parameter
Conditions
VFESD
Voltage limits to be applied on
any I/O pin to induce a functional
disturbance
VEFTB
Fast transient voltage burst limits
VDD 3.3 V, TA +25 °C, Using HSI
to be applied through 100 pF on
fCPU 16 MHz,
VDD and VSS pins to induce a
conforms to IEC 61000
Using HSE
functional disturbance
VDD 3.3 V, TA +25 °C,
fCPU16 MHz,
conforms to IEC 61000
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2B
4A
2B
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Electrical parameters
STM8L162M8 STM8L162R8
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.
Table 57. EMI data (1)
Symbol
SEMI
Parameter
Peak level
Monitored
frequency band
Conditions
VDD 3.6 V,
TA +25 °C,
LQFP80
conforming to
IEC61967-2
Max vs.
Unit
16 MHz
0.1 MHz to 30 MHz
10
30 MHz to 130 MHz
4
130 MHz to 1 GHz
1
SAE EMI Level
1.5
dBV
-
1. Not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.
Table 58. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Electrostatic discharge voltage
(human body model)
Electrostatic discharge voltage
VESD(CDM)
(charge device model)
Conditions
Maximum
value (1)
Unit
2000
TA +25 °C
V
750
1. Data based on characterization results, not tested in production.
Static latch-up
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LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
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STM8L162M8 STM8L162R8
Electrical parameters
Table 59. Electrical sensitivities
Symbol
LU
9.4
Parameter
Class
Static latch-up class
II
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 17: General operating conditions on page 64.
The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x JA)
Where:
TAmax is the maximum ambient temperature in C
JA is the package junction-to-ambient thermal resistance in C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = (VOL*IOL) + ((VDD-VOH)*I OH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in
the application.
Table 60. Thermal characteristics(1)
Symbol
Parameter
Value
Unit
JA
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm
48
°C/W
JA
Thermal resistance junction-ambient
LQFP 80 - 14 x 14 mm
38
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
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Package information
10
STM8L162M8 STM8L162R8
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
10.1
LQFP80 package information
Figure 42. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline
C
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!
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0,!.%
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MM
'!5'%0,!.%
#
!
CCC
,
$
K
,
$
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
3?-%
116/125
DocID17959 Rev 4
STM8L162M8 STM8L162R8
Package information
Table 61. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical
data(1)
millimeters
inches
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.220
0.320
0.380
0.0087
0.0126
0.0150
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.350
-
-
0.4862
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.350
-
-
0.4862
-
e
-
0.650
-
-
0.0256
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 43. LQFP80 14 x 14 mm low-profile quad flat package footprint
4@'1
1. Dimensions are in millimeters.
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Package information
STM8L162M8 STM8L162R8
Device marking
The following figure shows the marking for the LQFP80 package.
Figure 44. LQFP80 marking example (package top view)
2SWLRQDOJDWHPDUN
5HYLVLRQFRGH
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3
45.-
.5
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'DWHFRGH
: 88
069
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STM8L162M8 STM8L162R8
LQFP64 package information
Figure 45. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
PP
*$8*(3/$1(
F
$
$
6($7,1*3/$1(
&
$
$
FFF &
'
'
'
.
/
/
3,1
,'(17,),&$7,21
(
(
E
(
10.2
Package information
H
:B0(B9
1. Drawing is not to scale.
Table 62. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
E3
-
7.500
-
-
0.2953
-
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Package information
STM8L162M8 STM8L162R8
Table 62. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data
(continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
e
-
0.500
-
-
0.0197
-
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 46. LQFP64, 10 x 10 mm low-profile quad flat package footprint
AIC
1. Dimensions are in millimeters.
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STM8L162M8 STM8L162R8
Package information
Device marking
The following figure shows the marking for the LQFP64 package.
Figure 47. LQFP64 marking example (package top view)
3URGXFWLGHQWLILFDWLRQ
45.-
35
'DWHFRGH
: 88
6WDQGDUG67ORJR
5HYLVLRQFRGH
3LQLGHQWLILHU
3
069
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Ordering information scheme
11
STM8L162M8 STM8L162R8
Ordering information scheme
Table 63. Ordering information scheme
Example:
STM8
L 162
M
8
T
6
D
Device family
STM8 microcontroller
Product type
L = Low-power
Device subfamily
162: STM8L162 device family
Pin count
R = 64 pins
M = 80 pins
Program memory size
8 = 64 Kbytes of Flash memory
Package
T = LQFP
Temperature range
3 = Industrial temperature range, –40 to 125 °C
6 = Industrial temperature range, –40 to 85 °C
Option
Blank = VDD range from 1.8 to 3.6 V and BOR enabled
D = VDD range from 1.65 to 3.6 V and BOR disabled
For a list of available options (e.g. memory size, package) and order-able part numbers or
for further information on any aspect of this device, please go to www.st.com or contact the
ST Sales Office nearest to you.
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12
Revision history
Revision history
Table 64. Document revision history
Date
Revision
14-Sep-2010
1
Initial release.
2
Table 4: STM8L162x8 pin description: updated
“standard port” changed to “high sink port”.
Figure 5: Memory map: updated the address range of
the AES registers.
Table 8: General hardware register map: updated the
address range of the AES registers.
Table 14: Voltage characteristics: updated
Table 15: Current characteristics: updated
Table 34: RAM and hardware registers: updated VRM
data min. retention.
Added Table 9.3.6: I/O current injection characteristics.
Table 37: I/O static characteristics: updated
Table 44: LCD characteristics: updated
22-Mar-2011
Changes
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Revision history
STM8L162M8 STM8L162R8
Table 64. Document revision history
Date
10-Jul-2012
19-Feb-2015
124/125
Revision
Changes
3
Modified LCD pin names in Table 4: STM8L162x8 pin
description
Corrected LCD corresponding register numbers in
Table 8: General hardware register map
Corrected the user manual name in Section 7: Option
bytes
Replaced comparator tables with STM32 tables in
Section 9.3.12: Comparator characteristics
Added “The ram content is preserved” in Section 3.1:
Low-power modes
Modified capacitive sensing channel bullet in Features
Modified last sentence in Section 3.12: System
configuration controller and routing interface
Added Section 3.13: Touch sensing
Replaced “Vref+ - 0.2” with “VDDA - 0.2” for DAC_OUT
in Table 49: DAC characteristics
4
Updated
– Table 61: LQFP80 - 80-pin, 14 x 14 mm low-profile
quad flat package mechanical data
– Figure 42: LQFP80 - 80-pin, 14 x 14 mm low-profile
quad flat package outline
– Figure 43: LQFP80 14 x 14 mm low-profile quad flat
package footprint
– Table 62: LQFP64 - 64-pin, 10 x 10 mm low-profile
quad flat package mechanical data
– Figure 45: LQFP64 - 64-pin, 10 x 10 mm low-profile
quad flat package outline
– Figure 46: LQFP64, 10 x 10 mm low-profile quad flat
package footprint
Added:
– Figure 44: LQFP80 marking example (package top
view)
– Figure 47: LQFP64 marking example (package top
view)
DocID17959 Rev 4
STM8L162M8 STM8L162R8
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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