STM8S001J3M3TR

STM8S001J3 16 MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I2C Datasheet - production data Features Core • 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline SO8N 4.9x6 mm or 150 mils width • Extended instruction set Timers Memories • Program memory: 8-Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles • RAM: 1 Kbyte • Data memory: 128-byte true data EEPROM; endurance up to 100 k write/erase cycles • Advanced control timer: 16-bit, 2 CAPCOM channels, 2 outputs, dead-time insertion and flexible synchronization • 16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM) • 8-bit basic timer with 8-bit prescaler • Auto wakeup timer Clock, reset and supply management • Window and independent watchdog timers • 2.95 V to 5.5 V operating voltage • Flexible clock control, 3 master clock sources – External clock input – Internal, user-trimmable 16 MHz RC – Internal low-power 128 kHz RC • Clock security system with clock monitor • Power management – Low-power modes (wait, active-halt, halt) – Switch-off peripheral clocks individually – Permanently active, low-consumption power-on and power-down reset Communications interfaces • UART, SmartCard, IrDA, LIN master mode • SPI unidirectional interface up to 8 Mbit/s (master simplex mode, slave receiver only) • I2C interface up to 400 Kbit/s Analog to digital converter (ADC) • 10-bit ADC, ± 1 LSB ADC with up to 3 multiplexed channels, scan mode and analog watchdog Interrupt management • Internal reference voltage measurement • Nested interrupt controller with 32 interrupts I/Os • Up to 5 external interrupts • Up to 5 I/Os including 4 high-sink outputs • Highly robust I/O design, immune against current injection Development support • Embedded single-wire interface module (SWIM) or fast on-chip programming and nonintrusive debugging August 2020 This is information on a product in full production. DS12129 Rev 4 1/84 www.st.com Contents STM8S001J3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 6 2/84 4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 12 4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.10 TIM2 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.11 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.12 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13.3 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 STM8S001J3 SO8N pinout and pin description . . . . . . . . . . . . . . . . . . . . 21 5.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.1 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.2 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DS12129 Rev 4 STM8S001J3 Contents 6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 34 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1 10 Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 53 9.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 54 9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3.7 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.3.8 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.3.9 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 78 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 81 DS12129 Rev 4 3/84 4 Contents STM8S001J3 12.2 12.3 13 4/84 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DS12129 Rev 4 STM8S001J3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STM8S001J3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15 TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Legend/abbreviations for STM8S001J3 pin description tables. . . . . . . . . . . . . . . . . . . . . . 21 STM8S001J3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM8S001J3 alternate function remapping bits for 8-pin devices . . . . . . . . . . . . . . . . . . . 39 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Total current consumption with code execution in run mode at VDD = 5 V . . . . . . . . . . . . 45 Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 45 Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 47 Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . 47 Total current consumption in halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 49 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC accuracy with RAIN < 10 kΩ , VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, DS12129 Rev 4 5/84 6 List of tables Table 49. Table 50. 6/84 STM8S001J3 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DS12129 Rev 4 STM8S001J3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. STM8S001J3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM8S001J3 SO8N pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typ. IDD(RUN) vs VDD, HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . 50 Typ. IDD(RUN) vs fCPU, HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 50 Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typ. IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 51 Typ. IDD(WFI) vs. fCPU, HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 52 Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical LSI frequency variation vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typ. VOL @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typ. VDD - VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 75 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 STM8S001J3 ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DS12129 Rev 4 7/84 7 Introduction 1 STM8S001J3 Introduction This datasheet contains the description of the STM8S001J3 features, pinout, electrical characteristics, mechanical data and ordering information. 8/84 • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016). • For information on programming, erasing and protection of the internal Flash memory please refer to the PM0051 (How to program STM8S and STM8A Flash program memory and data EEPROM). • For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). • For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). DS12129 Rev 4 STM8S001J3 2 Description Description The STM8S001J3 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. It is referred to as low-density device in the STM8S microcontroller family reference manual (RM0016). The STM8S001J3 device provides the following benefits: performance, robustness and reduced system cost. Device performance and robustness are ensured by true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art technology at 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system. The system cost is reduced thanks to a high system integration level with internal clock oscillators, watchdog, and brown-out reset. Full documentation is offered as well as a wide choice of development tools. Table 1. STM8S001J3 features Features STM8S001J3 Pin count 8 Max. number of GPIOs (I/O) 5 External interrupt pins 5 Timer CAPCOM channels 3 Timer complementary outputs 1 A/D converter channels 3 High-sink I/Os 4 Low-density Flash program memory (byte) 8K RAM (byte) 1K 128(1) True data EEPROM (byte) Peripheral set Multi purpose timer (TIM1), SPI unidirectional, I2C, UART, Window WDG, independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4) 1. Without read-while-write capability. DS12129 Rev 4 9/84 24 Block diagram 3 STM8S001J3 Block diagram Figure 1. STM8S001J3 block diagram Reset block Ext. Clock input 1 – 16 MHz Clock controller Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Single wire debug interface Debug / SWIM 8 Kbyte program Flash 400 Kbit/s 8 Mbit/s I2C Unidirectional SPI LIN master UART1 Up to 3 channels ADC1 Address and data bus 128 byte data EEPROM 1 Kbyte RAM 16-bit advanced control timer (TM1) Up to 2 CAPCPOM channels 16-bit general purpose timer (TIM2) Up to 3 CAPCPOM channels 8-bit basic timer (TIM4) AWU timer MSv44651V1 10/84 DS12129 Rev 4 STM8S001J3 4 Functional overview Functional overview The following section intends to give an overview of the basic features of the STM8S001J3 functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers • Harvard architecture • 3-stage pipeline • 32-bit wide program memory bus - single cycle fetching for most instructions • X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations • 8-bit accumulator • 24-bit program counter - 16-Mbyte linear memory space • 16-bit stack pointer - access to a 64 K-level stack • 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing • 20 addressing modes • Indexed indirect addressing mode for look-up tables located anywhere in the address space • Stack pointer relative addressing mode for local variables and parameter passing Instruction set • 80 instructions with 2-byte average instruction size • Standard data movement and logic/arithmetic functions • 8-bit by 8-bit multiplication • 16-bit by 8-bit and 16-bit by 16-bit division • Bit manipulation • Data transfer between stack and accumulator (push/pop) with direct stack access • Data transfer using the X and Y registers or direct memory-to-memory transfers DS12129 Rev 4 11/84 24 Functional overview 4.2 STM8S001J3 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. • R/W to RAM and peripheral registers in real-time • R/W access to all resources by stalling the CPU • Breakpoints on all program-memory instructions (software breakpoints) • Two advanced breakpoints, 23 predefined configurations Recommendation for SWIM pin (pin #8) sharing As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever. This initial delay can be removed in the final (locked) code. If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for device debug/programming. 4.3 4.4 12/84 Interrupt controller • Nested interrupts with three software priority levels • 32 interrupt vectors with hardware priority • Up to 5 external interrupts including TLI • Trap and reset interrupts Flash program memory and data EEPROM • 8 Kbytes of Flash program single voltage Flash memory • 128 byte true data EEPROM • User option byte area DS12129 Rev 4 STM8S001J3 Functional overview Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 2. The size of the UBC is programmable through the UBC option byte (Table 12), in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: • Main program memory: 8 Kbyte minus UBC • User-specific boot code (UBC): Configurable up to 8 Kbyte The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2. Flash memory organization Option bytes Data EEPROM (128 bytes) UBC area Remains write protected during IAP Low density Flash program memory (8 Kbytes) Programmable area from 64 bytes (1 page) up to 8 Kbytes (in 1 page steps) Program memory area Write access possible for IAP MS36408V1 DS12129 Rev 4 13/84 24 Functional overview STM8S001J3 Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Recommendation for the device's programming: The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space). If the device's program memory is empty (0x00 content), it displays the behavior described below: • After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG (0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF). It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz HSI clock. • Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed. The reading of non-existing memory is a random content which can lead to the execution of invalid instructions. The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more. Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device. The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts). Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop. 14/84 DS12129 Rev 4 STM8S001J3 4.5 Functional overview Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features • Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. • Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • Master clock sources: Three different clock sources can be used to drive the master clock: – Up to 16 MHz high-speed user-external clock (HSE user-ext) – 16 MHz high-speed internal RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI) • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. • Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved DS12129 Rev 4 15/84 24 Functional overview 4.6 STM8S001J3 Power management For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources. 4.7 • Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. • Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. • Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. • Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 16/84 1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. 2. Refresh out of window: the down-counter is refreshed before its value is lower than the one stored in the window register. DS12129 Rev 4 STM8S001J3 Functional overview Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s. 4.8 4.9 Auto wakeup counter • Used for auto wakeup from active halt mode • Clock source: internal 128 kHz internal low frequency RC oscillator or external clock • LSI clock can be internally connected to TIM1 input capture channel 1 for calibration TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to lighting and half-bridge driver. 4.10 4.11 • 16-bit up, down and up/down autoreload counter with 16-bit prescaler • Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output • Synchronization module to control the timer with external signals • Break input to force the timer outputs into a defined state • One complementary output (CH1 with CH1N option) with adjustable dead time • Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break TIM2 - 16-bit general purpose timer • 16-bit autoreload (AR) up-counter • 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 • 3 individually configurable capture/compare channels • PWM mode • Interrupt sources: 3 x input capture/output compare, 1 x overflow/update TIM4 - 8-bit basic timer • 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 • Clock source: CPU clock • Interrupt source: 1 x overflow/update DS12129 Rev 4 17/84 24 Functional overview STM8S001J3 Table 3. TIM timer features Timer Counter size (bits) TIM1 16 Any integer from 1 to 65536 TIM2 16 TIM4 8 Counting CAPCOM Complem. Ext. mode trigger channels outputs Prescaler Up/down 2 1(1) No Any power of 2 from 1 to 32768 Up 3 0 No Any power of 2 from 1 to 128 Up 0 0 No Timer synchronization/ chaining No 1. TIM1_CH2N with TIM1_CH1 4.12 Analog-to-digital converter (ADC1) STM8S001J3 contains a 10-bit successive approximation A/D converter (ADC1) with up to three external and one internal multiplexed input channels and the following main features: • Input voltage range: 0 to VDDA • Conversion time: 14 clock cycles • Single and continuous, buffered continuous conversion modes • Buffer size (10 x 10 bits) • Scan mode for single and continuous conversion of a sequence of channels • Analog watchdog capability with programmable upper and lower thresholds • Analog watchdog interrupt • Internal reference voltage on channel AIN7 • External trigger input • Trigger from TIM1 TRGO • End of conversion (EOC) interrupt next paragraph : Internal bandgap reference voltage Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal bandgap reference is constant and can be used, for example, to monitor VDD or to determine the absolute voltage on external input channels. It is independent of variations in VDD and ambient temperature TA. 4.13 Communication interfaces The following communication interfaces are implemented: 18/84 • UART1: full feature UART, synchronous mode, SmartCard mode, IrDA mode, LIN2.1 master capability • SPI: master mode transmit/receive only, slave mode receive only, 8 Mbit/s • I²C: up to 400 Kbit/s DS12129 Rev 4 STM8S001J3 4.13.1 Functional overview UART1 Main features • 1 Mbit/s full duplex SCI • High precision baud rate generator • Smartcard reader emulation • IrDA SIR encoder decoder • LIN master mode • Single wire half duplex mode Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver • Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt) • Transmission error detection with interrupt generation • Parity control LIN master mode 4.13.2 • Emission: generates 13-bit synch. break frame • Reception: detects 11-bit break frame SPI • Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave • Unidirectional transfer: SPI master mode transmit/receive only, SPI slave mode receive only • Simplex master synchronous transfers on two lines with a possible bidirectional data line • Master or slave operation - selectable by software • CRC calculation • 1 byte Tx and Rx buffer DS12129 Rev 4 19/84 24 Functional overview 4.13.3 I2C • • 20/84 STM8S001J3 I2C master features – Clock generation – Start and stop generation I2C slave features – Programmable I2C address detection – Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz) DS12129 Rev 4 STM8S001J3 5 Pinouts and pin descriptions Pinouts and pin descriptions This section presents the pinouts and pin descriptions for STM8S001J3. Table 4 introduces the legends and abbreviations that are used in the upcoming subsections. Table 4. Legend/abbreviations for STM8S001J3 pin description tables Type I = input, O = output, S = power supply Level Port and control configuration 5.1 CM = CMOS Output HS = high sink O1 = slow (up to 2 MHz) O2 = fast (up to 10 MHz) O3 = fast/slow programmability with slow as default state after reset O4 = fast/slow programmability with fast as default state after reset Output speed Reset state Input Input float = floating, wpu = weak pull-up Output T = true open drain, OD = open drain, PP = push pull Bold x (pin state after internal reset release) Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. STM8S001J3 SO8N pinout and pin description Figure 3 presents the STM8S001J3 pinout image and Table 5 below presents the device’s pins description. Figure 3. STM8S001J3 SO8N pinout PD5/AIN5/UART1_TX/ PD3/AIN4/TIM2_CH2/ADC_ETR/ PD1/SWIM/ PC6/SPI_MOSI/[TIM1_CH1] PD6/AIN6/UART1_RX/ PA1/OSCIN 1 8 VSS/VSSA 2 7 PC5/SPI_SCK/[TIM2_CH1]/ PC4/CLK_CCO/TIM1_CH4/[AIN2]/[TIM1_CH2N] PC3/TIM1_CH3/[TLI]/[TIM1_CH1N] VCAP 3 6 PB4/I2C_SCL/[ADC_ETR] VDD/VDDA 4 5 PB5/I2C_SDA/[TIM1_BKIN]/ PA3/TIM2_CH3/[SPI_NSS]/[UART1_TX] STM8S MSv44652V2 1. [ ] Alternative function option (if the same alternate function is shown twice, it indicated an exclusive choice and not a duplication of the function). DS12129 Rev 4 21/84 24 Pinouts and pin descriptions STM8S001J3 Table 5. STM8S001J3 pin description PD6/ AIN6/ UART1 _RX(2) I/O I/O Alternate function after remap [option bit] High sink(1) OD X X X HS O3 X X Port D6 Analog input 6/ UART1 data receive - X X X - O1 X X Port A1 External clock input (HSE clock) - 1 PA1/ OSCIN(3) Default alternate function Speed Type Main function (after PP reset) Ext. interr. Pin name SO8N Output wpu Input Floating Pin no. 2 VSS/VSSA S - - - - - - - Ground - 3 VCAP S - - - - - - - 1.8 V regulator capacitor - 4 VDD/VDDA S - - - - - - - Power supply - 5 6 PA3/ TIM2_ CH3 [SPI_ NSS]\ [UART1_TX](2) I/O X X X HS O3 X X Port A3 Timer 2 channel 3 SPI master/ slave select [AFR1] UART1 data transmit [AFR1 and AFR0] PB5/ I2C_ SDA [TIM1_ BKIN] I/O X - X - O1 T(4) - Port B5 I2C data Timer 1 break input [AFR4] O1 T(4) I2C clock ADC external trigger [AFR4] Port C3 Timer 1 channel 3 Top level interrupt [AFR3] Timer 1 inverted channel 1 [AFR7] Analog input 2 [AFR2], Timer 1 inverted channel 2 [AFR7] Timer 2 channel 1 [AFR0] PB4/ I2C_ SCL /[ADC_ETR] PC3/ TIM1_CH3 [TLI] [TIM1_ CH1N] 7 22/84 I/O I/O X X - X X X - HS O3 X - X Port B4 PC4/ CLK_CCO/ TIM1_ CH4/[AIN2]/ [TIM1_ CH2N] I/O X X X HS O3 X X Port C4 Configurable clock output/Timer 1 - channel 4 PC5/ SPI_SCK [TIM2_ CH1] I/O X X X HS O3 X X Port C5 SPI clock DS12129 Rev 4 STM8S001J3 Pinouts and pin descriptions Table 5. STM8S001J3 pin description (continued) PC6/ SPI_MOSI [TIM1_ CH1] PD1/ SWIM(5) 8 I/O I/O Default alternate function Alternate function after remap [option bit] High sink(1) Speed Type Main function (after PP reset) Ext. interr. Pin name SO8N Output wpu Input Floating Pin no. OD X(5) X X HS O3 X X Port C6 X X(5) X HS O4 X X Port D1 SWIM data interface - - - SPI master out/slave in PD3/ AIN4/ TIM2_ CH2/ ADC_ ETR I/O X(5) X X HS O3 X X Port D3 Analog input 4/ Timer 2 channel 2/ADC external trigger PD5/ AIN5/ UART1 _TX I/O X(5) X X HS O3 X X Port D5 Analog input 5/ UART1 data transmit Timer 1 channel 1 [AFR0] 1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings. 2. By remapping UART1_TX (AFR0=1 and AFR1=1) to PA3 the UART1_RX alternate function on PD6 becomes unavailable. UART1 can be then used only in Single wire half-duplex mode or in Smartcard-reader emulation mode. 3. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input mode if halt/active-halt is used in the application. 4. In the open-drain output column, “T” defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). Although PB5 itself is a true open drain GPIO with its respective internal circuitry and characteristics, VIN maximum of the pin number 5 is limited by the standard GPIO PA3 which is also bonded to pin number 5. 5. The PD1 pin is in input pull-up during the reset phase and after internal reset release. This PD1 default state influences all GPIOs connected in parallel on pin# 8 (PC6, PD3, PD5). Note: The PA2, PB0, PB1, PB2, PB3, PB6, PB7, PC1, PC2, PC7, PD0, PD2, PD4, PD7, PE5 and PF4 GPIOs should be configured after device reset in output push-pull mode with output low-state to reduce the device’s consumption and to improve its EMC immunity. The GPIOs mentioned above are not connected to pins, and they are in input-floating mode after a device reset. Note: As several pins provide a connection to multiple GPIOs, the mode selection for any of those GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PD1 is also seen on PC6, PD3 and PD5. Push-pull configuration of PC3 is also seen on PC4 and PC5, etc. DS12129 Rev 4 23/84 24 Pinouts and pin descriptions 5.2 STM8S001J3 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). 24/84 DS12129 Rev 4 STM8S001J3 Memory and register map 6 Memory and register map 6.1 Memory map Figure 4. Memory map 0x00 0000 RAM (1 Kbyte) 0x00 03FF 0x00 0800 513 byte stack Reserved 0x00 4000 Data EEPROM 0x00 407F 0x00 47FF 0x00 4800 0x00 480A 0x00 480B Reserved Option bytes Reserved 0x00 4FFF 0x00 5000 GPIO and periph. reg. 0x00 57FF 0x00 5800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 0x00 9FFF 0x00 A000 CPU/SWIM/debug/ITC registers 32 interrupt vectors Flash program memory (8 Kbyte) Reserved 0x02 7FFF DS12129 Rev 4 MS36410V1 25/84 36 Memory and register map STM8S001J3 Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 6. Flash, Data EEPROM and RAM boundary addresses Memory area Size (byte) Start address End address Flash program memory 8K 0x00 8000 0x00 9FFF RAM 1K 0x00 0000 0x00 03FF Data EEPROM 128 0x00 4000 0x00 407F 6.2 Register map 6.2.1 I/O port hardware register map Table 7. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX(1) PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX(1) PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0xXX(1) PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX(1) PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 26/84 Block Port A Port B Port C Port D DS12129 Rev 4 STM8S001J3 Memory and register map Table 7. I/O port hardware register map (continued) Register label Register name Reset status 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xXX(1) PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xXX(1) PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 Address 0x00 5016 0x00 501B Block Port E Port F 1. Depends on the external circuitry. DS12129 Rev 4 27/84 36 Memory and register map 6.2.2 STM8S001J3 General hardware register map Table 8. General hardware register map Address Block Register label 0x00 501E to 0x00 5059 Reset status Reserved area (60 byte) 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF 0x00 505F FLASH _IAPSR Flash in-application programming status register 0x00 0x00 505D Flash 0x00 5060 to 0x00 5061 0x00 5062 Reserved area (2 byte) Flash FLASH _PUKR 0x00 5063 0x00 5064 0x00 50A0 0x00 50A1 Flash FLASH _DUKR ITC 0x00 50C1 Data EEPROM unprotection register 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reserved area (17 byte) RST RST_SR 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 Reserved area (59 byte) 0x00 50A2 to 0x00 50B2 0x00 50B3 Flash Program memory unprotection register Reserved area (1 byte) 0x00 5065 to 0x00 509F Reset status register 0xXX(1) Reserved area (12 byte) CLK CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX CLK_CKDIVR Clock divider register 0x18 CLK_PCKENR1 Peripheral clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50C6 0x00 50C7 28/84 Register name CLK DS12129 Rev 4 STM8S001J3 Memory and register map Table 8. General hardware register map (continued) Address Block Register label 0x00 50CB CLK CLK_HSITRIMR HSI clock calibration trimming register 0x00 CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 0x00 50CE to 0x00 50D0 0x00 50D1 0x00 50D2 Reserved area (3 byte) WWDG WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F 0x00 50D3 to 0x00 50DF Reserved area (13 byte) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0xXX(2) IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 byte) 0x00 50F0 0x00 50F1 Reset status Reserved area (1 byte) 0x00 50CC 0x00 50CD Register name AWU 0x00 50F2 AWU_CSR1 AWU control/status register 1 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 0x00 50F3 to 0x00 50FF Reserved area (13 byte) 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 SPI_SR SPI status register 0x02 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0x00 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0x00 0x00 5203 0x00 5204 SPI 0x00 5208 to 0x00 520F Reserved area (8 byte) 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 I2C_FREQR I2C frequency register 0x00 I2C_OARL I2C own address register low 0x00 I2C_OARH I2C own address register high 0x00 0x00 5212 0x00 5213 0x00 5214 I2C 0x00 5215 Reserved DS12129 Rev 4 29/84 36 Memory and register map STM8S001J3 Table 8. General hardware register map (continued) Register label Register name Reset status 0x00 5216 I2C_DR I2C data register 0x00 0x00 5217 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C clock control register low 0x00 0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 521E I2C_PECR I2C packet error checking register 0x00 Address 0x00 521A Block I2C 0x00 521F to 0x00 522F Reserved area (17 byte) 0x00 5230 UART1_SR UART1 status register 0xC0 0x00 5231 UART1_DR UART1 data register 0xXX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 0x00 5235 UART1 0x00 523B to 0x00 523F Reserved area (5 bytes) 0x00 523B to 0x00523F Reserved area (21 byte) 30/84 DS12129 Rev 4 STM8S001J3 Memory and register map Table 8. General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 Address 0x00 525F 0x00 5260 0x00 5270 to 0x00 52FF Block TIM1 Reserved area (147 byte) DS12129 Rev 4 31/84 36 Memory and register map STM8S001J3 Table 8. General hardware register map (continued) Address Block 0x00 5300 Register label Register name Reset status TIM2_CR1 TIM2 control register 1 0x00 0x00 5301 Reserved 0x00 5302 Reserved 0x00 5303 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5304 TIM2_SR1 TIM2 status register 1 0x00 0x00 5305 TIM2_SR2 TIM2 status register 2 0x00 0x00 5306 TIM2_EGR TIM2 event generation register 0x00 0x00 5307 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5308 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 5309 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00 0x00 530A TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 TIM2_CCER2 TIM2 capture/compare enable register 2 0x00 0x00 530C TIM2_CNTRH TIM2 counter high 0x00 0x00 530D TIM2_CNTRL TIM2 counter low 0x00 0x00 530E TIM2_PSCR TIM2 prescaler register 0x00 0x00 530F TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 5310 TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5311 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5312 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5313 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00 0x00 5314 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5315 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00 0x00 5316 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00 0x00 530B TIM2 0x00 5317 to 0x00 533F Reserved area (43 byte) 0x00 5340 TIM4_CR1 0x00 5341 Reserved 0x00 5342 Reserved 0x00 5343 0x00 TIM4_IER TIM4 interrupt enable register 0x00 TIM4_SR TIM4 status register 0x00 0x00 5345 TIM4_EGR TIM4 event generation register 0x00 0x00 5346 TIM4_CNTR TIM4 counter 0x00 0x00 5347 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5348 TIM4_ARR TIM4 auto-reload register 0xFF 0x00 5344 32/84 TIM4 control register 1 TIM4 DS12129 Rev 4 STM8S001J3 Memory and register map Table 8. General hardware register map (continued) Address Block Register label 0x00 5349 to 0x00 53DF 0x00 53E0 to 0x00 53F3 Register name Reset status Reserved area (153 byte) ADC1 ADC_DBxR 0x00 53F4 to 0x00 53FF ADC data buffer registers 0x00 Reserved area (12 byte) 0x00 5400 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 ADC_TDRL ADC Schmitt trigger disable register low 0x00 ADC_HTRH ADC high threshold register high 0x03 0x00 5409 ADC_HTRL ADC high threshold register low 0xFF 0x00 540A ADC_LTRH ADC low threshold register high 0x00 0x00 540B ADC_LTRL ADC low threshold register low 0x00 0x00 540C ADC_AWSRH ADC analog watchdog status register high 0x00 0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00 0x00 540E ADC_AWCRH ADC analog watchdog control register high 0x00 0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00 0x00 5407 0x00 5408 ADC1 0x00 5410 to 0x00 57FF Reserved area (1008 byte) 1. Depends on the previous reset source. 2. Write only register. DS12129 Rev 4 33/84 36 Memory and register map 6.2.3 STM8S001J3 CPU/SWIM/debug module/interrupt controller registers Table 9. CPU/SWIM/debug module/interrupt controller registers Register Label Register Name Reset Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 (1) CPU 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 byte) CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF ITC_SPR4 Interrupt software priority register 4 0xFF ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F73 0x00 7F74 CPU ITC 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F 34/84 Reserved area (2 byte) SWIM SWIM_CSR SWIM control status register Reserved area (15 byte) DS12129 Rev 4 0x00 STM8S001J3 Memory and register map Table 9. CPU/SWIM/debug module/interrupt controller registers (continued) Register Label Register Name Reset Status 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF Address 0x00 7F95 Block DM 0x00 7F9B to 0x00 7F9F Reserved area (5 byte) 1. Accessible by debug module only DS12129 Rev 4 35/84 36 Interrupt vector mapping 7 STM8S001J3 Interrupt vector mapping Table 10. Interrupt mapping IRQ no. Source block - RESET - TRAP 0 TLI 1 2 Wakeup from Wakeup from Halt mode Active-halt mode Description Reset Vector address Yes Yes 0x00 8000 Software interrupt - - 0x00 8004 External top level interrupt - - 0x00 8008 AWU Auto wake up from halt - Yes 0x00 800C CLK Clock controller - - 0x00 8010 Yes(1) 0x00 8014 Yes (1) 3 EXTI0 Port A external interrupts 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 - Reserved 0x00 8028 9 - Reserved 0x00 802C 10 SPI 11 TIM1 12 End of transfer Yes Yes 0x00 8030 TIM1 update/overflow/underflow/ trigger/break - - 0x00 8034 TIM1 TIM1 capture/compare - - 0x00 8038 13 TIM2 TIM2 update /overflow - - 0x00 803C 14 TIM2 TIM2 capture/compare - - 0x00 8040 15 - Reserved 0x00 8044 16 - Reserved 0x00 8048 17 UART1 Tx complete - - 0x00 804C 18 UART1 Receive register DATA FULL - - 0x00 8050 19 I2C Yes Yes 0x00 8054 20 - Reserved 0x00 8058 21 - Reserved 0x00 805C 22 ADC1 ADC1 end of conversion/analog watchdog interrupt - - 0x00 8060 23 TIM4 TIM4 update/overflow - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 I2C interrupt Reserved 1. Except PA1 36/84 DS12129 Rev 4 0x00 806C to 0x00 807C STM8S001J3 8 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 11: Option bytes below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 11. Option bytes Option name Addr. 0x4800 0x4801 0x4802 0x4803 0x4804 Read-out protection (ROP) User boot code (UBC) Alternate function remapping (AFR) 0x4805 Option byte no. Option bits 7 6 5 0x4807 0x4809 0x480A HSE clock startup 2 1 0 ROP[7:0] 0x00 OPT1 UBC[7:0] 0x00 NUBC[7:0] 0xFF NOPT1 OPT2 NOPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF WWDG _HW WWDG _HALT 0x00 OPT3 Reserved HSITRIM LSI _EN IWDG _HW NOPT3 Reserved NHSI TRIM NLSI _EN NIWDG _HW NWWDG NWWDG _HW _HALT 0xFF OPT4 Reserved EXT CLK CKAWU SEL PRS C1 PRS C0 0x00 NOPT4 Reserved NEXT CLK NCKAW USEL NPR SC1 NPR SC0 0xFF Clock option 0x4808 3 OPT0 Misc. option 0x4806 4 Factory default setting OPT5 NOPT5 HSECNT[7:0] 0x00 NHSECNT[7:0] 0xFF Table 12. Option byte description Option byte no. OPT0 Description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. DS12129 Rev 4 37/84 39 Option bytes STM8S001J3 Table 12. Option byte description (continued) Option byte no. Description OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Pages 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected Page 0 and page 1 contain the interrupt vectors. ... 0x7F: Pages 0 to 126 defined as UBC, memory write-protected Other values: Pages 0 to 127 defined as UBC, memory-write protected. Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details. OPT2 AFR[7:0] Refer to the following section for alternate function remapping descriptions of bits [7:2] and [1:0] respectively. HSITRIM: high-speed internal clock trimming register size 0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source OPT3 IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN OPT4 CKAWUSEL: Auto wakeup unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 38/84 HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilization time. 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles DS12129 Rev 4 STM8S001J3 8.1 Option bytes Alternate function remapping bits Table 13. STM8S001J3 alternate function remapping bits for 8-pin devices Option byte number OPT2 Description AFR7Alternate function remapping option 7 0: AFR7 remapping option inactive: default alternate function(1) 1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N. AFR6 Alternate function remapping option 6 Reserved. AFR5 Alternate function remapping option 5 Reserved. AFR4 Alternate function remapping option 4 0: AFR4 remapping option inactive: default alternate function(1). 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN. AFR3 Alternate function remapping option 3 0: AFR3 remapping option inactive: default alternate function(1) 1: Port C3 alternate function = TLI. AFR2 Alternate function remapping option 2 0: AFR2 remapping option inactive: default alternate function(1) 1: Port C4 alternate function = AIN2. AFR1 Alternate function remapping option 1 (2) 0: AFR1 remapping option inactive: default alternate function(1) 1: If AFR0=0: Port A3 alternate function = SPI_NSS. If AFR0=1: Port A3 alternate function = UART_TX; port D6 alternate function UART_RX unavailable. AFR0 Alternate function remapping option 0(2) 0: AFR0 remapping option inactive: Default alternate functions(1) 1: Port C5 alternate function = TIM2_CH1; port C6 alternate function = TIM1_CH1. 1. Refer to the pinout description. 2. Do not use more than one remapping option in the same port. DS12129 Rev 4 39/84 39 Electrical characteristics STM8S001J3 9 Electrical characteristics 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 σ). 9.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 σ). 9.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 5. Figure 5. Pin loading conditions STM8 pin 50 pF 40/84 DS12129 Rev 4 STM8S001J3 9.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6. Figure 6. Pin input voltage STM8 pin VIN 9.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 14. Voltage characteristics Symbol VDDx - VSS VIN VESD Ratings Supply voltage(1) Input voltage on true open drain pins(2) (2) Input voltage on any other pin Electrostatic discharge voltage Min Max -0.3 6.5 VSS - 0.3 6.5 VSS - 0.3 VDD + 0.3 see Absolute maximum ratings (electrical sensitivity) on page 73 Unit V - 1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN