STM8S007C8T6

STM8S007C8 Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash, true data EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C Datasheet - production data Features • Core – Max fCPU: up to 24 MHz, 0 wait states @ fCPU ≤ 16 MHz – Advanced STM8 core with Harvard architecture and 3-stage pipeline – Extended instruction set – Max 20 MIPS @ 24 MHz • Memories – Program: 64 Kbytes Flash; data retention 20 years at 55 °C after 100 cycles – Data: 128 bytes true data EEPROM; endurance 100 kcycles – RAM: 6 Kbytes • Clock, reset and supply management – 2.95 to 5.5 V operating voltage – Low power crystal resonator oscillator – External clock input – Internal, user-trimmable 16 MHz RC – Internal low power 128 kHz RC – Clock security system with clock monitor – Wait, active-halt, & halt low power modes – Peripheral clocks switched off individually – Permanently active, low consumption power-on and power-down reset LQFP48 7 x 7mm • Communications interfaces – UART with clock output for synchronous operation - LIN master mode – UART with LIN 2.1 compliant, master/slave modes and automatic resynchronization – SPI interface up to 10 Mbit/s – I2C interface up to 400 Kbit/s • 10-bit ADC with up to 16 channels • I/Os – 38 I/Os including 16 high sink outputs – Highly robust I/O design, immune against current injection – Development support – Single wire interface module (SWIM) and debug module (DM) • Interrupt management – Nested interrupt controller with 32 interrupts – Up to 37 external interrupts on 6 vectors • Timers – 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) – Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization – 8-bit basic timer with 8-bit prescaler – Auto wakeup timer – Window watchdog, independent watchdog October 2018 This is information on a product in full production. DS8633 Rev 6 1/93 www.st.com Contents STM8S007C8 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 12 4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 16 4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.13 Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/93 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14.2 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14.4 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 6 4.14.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DS8633 Rev 6 STM8S007C8 Contents 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1 10 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1.5 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.6 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 56 9.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 58 9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.3.9 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 88 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DS8633 Rev 6 3/93 4 Contents STM8S007C8 12.3 13 4/93 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DS8633 Rev 6 STM8S007C8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STM8S007C8 value line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 14 TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Legend/abbreviations for STM8S007C8 pin description table . . . . . . . . . . . . . . . . . . . . . . 22 STM8S007C8 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Total current consumption with code execution in run mode at VDD = 5 V . . . . . . . . . . . . 49 Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 50 Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85° C . . . . . . . . . . 52 Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . 52 Total current consumption in halt mode at VDD = 5 V, TA -40 to 85° C . . . . . . . . . . . . . . . 53 Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 54 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DS8633 Rev 6 5/93 6 List of tables Table 49. Table 50. Table 51. 6/93 STM8S007C8 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 84 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DS8633 Rev 6 STM8S007C8 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. STM8S007C8 value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typical HSI frequency variation vs VDD at 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 59 Typical LSI frequency variation vs VDD @ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Typical VIL and VIH vs VDD @ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Typical pull-up resistance vs VDD @ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Typical pull-up current vs VDD @ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typ. VOL @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typ. VDD - VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical NRST VIL and VIH vs VDD @ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical NRST pull-up resistance vs VDD @ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . 71 Typical NRST pull-up current vs VDD @ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 83 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . 85 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 STM8S007C8 value line ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DS8633 Rev 6 7/93 7 Introduction 1 STM8S007C8 Introduction This datasheet contains the description of the STM8S007C8 value line features, pinout, electrical characteristics, mechanical data and ordering information. 8/93 • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016). • For information on programming, erasing and protection of the internal Flash memory please refer to the PM0051 (How to program STM8S and STM8A Flash program memory and data EEPROM). • For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). • For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). DS8633 Rev 6 STM8S007C8 2 Description Description The STM8S007C8 value line 8-bit microcontrollers offer 64 Kbytes of Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family reference manual (RM0016). The STM8S007C8 value line devices provide the following benefits: reduced system cost, performance, robustness, short development cycles, and product longevity. The system cost is reduced thanks to a true data EEPROM for up to 100 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system. Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. Full documentation is offered with a wide choice of development tools. Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply. Table 1. STM8S007C8 value line features Features STM8S007C8 Pin count 48 Max. number of GPIOs (I/O) 38 External interrupt pins 35 Timer CAPCOM channels 9 Timer complementary outputs 3 A/D converter channels 10 High-sink I/Os 16 High-density Flash program memory 64 Kbyte Data EEPROM 128 bytes RAM 6 Kbytes DS8633 Rev 6 9/93 25 Block diagram 3 STM8S007C8 Block diagram Figure 1. STM8S007C8 value line block diagram Reset block XTAL 1-24 MHz Clock controller Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Debug / SWIM 64 Kbyte high density program Flash 400 Kbit/s I2C 128 byte data EEPROM 10 Mbit/s SPI LIN master SPI emul. UART1 Master/slave autosynchro UART3 16 channels ADC2 Address and data bus Single wire debug interface 6 Kbyte RAM Boot ROM 16-bit advanced control timer (TM1) 16-bit general purpose timers (TIM2, TIM3) Up to 4 CAPCOM channels + 3 complementary outputs Up to 5 CAPCPOM channels 8-bit basic timer (TIM4) 1/2/4 kHz beep Beeper AWU timer MS61103V1 10/93 DS8633 Rev 6 STM8S007C8 4 Product overview Product overview The following section intends to give an overview of the basic features of the STM8S007C8 value line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers • Harvard architecture • 3-stage pipeline • 32-bit wide program memory bus - single cycle fetching for most instructions • X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations • 8-bit accumulator • 24-bit program counter - 16-Mbyte linear memory space • 16-bit stack pointer - access to a 64 K-level stack • 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing • 20 addressing modes • Indexed indirect addressing mode for look-up tables located anywhere in the address space • Stack pointer relative addressing mode for local variables and parameter passing Instruction set • 80 instructions with 2-byte average instruction size • Standard data movement and logic/arithmetic functions • 8-bit by 8-bit multiplication • 16-bit by 8-bit and 16-bit by 16-bit division • Bit manipulation • Data transfer between stack and accumulator (push/pop) with direct stack access • Data transfer using the X and Y registers or direct memory-to-memory transfers DS8633 Rev 6 11/93 25 Product overview 4.2 STM8S007C8 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. 4.3 4.4 • R/W to RAM and peripheral registers in real-time • R/W access to all resources by stalling the CPU • Breakpoints on all program-memory instructions (software breakpoints) • Two advanced breakpoints, 23 predefined configurations Interrupt controller • Nested interrupts with three software priority levels • 32 interrupt vectors with hardware priority • Up to 33 external interrupts on six vectors including TLI • Trap and reset interrupts Flash program memory and data EEPROM • 64 Kbyte of high-density Flash program single voltage Flash memory • 128 byte true data EEPROM • Read while write: Writing in data memory possible while executing code in program memory. • User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 2. 12/93 DS8633 Rev 6 STM8S007C8 Product overview The size of the UBC is programmable through the UBC option byte (Table 12), in increments of 1 page (512 byte) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: • Main program memory: 64 Kbyte minus UBC • User-specific boot code (UBC): Configurable up to 64 Kbyte The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2. Flash memory organization Data EEPROM memory Data memory area (up to 2 Kbyte) Option bytes UBC area Remains write protected during IAP 64 Kbytes Flash program memory Programmable area from 1 Kbyte (2 first pages) up to 64 Kbytes (1 page steps) Program memory area Write access possible for IAP Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. DS8633 Rev 6 13/93 25 Product overview 4.5 STM8S007C8 Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features • Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. • Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • Master clock sources: Four different clock sources can be used to drive the master clock: – 1-24 MHz high-speed external crystal (HSE) – Up to 24 MHz high-speed user-external clock (HSE user-ext) – 16 MHz high-speed internal RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI) • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. • Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers 14/93 Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved DS8633 Rev 6 STM8S007C8 4.6 Product overview Power management For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources. 4.7 • Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. • Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. • Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. • Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. 2. Refresh out of window: the down-counter is refreshed before its value is lower than the one stored in the window register. DS8633 Rev 6 15/93 25 Product overview STM8S007C8 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s. 4.8 4.9 Auto wakeup counter • Used for auto wakeup from active halt mode • Clock source: internal 128 kHz internal low frequency RC oscillator or external clock • LSI clock can be internally connected to TIM3 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver. 4.11 16/93 • 16-bit up, down and up/down autoreload counter with 16-bit prescaler • Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output • Synchronization module to control the timer with external signals • Break input to force the timer outputs into a defined state • Three complementary outputs with adjustable dead time • Encoder mode • Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break TIM2, TIM3 - 16-bit general purpose timers • 16-bit autoreload (AR) up-counter • 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 • Timers with 3 or 2 individually configurable capture/compare channels • PWM mode • Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update DS8633 Rev 6 STM8S007C8 4.12 Product overview TIM4 - 8-bit basic timer • 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 • Clock source: CPU clock • Interrupt source: 1 x overflow/update Table 3. TIM timer features Timer Counter size (bits) TIM1 16 Any integer from 1 to 65536 TIM2 16 TIM3 TIM4 4.13 Counting CAPCOM Complem. Ext. mode trigger channels outputs Prescaler Up/down 4 3 Yes Any power of 2 from 1 to 32768 Up 3 0 No 16 Any power of 2 from 1 to 32768 Up 2 0 No 8 Any power of 2 from 1 to 128 Up 0 0 No Timer synchronization/ chaining No Analog-to-digital converter (ADC2) STM8S007C8 value line products contain a 10-bit successive approximation A/D converter (ADC2) with up to 10 multiplexed input channels and the following main features: 4.14 • Input voltage range: 0 to VDDA • Conversion time: 14 clock cycles • Single and continuous modes • External trigger input • Trigger from TIM1 TRGO • End of conversion (EOC) interrupt Communication interfaces The following communication interfaces are implemented: • UART1: full feature UART, SPI master mode, SmartCard mode, IrDA mode, LIN2.1 master capability, single-wire mode • UART3: full feature UART, LIN2.1 master/slave capability • SPI: full and half-duplex, 10 Mbit/s • I²C: up to 400 Kbit/s DS8633 Rev 6 17/93 25 Product overview 4.14.1 STM8S007C8 UART1 Main features • 1 Mbit/s full duplex SCI • SPI emulation • High precision baud rate generator • Smartcard emulation • IrDA SIR encoder decoder • LIN master mode • Single wire half duplex mode Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver • Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt) • Transmission error detection with interrupt generation • Parity control Synchronous communication • Full duplex synchronous transfers • SPI master operation • 8-bit data communication • Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16) LIN master mode 4.14.2 • Emission: generates 13-bit synch. break frame • Reception: detects 11-bit break frame UART3 Main features 18/93 • 1 Mbit/s full duplex SCI • LIN master capable • High precision baud rate generator DS8633 Rev 6 STM8S007C8 Product overview Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver • Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt) • Transmission error detection with interrupt generation • Parity control LIN master capability • Emission: Generates 13-bit synch break frame • Reception: Detects 11-bit break frame LIN slave mode 4.14.3 • Autonomous header handling - one single interrupt per valid message header • Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 % • Synch delimiter checking • 11-bit LIN synch break detection - break detection always active • Parity check on the LIN identifier field • LIN error management • Hot plugging support SPI • Maximum speed: 10 Mbit/s (fMASTER/2) both for master and slave • Full duplex synchronous transfers • Simplex synchronous transfers on two lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • CRC calculation • 1 byte Tx and Rx buffer • Slave/master selection input pin DS8633 Rev 6 19/93 25 Product overview 4.14.4 I2C • • 20/93 STM8S007C8 I2C master features – Clock generation – Start and stop generation I2C slave features – Programmable I2C address detection – Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz) DS8633 Rev 6 STM8S007C8 Pinouts and pin descriptions PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PE3/TIM1_BKIN Figure 3. LQFP 48-pin pinout NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/(HS) PA4 UART1_TX/(HS) PA5 UART1_CK/(HS) PA6 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 2223 24 PG1 PG0 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS VDDA VSSA AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR/AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 AIN8/PE7 AIN9/PE6 5 Pinouts and pin descriptions 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). DS8633 Rev 6 21/93 25 Pinouts and pin descriptions STM8S007C8 Table 4. Legend/abbreviations for STM8S007C8 pin description table Type I = input, O = output, S = power supply floating Input wpu = weak pull-up Ext. interrupt = external interrupt HS = high sink O1 = Slow (up to 2 MHz) Speed Output O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset OD = open drain PP = push pull Reset state Bold X (pin state after internal reset release) Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. Table 5. STM8S007C8 pin description wpu Ext. interrupt High sink Speed OD PP Main function (after reset) floating Alternate function after remap [option bit] 1 NRST I/O - X - - - - - Reset 2 PA1/OSCIN I/O X X - - O1 X X Port A1 Resonator/ crystal in - 3 PA2/OSCOUT I/O X X X - O1 X X Port A2 Resonator/ crystal out - 4 VSSIO_1 S - - - - - - - I/O ground - 5 VSS S - - - - - - - Digital ground - 6 VCAP S - - - - - - - 1.8 V regulator capacitor - 7 VDD S - - - - - - - Digital power supply - 8 VDDIO_1 S - - - - - - - I/O power supply - 9 PA3/TIM2_CH3 I/O X X X - O1 X X Port A3 Timer 2 channel3 (1) I/O X X X HS O3 X X Port A4 UART1 receive - 11 PA5/UART1_TX I/O X X X HS O3 X X Port A5 UART1 transmit - 12 PA6/UART1_CK I/O X X X HS O3 X X UART1 Port A6 synchronous clock 10 22/93 Output Type Pin number Input Pin name PA4/UART1_RX DS8633 Rev 6 Default alternate function - TIM3_CH1 [AFR1] - STM8S007C8 Pinouts and pin descriptions Table 5. STM8S007C8 pin description (continued) wpu Ext. interrupt High sink Speed OD PP Alternate function after remap [option bit] floating Main function (after reset) Output Type Pin number Input 13 VDDA S - - - - - - - Analog power supply - 14 VSSA S - - - - - - - Analog ground - 15 PB7/AIN7 I/O X X X - O1 X X Port B7 Analog input 7 - 16 PB6/AIN6 I/O X X X - O1 X X Port B6 Analog input 6 - 17 PB5/AIN5 I/O X X X - O1 X X Port B5 Analog input 5 I2C_SDA [AFR6] 18 PB4/AIN4 I/O X X X - O1 X X Port B4 Analog input 4 I2C_SCL [AFR6] 19 PB3/AIN3 I/O X X X - O1 X X Port B3 Analog input 3 TIM1_ETR [AFR5] 20 PB2/AIN2 I/O X X X - O1 X X Port B2 Analog input 2 TIM1_ CH3N [AFR5] 21 PB1/AIN1 I/O X X X - O1 X X Port B1 Analog input 1 TIM1_ CH2N [AFR5] 22 PB0/AIN0 I/O X X X - O1 X X Port B0 Analog input 0 TIM1_ CH1N [AFR5] 23 PE7/AIN8 I/O X X X - O1 X X Port E7 Analog input 8 - 24 PE6/AIN9 I/O X X X - O1 X X Port E6 Analog input 9 - 25 PE5/SPI_NSS I/O X X X - O1 X X SPI Port E5 master/slave select - 26 PC1/TIM1_CH1 I/O X X X HS O3 X X Port C1 Timer 1 channel 1 - 27 PC2/TIM1_CH2 I/O X X X HS O3 X X Port C2 Timer 1channel 2 - 28 PC3/TIM1_CH3 I/O X X X HS O3 X X Port C3 Timer 1 channel 3 - 29 PC4/TIM1_CH4 I/O X X X HS O3 X X Port C4 Timer 1 channel 4 - 30 PC5/SPI_SCK I/O X X X HS O3 X X Port C5 SPI clock - 31 VSSIO_2 S - - - - - - - I/O ground - 32 VDDIO_2 S - - - - - - - I/O power supply - Pin name DS8633 Rev 6 Default alternate function 23/93 25 Pinouts and pin descriptions STM8S007C8 Table 5. STM8S007C8 pin description (continued) Alternate function after remap [option bit] SPI master X Port C6 out/ slave in 34 PC7/SPI_MISO I/O X X X HS O3 X X Port C7 SPI master in/ slave out - 35 PG0 I/O X X - - O1 X X Port G0 - - 36 PG1 I/O X X - - O1 X X Port G1 - - 37 PE3/TIM1_BKIN I/O X X X - O1 X X 38 PE2/I2C_SDA I/O X - X - O1 T(2) - Port E2 I2C data - 39 PE1/I2C_SCL I/O X - X - O1 T(2) - Port E1 I2C clock - 40 PE0/CLK_CCO I/O X X X HS O3 X X PP X HS O3 X OD X Speed I/O X High sink PC6/SPI_MOSI floating 33 Pin name Type Ext. interrupt Main function (after reset) Output wpu Pin number Input Port E3 Port E0 Default alternate function Timer 1 break input Configurable clock output - - TIM1_BKIN [AFR3]/ CLK_CCO [AFR2] 41 PD0/TIM3_CH2 I/O X X X HS O3 X Timer 3 X Port D0 channel 2 42 PD1/SWIM(3) I/O X X X HS O4 X X Port D1 SWIM data interface 43 PD2/TIM3_CH1 I/O X X X HS O3 X X Port D2 Timer 3 channel 1 TIM2_CH3 [AFR1] 44 PD3/TIM2_CH2 I/O X X X HS O3 X X Port D3 Timer 2 channel 2 ADC_ETR [AFR0] 45 PD4/TIM2_CH1/B I/O X EEP X X HS O3 X X Port D4 Timer 2 channel 1 BEEP output [AFR7] 46 PD5/ UART3_TX I/O X X X - O1 X X Port D5 UART3 data transmit - 47 PD6/ UART3_RX(1) I/O X X X - O1 X X Port D6 UART3 data receive - 48 PD7/TLI I/O X X X - O1 X X Port D7 Top level interrupt - - 1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader. 2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). 3. The PD1 pin is in input pull-up during the reset phase and after the internal reset release. 24/93 DS8633 Rev 6 STM8S007C8 Pinouts and pin descriptions Note: The slope control of true open drain pins cannot be programmed and by default is limited to 2 MHz. 5.1 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). DS8633 Rev 6 25/93 25 Memory and register map STM8S007C8 6 Memory and register map 6.1 Memory map Figure 4. Memory map 0x00 0000 RAM (6 Kbytes) 0x00 17FF 0x00 1800 1024 bytes stack Reserved 0x00 3FFF 0x00 4000 128 bytes data EEPROM 0x00 407F 0x00 4080 0x00 47FF 0x00 4800 0x00 487F 0x00 4900 Reserved Option bytes Reserved 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 GPIO and peripheral registers (see Table 8 and Table 9 ) Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 CPU/SWIM/debug/ITC register (see Table 10 ) 32 interrupt vectors Flash program memory (64 bytes) 0x01 7FFF MS19412V2 26/93 DS8633 Rev 6 STM8S007C8 Memory and register map Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 6. Flash, Data EEPROM and RAM boundary addresses 6.2 Memory area Size (byte) Start address End address Flash program memory 64 K 0x00 8000 0x01 7FFF RAM 6K 0x00 0000 0x00 17FF Data EEPROM 128 0x00 4000 0x00 407F Register map Table 7. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0x00 PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 Block Port A Port B Port C Port D DS8633 Rev 6 27/93 37 Memory and register map STM8S007C8 Table 7. I/O port hardware register map (continued) Register label Register name Reset status 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0x00 PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0x00 PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 PH_ODR Port H data output latch register 0x00 0x00 5024 PH_IDR Port H input pin value register 0x00 PH_DDR Port H data direction register 0x00 0x00 5026 PH_CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 PI_ODR Port I data output latch register 0x00 0x00 5029 PI_IDR Port I input pin value register 0x00 PI_DDR Port I data direction register 0x00 0x00 502B PI_CR1 Port I control register 1 0x00 0x00 502C PI_CR2 Port I control register 2 0x00 Address 0x00 5016 0x00 501B 0x00 5020 0x00 5025 0x00 502A 28/93 Block Port E Port F Port G Port H Port I DS8633 Rev 6 STM8S007C8 Memory and register map Table 8. General hardware register map Address Block Register label 0x00 5050 to 0x00 5059 Register name Reset status Reserved area (10 byte) 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF 0x00 505F FLASH _IAPSR Flash in-application programming status register 0x00 0x00 505D Flash 0x00 5060 to 0x00 5061 0x00 5062 Reserved area (2 byte) Flash FLASH _PUKR 0x00 5063 0x00 5064 0x00 50A1 Flash FLASH _DUKR ITC 0x00 50C1 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reserved area (17 byte) RST RST_SR 0x00 50B4 to 0x00 50BF 0x00 50C0 Data EEPROM unprotection register Reserved area (59 byte) 0x00 50A2 to 0x00 50B2 0x00 50B3 0x00 Reserved area (1 byte) 0x00 5065 to 0x00 509F 0x00 50A0 Flash Program memory unprotection register Reset status register 0xXX(1) Reserved area (12 byte) CLK CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX CLK_CKDIVR Clock divider register 0x18 CLK_PCKENR1 Peripheral clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50C6 0x00 50C7 0x00 50CB CLK Reserved area (1 byte) DS8633 Rev 6 29/93 37 Memory and register map STM8S007C8 Table 8. General hardware register map (continued) Address Block 0x00 50CC 0x00 50CD CLK Register label Register name Reset status CLK_HSITRIMR HSI clock calibration trimming register 0x00 CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 0x00 50CE to 0x00 50D0 0x00 50D1 0x00 50D2 Reserved area (3 byte) WWDG WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F 0x00 50D3 to 0x00 50DF Reserved area (13 byte) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0xXX(2) IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 byte) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 BEEP AWU_CSR1 AWU control/status register 1 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F 0x00 50F4 to 0x00 50FF Reserved area (12 byte) 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 SPI_SR SPI status register 0x02 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0x00 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0x00 0x00 5203 0x00 5204 SPI 0x00 5208 to 0x00 520F Reserved area (8 byte) 0x00 5211 0x00 5212 0x00 5213 0x00 5214 I2C_CR2 I2C I 2C I2C I2C_FREQR 2C 0x00 control register 2 0x00 frequency register 0x00 I2C_OARL I own address register low 0x00 I2C_OARH I2C own address register high 0x00 0x00 5215 30/93 I2C control register 1 I2C_CR1 0x00 5210 Reserved DS8633 Rev 6 STM8S007C8 Memory and register map Table 8. General hardware register map (continued) Address Block 0x00 5216 Register label Register name Reset status I2C_DR I2C data register 0x00 2 0x00 5217 I2C_SR1 I C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 I2C_SR3 I2 0x00 0x00 5219 0x00 521A I2 C I2C_ITR C status register 3 2 I C interrupt control register 0x00 2 0x00 521B I2C_CCRL I C clock control register low 0x00 0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER 0x00 521E to 0x00 522F I 2C TRISE register 0x02 Reserved area (18 byte) 0x00 5230 UART1_SR UART1 status register 0xC0 0x00 5231 UART1_DR UART1 data register 0xXX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 0x00 5235 UART1 0x00 523B to 0x00 523F Reserved area (5 bytes) 0x00 5240 UART3_SR UART3 status register C0h 0x00 5241 UART3_DR UART3 data register 0xXX 0x00 5242 UART3_BRR1 UART3 baud rate register 1 0x00 0x00 5243 UART3_BRR2 UART3 baud rate register 2 0x00 UART3_CR1 UART3 control register 1 0x00 UART3_CR2 UART3 control register 2 0x00 0x00 5246 UART3_CR3 UART3 control register 3 0x00 0x00 5247 UART3_CR4 UART3 control register 4 0x00 0x00 5244 0x00 5245 UART3 0x00 5248 0x00 5249 0x00 524A to 0x00 524F Reserved UART3_CR6 UART3 control register 6 0x00 Reserved area (6 bytes) DS8633 Rev 6 31/93 37 Memory and register map STM8S007C8 Table 8. General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 Address 0x00 525F 0x00 5260 0x00 5270 to 0x00 52FF 32/93 Block TIM1 Reserved area (147 byte) DS8633 Rev 6 STM8S007C8 Memory and register map Table 8. General hardware register map (continued) Register label Register name Reset status 0x00 5300 TIM2_CR1 TIM2 control register 1 0x00 0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00 0x00 5308 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 5309 TIM2_CCER2 TIM2 capture/compare enable register 2 0x00 0x00 530A TIM2_CNTRH TIM2 counter high 0x00 TIM2_CNTRL TIM2 counter low 0x00 0x00 530C TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00 0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00 0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00 Address 0x00 530B Block TIM2 0x00 5315 to 0x00 531F Reserved area (11 byte) 0x00 5320 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 0x00 5327 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00 0x00 5328 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 5325 TIM3 DS8633 Rev 6 33/93 37 Memory and register map STM8S007C8 Table 8. General hardware register map (continued) Register label Register name Reset status 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 Address 0x00 532D 0x00 532E Block TIM3 0x00 5331 to 0x00 533F Reserved area (15 bytes) 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4_EGR TIM4 event generation register 0x00 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF 0x00 5344 TIM4 0x00 5347 to 0x00 53FF Reserved area (185 byte) 0x00 5400 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 ADC_CR3 ADC configuration register 3 0x00 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 0x00 5403 0x00 5404 ADC2 0x00 5408 to 0x00 57FF Reserved area (1016 byte) 1. Depends on the previous reset source. 2. Write only register. 34/93 DS8633 Rev 6 STM8S007C8 Memory and register map Table 9. CPU/SWIM/debug module/interrupt controller registers Register Label Register Name Reset Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17(2) 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 CPU(1) 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 byte) CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF ITC_SPR4 Interrupt software priority register 4 0xFF ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F73 0x00 7F74 CPU ITC 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F Reserved area (2 byte) SWIM SWIM_CSR SWIM control status register 0x00 Reserved area (15 byte) DS8633 Rev 6 35/93 37 Memory and register map STM8S007C8 Table 9. CPU/SWIM/debug module/interrupt controller registers (continued) Register Label Register Name Reset Status 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF Address 0x00 7F95 Block DM 0x00 7F9B to 0x00 7F9F Reserved area (5 byte) 1. Accessible by debug module only 2. Product dependent value, see Figure 4: Memory map. 36/93 DS8633 Rev 6 STM8S007C8 7 Interrupt vector mapping Interrupt vector mapping Table 10. Interrupt mapping IRQ no. Source block - RESET - TRAP 0 TLI 1 2 Wakeup from Wakeup from Halt mode Active-halt mode Description Reset Vector address Yes Yes 0x00 8000 Software interrupt - - 0x00 8004 External top level interrupt - - 0x00 8008 AWU Auto wake up from halt - Yes 0x00 800C CLK Clock controller - - 0x00 8010 Yes(1) 0x00 8014 Yes (1) 3 EXTI0 Port A external interrupts 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 - Reserved 0x00 8028 9 - Reserved 0x00 802C 10 SPI 11 TIM1 12 End of transfer Yes Yes 0x00 8030 TIM1 update/overflow/underflow/ trigger/break - - 0x00 8034 TIM1 TIM1 capture/compare - - 0x00 8038 13 TIM2 TIM2 update /overflow - - 0x00 803C 14 TIM2 TIM2 capture/compare - - 0x00 8040 15 TIM3 Update/overflow - - 0x00 8044 16 TIM3 Capture/compare - - 0x00 8048 17 UART1 Tx complete - - 0x00 804C 18 UART1 Receive register DATA FULL - - 0x00 8050 19 I2C I2C interrupt Yes Yes 0x00 8054 20 UART3 Tx complete - - 0x00 8058 21 UART3 Receive register DATA FULL - - 0x00 805C 22 ADC2 ADC2 end of conversion - - 0x00 8060 23 TIM4 TIM4 update/overflow - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 Reserved 0x00 806C to 0x00 807C 1. Except PA1 DS8633 Rev 6 37/93 37 Option bytes 8 STM8S007C8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 11: Option bytes below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 11. Option bytes Addr. 0x4800 0x4801 0x4802 0x4803 0x4804 Option name Read-out protection (ROP) User boot code (UBC) Alternate function remapping (AFR) Option byte no. Option bits 7 6 5 4 3 2 1 0 Factory default setting OPT0 ROP[7:0] 0x00 OPT1 UBC[7:0] 0x00 NUBC[7:0] 0xFF NOPT1 OPT2 NOPT2 AFR7 AFR6 AFR5 Reserve d AFR3 AFR2 AFR1 AFR0 0x00 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF WWDG _HW WWDG _HALT 0x00 OPT3 Reserved LSI _EN IWDG _HW 0x4806 NOPT3 Reserved NLSI _EN NIWDG _HW 0x4807 OPT4 Reserved EXT CLK CKAWU SEL PRS C1 PRS C0 0x00 NOPT4 Reserved NEXT CLK NCKAW USEL NPR SC1 NPR SC0 0xFF 0x4805 Watchdog option Clock option 0x4808 0x4809 0x480A 0x480B 0x480C 0x480D 0x480E 0x487E 0x487F 38/93 HSE clock startup Reserved Flash wait states Bootloader OPT5 NWWDG NWWDG _HW _HALT 0xFF HSECNT[7:0] 0x00 NHSECNT[7:0] 0xFF OPT6 Reserved 0x00 NOPT6 Reserved 0xFF NOPT5 OPT7 Reserved Wait state 0x00 NOPT7 Reserved Nwait state 0xFF OPTBL NOPTBL DS8633 Rev 6 BL[7:0] 0x00 NBL[7:0] 0xFF STM8S007C8 Option bytes Table 12. Option byte description Option byte no. Description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Pages 0 to 1 defined as UBC, memory write-protected 0x02: Pages 0 to 3 defined as UBC, memory write-protected 0x03: Pages 0 to 4 defined as UBC, memory write-protected ... 0xFE: Pages 0 to 255 defined as UBC, memory write-protected 0xFF: Reserved Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details. OPT2 AFR7Alternate function remapping option 7 0: Port D4 alternate function = TIM2_CH1 1: Port D4 alternate function = BEEP AFR6 Alternate function remapping option 6 0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL AFR5 Alternate function remapping option 5 0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N AFR4 Alternate function remapping option 4 Reserved AFR3 Alternate function remapping option 3 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = TIM1_BKIN AFR2 Alternate function remapping option 2 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = CLK_CCO Note: AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0: Port A3 alternate function = TIM2_CH3, port D2 alternate function TIM3_CH1 1: Port A3 alternate function = TIM3_CH1, port D2 alternate function TIM2_CH3 AFR0 Alternate function remapping option 0 0: Port D3 alternate function = TIM2_CH2 1: Port D3 alternate function = ADC_ETR DS8633 Rev 6 39/93 41 Option bytes STM8S007C8 Table 12. Option byte description (continued) Option byte no. Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source OPT3 IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN OPT4 CKAWUSEL: Auto wakeup unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 00: 24 MHz to 128 kHz prescaler 01: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler 40/93 OPT5 HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilization time. 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles OPT6 Reserved OPT7 WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory. 1 wait state is required if fCPU > 16 MHz. 0: No wait state 1: 1 wait state DS8633 Rev 6 STM8S007C8 Option bytes Table 12. Option byte description (continued) Option byte no. OPTBL Description BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details. DS8633 Rev 6 41/93 41 Electrical characteristics STM8S007C8 9 Electrical characteristics 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ). 9.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ). 9.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 Typical current consumption For typical current consumption measurements, VDD, VDDIO and VDDA are connected together in the configuration shown in Figure 5. Figure 5. Supply current measurement conditions 5 V or 3.3 V A VDD VDDA VDDIO VSS VSSA VSSIO 42/93 DS8633 Rev 6 STM8S007C8 9.1.5 Electrical characteristics Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Figure 6. Pin loading conditions STM8 pin 50 pF 9.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 7. Pin input voltage STM8 pin VIN 9.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics, Table 14: Current characteristics and Table 15: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device’s reliability. The device’s mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 13. Voltage characteristics Symbol Min Max -0.3 6.5 VSS - 0.3 6.5 VSS - 0.3 VDD + 0.3 |VDDx - VDD| Variations between different power pins - 50 |VSSx - VSS| Variations between all the different ground pins - 50 VDDx - VSS VIN VESD Ratings Supply voltage (including VDDA and VDDIO)(1) Input voltage on true open drain pins (PE1, PE2)(2) (2) Input voltage on any other pin Electrostatic discharge voltage DS8633 Rev 6 see Absolute maximum ratings (electrical sensitivity) on page 81 Unit V mV - 43/93 82 Electrical characteristics STM8S007C8 1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN> gmcrit 9.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI) Table 31. HSI oscillator characteristics Symbol fHSI Parameter Conditions Min Typ Max Unit - - 16 - MHz -1.0(1) - 1.0 Frequency Trimmed by the CLK_HSITRIMR register Accuracy of HSI oscillator for given VDD and TA ACCHSI conditions Accuracy of HSI oscillator VDD = 5 V, (factory calibrated) -40°C ≤ TA ≤ 85° C -5 - 5 tsu(HSI) HSI oscillator wakeup time including calibration - - - 1.0(1) µs IDD(HSI) HSI oscillator power consumption - - 170 250(2) µA 1. Guaranteed by design. 2. Guaranteed by characterization results. 58/93 % DS8633 Rev 6 STM8S007C8 Electrical characteristics Figure 14. Typical HSI frequency variation vs VDD at 3 temperatures -40ºC 25ºC 3% 85ºC % accuracy 2% 1% 0% -1% -2% -3% 2.5 3 3.5 4.5 4 VDD [V] 5 5.5 6 ai15067c Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 32. LSI oscillator characteristics Symbol Conditions Min Typ Max Unit Frequency - - 128 - kHz tsu(LSI) LSI oscillator wakeup time - - - 7(1) µs IDD(LSI) LSI oscillator power consumption - - 5 - µA fLSI Parameter 1. Guaranteed by design. Figure 15. Typical LSI frequency variation vs VDD @ 25 °C 3% % accuracy 2% 1% 0% -1% -2% -3% 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] ai15070V2 DS8633 Rev 6 59/93 82 Electrical characteristics 9.3.5 STM8S007C8 Memory characteristics RAM and hardware registers Table 33. RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode(1) Halt mode (or reset) VIT-max(2) V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design. 2. Refer to Table 17 on page 47 for the value of VIT-max. Flash program memory and data EEPROM General conditions: TA = -40 to 85 °C. Table 34. Flash program memory and data EEPROM Symbol VDD tprog terase Parameter Conditions Operating voltage (all modes, execution/write/erase) IDD Unit 2.95 - 5.5 V Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) - - 6.0 6.6 ms Fast programming time for 1 block (128 bytes) - - 3.0 3.3 ms Erase time for 1 block (128 bytes) - - 3.0 3.3 ms 100 - - Erase/write (program memory) TA = 85 °C Erase/write cycles(2) (data memory) Data retention (program memory) after 100 erase/write cycles at TA = 85 °C tRET Max fCPU ≤ 16 MHz cycles(2) NRW Min(1) Typ cycles 100 k - - 20 - - 20 - - TRET = 55° C Data retention (data memory) after 10 k erase/write cycles at TA = 85 °C Data retention (data memory) after 100 k erase/write cycles at TA = 85 °C TRET = 85° C 1.0 - - Supply current (Flash programming or erasing for 1 to 128 bytes) - - 2.0 - 1. Guaranteed by characterization results. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 60/93 DS8633 Rev 6 years mA STM8S007C8 9.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 35. I/O static characteristics Symbol Parameter Min Typ Max Unit -0.3 - 0.3 x VDD V 0.7 x VDD - VDD + 0.3 V V - 700 - mV 30 55 80 kΩ Fast I/Os Load = 50 pF - - 20(2) ns Standard and high sink I/Os Load = 50 pF - - 125(2) ns Input leakage current, analog and digital VSS ≤ VIN ≤ VDD - - ±1 µA Ilkg ana Analog input leakage current VSS ≤ VIN ≤ VDD - - ±250 (3) nA Ilkg(inj) Leakage current in adjacent I/O Injection current ±4 mA - - ±1(3) µA VIL Input low level voltage VIH Input high level voltage Vhys Hysteresis(1) Rpu Pull-up resistor tR, tF Rise and fall time (10% - 90%) Ilkg Conditions VDD = 5 V VDD = 5 V, VIN = VSS 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results. 2. Data guaranteed by design. 3. Guaranteed by characterization results. DS8633 Rev 6 61/93 82 Electrical characteristics STM8S007C8 Figure 16. Typical VIL and VIH vs VDD @ 3 temperatures -40ºC 6 25ºC 85ºC VIL/VIH [mA] 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] ai18798V2 Figure 17. Typical pull-up resistance vs VDD @ 3 temperatures -40ºC 25ºC 60 Pull-up resisitance [kohm] 85ºC 55 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] ai18799V2 62/93 DS8633 Rev 6 STM8S007C8 Electrical characteristics Figure 18. Typical pull-up current vs VDD @ 3 temperatures 140 Pull-up current [μA] 120 100 80 -40ºC 60 25ºC 40 85ºC 20 0 0 1 2 3 4 5 6 VDD [V] ai15068c 1. The pull-up is a pure resistor (slope goes through 0). Table 36. Output driving current (standard ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V - 2 Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V - 1(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 2.8 - IIO = 4 mA, VDD = 3.3 V 2.1(1) - Output high level with 4 pins sourced Unit V V 1. Guaranteed by characterization results. Table 37. Output driving current (true open drain ports) Symbol Parameter Conditions IIO = 10 mA, VDD = 5 V VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 3.3 V IIO = 20 mA, VDD = 5 V Max Unit 1 1.5(1) V 2(1) 1. Guaranteed by characterization results. DS8633 Rev 6 63/93 82 Electrical characteristics STM8S007C8 Table 38. Output driving current (high sink ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V - 0.8 Output low level with 4 pins sunk IIO = 10 mA, VDD = 3.3 V - 1.0(1) Output low level with 4 pins sunk IIO = 20 mA, VDD = 5 V - 1.5(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 4.0 - Output high level with 4 pins sourced IIO = 10 mA, VDD = 3.3 V 2.1(1) - (1) - IIO = 20 mA, VDD = 5 V Output high level with 4 pins sourced 3.3 Unit V 1. Guaranteed by characterization results. Typical output level curves Figure 20 to Figure 27 show typical output level curves measured with output on a single pin. Figure 19. Typ. VOL @ VDD = 5 V (standard ports) -40ºC 1.5 25ºC 85ºC 1.25 VOL [V] 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOL [mA] MS19400V2 64/93 DS8633 Rev 6 STM8S007C8 Electrical characteristics Figure 20. Typ. VOL @ VDD = 3.3 V (standard ports) -40ºC 1.5 25ºC 85ºC 1.25 0.75 0.5 0.25 0 0 1 2 3 4 5 6 7 IOL [mA] MS19401V2 Figure 21. Typ. VOL @ VDD = 5 V (true open drain ports) -40ºC 2 25ºC 1.75 85ºC 1.5 1.25 VOL [V] VOL [V] 1 1 0.75 0.5 0.25 0 0 5 10 15 20 25 IOL [mA] MS19402V2 DS8633 Rev 6 65/93 82 Electrical characteristics STM8S007C8 Figure 22. Typ. VOL @ VDD = 3.3 V (true open drain ports) -40ºC 2 25ºC 1.75 85ºC 1.5 VOL [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 IOL [mA] MS19403V2 Figure 23. Typ. VOL @ VDD = 5 V (high sink ports) -40ºC 1.5 25ºC 85ºC 1.25 VOL [V] 1 0.75 0.5 0.25 0 0 5 10 IOL [mA] 66/93 DS8633 Rev 6 15 20 25 MS19404V2 STM8S007C8 Electrical characteristics Figure 24. Typ. VOL @ VDD = 3.3 V (high sink ports) -40ºC 1.5 25ºC 85ºC 1.25 VOL [V] 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 IOL [mA] MS19405V2 Figure 25. Typ. VDD - VOH @ VDD = 5 V (standard ports) -40ºC 2 25ºC 1.75 85ºC 1.5 VOL [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 IOL [mA] DS8633 Rev 6 8 10 12 MS19406V2 67/93 82 Electrical characteristics STM8S007C8 Figure 26. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) -40ºC 2 25ºC 1.75 85ºC 1.5 VOL [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 12 10 IOL [mA] MS19407V2 Figure 27. Typ. VDD - VOH @ VDD = 5 V (high sink ports) -40ºC 2 25ºC 1.75 85ºC VDD - VOH [V] 1.5 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOH [mA] MS19408V3 68/93 DS8633 Rev 6 STM8S007C8 Electrical characteristics Figure 28. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) -40ºC 2 25ºC VDD - VOH [V] 1.75 85ºC 1.5 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOH [mA] MS19409V2 DS8633 Rev 6 69/93 82 Electrical characteristics 9.3.7 STM8S007C8 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 39. NRST pin characteristics Symbol VIL(NRST) VIH(NRST) VOL(NRST) Parameter NRST input high level voltage (1) NRST output low level voltage (1) Typ 1) Max - -0.3 V - 0.3 x VDD - 0.7 x VDD - VDD + 0.3 - - 0.5 - 30 55 80 kΩ - - - 75 ns - 500 - - ns tIFP(NRST) NRST input filtered pulse (3) NRST Input not filtered NRST output pulse - 15 - - µs IOL= 2 mA (2) NRST pull-up resistor tOP(NRST) Min NRST input low level voltage (1) RPU(NRST) tINFP(NRST) Conditions pulse (3) (1) Unit V 1. Guaranteed by characterization results. 2. The RPU pull-up equivalent resistor is based on a resistive transistor. 3. Data guaranteed by design. Figure 29. Typical NRST VIL and VIH vs VDD @ 3 temperatures -40ºC 6 25ºC 85ºC VIL/VIH [V] 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] MS19410V3 70/93 DS8633 Rev 6 STM8S007C8 Electrical characteristics Figure 30. Typical NRST pull-up resistance vs VDD @ 3 temperatures -40ºC 25ºC 60 NRESET pull-up resistance [kohm] 85ºC 55 50 45 40 35 30 2.5 3 3.5 4 4.5 VDD [V] 5 5.5 6 MS19411V3 Figure 31. Typical NRST pull-up current vs VDD @ 3 temperatures NREST pull-up current [μA] 140 120 100 80 -40ºC 60 25ºC 85ºC 40 20 0 0 1 2 3 VDD [V] 4 5 6 ai15069c The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 35. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. If the NRST signal is used to reset the external circuitry, care must be taken of the charge/discharge time of the external capacitor to fulfill the external device’s reset timing conditions. The minimum recommended capacity is 10 nF. DS8633 Rev 6 71/93 82 Electrical characteristics STM8S007C8 Figure 32. Recommended reset pin protection STM8 VDD RPU External reset circuit NRST Filter 0.1 μF (Optional) MSv36491V1 SPI serial peripheral interface 9.3.8 Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40. SPI characteristics Symbol Min Max Master mode 0 10 Slave mode 0 6 SPI clock rise and fall time Capacitive load: C = 30 pF - 25 tsu(NSS)(1) NSS setup time Slave mode 4 x tMASTER - th(NSS)(1) NSS hold time Slave mode 70 - SCK high and low time Master mode tSCK/2 - 15 tSCK/2 + 15 Master mode 5 - Slave mode 5 - Master mode 7 - Slave mode 10 - Data output access time Slave mode - 3 x tMASTER Data output disable time Slave mode 25 - tv(SO) (1) Data output valid time Slave mode (after enable edge) - 75 tv(MO)(1) Data output valid time Master mode (after enable edge) - 30 Slave mode (after enable edge) 31 - Master mode (after enable edge) 12 - fSCK 1/tc(SCK) tr(SCK) tf(SCK) (1) tw(SCKH) tw(SCKL)(1) Parameter SPI clock frequency tsu(MI) (1) tsu(SI)(1) Data input setup time th(MI) (1) th(SI)(1) Data input hold time ta(SO) (1)(2) tdis(SO) (1)(3) th(SO) (1) th(MO) (1) Data output hold time Conditions 1. Values based on design simulation and/or characterization results, and not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 72/93 DS8633 Rev 6 Unit MHz ns STM8S007C8 Electrical characteristics 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Figure 33. SPI timing diagram - slave mode and CPHA = 0 Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DS8633 Rev 6 73/93 82 Electrical characteristics STM8S007C8 Figure 35. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. 74/93 DS8633 Rev 6 STM8S007C8 9.3.9 Electrical characteristics I2C interface characteristics Table 41. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Min(2) Max(2) Min(2) Max(2) Unit tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0(3) - 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - µs STOP to START condition time (bus free) 4.7 - 1.3 - µs - 400 - 400 pF tw(STO:STA) Cb Capacitive load for each bus line 1. fMASTER, must be at least 8 MHz to achieve max fast I2C µs ns µs speed (400kHz) 2. Data based on standard I2C protocol requirement, not tested in production 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL DS8633 Rev 6 75/93 82 Electrical characteristics STM8S007C8 Figure 36. Typical application with I2C bus and timing diagram VDD VDD 4.7 kΩ 4.7 kΩ STM8 100 Ω SDA I²C bus SCL 100 Ω S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) th(STA) SCL tw(SCLH) tsu(SDA) th(SDA) tw(SCLL) tr(SCL) tf(SCL) S TOP tsu(STA:STO) tsu(STO) ai17490V2 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD 76/93 DS8633 Rev 6 STM8S007C8 9.3.10 Electrical characteristics 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 42. ADC characteristics Symbol Parameter Conditions Min Typ Max VDDA = 3 to 5.5 V 1 - 4 VDDA = 4.5 to 5.5 V 1 - 6 Unit fADC ADC clock frequency VDDA Analog supply - 3 - 5.5 V VREF+ Positive reference voltage - 2.75(1) - VDDA V VREF- Negative reference voltage - VSSA - 0.5(1) V VAIN Conversion voltage range(2) - VREF- - VREF+ V CADC Internal sample and hold capacitor - - 3 - pF fADC = 4 MHz - 0.75 - fADC = 6 MHz - 0.5 - - - 7 - tS(2) Sampling time tSTAB Wakeup time from standby tCONV Total conversion time (including sampling time, 10-bit resolution) MHz µs µs fADC = 4 MHz 3.5 µs fADC = 6 MHz 2.33 µs - 14 1/fADC 1. Guaranteed by design. 2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. DS8633 Rev 6 77/93 82 Electrical characteristics STM8S007C8 Table 43. ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V Symbol |ET| |EO| |EG| |ED| |EL| Parameter Total unadjusted error Offset error (1) (1) Gain error (1) Differential linearity Integral linearity error (1) error (1) Conditions Typ Max fADC = 2 MHz 1.0 2.5 fADC = 4 MHz 1.4 3 fADC = 6 MHz 1.6 3.5 fADC = 2 MHz 0.6 2.0 fADC = 4 MHz 1.1 2.5 fADC = 6 MHz 1.2 2.5 fADC = 2 MHz 0.2 2 fADC = 4 MHz 0.6 2.5 fADC = 6 MHz 0.8 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 0.7 1.5 fADC = 6 MHz 0.8 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 fADC = 6 MHz 0.6 1.5 Unit LSB 1. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy. Table 44. ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V Symbol Parameter |ET| Total unadjusted error(1) |EO| Offset error(1) |EG| Gain error(1) |ED| Differential linearity error(1) |EL| Integral linearity error(1) Conditions Typ Max fADC = 2 MHz 1.1 2.0 fADC = 4 MHz 1.6 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 1.3 2.0 fADC = 2 MHz 0.2 1.5 fADC = 4 MHz 0.5 2.0 fADC = 2 MHz 0.7 1.0 fADC = 4 MHz 0.7 1.0 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 Unit LSB 1. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy. 78/93 DS8633 Rev 6 STM8S007C8 Electrical characteristics Figure 37. ADC accuracy characteristics EG 1023 1022 1021 1LSB IDEAL V –V DDA SSA = ----------------------------------------1024 (2) ET 7 (3) (1) 6 5 EO 4 EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 1021102210231024 VDDA 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 38. Typical application with ADC VDD VAIN STM8 VT 0.6V RAIN AINx CAIN 10-bit A/D conversion VT 0.6V DS8633 Rev 6 IL ±1µA CADC 79/93 82 Electrical characteristics 9.3.11 STM8S007C8 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). • ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 45. EMS data Symbol 80/93 Parameter Conditions Level/class VFESD VDD = 5 V, TA = 25 °C, Voltage limits to be applied on any I/O pin to fMASTER = 16 MHz, induce a functional disturbance conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be VDD = 5 V, TA = 25 °C, applied through 100pF on VDD and VSS pins fMASTER = 16 MHz, to induce a functional disturbance conforming to IEC 61000-4-4 4A DS8633 Rev 6 STM8S007C8 Electrical characteristics Electromagnetic interference (EMI) Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading. Table 46. EMI data Conditions Symbol Parameter Monitored frequency band General conditions SEMI Peak level EMI level VDD = 5 V TA = 25 °C LQFP48 package conforming to IEC 61967-2 Max fHSE/fCPU(1) Unit 16 MHz/ 16 MHz/ 24 MHz/ 8 MHz 16 MHz 24 MHz 0.1MHz to 30 MHz 14 13 24 30 MHz to 130 MHz 19 23 17 130 MHz to 1 GHz -4 -4 7 1.5 2 2.5 - dBµV - 1. Data based on characterization results, not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (three positive then three negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 47. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum Unit value(1) VESD(HBM) Electrostatic discharge voltage (Human body model) TA = 25°C, conforming to JESD22-A114 A 2000 V VESD(CDM) Electrostatic discharge voltage (Charge device model) TA= 25°C, conforming to JESD22-C101 IV 1000 V 1. Guaranteed by characterization results. DS8633 Rev 6 81/93 82 Electrical characteristics STM8S007C8 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: • A supply overvoltage (applied to each power supply pin) • A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 48. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions Class(1) TA = 25 °C A TA = 85 °C A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 82/93 DS8633 Rev 6 STM8S007C8 10 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LQFP48 package information Figure 39. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline SEATING PLANE C c A1 A A2 0.25 mm GAUGE PLANE ccc C K D A1 L D1 L1 D3 36 25 37 24 48 PIN 1 IDENTIFICATION E E1 b E3 10.1 13 1 12 e 5B_ME_V2 1. Drawing is not to scale. DS8633 Rev 6 83/93 88 Package information STM8S007C8 Table 49. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 84/93 DS8633 Rev 6 STM8S007C8 Package information Figure 40. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint 0.50 1.20 36 9.70 0.30 25 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911d 1. Dimensions are expressed in millimeters. DS8633 Rev 6 85/93 88 Package information STM8S007C8 Device marking for LQFP48 The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 41. LQFP48 marking example (package top view) Product (1) identification STM8S007 C8T6 Date code Standard ST logo Y WW Revision code Pin 1 identifier R MS37489V1 1. 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 86/93 DS8633 Rev 6 STM8S007C8 10.2 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 16: General operating conditions. The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x ΘJA) Where: • TAmax is the maximum ambient temperature in ° C • ΘJA is the package junction-to-ambient thermal resistance in ° C/W • PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) • PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. • PI/Omax represents the maximum power dissipation on output pins, where: PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH), and taking account of the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Table 50. Thermal characteristics(1) Symbol ΘJA Parameter Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm Value Unit 57 °C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 10.2.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. DS8633 Rev 6 87/93 88 Package information 10.2.2 STM8S007C8 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 42: STM8S007C8 value line ordering information scheme(1)). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: • Maximum ambient temperature TAmax= 82 °C (measured according to JESD51-2) • IDDmax = 15 mA, VDD = 5.5 V • Maximum eight standard I/Os used at the same time in output at low level with IOL = 10 mA, VOL= 2 V • Maximum four high sink I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.5 V • Maximum two true open drain I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 2 V PINTmax = 15 mA x 5.5 V = 82.5 mW PIOmax = (10 mA x 2 V x 8 ) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW This gives: PINTmax = 82.5 mW and PIOmax 360 mW: PDmax = 82.5 mW + 360 mW Thus: PDmax = 443 mW Using the values obtained in Table 50: Thermal characteristics on page 87 TJmax is calculated as follows for LQFP64 10 x 10 mm = 46 °C/W: TJmax = 82 °C + (46 °C/W x 443 mW) = 82 °C + 20 °C = 102 °C This is within the range of the suffix 6 version parts (-40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6. 88/93 DS8633 Rev 6 STM8S007C8 11 Ordering information Ordering information Figure 42. STM8S007C8 value line ordering information scheme(1) Example: STM8 S 007 C 8 T 6 TR Product class STM8 microcontroller Family type S = standard Sub-family type(2) 00x = Value line sub-family 007 = high density Pin count C = 48 pins Program memory size 8 = 64 Kbyte Package type T = LQFP Temperature range 6 = -40 °C to 85 °C Packing No character = Tray or tube TR = Tape and reel 1. For a list of available options (such as memory size and package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 2. Refer to Table 1: STM8S007C8 value line features for detailed description. DS8633 Rev 6 89/93 89 STM8 development tools 12 STM8S007C8 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers. STice key features 90/93 • Occurrence and time profiling and code coverage (new features) • Advanced breakpoints with up to 4 levels of conditions • Data breakpoints • Program and data trace recording up to 128 KB records • Read/write on the fly of memory during emulation • In-circuit debugging/programming via SWIM protocol • 8-bit probe analyzer • 1 input and 2 output triggers • Power supply follower managing application voltages between 1.62 to 5.5 V • Modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements • Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. DS8633 Rev 6 STM8S007C8 12.2 STM8 development tools Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code is available. 12.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring • Seamless integration of C and ASM toolsets • Full-featured debugger • Project management • Syntax highlighting editor • Integrated programming interface • Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify the user STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface. Available toolchains include: 12.3 • Cosmic C compiler for STM8 – One free version that outputs up to 32 Kbytes of code is available. For more information, see www.cosmic-software.com. • Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of code. For more information, see www.raisonance.com. • STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows users to assemble and link the user application source code. Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the user STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. DS8633 Rev 6 91/93 91 Revision history 13 STM8S007C8 Revision history Table 51. Document revision history Date Revision 31-Oct-2011 1 Initial release. 2 Table 34: Flash program memory/data EEPROM memory: updated VDD condition; updated tRET parameters. Table 39: NRST pin characteristics: updated typ and max values of the NRST Pull-up resistor. 26-Apr-2012 3 Added the document status on the cover page (datasheet-production data). Modified temperature range and ACCHSI values in Table 31: HSI oscillator characteristics on page 58 (ACCHSI parameter). Modified Figure 35: SPI timing diagram - master mode(1) on page 74 (SCK output instead of SCK input). 10-Mar-2015 4 Updated the disclaimer. Added Figure 41: LQFP48 marking example (package top view). 5 Updated: – Figure 27: Typ. VDD - VOH @ VDD = 5 V (high sink ports), – Figure 29: Typical NRST VIL and VIH vs VDD @ 3 temperatures, – Figure 30: Typical NRST pull-up resistance vs VDD @ 3 temperatures. Added a note to Power-on reset threshold parameter in Table 17: Operating conditions at power-up/power-down. 6 Updated: – Figure 1: STM8S007C8 value line block diagram – Title of Section 4.4: Flash program memory and data EEPROM – Section 4.14: Communication interfaces – Table 5: STM8S007C8 pin description – Table 8: General hardware register map – Table 11: Option bytes – Table’s footnotes standardized on Section 9: Electrical characteristics – Section 9.2: Absolute maximum ratings – Table 31: HSI oscillator characteristics – Table 42: ADC characteristics – Section : Device marking for LQFP48 – Section 11: Ordering information 06-Jan-2012 20-Mar-2015 16-Oct-2018 92/93 Changes DS8633 Rev 6 STM8S007C8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS8633 Rev 6 93/93 93