STM8S105S6T6C

STM8S105C4/6 STM8S105K4/6 STM8S105S4/6 Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash, integrated EEPROM, 10-bit ADC, timers, UART, SPI, I²C Datasheet - production data Features Core  16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline  Extended instruction set LQFP48 (7x7 mm) LQFP44 (10x10 mm) LQFP32 (7x7 mm) Memories   Program memory: up to 32 Kbyte Flash; data retention 20 years at 55 °C after 10 kcycle  Data memory: up to 1 Kbyte true data EEPROM; endurance 300 kcycle UFQFPN32 (5x5 mm)  SDIP32 400ml  2x16-bit general purpose timer, with 2+3 CAPCOM channels (IC, OC or PWM)  RAM: up to 2 Kbyte  8-bit basic timer with 8-bit prescaler Clock, reset and supply management  Auto wake-up timer  2.95 to 5.5 V operating voltage  Window watchdog and independent watchdog timers  Flexible clock control, 4 master clock sources – Low power crystal resonator oscillator – External clock input – Internal, user-trimmable 16 MHz RC – Internal low-power 128 kHz RC  Clock security system with clock monitor  Power management: – Low-power modes (wait, active-halt, halt) – Switch-off peripheral clocks individually  Permanently active, low-consumption poweron and power-down reset  Nested interrupt controller with 32 interrupts  Up to 37 external interrupts on 6 vectors Timers  Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization This is information on a product in full production.  UART with clock output for synchronous operation, SmartCard, IrDA, LIN master mode  SPI interface up to 8 Mbit/s  I2C interface up to 400 kbit/s Analog to digital converter (ADC)  10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog I/Os Interrupt management September 2015 Communication interfaces  Up to 38 I/Os on a 48-pin package including  16 high sink outputs  Highly robust I/O design, immune against current injection Unique ID  96-bit unique key for each device DocID14771 Rev 15 1/121 www.st.com Contents STM8S105x4/6 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14 4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18 4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/121 UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14.3 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 6 4.14.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.2 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID14771 Rev 15 STM8S105x4/6 Contents 6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 42 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.5 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.6 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 66 10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69 10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.3.7 Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.8 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.9 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.3.10 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.2 LQFP44 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DocID14771 Rev 15 3/121 4 Contents STM8S105x4/6 11.5 12 13 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 107 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.1 14 SDIP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 STM8S105 FASTROM microcontroller option list . . . . . . . . . . . . . . . . . 109 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .113 14.1.1 14.2 14.3 15 4/121 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 14.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DocID14771 Rev 15 STM8S105x4/6 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STM8S105x4/6 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16 TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Legend/abbreviations for pin description tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM8S105x4/6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash, data EEPROM and RAM boundary address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Alternate function remapping bits [7:0] of OPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 57 Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 58 Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 59 Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 60 Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 61 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC accuracy with RAIN< 10 k, VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADC accuracy with RAIN< 10 k, VDDA = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DocID14771 Rev 15 5/121 6 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. 6/121 STM8S105x4/6 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package  mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package  mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package  mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat  package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SDIP32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DocID14771 Rev 15 STM8S105x4/6 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. STM8S105x4/6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LQFP44 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 UFQFPN32/LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SDIP32 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . 62 Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 63 Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typ IDD(WFI) vs. VDD HSE external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typ IDD(WFI) vs. fCPU HSE external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typ IDD(WFI) vs. VDD HSI RC osc., fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical HSI accuracy @ VDD = 5 V vs 5 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical HSI frequency variation vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical LSI frequency variation vs VDD@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VOL @ VDD = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typ. VDD - VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD - VOH @ VDD = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 79 Typical NRST pull-up current Ipu vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 79 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI timing diagram where slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SPI timing diagram where slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 91 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package  DocID14771 Rev 15 7/121 8 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. 8/121 STM8S105x4/6 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 94 LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package  recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP44 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package  recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat  package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 UFQFPN32 - 32-pin, 5 x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat  package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SDIP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SDIP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 STM8S105x4/6 access line ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . 108 DocID14771 Rev 15 STM8S105x4/6 1 Introduction Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.  For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).  For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051).  For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).  For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). DocID14771 Rev 15 9/121 21 Description 2 STM8S105x4/6 Description The STM8S105x4/6 access line 8-bit microcontrollers offer from 16 to 32 Kbyte Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as medium-density. All devices of the STM8S105x4/6 access line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity. The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog and brown-out reset. Device performance is ensured by a 16 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system. Short development cycles are guaranteed due to application scalability across common family product architecture with compatible pinout, memory map and modular peripherals. Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state-of-the-art technology for applications with 2.95 V to 5.5 V operating supply. Full documentation is offered as well as a wide choice of development tools. 10/121 DocID14771 Rev 15 STM8S105x4/6 Description Table 1. STM8S105x4/6 access line features Device STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4 Pin count 48 48 44 44 32 32 Maximum number of GPIOs 38 38 34 34 25 25 Ext. Interrupt pins 35 35 31 31 23 23 Timer CAPCOM channels 9 9 8 8 8 8 Timer complementar y outputs 3 3 3 3 3 3 A/D Converter channels 10 10 9 9 7 7 High sink I/Os 16 16 15 15 12 12 Medium density Flash Program memory (byte) 32K 16K 32K 16K 32K 16K Data EEPROM (bytes) 1024 1024 1024 1024 1024 1024 2K 2K 2K 2K 2K 2K RAM (bytes) Peripheral set Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C, UART, Window WDG, Independent WDG, ADC DocID14771 Rev 15 11/121 21 Block diagram 3 STM8S105x4/6 Block diagram Figure 1. STM8S105x4/6 block diagram 5HVHWEORFN ;7$/0+] &ORFNFRQWUROOHU 5HVHW 5HVHW 5&LQW0+] %25 325 'HWHFWRU 5&LQWN+] &ORFNWRSHULSKHUDOVDQGFRUH :LQGRZ :'* 670 FRUH ,QGHSHQGHQW:'* 6LQJOHZLUH GHEXJLQWHUI 8SWR.E\WH 3URJUDP )ODVK 'HEXJ6:,0 .ELWV ,& 0ELWV 63, 0DVWHUVODYH DXWRV\QFKUR /,1PDVWHU 63,HPXO $GGUHVVDQGGDWDEXV .E\WH GDWD((3520 8SWR.E\WH 5$0 %RRW520 ELWDGYDQFHG FRQWUROWLPHU70 8SWR&$3&20 FKDQQHOV FRPSOHPHQWDU\ RXWSXWV ELWJHQHUDOSXUSRVH WLPHU7,07,0 8SWR&$3&20 FKDQQHOV 8$57 8SWR FKDQQHOV $'& N+] EHHS %HHSHU ELWEDVLFWLPHU 7,0 $:8WLPHU 06Y9 12/121 DocID14771 Rev 15 STM8S105x4/6 4 Product overview Product overview The following section provides an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers  Harvard architecture,  3-stage pipeline,  32-bit wide program memory bus - single cycle fetching for most instructions,  X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations,  8-bit accumulator,  24-bit program counter - 16-Mbyte linear memory space,  16-bit stack pointer - access to a 64 K-level stack,  8-bit condition code register - 7 condition flags for the result of the last instruction. Addressing  20 addressing modes,  Indexed indirect addressing mode for look-up tables located anywhere in the address space,  Stack pointer relative addressing mode for local variables and parameter passing. Instruction set  80 instructions with 2-byte average instruction size,  Standard data movement and logic/arithmetic functions,  8-bit by 8-bit multiplication,  16-bit by 8-bit and 16-bit by 16-bit division,  Bit manipulation,  Data transfer between stack and accumulator (push/pop) with direct stack access,  Data transfer using the X and Y registers or direct memory-to-memory transfers. DocID14771 Rev 15 13/121 21 Product overview 4.2 STM8S105x4/6 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. 4.3 4.4  R/W to RAM and peripheral registers in real-time  R/W access to all resources by stalling the CPU  Breakpoints on all program-memory instructions (software breakpoints)  Two advanced breakpoints, 23 predefined configurations Interrupt controller  Nested interrupts with three software priority levels,  32 interrupt vectors with hardware priority,  Up to 37 external interrupts on 6 vectors including TLI,  Trap and reset interrupts Flash program and data EEPROM memory  Up to 32 Kbyte of Flash program single voltage Flash memory,  Up to 1 Kbyte true data EEPROM,  Read while write: writing in data memory possible while executing code in program memory,  User option byte area. Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below. 14/121 DocID14771 Rev 15 STM8S105x4/6 Product overview The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 byte) by programming the UBC option byte in ICP mode. This divides the program memory into two areas:  Main program memory: up to 32 Kbyte minus UBC  User-specific boot code (UBC): Configurable up to 32 Kbyte The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2. Flash memory organization 'DWDPHPRU\DUHD.E\WH 'DWD ((3520 PHPRU\ 2SWLRQE\WHV 8%&DUHD 5HPDLQVZULWHSURWHFWHGGXULQJ,$3 0HGLXPGHQVLW\ )ODVKSURJUDP PHPRU\ XSWR.E\WH 3URJUDPPDEOHDUHD IURP.E\WH ILUVWSDJHVXSWR .E\WHSDJHVWHS 3URJUDPPHPRU\DUHD :ULWHDFFHVVSRVVLEOHIRU,$3 06Y9 Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. DocID14771 Rev 15 15/121 21 Product overview 4.5 STM8S105x4/6 Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features  Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.  Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.  Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.  Master clock sources: four different clock sources can be used to drive the master clock: – 1-16 MHz high-speed external crystal (HSE) – Up to 16 MHz high-speed user-external clock (HSE user-ext) – 16 MHz high-speed internal RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI)  Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.  Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.  Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock PCKEN17 TIM1 PCKEN13 UART2 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM3 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved 16/121 DocID14771 Rev 15 STM8S105x4/6 4.6 Product overview Power management For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. 4.7  Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.  Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.  Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.  Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. 2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register. Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure DocID14771 Rev 15 17/121 21 Product overview STM8S105x4/6 The IWDG time base spans from 60 µs to 1 s. 4.8 4.9 Auto wakeup counter  Used for auto wakeup from active halt mode,  Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock,  LSI clock can be internally connected to TIM1 input capture channel 1 for calibration. Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. The beeper output port is only available through the alternate function remap option bit AFR7. 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver 4.11 18/121  16-bit up, down and up/down autoreload counter with 16-bit prescaler  Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output  Synchronization module to control the timer with external signals  Break input to force the timer outputs into a defined state  Three complementary outputs with adjustable dead time  Encoder mode  Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break TIM2, TIM3 - 16-bit general purpose timers  16-bit auto reload (AR) up-counter  15-bit prescaler adjustable to fixed power of 2 ratios 1…32768  Timers with 3 or 2 individually configurable capture/compare channels  PWM mode  Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update DocID14771 Rev 15 STM8S105x4/6 4.12 Product overview TIM4 - 8-bit basic timer  8-bit auto reload, adjustable prescaler ratio to any power of 2 from 1 to 128  Clock source: CPU clock  Interrupt source: 1 x overflow/update Table 3. TIM timer features Counter size (bits) Prescaler Counting mode TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No Timer 4.13 CAPCOM Complementary channels outputs Ext. trigger Timer synchronization/ chaining No Analog-to-digital converter (ADC1) The STM8S105x4/6 products contain a 10-bit successive approximation A/D converter (ADC1) with up to 10 multiplexed input channels and the following main features: Note:  Input voltage range: 0 to VDD  Conversion time: 14 clock cycles  Single and continuous and buffered continuous conversion modes  Buffer size (n x 10 bits) where n = number of input channels  Scan mode for single and continuous conversion of a sequence of channels  Analog watchdog capability with programmable upper and lower thresholds  Analog watchdog interrupt  External trigger input  Trigger from TIM1 TRGO  End of conversion (EOC) interrupt Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers. DocID14771 Rev 15 19/121 21 Product overview 4.14 STM8S105x4/6 Communication interfaces The following communication interfaces are implemented: 4.14.1  UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.1 master capability  SPI: Full and half-duplex, 8 Mbit/s  I²C: Up to 400 kbit/s UART2 Main features  1 Mbit/s full duplex SCI  SPI emulation  High precision baud rate generator  Smartcard emulation  IrDA SIR encoder decoder  LIN master mode  LIN slave mode Asynchronous communication (UART mode)  Full duplex communication - NRZ standard format (mark/space)  Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency  Separate enable bits for transmitter and receiver  Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt)  Transmission error detection with interrupt generation  Parity control Synchronous communication  Full duplex synchronous transfers  SPI master operation  8-bit data communication  Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16) LIN master mode 20/121  Emission: Generates 13-bit synch. break frame  Reception: Detects 11-bit break frame DocID14771 Rev 15 STM8S105x4/6 Product overview LIN slave mode 4.14.2 4.14.3  Autonomous header handling - one single interrupt per valid message header  Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15%  Synch delimiter checking  11-bit LIN synch break detection - break detection always active  Parity check on the LIN identifier field  LIN error management  Hot plugging support SPI  Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave  Full duplex synchronous transfers  Simplex synchronous transfers on two lines with a possible bidirectional data line  Master or slave operation - selectable by hardware or software  CRC calculation  1 byte Tx and Rx buffer  Slave/master selection input pin I2C   I²C master features: – Clock generation – Start and stop generation I²C slave features: – Programmable I2C address detection – Stop bit detection  Generation and detection of 7-bit/10-bit addressing and general call  Supports different communication speeds: – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz) DocID14771 Rev 15 21/121 21 Pinout and pin description 5 STM8S105x4/6 Pinout and pin description Table 4. Legend/abbreviations for pin description tables Type Level Output speed Port and control configuration Reset state 22/121 I= Input, O = Output, S = Power supply Input CM = CMOS Output HS = High sink O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Input float = floating, wpu = weak pull-up Output T = True open drain, OD = Open drain, PP = Push pull Bold X (pin state after internal reset release). Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. DocID14771 Rev 15 STM8S105x4/6 Pinout and pin description                                     3* 3* 3&+663,B0,62 3&+663,B026, 9'',2B 966,2B 3&+663,B6&. 3&+67,0B&+ 3&+67,0B&+ 3&+67,0B&+ 3&+67,0B&+8$57B&. 3(63,B166 $,13( $,13( >7,0B(75@$,13% >7,0B&+1@$,13% >7,0B&+1@$,13% >7,0B&+1@$,13%             9''$ 966$ $,13% $,13% >,&B6'$@$,13% >,&B6&/@$,13% 1567 26&,13$ 26&2873$ 966,2B 966 9&$3 9'' 9'',2B >7,0B&+@7,0B&+3$ +63$ +63$ +63$ 3(+6&/.B&&2 3(7,&B6&/ 3(7,&B6'$$ 3(7,0B%.,1 3'7/,>7,0B&+@ 3'8$57B5; 3'8$57B7; 3'+67,0B&+>%((3@ 3'+67,0B&+>$'&B(75@ 3'+67,0B&+>7,0B&+@ 3'+66:,0 3'+67,0B&+>7,0B%.,1@>&/.B&&2@ Figure 3. LQFP48 pinout 069 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). DocID14771 Rev 15 23/121 30 Pinout and pin description STM8S105x4/6 3(+6&/.B&&2 3(7,&B6&/ 3(7,&B6'$ 3'+66:,0 3'+67,0B&+>7,0B%.,1@>&/.B&&2@ 3'7/,>7,0B&+@ 3'8$57B5; 3'8$57B7; 3'+67,0B&+>%((3@ 3'+67,0B&+>$'&B(75@ 3'+67,0B&+>7,0B&+@ Figure 4. LQFP44 pinout 1567 26&,13$ 26&2873$ 966,2B                  3* 3* 3&+663,B0,62   3&+663,B026, 966 9&$3 9'' 9'',2B         +63$ +63$ +63$     9'',2B 966,2B 3&+663,B6&. 3&+67,0B&+ 3&+67,0B&+ 3&+67,0B&+8$57B&. 3(63,B166 $,13( >7,0B&+1@$,13% >7,0B&+1@$,13% >7,0B&+1@$,13% >,&B6&/@$,13% >7,0B(75@$,13% >,&B6'$@$,13% $,13% $,13% 966$             9''$  069 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 24/121 DocID14771 Rev 15 STM8S105x4/6 Pinout and pin description 3'7/,>7,0B&+@ 3'8$57B5; 3'8$57B7; 3'+67,0B&+>%((3@ 3'+67,0B&+>$'&B(75@ 3'+67,0B&+>7,0B&+@ 3'+66:,0 3'+67,0B&+>7,0B%.,1@>&/.B&&2@ Figure 5. UFQFPN32/LQFP32 pinout         1567 26&,13$ 26&2873$ 966 9&$3 9'' 9'',2 $,13)                 >,&B6&/@$,13% >7,0B(75@$,13% >7,0B&+1@$,13% >7,0B&+1@$,13% >7,0B&+1@$,13% 9''$ 966$ >,&B6'$@$,13%         3&+663,B0,62 3&+663,B026, 3&+663,B6&. 3&+67,0B&+ 3&+67,0B&+ 3&+67,0B&+ 3&+67,0B&+8$57B&. 3(63,B166 069 1. (HS) high sink capability. 2. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). DocID14771 Rev 15 25/121 30 Pinout and pin description STM8S105x4/6 Figure 6. SDIP32 pinout $'&B(757,0B&++63' >%((3@7,0B&++63' 8$57B7;3' 8$57B5;3' >7,0B&+@7/,3' 1567 26&,13$ 26&2873$ 966 9&$3 9'' 9'',2 $,13) 9''$ 966$ >,&B6'$@$,13%                                 3'+67,0B&+>7,0B&+@ 3'+66:,0 3'+67,0B&+>7,0B%.,1@>&/.B&&2@ 3&+663,B0,62 3&+663,B026, 3&+663,B6&. 3&+67,0B&+ 3&+67,0B&+ 3&+67,0B&+ 3&+67,0B&+8$57B&. 3(63,B166 3%$,1>7,0B&+1@ 3%$,1>7,0B&+1@ 3%$,1>7,0B&+1@ 3%$,1>7,0B(75@ 3%$,1>,&B6&/@ 069 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 5. STM8S105x4/6 pin description wpu Ext. interrupt High sink 1 1 6 NRST I/O - X - - 2 2 2 7 PA1/ OSC IN I/O X X - - 3 3 3 8 PA2/ OSC OUT I/O X X - 4 4 - - VSSIO_1 S - - 5 5 4 9 VSS S - 6 6 5 10 VCAP S - 26/121 PP Floating 1 Type Alternate Main function Default function after alternate (after remap function reset) [option bit] OD SDIP32 Pin name Speed LQFP32/UFQFPN32 Output LQFP44 Input LQFP48 Pin number - - O1 X X Port A1 Resonato r/ crystal in - O1 X X Port A1 Resonato r/ crystal in - - - - - I/O ground - - - - - - - Digital ground - - - - - - - 1.8 V regulator capacitor - DocID14771 Rev 15 Reset - STM8S105x4/6 Pinout and pin description Table 5. STM8S105x4/6 pin description (continued) Output LQFP32/UFQFPN32 SDIP32 Pin name Floating wpu Ext. interrupt High sink Speed OD PP Alternate Main function Default function after alternate (after remap function reset) [option bit] LQFP44 Input LQFP48 Pin number 7 7 6 11 VDD S - - - - - - - Digital power supply - 8 8 7 12 VDDIO_1 S - - - - - - - I/O power supply - 9 - - - PA3/ TIM2_CH3 [TIM3_CH1] I/O X X X - O1 X X Port A3 Timer 2 channel 3 TIM3_ CH1 [AFR1] 10 9 - - PA4 I/O X X X HS O3 X X Port A4 - - 11 10 - - PA5 I/O X X X HS O3 X X Port A5 - - 12 11 - - PA6 I/O X X X HS O3 X X Port A6 - - - - 8 13 PF4/ AIN12(1) I/O X X - - O1 X X Port F4 Analog input 12(2) - 13 12 9 14 VDDA S - - - - - - - Analog power supply - 14 13 10 15 VSSA S - - - - - - - Analog ground - 15 14 - - PB7/ AIN7 I/O X X X - O1 X X Port B7 Analog input 7 - 16 15 - - PB6/ AIN6 I/O X X X - O1 X X Port B6 Analog input 6 - 17 16 11 16 PB5/ AIN5 [I2C_ SDA] I/O X X X - O1 X X Port B5 Analog input 5 I 2C_SDA [AFR6] 18 17 12 17 PB4/ AIN4 [I2C_SCL] I/O X X X - O1 X X Port B4 Analog input 4 I2C_SCL [AFR6] 19 18 13 18 PB3/ AIN3 [TIM1_ETR] I/O X X X - O1 X X Port B3 Analog input 3 TIM1_ET R [AFR5] 20 19 14 19 PB2/ AIN2 [TIM1_CH3N] I/O X X X - O1 X X Port B2 Analog input 2 TIM1_CH 3N [AFR5] 21 20 15 20 PB1/ AIN1 [TIM1_CH2N] I/O X X X - O1 X X Port B1 Analog input 1 TIM1_CH 2N [AFR5] 22 21 16 21 PB0/ AIN0 [TIM1_CH1N] I/O X X X - O1 X X Port B0 Analog input 0 TIM1_CH 1N [AFR5] 23 - - - PE7/ AIN8 I/O X X X - O1 X X Port E7 Analog input 8 - Type DocID14771 Rev 15 27/121 30 Pinout and pin description STM8S105x4/6 Table 5. STM8S105x4/6 pin description (continued) 25 23 17 PP PE6/ AIN9 OD - Speed - High sink 22 Ext. interrupt SDIP32 24 Type wpu LQFP32/UFQFPN32 Pin name Output Floating LQFP44 Input LQFP48 Pin number I/O X X X - O1 X X I/O Alternate Main function Default function after alternate (after remap function reset) [option bit] Port E6 Analog input 9(3) - Port E5 SPI master/ slave select - - 22 PE5/ SPI_NSS I/O X X X HS O3 X X Port C1 Timer 1 channel 1/ UART2 synchron ous clock X X X - O1 X X 26 24 18 23 PC1/ TIM1_CH1/ UART2_CK 27 25 19 24 PC2/ TIM1_CH2 I/O X X X HS O3 X X Port C2 Timer 1channel 2 - 28 26 20 25 PC3/ TIM1_CH3 I/O X X X HS O3 X X Port C3 Timer 1 channel 3 - 29 - 21 26 PC4/ TIM1_CH4 I/O X X X HS O3 X X Port C4 Timer 1 channel 4 - 30 27 22 27 PC5/ SPI_SCK I/O X X HS O3 X X Port C5 SPI clock - 31 28 - - VSSIO_2 S - - - - - - - I/O ground - 32 29 - - VDDIO_2 S - - - - - - - I/O power supply - I/O X X X HS O3 X X Port C6 SPI master out/slave in PC7/ SPI_ MISO I/O X X X HS O3 X X Port C7 SPI master in/ slave out - - PG0 I/O X X - - O1 X X Port G0 - - - - PG1 I/O X X - - O1 X X Port G1 - - - - - PE3/ TIM1_BKIN I/O X X X - O1 X X Port E3 Timer 1 break input - 38 34 - - PE2/ I 2C_ SDA I/O X - X - O1 (4) - Port E2 I 2C data - 39 35 - - PE1/ I2C_ SCL I/O X - X - O1 (4) - Port E1 I 2C clock - 33 30 23 28 PC6/ SPI_MOSI 34 31 24 29 35 32 - 36 33 37 28/121 DocID14771 Rev 15 T T - STM8S105x4/6 Pinout and pin description Table 5. STM8S105x4/6 pin description (continued) I/O X X X I/O X X X PP PE0/ CLK_CCO OD - Speed - High sink 36 Ext. interrupt SDIP32 40 Type wpu LQFP32/UFQFPN32 Pin name Output Floating LQFP44 Input LQFP48 Pin number HS O3 X X Alternate Main function Default function after alternate (after remap function reset) [option bit] Port E0 Configura ble clock output X Port D0 TIM1_BK IN Timer 3 [AFR3]/ channel 2 CLK_CC O [AFR2] X Port D1 SWIM data interface - 41 37 25 30 PD0/ TIM3_CH2 [TIM1_BKIN] [CLK_CCO] 42 38 26 31 PD1/ SWIM(5) I/O X X X 43 39 27 32 PD2/ TIM3_CH1 [TIM2_CH3] I/O X X X HS O3 X X Port D2 Timer 3 - TIM2_CH channel 1 3 [AFR1] 44 40 28 1 PD3/ TIM2_CH2 [ADC_ETR] I/O X X X HS O3 X X Port D3 Timer 2 - ADC_ET channel 2 R [AFR0] 45 41 29 2 PD4/ TIM2_CH1 [BEEP] I/O X X X HS O3 X X Port D4 Timer 2 channel 1 BEEP output [AFR7] 46 42 30 3 PD5/ UART2_TX I/O X X X - O1 X X Port D5 UART2 data transmit - 47 43 31 4 PD6/ UART2_RX I/O X X X - O1 X X Port D6 UART2 data receive - 48 44 32 5 PD7/ TLI [TIM1_CH4 I/O X X X - O1 X X Port D7 HS O3 X X HS O4 - Top level TIM1_CH interrupt 4 [AFR4] 1. A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release. 2. AIN12 is not selectable in ADC scan mode or with analog watchdog. 3. In 44-pin package, AIN9 cannot be used by ADC scan mode. 4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented). 5. The PD1 pin is in input pull-up during the reset phase and after internal reset release. DocID14771 Rev 15 29/121 30 Pinout and pin description 5.1 STM8S105x4/6 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). 30/121 DocID14771 Rev 15 STM8S105x4/6 Memory and register map 6 Memory and register map 6.1 Memory map Figure 7. Memory map [ 5$0 .E\WH [)) E\WHVWDFN 5HVHUYHG [ [)) [ [)) [ .E\WHGDWD((3520 5HVHUYHG 2SWLRQE\WHV [) [ 5HVHUYHG [))) [ *3,2DQGSHULSKUHJ [)) [ 5HVHUYHG [))) [ [)) [ [()) [) [))) [ .E\WHERRW520 5HVHUYHG &386:,0GHEXJ,7& UHJLVWHUV LQWHUUXSWYHFWRUV [) [)))) [ )ODVKSURJUDPPHPRU\ WR.E\WH 5HVHUYHG [))) 06Y9 The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. DocID14771 Rev 15 31/121 50 Memory and register map STM8S105x4/6 Table 6. Flash, data EEPROM and RAM boundary address Memory area Flash program memory Size (byte) Start address End address 32 K 0x00 8000 0x00 FFFF 16 K 0x00 8000 0x00 BFFF 2K 0x00 0000 0x00 07FF 1024 0x00 4000 0x00 43FF RAM Data EEPROM 6.2 Register map 6.2.1 I/O port hardware register map Table 7. I/O port hardware register map Address Block Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX(1) PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX(1) PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0xXX(1) PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX(1) PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5002 0x00 5007 0x00 500C 0x00 5011 32/121 Port A Port B Port C Port D DocID14771 Rev 15 STM8S105x4/6 Memory and register map Table 7. I/O port hardware register map (continued) Address Block Register label Register name Reset status 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xXX(1) PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xXX(1) PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX(1) PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 PH_ODR Port H data output latch register 0x00 0x00 5024 PH_IDR Port H input pin value register 0xXX(1) PH_DDR Port H data direction register 0x00 0x00 5026 PH_CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 PI_ODR Port I data output latch register 0x00 0x00 5029 PI_IDR Port I input pin value register 0xXX(1) PI_DDR Port I data direction register 0x00 0x00 502B PI_CR1 Port I control register 1 0x00 0x00 502C PI_CR2 Port I control register 2 0x00 0x00 5016 0x00 501B 0x00 5020 0x00 5025 0x00 502A Port E Port F Port G Port H Port I 1. Depends on the external circuitry. DocID14771 Rev 15 33/121 50 Memory and register map 6.2.2 STM8S105x4/6 General hardware register map Table 8. General hardware register map Address 0x00 5050 to 0x00 5059 Block Register label Register name Reset status Reserved area (10 byte) 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF 0x00 505F FLASH _IAPSR Flash in-application programming status register 0x00 Flash program memory unprotection register 0x00 Data EEPROM unprotection register 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reset status register 0xXX(1) CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 0x00 505D Flash 0x00 5060 to 0x00 5061 Reserved area (2 byte) 0x00 5062 Flash 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash 0x00 5065 to 0x00 509F Reserved area (59 byte) 0x00 50A0 FLASH _PUKR FLASH _DUKR ITC 0x00 50A1 0x00 50A2 to 0x00 50B2 Reserved area (17 byte) 0x00 50B3 RST 0x00 50B4 to 0x00 50BF Reserved area (12 byte) 0x00 50C0 0x00 50C1 0x00 50C2 34/121 CLK RST_SR Reserved area (1 byte) DocID14771 Rev 15 STM8S105x4/6 Memory and register map Table 8. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 50C3 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming 0x00 register 0x00 50CD CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F IWDG_KR IWDG key register 0xXX(2) IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF AWU_CSR1 AWU control/status register 1 0x00 AWU_APR AWU asynchronous prescaler 0x3F buffer register AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F 0x00 50C8 0x00 50CE to 0x00 50D0 0x00 50D1 0x00 50D2 0x00 50D3 to 00 50DF CLK Reserved area (3 byte) WWDG Reserved area (13 byte) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 0x00 50E3 to 0x00 50EF Reserved area (13 byte) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 BEEP 0x00 50F4 to 0x00 50FF Reserved area (12 byte) 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 SPI_SR SPI status register 0x02 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF 0x00 5203 0x00 5204 SPI DocID14771 Rev 15 35/121 50 Memory and register map STM8S105x4/6 Table 8. General hardware register map (continued) Address 0x00 5208 to 0x00 520F Block Register label Register name Reset status Reserved area (8 byte) 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C Own address register low 0x00 0x00 5214 I2C_OARH I2C Own address register high 0x00 0x00 5215 Reserved 0x00 5216 I2C_DR I2C data register 0x00 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x0X 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C Clock control register low 0x00 0x00 521C I2C_CCRH I2C Clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 521E I2C_PECR I2C packet error checking register 0x00 0x00 5217 I2C 0x00 521F to 0x00 522F Reserved area (17 byte) 0x00 5230 to 0x00 523F Reserved area (6 byte) 0x00 5240 UART2_SR UART2 status register 0xC0 0x00 5241 UART2_DR UART2 data register 0xXX 0x00 5242 UART2_BRR1 UART2 baud rate register 1 0x00 0x00 5243 UART2_BRR2 UART2 baud rate register 2 0x00 0x00 5244 UART2_CR1 UART2 control register 1 0x00 UART2_CR2 UART2 control register 2 0x00 UART2_CR3 UART2 control register 3 0x00 0x00 5247 UART2_CR4 UART2 control register 4 0x00 0x00 5248 UART2_CR5 UART2 control register 5 0x00 0x00 5249 UART2_CR6 UART2 control register 6 0x00 0x00 524A UART2_GTR UART2 guard time register 0x00 0x00 524B UART2_PSCR UART2 prescaler register 0x00 0x00 5245 0x00 5246 0x00 524C to 0x00 524F 36/121 UART2 Reserved area (4 byte) DocID14771 Rev 15 STM8S105x4/6 Memory and register map Table 8. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/compare enable 0x00 register 1 0x00 525D TIM1_CCER2 TIM1 capture/compare enable 0x00 register 2 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 TIM1 DocID14771 Rev 15 37/121 50 Memory and register map STM8S105x4/6 Table 8. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 0x00 526C 0x00 5270 to 0x00 52FF 38/121 TIM1 Reserved area (147 byte) DocID14771 Rev 15 STM8S105x4/6 Memory and register map Table 8. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 5300 TIM2_CR1 TIM2 control register 1 0x00 5301 TIM2_IER TIM2 Interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00 0x00 5308 TIM2_CCER1 TIM2 capture/compare enable 0x00 register 1 0x00 5309 TIM2_CCER2 TIM2 capture/compare enable 0x00 register 2 0x00 530A TIM2_CNTRH TIM2 counter high 0x00 TIM2_CNTRL TIM2 counter low 0x00 0x00 530C TIM2_PSCR IM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00 0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00 0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00 0x00 530B 0x00 5315 to 0x00 531F TIM2 0x00 Reserved area (11 byte) DocID14771 Rev 15 39/121 50 Memory and register map STM8S105x4/6 Table 8. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 5320 TIM3_CR1 TIM3 control register 1 0x00 5321 TIM3_IER TIM3 Interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 0x00 5327 TIM3_CCER1 TIM3 capture/compare enable 0x00 register 1 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/compare reg. 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 0x00 0x00 5328 0x00 5331 to 0x00 533F TIM3 0x00 Reserved area (15 byte) 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF ADC data buffer registers 0x00 0x00 5343 TIM4 0x00 5347 to 0x00 53DF Reserved area (153 byte) 0x00 53E0 to 0x00 53F3 ADC1 0x00 53F4 to 0x00 53FF Reserved area (12 byte) 40/121 ADC_DBxR DocID14771 Rev 15 STM8S105x4/6 Memory and register map Table 8. General hardware register map (continued) Address Block Register label Register name Reset status 0x00 5400 ADC_CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 0x00 5408 ADC_HTRH ADC high threshold register high 0x03 ADC_HTRL ADC high threshold register low 0xFF 0x00 540A ADC_LTRH ADC low threshold register high 0x00 0x00 540B ADC_LTRL ADC low threshold register low 0x00 0x00 540C ADC_AWSRH ADC analog watchdog status register high 0x00 0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00 0x00 540E ADC _AWCRH ADC analog watchdog control 0x00 register high 0x00 540F ADC_AWCRL ADC analog watchdog control 0x00 register low 0x00 5409 0x00 5410 to 0x00 57FF ADC1 cont’d Reserved area (1008 byte) 1. Depends on the previous reset source. 2. Write-only register. DocID14771 Rev 15 41/121 50 Memory and register map 6.2.3 STM8S105x4/6 CPU/SWIM/debug module/interrupt controller registers Table 9. CPU/SWIM/debug module/interrupt controller registers Address Block Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF SWIM control status register 0x00 0x00 7F04 0x00 7F05 CPU (1) 0x00 7F0B to 0x00 7F5F Reserved area (85 byte) 0x00 7F60 CPU ITC 0x00 7F78 to 0x00 7F79 Reserved area (2 byte) 0x00 7F80 SWIM 0x00 7F81 to 0x00 7F8F Reserved area (15 byte) 42/121 SWIM_CSR DocID14771 Rev 15 STM8S105x4/6 Memory and register map Table 9. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register label Register name Reset status 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF 0x00 7F95 0x00 7F9B to 0x00 7F9F DM Reserved area (5 byte) 1. Accessible by debug module only. DocID14771 Rev 15 43/121 50 Interrupt vector mapping 7 STM8S105x4/6 Interrupt vector mapping Table 10. Interrupt mapping IRQ no. Source block Wakeup from halt mode Description Wakeup from active-halt mode Vector address - RESET Reset Yes Yes 0x00 8000 - TRAP Software interrupt - - 0x00 8004 0 TLI External top level interrupt - - 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller - - 0x00 8010 3 EXTI0 Port A external interrupts Yes(1) Yes(1) 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 Reserved - - - 0x00 8028 9 Reserved - - - 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIM1 TIM1 update/ overflow/ underflow/ trigger/ break - - 0x00 8034 12 TIM1 TIM1 capture/ compare - - 0x00 8038 13 TIM2 TIM2 update/ overflow - - 0x00 803C 14 TIM2 TIM2 capture/ compare - - 0x00 8040 15 TIM3 TIM3 update/ overflow - - 0x00 8044 16 TIM3 TIM3 capture/ compare - - 0x00 8048 17 Reserved - - - 0x00 804C 18 Reserved - - - 0x00 8050 19 I2C I2C interrupt Yes Yes 0x00 8054 44/121 DocID14771 Rev 15 STM8S105x4/6 Interrupt vector mapping Table 10. Interrupt mapping (continued) IRQ no. Source block Wakeup from halt mode Description Wakeup from active-halt mode Vector address 20 UART2 Tx complete - - 0x00 8058 21 UART2 Receive register DATA FULL - - 0x00 805C 22 ADC1 ADC1 end of conversion/ analog watchdog interrupt - 0x00 8060 23 TIM4 TIM4 update/ overflow - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 0x00 806C to 0x00 807C Reserved 1. Except PA1. DocID14771 Rev 15 45/121 50 Option byte 8 STM8S105x4/6 Option byte Option byte contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option byte can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below. Option byte can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 11. Option byte Addr. Option name Option byte no. Option bits 7 6 5 4 3 2 1 0 Factory default setting Read-out 0x4800 protection OPT0 ROP [7:0] 0x00 (ROP) 0x4801 User boot OPT1 UBC [7:0] 0x00 0x4802 code (UBC) NOPT1 NUBC [7:0] 0xFF 0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00 NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF IWDG WWDG WWDG _HW _HW _HALT function 0x4804 remapping (AFR) 0x4805h OPT3 Reserved 0x4806 NOPT3 Reserved 0x4807 OPT4 Reserved NOPT4 Reserved HSI TRIM LSI _ EN 0x00 Misc. option NHSI NLSI NIWDG NWWDG NWWG TRIM _ EN _HW _HW _HALT PRS C1 PRS C0 0x00 NPRSC1 NPR SC0 0xFF EXT CLK CKAWU SEL 0xFF Clock option 0x4808 NEXT NCKA CLK WUSEL 0x4809 HSE clock OPT5 HSECNT [7:0] 0x00 0x480A startup NOPT5 NHSECNT [7:0] 0xFF OPT6 Reserved 0x00 NOPT6 Reserved 0xFF OPT7 Reserved 0x00 NOPT7 Reserved 0xFF - Reserved - - Reserved - 0x480B Reserved 0x480C 0x480D Reserved 0x480E 0x480F Reserved 0x48FD 46/121 DocID14771 Rev 15 STM8S105x4/6 Option byte Table 11. Option byte (continued) Addr. Option name 0x487E Option byte no. Option bits 7 6 5 4 3 2 1 0 Factory default setting OPTBL BL[7:0] 0x00 NOPTBL NBL[7:0] 0xFF Bootloader 0x487F Table 12. Option byte description Option byte no. Description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 to 1 defined as UBC, memory write-protected 0x02: Page 0 to 3 defined as UBC, memory write-protected 0x03: Page 0 to 4 defined as UBC, memory write-protected ... 0x3E: Pages 0 to 63 defined as UBC, memory write-protected Other values: Reserved Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details. OPT2 AFR[7:0] Refer to the following table for the description of the alternate function remapping description of bits [7:2]. HSITRIM: High speed internal clock trimming register size 0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source OPT3 IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active DocID14771 Rev 15 47/121 50 Option byte STM8S105x4/6 Table 12. Option byte description (continued) Option byte no. Description EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN OPT4 CKAWUSEL: Auto wake-up unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for AWU PRSC[1:0] AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler 48/121 OPT5 HSECNT[7:0]: HSE crystal oscillator stabilization time 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles OPT6 Reserved OPT7 Reserved OPTBL BL[7:0]: Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 byte). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details. DocID14771 Rev 15 STM8S105x4/6 8.1 Option byte Alternate function remapping bits Table 13. Alternate function remapping bits [7:0] of OPT2 Description(1) Option byte no. OPT2 AFR7 Alternate function remapping option 7 0: AFR7 remapping option inactive: Default alternate functions.(2) 1: Port D4 alternate function = BEEP. AFR6 Alternate function remapping option 6 0: AFR6 remapping option inactive: Default alternate function.(2) 1: Port B5 alternate function = I2C_SDA; port B4 alternate function = I2C_SCL. AFR5 Alternate function remapping option 5 0: AFR5 remapping option inactive: Default alternate function.(2) 1: Port B3 alternate function = TIM1_ETR; port B2 alternate function = TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0 alternate function = TIM1_CH1N. AFR4 Alternate function remapping option 4 0: AFR4 remapping option inactive: Default alternate functions.(2) 1: Port D7 alternate function = TIM1_CH4. AFR3 Alternate function remapping option 3 0: AFR3 remapping option inactive: Default alternate function.(2) 1: Port D0 alternate function = TIM1_BKIN. AFR2 Alternate function remapping option 2 0: AFR2 remapping option inactive: Default alternate functions.(2) 1: Port D0 alternate function = CLK_CCO. Note: AFR2 option has priority over AFR3 if both are activated. AFR1 Alternate function remapping option 1 0: AFR1 remapping option inactive: Default alternate functions.(2) 1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3 AFR0 Alternate function remapping option 0 0: AFR0 remapping option inactive: Default alternate functions.(2) 1: Port D3 alternate function = ADC_ETR. 1. Do not use more than one remapping option in the same port. 2. Refer to STM8S105x4/6 pin descriptions. DocID14771 Rev 15 49/121 50 Unique ID 9 STM8S105x4/6 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single byte and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited:  For use as serial numbers  For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory.  To activate secure boot processes Table 14. Unique ID registers (96 bits) Address Content description Unique ID bits 7 0x48CD 0x48CE 0x48CF 5 4 3 U_ID[7:0] X co-ordinate on the wafer U_ID[15:8] U_ID[23:16] 0x48D0 Y co-ordinate on the wafer U_ID[31:24] 0x48D1 Wafer number U_ID[39:32] 0x48D2 U_ID[47:40] 0x48D3 U_ID[55:48] 0x48D4 U_ID[63:56] 0x48D5 50/121 6 Lot number U_ID[71:64] 0x48D6 U_ID[79:72] 0x48D7 U_ID[87:80] 0x48D8 U_ID[95:88] DocID14771 Rev 15 2 1 0 STM8S105x4/6 Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C, and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ). 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5.0 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ). 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Typical current consumption For typical current consumption measurements, VDD, VDDIO and VDDA are connected together in the configuration shown in the following figure. Figure 8. Supply current measurement conditions 9RU9 $ 9'' 9''$ 9'',2 966 966$ 966,2 06Y9 DocID14771 Rev 15 51/121 90 Electrical characteristics 10.1.5 STM8S105x4/6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. Figure 9. Pin loading conditions 67063,1 S) 06Y9 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 10. Pin input voltage 67063,1 9,1 06Y9 52/121 DocID14771 Rev 15 STM8S105x4/6 10.2 Electrical characteristics Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15. Voltage characteristics Symbol Min Max Unit -0.3 6.5 V VSS - 0.3 6.5 VSS - 0.3 VDD + 0.3 |VDDx - VDD| Variations between different power pins - 50 |VSSx - VSS| Variations between all the different ground pins - 50 VESD Electrostatic discharge voltage VDDx - VSS Ratings Supply voltage (including VDDA and VDDIO)(1) Input voltage on true open drain pins (PE1, PE2)(2) VIN Input voltage on any other pin(2) V mV see Absolute maximum ratings (electrical sensitivity) on page 89 1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected Table 16. Current characteristics Symbol Ratings Max.(1) Unit mA IVDD Total current into VDD power lines (source)(2) 100 IVSS (sink)(1) 80 Total current out of VSS ground lines IIO ΣIIO IINJ(PIN) (4) (5) Output current sunk by any I/O and control pin 20 Output current source by any I/Os and control pin -20 Total output current sourced (sum of all I/O and control pins) for devices with two VDDIO pins(3) 200 Total output current sourced (sum of all I/O and control pins) for devices with one VDDIO pin(3) 100 Total output current sunk (sum of all I/O and control pins) for devices with two VSSIO pins(3) 160 Total output current sunk (sum of all I/O and control pins) for devices with one VSSIO pin(3) 80 Injected current on NRST pin ±4 Injected current on OSCIN pin Injected current on any other ΣIINJ(PIN)(4) pin(6) Total injected current (sum of all I/O and control pins)(6) ±4 ±4 ±20 1. Data based on characterization results, not tested in production. 2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. DocID14771 Rev 15 53/121 90 Electrical characteristics STM8S105x4/6 3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package between the VDDIO/VSSIO pins. 4. IINJ(PIN) must never be exceeded. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true opendrain pads, there is no positive injection current allowed and the corresponding VIN maximum must always be respected. 5. Negative injection disturbs the analog performance of the device. See note in Section: TIM2, TIM3 - 16-bit general purpose timers. 6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. Table 17. Thermal characteristics Symbol 10.3 Ratings Value Unit 65 to 150 TSTG Storage temperature range TJ Maximum junction temperature °C 150 Operating conditions The device must be used in operating conditions that respect the parameters described in the table below. In addition, full account must be taken of all physical capacitor characteristics and tolerances. Table 18. General operating conditions Symbol Parameter Min Max Unit fCPU Internal CPU clock frequency - 0 16 MHz VDD/VDDIO Standard operating voltage - 2.95 5.5 V CEXT: capacitance of external capacitor - 470 3300 nF - 0.3 Ω - 15 nH 44- and 48-pin devices, with output on eight standard ports, two high sink ports and two open drain ports simultaneously(4) - 443 32-pin package, with output on eight standard ports and two high sink ports simultaneously(4) - VCAP(1) ESR of external capacitor ESL of external capacitor PD(3) 54/121 Conditions Power dissipation at TA = 85 °C for suffix 6 or TA= 125° C for suffix 3 at 1 MHz(2) DocID14771 Rev 15 mW 360 STM8S105x4/6 Electrical characteristics Table 18. General operating conditions (continued) Symbol Parameter Conditions Min Max TA Ambient temperature for suffix 6 version Maximum power dissipation -40 85 TA Ambient temperature for suffix 3 version Maximum power dissipation -40 125 TJ Junction temperature range Suffix 6 version -40 105 Suffix 3 version -40 130 Unit °C 1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. 2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator. 3. To calculate PDmax(TA), use the formula PDmax=(TJmax- TA)/JA (see Section 12: Thermal characteristics) with the value for TJmax given in the previous table and the value for JA given in Section 12: Thermal characteristics. 4. See Section 12: Thermal characteristics. Figure 11. fCPUmax versus VDD I&380+] )XQFWLRQDOLW\ QRW JXDUDQWHHGLQ ϭϲ WKLVDUHD ϭϮ )XQFWLRQDOLW\JXDUDQWHHG #7$WRƒ& ϴ ϰ Ϭ     6XSSO\YROWDJH 06Y9 Table 19. Operating conditions at power-up/power-down Symbol tVDD tTEMP Parameter Conditions Min Typ Max VDD rise time rate - 2(1) -  VDD fall time rate - 2(1) -  VDD rising - - 1.7(1) Reset release delay DocID14771 Rev 15 Unit µs/V ms 55/121 90 Electrical characteristics STM8S105x4/6 Table 19. Operating conditions at power-up/power-down (continued) Symbol Parameter Conditions Min Typ Max VIT+ Power-on reset threshold - 2.65 2.8 2.95 VIT- Brown-out reset threshold - 2.58 2.65 2.88 VHYS(BOR) Brown-out reset hysteresis - - 70 - V 1. Guaranteed by design, not tested in production. 56/121 Unit DocID14771 Rev 15 mV STM8S105x4/6 10.3.1 Electrical characteristics VCAP external capacitor The stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 18. Care should be taken to limit the series inductance to less than 15 nH. Figure 12. External capacitor CEXT (6/ & (65 5/HDN 06Y9 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as illustrated in Figure 10: Pin input voltage. Total current consumption in run mode Table 20. Total current consumption with code execution in run mode at VDD = 5 V Symbol Typ Max(1) HSE crystal osc. (16 MHz) 3.2 - HSE user ext. clock (16 MHz) 2.6 3.2 HSI RC osc. (16 MHz) 2.5 3.2 HSE user ext. clock (16 MHz) 1.6 2.2 HSI RC osc. (16 MHz) 1.3 2.0 fCPU = fMASTER /128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.55 - HSE crystal osc. (16 MHz) 7.7 - HSE user ext. clock (16 MHz) 7.0 8.0 HSI RC osc. (16 MHz) 7.0 8.0 fCPU = fMASTER = 2 MHz HSI RC osc. (16 MHz/8)(2) 1.5 - fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.35 2.0 fCPU = fMASTER /128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.6 - Parameter Conditions fCPU = fMASTER = 16 MHz IDD(RUN) Supply current in Run mode, code executed from RAM fCPU = fMASTER /128 = 125 kHz fCPU = fMASTER = 16 MHz IDD(RUN) Supply current in Run mode, code executed from Flash Unit mA mA 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. DocID14771 Rev 15 57/121 90 Electrical characteristics STM8S105x4/6 Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V Symbol Typ Max(1) HSE crystal osc. (16 MHz) 2.8 - HSE user ext. clock (16 MHz) 2.6 3.2 HSI RC osc. (16 MHz) 2.5 3.2 HSE user ext. clock (16 MHz) 1.6 2.2 HSI RC osc. (16 MHz) 1.3 2.0 fCPU = fMASTER /128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.55 - HSE crystal osc. (16 MHz) 7.3 - HSE user ext. clock (16 MHz) 7.0 8.0 7.0 8.0 Parameter Conditions fCPU = fMASTER = 16 MHz IDD(RUN) Supply current in Run mode, code executed from RAM fCPU = fMASTER /128 = 125 kHz fCPU = fMASTER = 16 MHz IDD(RUN) Supply current in Run mode, code executed from Flash HSI RC osc. (16 MHz) (2) fCPU = fMASTER = 2 MHz HSI RC osc. (16 MHz/8) 1.5 - fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.35 2.0 fCPU = fMASTER /128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.6 - Unit mA mA 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. Total current consumption in wait mode Table 22. Total current consumption in wait mode at VDD = 5 V Symbol Typ Max(1) HSE crystal osc. (16 MHz) 2.15 - HSE user ext. clock (16 MHz) 1.55 2.0 HSI RC osc. (16 MHz) 1.5 1.9 fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.3 - fCPU = fMASTER /s128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.7 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5 - Parameter Conditions fCPU = fMASTER = 16 MHz IDD(WFI) Supply current in wait mode 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. 58/121 DocID14771 Rev 15 Unit mA STM8S105x4/6 Electrical characteristics Table 23. Total current consumption in wait mode at VDD = 3.3 V Symbol Typ Max(1) HSE crystal osc. (16 MHz) 1.75 - HSE user ext. clock (16 MHz) 1.55 2.0 HSI RC osc. (16 MHz) 1.5 1.9 fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.3 - fCPU = fMASTER /s128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.7 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5 - Parameter Conditions fCPU = fMASTER = 16 MHz IDD(WFI) Supply current in wait mode Unit mA 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. Total current consumption in active halt mode Table 24. Total current consumption in active halt mode at VDD = 5 V Conditions Symbol Parameter IDD(AH) Supply current in active halt mode Main voltage regulator (MVR)(2) On Off 1. Typ Flash mode(3) Clock source Max at Max at Unit 85 °C(1) 85 °C(1) Operating mode HSE crystal osc. (16 MHz) 1080 - - Operating mode LSI RC osc. (128 kHz) 200 320 400 Power down mode HSE crystal osc. (16 MHz) 1030 - - Power down mode LSI RC osc. (128 kHz) 140 270 350 Operating mode LSI RC osc. (128 kHz) 68 120 220 Power down mode LSI RC osc. (128 kHz) 12 60 150 µA Data based on characterization results, not tested in production. 2. Configured by the REGAH bit in the CLK_ICKR register. 3. Configured by the AHALT bit in the FLASH_CR1 register. DocID14771 Rev 15 59/121 90 Electrical characteristics STM8S105x4/6 Table 25. Total current consumption in active halt mode at VDD = 3.3 V Conditions Symbol Parameter IDD(AH) Supply current in active halt mode Main voltage regulator (MVR)(2) On Off 1. Typ Flash mode(3) Clock source Max at Max at Unit 85 °C(1) 85 °C(1) Operating mode HSE crystal osc. (16 MHz) 680 - - Operating mode LSI RC osc. (128 kHz) 200 320 400 Power down mode HSE crystal osc. (16 MHz) 630 - - Power down mode LSI RC osc. (128 kHz) 140 270 350 Operating mode LSI RC osc. (128 kHz) 66 120 220 Power down mode LSI RC osc. (128 kHz) 10 60 150 µA Data based on characterization results, not tested in production. 2. Configured by the REGAH bit in the CLK_ICKR register. 3. Configured by the AHALT bit in the FLASH_CR1 register. Total current consumption in halt mode Table 26. Total current consumption in halt mode at VDD = 5 V Symbol IDD(H) 1. Parameter Supply current in halt mode Conditions Typ Flash in operating mode, HSI clock after wakeup 62 Flash in power-down mode, HSI clock after wakeup 6.5 Max at Max at Unit 85 °C(1) 85 °C(1) 90 150 µA 25 80 Data based on characterization results, not tested in production. Table 27. Total current consumption in halt mode at VDD = 3.3 V Symbol IDD(H) 1. 60/121 Parameter Supply current in halt mode Conditions Typ Flash in operating mode, HSI clock after wakeup 60 Flash in power-down mode, HSI clock after wakeup 4.5 Data based on characterization results, not tested in production. DocID14771 Rev 15 Max at Max at Unit 85 °C(1) 85 °C(1) 90 150 µA 20 80 STM8S105x4/6 Electrical characteristics Low power mode wakeup times Table 28. Wakeup times Typ Max(1) - See note(3) 0.56 - HSI (after wakeup) 1(6) 2(6) Flash in Wakeup time active halt MVR voltage operating (4) (2) regulator off mode to run mode mode(5) HSI (after wakeup) 3(6) - tWU(AH) Flash in Wakeup time active halt MVR voltage operating regulator off(4) mode to run mode(2) mode(5) HSI (after wakeup) 48(6) - tWU(AH) Flash in Wakeup time active halt MVR voltage HSI (after power-down (4) regulator off wakeup) mode to run mode(2) mode(5) 50(6) - tWU(H) Wakeup time from halt mode to run mode(2) Flash in operating mode(5) 52 - tWU(H) Wakeup time from halt mode to run mode(2) Flash in power-down mode(5) 54 - Symbol Parameter tWU(WFI) Wakeup time from wait mode to run mode(2) 0 to 16 MHz tWU(WFI) Wakeup time from run mode(2) fCPU= fMASTER= 16 MHz tWU(AH) Flash in Wakeup time active halt MVR voltage (4) operating (2) regulator on mode to run mode mode(5) tWU(AH) 1. Conditions Unit µs Data based on characterization results, not tested in production. 2. Measured from interrupt event to interrupt vector fetch 3. tWU(WFI) = 2 x 1/fmaster + 67 x 1/fCPU 4. Configured by the REGAH bit in the CLK_ICKR register. 5. Configured by the AHALT bit in the FLASH_CR1 register. 6. Plus 1 LSI clock depending on synchronization. Total current consumption and timing in forced reset state Table 29. Total current consumption and timing in forced reset state Symbol Parameter IDD(R) Supply current in reset state(2) tRESETBL Reset pin release to vector fetch Conditions Typ Max(1) VDD = 5 V 500 - VDD = 3.3 V 400 - - - 150 Unit µA µs 1. Data guaranteed by design, not tested in production. 2. Characterized with all I/Os tied to VSS. Current consumption of on-chip peripherals Subject to general operating conditions for VDD and TA. DocID14771 Rev 15 61/121 90 Electrical characteristics STM8S105x4/6 HSI internal RC/fCPU= fMASTER = 16 MHz, VDD = 5 V Table 30. Peripheral current consumption Symbol Parameter Typ IDD(TIM1) TIM1 supply current (1) 230 IDD(TIM2) TIM2 supply current(1) 115 IDD(TIM3) TIM3 supply current (1) 90 TIM4 supply current (1) IDD(TIM4) IDD(UART2) UART2 supply current IDD(SPI) SPI supply current (2) IDD(I2C) current(2) I2C supply IDD(ADC1) 30 (2) ADC1 supply current when 110 Unit µA 45 65 converting(3) 955 1. Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. 2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production. 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Not tested in production. Current consumption curves The following figures show typical current consumption measured with code executing in RAM. Figure 13. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz 62/121 DocID14771 Rev 15 STM8S105x4/6 Electrical characteristics Figure 14. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V Figure 15. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz DocID14771 Rev 15 63/121 90 Electrical characteristics STM8S105x4/6 Figure 16. Typ IDD(WFI) vs. VDD HSE external clock, fCPU = 16 MHz Figure 17. Typ IDD(WFI) vs. fCPU HSE external clock, VDD = 5 V 64/121 DocID14771 Rev 15 STM8S105x4/6 Electrical characteristics Figure 18. Typ IDD(WFI) vs. VDD HSI RC osc., fCPU = 16 MHz DocID14771 Rev 15 65/121 90 Electrical characteristics 10.3.3 STM8S105x4/6 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 31. HSE user external clock characteristics Symbol Parameter Conditions Min Max Unit MHz fHSE_ext User external clock source frequency - 0 16 VHSEH(1) OSCIN input pin high level voltage - 0.7 x VDD VDD + 0.3 V VHSEL(1) OSCIN input pin low level voltage - VSS 0.3 x VDD ILEAK_HSE OSCIN input leakage current VSS < VIN < VDD -1 +1 V 1. Data based on characterization results, not tested in production. Figure 19. HSE external clock source +6(+ +6(/ ([WHUQDOFORFN VRXUFH I+6( 26&,1 670 069 66/121 DocID14771 Rev 15 µA STM8S105x4/6 Electrical characteristics HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 32. HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE External high speed oscillator frequency - 1 - 16 MHz RF Feedback resistor - - 220 - k C(1) Recommended load capacitance(2) - - - 20 pF C = 20 pF fOSC = 16 MHz - - 6 (start up) 1.6 (stabilized)(3) IDD(HSE) HSE oscillator power consumption gm Oscillator transconductance tSU(HSE)(4) Startup time mA C = 10 pF fOSC = 16 MHz - - 6 (start up) 1.2 (stabilized)(3) - 5 - - mA/V VDD is stabilized - 1 - ms 1. C is approximately equivalent to 2 x crystal Cload. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details 3. Data based on characterization results, not tested in production. 4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. DocID14771 Rev 15 67/121 90 Electrical characteristics STM8S105x4/6 Figure 20. HSE oscillator circuit diagram 5P /P I+6(WRFRUH &2 5) &/ &P 26&,1 JP 5HVRQDWRU &RQVXPSWLRQ FRQWURO 5HVRQDWRU &/ 26&287 670 069 HSE oscillator critical gm equation g mcrit =  2    f HSE  2  R m  2Co + C  2 Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1 = CL2 = C: Grounded external capacitance g m » g mcrit 68/121 DocID14771 Rev 15 STM8S105x4/6 10.3.4 Electrical characteristics Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI) Table 33. HSI oscillator characteristics Symbol fHSI Parameter Conditions Min Typ Max Unit - - 16 - MHz - - 1(2) VDD V, TA  25 °C(3) -1.0 - 1.0 VDD= 5 V,  -25°C TA  85 °C -2.0 - 2.0 -3.0(3) - 3.0(3) Frequency User-trimmed with CLK_HSITRIMR register for Accuracy of HSI oscillator given VDD and TA conditions(1) ACCHS HSI oscillator accuracy (factory calibrated) 2.95 V VDD  5.5 V,  -40°C TA  125 °C % tsu(HSI) HSI oscillator wakeup time including calibration - - - 1.0(2) µs IDD(HSI) HSI oscillator power consumption - - 170 250(3) µA 1. Refer to application note. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. Figure 21. Typical HSI accuracy @ VDD = 5 V vs 5 temperatures DocID14771 Rev 15 69/121 90 Electrical characteristics STM8S105x4/6 Figure 22. Typical HSI frequency variation vs VDD @ 4 temperatures 70/121 DocID14771 Rev 15 STM8S105x4/6 Electrical characteristics Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 34. LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fLSI Frequency - 110 128 150 kHz tsu(LSI) LSI oscillator wakeup time - - - 7(1) µs - - 5 - µA IDD(LSI) LSI oscillator power consumption 1. Guaranteed by design, not tested in production. Figure 23. Typical LSI frequency variation vs VDD@ 4 temperatures DocID14771 Rev 15 71/121 90 Electrical characteristics 10.3.5 STM8S105x4/6 Memory characteristics RAM and hardware registers Table 35. RAM and hardware registers Symbol VRM Parameter Data retention mode(1) Conditions Min Unit Halt mode (or reset) VIT-max(2) V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. 2. Refer to Section 10.3: Operating conditions for the value of VIT-max. Flash program memory/data EEPROM memory Table 36. Flash program memory/data EEPROM memory Symbol VDD tprog terase NRW Parameter Operating voltage  (all modes, execution/write/erase) IDD Min(1) Typ Max Unit V fCPU≤ 16 MHz 2.95 - 5.5 Standard programming time (including erase) for byte/word/block  (1 byte/4 byte/128 byte) - - 6 6.6 Fast programming time for 1 block  (128 byte) - - 3 3.33 Erase time for 1 block (128 byte) - - 3 3.33 TA = +85 °C 10k - - TA = +125 °C 300k 1M - Data retention (program and data memory) after 10k erase/write cycles at TA= +55 °C TRET = 55 °C 20 - - Data retention (data memory) after 300k erase/write cycles at  TA= +125°C TRET = 85 °C 1 - - - - 2 - ms Erase/write cycles  (program memory)(2) Erase/write cycles (data tRET Conditions memory)(2) year Supply current (Flash programming or erasing for 1 to 128 byte) 1. Data based on characterization results, not tested in production. 2. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a write/erase operation addresses a single byte. 72/121 cycle DocID14771 Rev 15 mA STM8S105x4/6 10.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 37. I/O static characteristics Symbol Parameter VIL Input low level voltage VIH Input high level voltage Vhys Hysteresis(1) Rpu Pull-up resistor tR, tF tR, tF Rise and fall time (10% - 90%) Rise and fall time (10% - 90%) Conditions Min Typ Max -0.3 V - 0.3 x VDD 0.7 x VDD - VDD + 0.3 V - 700 - mV VDD = 5 V, VIN = VSS 30 55 80 k Fast I/Os Load = 50 pF - - 35(2) VDD = 5 V Unit V ns Standard and high sink I/Os Load = 50 pF - - 125(2) Fast I/Os Load = 20 pF - - 20(2) (2) ns Standard and high sink I/Os Load = 20 pF - - 50 Ilkg Digital input leakage current VSS VIN VDD - - ±1(3) µA Ilkg ana Analog input leakage current VSS VIN VDD - - ±250(3) nA Ilkg(inj) Leakage current in adjacent I/O Injection current ±4 mA - - ±1(3) µA 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. Data guaranteed by design. 3. Data based on characterization results, not tested in production DocID14771 Rev 15 73/121 90 Electrical characteristics STM8S105x4/6 Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures Figure 25. Typical pull-up current vs VDD @ 4 temperatures Figure 26. Typical pull-up resistance vs VDD @ 4 temperatures Û&  Û&  Û& 3XOOXSUHVLVWDQFH >Ÿ :@ Û&              9''>9@ 069 Table 38. Output driving current (standard ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO= 10 mA, VDD = 5 V - 2.0 Output low level with 4 pins sunk IIO= 4 mA, VDD = 3.3 V - 1.0(1) Output high level with 8 pins sourced IIO= 10 mA, VDD = 5 V 2.4 - Output high level with 4 pins sourced IIO= 4 mA, VDD = 3.3 V 2.0(1) - 1. Data based on characterization results, not tested in production 74/121 DocID14771 Rev 15 Unit V STM8S105x4/6 Electrical characteristics Table 39. Output driving current (true open drain ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 2 pins sunk IIO= 10 mA, VDD = 5 V - 1.0 Output low level with 2 pins sunk IIO= 10 mA, VDD = 3.3 V - 1.5(1) Output high level with 2 pins sourced IIO= 10 mA, VDD = 5 V - 2.0(1) Unit V 1. Data based on characterization results, not tested in production Table 40. Output driving current (high sink ports) Symbol Parameter Output low level with 8 pins sunk VOL Output low level with 4 pins sunk Output high level with 8 pins sourced VOH Output high level with 4 pins sourced Conditions Min Max IIO= 10 mA, VDD = 5 V - 0.9 IIO= 10 mA, VDD = 3.3 V - 1.1(1) IIO= 20 mA, VDD = 5 V - 1.6(1) IIO= 10 mA, VDD = 5 V 3.8 - IIO= 10 mA, VDD = 3.3 V 1.9(1) - IIO= 20 mA, VDD = 5 V 2.9(1) - Unit V 1. Data based on characterization results, not tested in production. 10.3.7 Typical output level curves The following figures show the typical output level curves measured with the output on a single pin. Figure 27. Typ. VOL @ VDD = 3.3 V (standard ports) Figure 28. Typ. VOL @ VDD = 5.0 V (standard ports) DocID14771 Rev 15 75/121 90 Electrical characteristics STM8S105x4/6 Figure 29. Typ. VOL @ VDD = 3.3 V (true open drain ports) Figure 30. Typ. VOL @ VDD = 5.0 V (true open drain ports) Figure 31. Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 32. Typ. VOL @ VDD = 5.0 V (high sink ports) 76/121 DocID14771 Rev 15 STM8S105x4/6 Electrical characteristics Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) Figure 34. Typ. VDD - VOH @ VDD = 5.0 V (standard ports) Figure 35. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) Figure 36. Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) DocID14771 Rev 15 77/121 90 Electrical characteristics 10.3.8 STM8S105x4/6 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 41. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST) NRST input low level voltage(1) - -0.3 - 0.3 x VDD VIH(NRST) NRST input high level voltage(1) IOL= 2 mA 0.7 x VDD - VDD+ 0.3 VOL(NRST) NRST output low level voltage(1) IOL= 3 mA - - 0.5 - 30 55 80 RPU(NRST) NRST pull-up resistor(2) tIFP(NRST) NRST input filtered pulse(3) - - - 75 tINFP(NRST) NRST Input not filtered pulse(3) - 500 - - NRST output pulse(3) - 20 - - tOP(NRST) 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor. 3. Data guaranteed by design, not tested in production. Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures 78/121 DocID14771 Rev 15 Unit V k ns µs STM8S105x4/6 Electrical characteristics Figure 38. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures Figure 39. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures The reset network shown in Figure 40 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 41: NRST pin characteristics), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF. DocID14771 Rev 15 79/121 90 Electrical characteristics STM8S105x4/6 Figure 40. Recommended reset pin protection 670 9'' 538 ([WHUQDO UHVHW FLUFXLW 1567 )LOWHU ȝ) 2SWLRQDO 06Y9 10.3.9 SPI serial peripheral interface Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42. SPI characteristics Symbol fSCK 1/tc(SCK) 80/121 Conditions(1) Parameter SPI clock frequency Min Max Master mode 0 8 Slave mode 0 6 DocID14771 Rev 15 Unit MHz STM8S105x4/6 Electrical characteristics Table 42. SPI characteristics (continued) Symbol Conditions(1) Parameter Min Max - 25 SPI clock rise and fall time Capacitive load:  C = 30 pF tsu(NSS)(2) NSS setup time Slave mode 4 * tMASTER - th(NSS)(2) NSS hold time Slave mode 70 - Master mode tSCK/2 - 15 tSCK/2 + 15 Master mode 5 - Slave mode 5 - Master mode 7 - Slave mode 10 - Data output access time Slave mode - 3* tMASTER Data output disable time Slave mode 25 - tv(SO)(2) Data output valid time Slave mode (after enable edge) - 73 tv(MO)(2) Data output valid time Master mode (after enable edge) - 36 Slave mode (after enable edge) 28 - Master mode (after enable edge) 12 - tr(SCK) tf(SCK) (2) tw(SCKH) SCK high and low time tw(SCKL)(2) tsu(MI)(2) tsu(SI)(2) Data input setup time th(MI)(2) th(SI)(2) Data input hold time ta(SO) (2)(3) tdis(SO) (2)(4) th(SO)(2) Data output hold time th(MO)(2) Unit ns 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. DocID14771 Rev 15 81/121 90 Electrical characteristics STM8S105x4/6 Figure 41. SPI timing diagram where slave mode and CPHA = 0 166LQSXW 6&.,QSXW W68166 &3+$  &32/  WK166 WF6&. WZ6&.+ WZ6&./ &3+$  &32/  W962 WD62 0,62 287387 WU6&. WI6&. WK62 06%287 %,7287 06%,1 %,7,1 WGLV62 /6%287 WVX6, 026, ,1387 /6%,1 WK6, DLF 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 42. SPI timing diagram where slave mode and CPHA = 1 166LQSXW 6&.LQSXW W68166 &3+$ &32/ &3+$ &32/     WZ6&.+ WZ6&./ WK62 WY62 WD62 0,62 287387 06%287 %,7287 WU6&. WI6&. WGLV62 /6%287 WK6, WVX6, 026, ,1387 WK166 WF6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. 82/121 DocID14771 Rev 15 STM8S105x4/6 Electrical characteristics Figure 43. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$  &32/  6&.2XWSXW WF6&. &3+$  &32/  &3+$  &32/  &3+$  &32/  WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 % , 7287 06%287 WY02 /6%287 WK02 DLF 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. DocID14771 Rev 15 83/121 90 Electrical characteristics 10.3.10 STM8S105x4/6 I2C interface characteristics Table 43. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Unit Min(2) Max(2) Min(2) Max(2) tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0(3) - 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time (VDD = 3 to 5.5 V) - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time (VDD = 3 to 5.5 V) - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - tw(STO:STA) STOP to START condition time  (bus free) 4.7 - 1.3 - Cb Capacitive load for each bus line - 400 - 400 µs ns µs pF 1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400 kHz) 2. Data based on standard I2C protocol requirement, not tested in production 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Figure 44. Typical application with I2C bus and timing diagram 9'' NŸ 9'' NŸ ,&EXV 670 Ÿ 6'$ Ÿ 6&/ 5HSHDWHG VWDUW 67$57 WVX67$ WZ67267$ 6'$ WI6'$ WU6'$ WVX6'$ WK6'$ 67$57 6723 6&/ WK67$ WZ6&/+ WZ6&// WU6&/ WI6&/ WVX672 06Y9 84/121 DocID14771 Rev 15 STM8S105x4/6 10.3.11 Electrical characteristics 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 44. ADC characteristics Symbol Parameter Conditions Min Typ Max VDD= 2.95 to 5.5 V 1 - 4 VDD= 4.5 to 5.5 V 1 - 6 fADC ADC clock frequency VDDA Analog supply - 3.0 - 5.5 VREF+ Positive reference voltage - 2.75(1) - VDDA VREF- Negative reference voltage - VSSA - 0.5(1) - VSSA - VDDA Devices with external VREF+/VREF- VREF- - VREF+ - - 3 - fADC = 4 MHz - 0.75 - fADC = 6 MHz - 0.5 - - - 7.0 - VAIN Conversion voltage range(2) CADC Internal sample and hold capacitor tS(2) Minimum sampling time tSTAB Wakeup time from standby tCONV Minimum total conversion time (including sampling time, 10bit resolution) Unit MHz V V pF µs µs fADC = 4 MHz 3.5 µs fADC = 6 MHz 2.33 µs - 14 1/fADC 1. Data guaranteed by design, not tested in production. 2. During the sample time, the sampling capacitance, CAIN (3 pF max), can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. DocID14771 Rev 15 85/121 90 Electrical characteristics STM8S105x4/6 Table 45. ADC accuracy with RAIN< 10 k, VDDA = 5 V Symbol |ET| |EO| |EG| |ED| |EL| Parameter Total unadjusted Offset Gain error(2) error(2) error(2) Differential linearity Integral linearity error(2) error(2) Conditions Typ Max(1) fADC = 2 MHz 1.0 2.5 fADC = 4 MHz 1.4 3.0 fADC = 6 MHz 1.6 3.5 fADC = 2 MHz 0.6 2.0 fADC = 4 MHz 1.1 2.5 fADC = 6 MHz 1.2 2.5 fADC = 2 MHz 0.2 2.0 fADC = 4 MHz 0.6 2.5 fADC = 6 MHz 0.8 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 0.7 1.5 fADC = 6 MHz 0.8 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 fADC = 6 MHz 0.6 1.5 Unit LSB 1. Data based on characterization results, not tested in production. 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy. Table 46. ADC accuracy with RAIN< 10 k, VDDA = 3.3 V Symbol Parameter |ET| Total unadjusted error(2) |EO| Offset error(2) |EG| Gain error(2) |ED| Differential linearity error(2) |EL| Integral linearity error(2) Conditions Typ Max(1) fADC = 2 MHz 1.1 2.0 fADC = 4 MHz 1.6 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 1.3 2.0 fADC = 2 MHz 0.2 1.5 fADC = 4 MHz 0.5 2.0 fADC = 2 MHz 0.7 1.0 fADC = 4 MHz 0.7 1.0 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 1. Data based on characterization results, not tested in production. 86/121 DocID14771 Rev 15 Unit LSB STM8S105x4/6 Electrical characteristics 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy. Figure 45. ADC accuracy characteristics 1023 1022 1021 EG V –V DDA SSA 1LSB = ----------------------------------------IDEAL 1024 (2) ET 7 (3) (1) 6 5 4 EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 1021102210231024 VDDA 1. Example of an actual transfer curve 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 46. Typical application with ADC s 9$,1 5$,1 &$,1 /Edž ^dDϴ 97 9 97 9 ELW$' FRQYHUVLRQ ,/ цϭђ &$'& 06Y9 1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor. DocID14771 Rev 15 87/121 90 Electrical characteristics 10.3.12 STM8S105x4/6 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).  ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.  FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STM microcontrollers). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:  Corrupted program counter  Unexpected reset  Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance). Table 47. EMS data Symbol 88/121 Parameter Conditions Level/class VFESD VDD 5 V, TA25 °C,  Voltage limits to be applied on any I/O pin fMASTER 16 MHz (HSI clock), to induce a functional disturbance Conforms to IEC 1000-4-2 2/B(1) VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD 5 V, TA25 °C,  fMASTER 16 MHz (HSI clock), Conforms to IEC 1000-4-4 4/A(1) DocID14771 Rev 15 STM8S105x4/6 Electrical characteristics 1. Data obtained with HSI clock configuration, after applying the hardware recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC 61967-2 which specifies the board and the loading of each pin. Table 48. EMI data Conditions Symbol Parameter General conditions SEMI Peak level EMI level VDD 5 V,  TA 25 °C,  LQFP48 package. Conforming to  IEC 61967-2 Monitored frequency band Max fHSE/fCPU(1) 8 MHz/ 8 MHz 8 MHz/ 16 MHz 0.1 MHz to 30 MHz 13 14 30 MHz to 130 MHz 23 19 130 MHz to 1 GHz -4.0 -4.0 EMI level 2.0 1.5 Unit dBµV - 1. Data based on characterization results, not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pin). One model can be simulated: Human body model. This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 49. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum Unit value(1) VESD(HBM) Electrostatic discharge voltage (Human body model) TA 25°C, conforming to JESD22-A114 A 2000 VESD(CDM) Electrostatic discharge voltage (Charge device model) TA 25°C, conforming to SD22-C101 IV 1000 V 1. Data based on characterization results, not tested in production DocID14771 Rev 15 89/121 90 Electrical characteristics STM8S105x4/6 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance.  A supply overvoltage (applied to each power supply pin), and  A current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 50. Electrical sensitivities Symbol Parameter Conditions Class(1) TA 25 °C LU TA 85 °C Static latch-up class A TA 125 °C 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 90/121 DocID14771 Rev 15 STM8S105x4/6 11 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LQFP48 package information Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 3%!4).' 0,!.% # C ! ! ! MM '!5'%0,!.% CCC # $ + ! $ , , $      0). )$%.4)&)#!4)/. % % B % 11.1    E "?-%?6 1. Drawing is not to scale. DocID14771 Rev 15 91/121 107 Package information STM8S105x4/6 Table 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 92/121 DocID14771 Rev 15 STM8S105x4/6 Package information Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint                    AID 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 49. LQFP48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ  45.4 $5 'DWHFRGH 6WDQGDUG67ORJR : 88 5HYLVLRQFRGH 3LQLGHQWLILHU 3 069 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such DocID14771 Rev 15 93/121 107 Package information STM8S105x4/6 usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 11.2 LQFP44 package information Figure 50. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline 3%!4).' 0,!.% ! ! ! # MM '!5'%0,!.% # ! CCC + , $ , $ $     0). )$%.4)&)#!4)/. % % % B     E :@.& 1. Drawing is not to scale. 94/121 DocID14771 Rev 15 STM8S105x4/6 Package information Table 52. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3858 0.3937 0.4016 D3 - 8.000 - - 0.3150 - E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3858 0.3937 0.4016 E3 - 8.000 - - 0.3150 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID14771 Rev 15 95/121 107 Package information STM8S105x4/6         Figure 51. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package recommended footprint