STM8S207xx STM8S208xx
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash,
integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
Datasheet - production data
Features
Core
– Max fCPU: up to 24 MHz, 0 wait states @
fCPU 16 MHz
– Advanced STM8 core with Harvard
architecture and 3-stage pipeline
– Extended instruction set
– Max 20 MIPS @ 24 MHz
Memories
– Program: up to 128 Kbytes Flash; data
retention 20 years at 55 °C after 10 kcycles
– Data: up to 2 Kbytes true data EEPROM;
endurance 300 kcycles
– RAM: up to 6 Kbytes
Clock, reset and supply management
– 2.95 to 5.5 V operating voltage
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
– Clock security system with clock monitor
– Wait, active-halt, & halt low power modes
– Peripheral clocks switched off individually
– Permanently active, low consumption
power-on and power-down reset
Interrupt management
– Nested interrupt controller with 32
interrupts
– Up to 37 external interrupts on 6 vectors
Timers
– 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, deadtime insertion and flexible synchronization
– 8-bit basic timer with 8-bit prescaler
– Auto wakeup timer
– Window watchdog, independent watchdog
February 2015
This is information on a product in full production.
LQFP80
14 x 14 mm
LQFP64
14 x 14 mm
LQFP64
10 x 10 mm
LQFP48
7 x 7 mm
LQFP44
10 x 10mm
LQFP32
7 x 7 mm
Communications interfaces
– High speed 1 Mbit/s active beCAN 2.0B
– UART with clock output for synchronous
operation - LIN master mode
– UART with LIN 2.1 compliant, master/slave
modes and automatic resynchronization
– SPI interface up to 10 Mbit/s
– I2C interface up to 400 Kbit/s
10-bit ADC with up to 16 channels
I/Os
– Up to 68 I/Os on an 80-pin package
including 18 high sink outputs
– Highly robust I/O design, immune against
current injection
– Development support
– Single wire interface module (SWIM) and
debug module (DM)
96-bit unique ID key for each device
Table 1. Device summary
Reference
Part number
STM8S207xx
STM8S207MB, STM8S207M8, STM8S207RB,
STM8S207R8, STM8S207R6, STM8S207CB,
STM8S207C8, STM8S207C6, STM8S207SB,
STM8S207S8, STM8S207S6, STM8S207K8,
STM8S207K6
STM8S208xx
STM8S208MB, STM8S208RB, STM8S208R8,
STM8S208R6, STM8S208CB, STM8S208C8,
STM8S208C6, STM8S208SB, STM8S208S8,
STM8S208S6
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Contents
STM8S207xx STM8S208xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
6
4.1
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14
4.3
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8
Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11
TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18
4.12
TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13
Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.2
UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.3
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14.4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.14.5
beCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
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4.14.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Contents
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.4
Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.5
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.6
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.7
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.3.1
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3.2
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3.3
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65
10.3.4
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67
10.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.6
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.7
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.8
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.3.9
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.1
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.1.1
LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.1.2
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.1.3
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.1.4
LQFP44 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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11.1.5
11.2
12
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.2.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 109
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.1
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .110
12.2
Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3
12.2.1
STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.2.2
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8S20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviations for pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 58
Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 59
Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85° C . . . . . . . . . . 61
Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 61
Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC accuracy with RAIN < 10 k, VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC accuracy with RAIN < 10 kRAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
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ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LQFP64 - 64-pin, 14 x 14 mm low-profile quad flat package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanical . . . . . . . . . . . . . . . . 99
LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM8S20xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LQFP 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical HSI frequency variation vs VDD at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical LSI frequency variation vs VDD @ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 79
Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 92
LQFP80 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
LQFP64 - 64-pin 14 mm x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 95
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 96
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . . 97
DocID14733 Rev 13
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8
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
8/117
STM8S207xx STM8S208xx
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 99
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 100
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 102
LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 104
LQFP44 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 105
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 106
LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
STM8S207xx/208xx performance line ordering information scheme(1) . . . . . . . . . . . . . . 112
DocID14733 Rev 13
STM8S207xx STM8S208xx
1
Introduction
Introduction
This datasheet contains the description of the STM8S20xxx features, pinout, electrical
characteristics, mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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116
Description
2
STM8S207xx STM8S208xx
Description
The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash
program memory. They are referred to as high-density devices in the STM8S
microcontroller family reference manual.
All STM8S20xxx devices provide the following benefits: reduced system cost, performance
robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and modular peripherals.
Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8S family thanks to their advanced core which is
made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
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Description
Device
Pin count
Max. number of GPIOs
(I/O)
Ext. interrupt pins
Timer CAPCOM channels
Timer complementary outputs
A/D converter channels
High sink I/Os
High density Flash program memory
(bytes)
Data EEPROM
(bytes
RAM (bytes)
beCAN interface
Table 2. STM8S20xxx performance line features
STM8S207MB
STM8S207M8
STM8S207RB
STM8S207R8
STM8S207R6
STM8S207CB
STM8S207C8
STM8S207C6
STM8S207SB
STM8S207S8
STM8S207S6
STM8S207K8
STM8S207K6
80
80
64
64
64
48
48
48
44
44
44
32
32
68
68
52
52
52
38
38
38
34
34
34
25
25
37
37
36
36
36
35
35
35
31
31
31
23
23
9
9
9
9
9
9
9
9
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
16
16
16
16
16
10
10
10
9
9
9
7
7
18
18
16
16
16
16
16
16
15
15
15
12
12
128 K
64 K
128 K
64 K
32 K
128 K
64 K
32 K
128 K
64 K
32 K
64 K
32 K
2048
2048
2048
1536
1024
2048
1536
1024
1536
1536
1024
1024
1024
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
No
STM8S208MB
STM8S208RB
STM8S208R8
STM8S208R6
STM8S208CB
STM8S208C8
STM8S208C6
STM8S208SB
STM8S208S8
STM8S208S6
80
64
64
64
48
48
48
44
44
44
68
52
52
52
38
38
38
34
34
34
37
37
37
37
35
35
35
31
31
31
9
9
9
9
9
9
9
8
8
8
3
3
3
3
3
3
3
3
3
3
16
16
16
16
10
10
10
9
9
9
18
16
16
16
16
16
16
15
15
15
128 K
128 K
64 K
32 K
128 K
64 K
32 K
128 K
64 K
32 K
2048
2048
2048
2048
2048
2048
2048
1536
1536
1536
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
Yes
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Block diagram
3
STM8S207xx STM8S208xx
Block diagram
Figure 1. STM8S20xxx block diagram
Reset block
XTAL 1-24 MHz
Clock controller
Reset
Reset
RC int. 16 MHz
POR/PDR
Detector
RC int. 128 kHz
BOR
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
high density program
Flash
400 Kbit/s
I2C
10 Mbit/s
SPI
LIN master
SPI emul.
UART1
Master/slave
autosynchro
UART3
1 Mbit/s
beCAN
16 channels
ADC2
1/2/4 kHz
beep
Up to 128 Kbytes
Debug/SWIM
Up to 2 Kbytes
data EEPROM
Address and data bus
Single wire
debug interf.
Boot ROM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
Beeper
AWU timer
1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
Independent WDG: Independent watchdog
POR/PDR: Power on reset / power down reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
UART: Universal asynchronous receiver transmitter
Window WDG: Window watchdog
12/117
Up to 6 Kbytes
RAM
DocID14733 Rev 13
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
Up to
5 CAPCOM
channels
STM8S207xx STM8S208xx
4
Product overview
Product overview
The following section intends to give an overview of the basic features of the STM8S20xxx
functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
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Product overview
4.2
STM8S207xx STM8S208xx
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
4.3
4.4
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
Interrupt controller
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 37 external interrupts on six vectors including TLI
Trap and reset interrupts
Flash program and data EEPROM memory
Up to 128 Kbytes of high density Flash program single voltage Flash memory
Up to 2K bytes true data EEPROM
Read while write: Writing in data memory possible while executing code in program
memory.
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by
writing a MASS key sequence in a control register. This allows the application to write to
data EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
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STM8S207xx STM8S208xx
Product overview
The size of the UBC is programmable through the UBC option byte (Table 13.), in
increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: Up to 128 Kbytes minus UBC
User-specific boot code (UBC): Configurable up to 128 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually
the IAP and communication routines.
Figure 2. Flash memory organization
Data
EEPROM
memory
Data memory area (2 Kbytes)
Option bytes
UBC area
Remains write protected during IAP
Programmable area from 1 Kbyte
(2 first pages) up to 128 Kbytes
(1 page steps)
Up to
128 Kbytes
Flash
program
memory
Program memory area
Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
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Product overview
4.5
STM8S207xx STM8S208xx
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
–
1-24 MHz high-speed external crystal (HSE)
–
Up to 24 MHz high-speed user-external clock (HSE user-ext)
–
16 MHz high-speed internal RC oscillator (HSI)
–
128 kHz low-speed internal RC (LSI)
Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
16/117
Bit
Peripheral
clock
Bit
Peripheral
clock
Bit
Peripheral
clock
Bit
Peripheral
clock
PCKEN17
TIM1
PCKEN13
UART3
PCKEN27
beCAN
PCKEN23
ADC
PCKEN16
TIM3
PCKEN12
UART1
PCKEN26
Reserved
PCKEN22
AWU
PCKEN15
TIM2
PCKEN11
SPI
PCKEN25
Reserved
PCKEN21
Reserved
PCKEN14
TIM4
PCKEN10
I2C
PCKEN24
Reserved
PCKEN20
Reserved
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STM8S207xx STM8S208xx
4.6
Product overview
Power management
For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.
4.7
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1.
Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2.
Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
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Product overview
STM8S207xx STM8S208xx
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
4.9
Auto wakeup counter
Used for auto wakeup from active halt mode
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
4.11
18/117
16-bit up, down and up/down autoreload counter with 16-bit prescaler
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2, TIM3 - 16-bit general purpose timers
16-bit autoreload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
Timers with 3 or 2 individually configurable capture/compare channels
PWM mode
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
DocID14733 Rev 13
STM8S207xx STM8S208xx
4.12
Product overview
TIM4 - 8-bit basic timer
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Table 4. TIM timer features
Timer
Counter
size
(bits)
Prescaler
TIM1
16
Any integer from 1 to 65536
Up/down
4
3
Yes
TIM2
16
Any power of 2 from 1 to 32768
Up
3
0
No
TIM3
16
Any power of 2 from 1 to 32768
Up
2
0
No
TIM4
8
Any power of 2 from 1 to 128
Up
0
0
No
Counting CAPCOM Complem.
Ext.
mode
trigger
channels outputs
Timer
synchronization/
chaining
No
4.13
Analog-to-digital converter (ADC2)
STM8S20xxx performance line products contain a 10-bit successive approximation A/D
converter (ADC2) with up to 16 multiplexed input channels and the following main features:
4.14
Input voltage range: 0 to VDDA
Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices
Conversion time: 14 clock cycles
Single and continuous modes
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
Communication interfaces
The following communication interfaces are implemented:
UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode,
IrDA mode, single wire mode.
UART3: Full feature UART, LIN2.1 master/slave capability
SPI: Full and half-duplex, 10 Mbit/s
I²C: Up to 400 Kbit/s
beCAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s
DocID14733 Rev 13
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116
Product overview
4.14.1
STM8S207xx STM8S208xx
UART1
Main features
One Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
–
Address bit (MSB)
–
Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
Synchronous communication
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode
4.14.2
Emission: Generates 13-bit sync break frame
Reception: Detects 11-bit break frame
UART3
Main features
20/117
1 Mbit/s full duplex SCI
LIN master capable
High precision baud rate generator
DocID14733 Rev 13
STM8S207xx STM8S208xx
Product overview
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
–
Address bit (MSB)
–
Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
LIN master capability
Emission: Generates 13-bit sync break frame
Reception: Detects 11-bit break frame
LIN slave mode
4.14.3
Autonomous header handling - one single interrupt per valid message header
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15%
Sync delimiter checking
11-bit LIN sync break detection - break detection always active
Parity check on the LIN identifier field
LIN error management
Hot plugging support
SPI
Maximum speed: 10 Mbit/s (fMASTER/2) both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
DocID14733 Rev 13
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116
Product overview
4.14.4
I2C
4.14.5
STM8S207xx STM8S208xx
I2C master features:
–
Clock generation
–
Start and stop generation
I2C
slave features:
–
Programmable I2C address detection
–
Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
–
Standard speed (up to 100 kHz)
–
Fast speed (up to 400 kHz)
beCAN
The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the
CAN protocol version 2.0A and B. It has been designed to manage a high number of
incoming messages efficiently with a minimum CPU load.
For safety-critical applications the beCAN controller provides all hardware functions to
support the CAN time triggered communication option (TTCAN).
The maximum transmission speed is 1 Mbit.
Transmission
Three transmit mailboxes
Configurable transmit priority by identifier or order request
Time stamp on SOF transmission
Reception
8-, 11- and 29-bit ID
One receive FIFO (3 messages deep)
Software-efficient mailbox mapping at a unique address space
FMI (filter match index) stored with message
Configurable FIFO overrun
Time stamp on SOF reception
Six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking
configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID
Filtering modes:
22/117
–
Mask mode permitting ID range filtering
–
ID list mode
Time triggered communication option
–
Disable automatic retransmission mode
–
16-bit free running timer
–
Configurable timer resolution
–
Time stamp sent in last two data bytes
DocID14733 Rev 13
STM8S207xx STM8S208xx
Pinouts and pin description
5
Pinouts and pin description
5.1
Package pinouts
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD7/TLI
PD6/UART3_RX
PD5/UART3_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PI7
PI6
PE0 (HS)/CLK_CCO
PE1(T)/I2C_SCL
PE2 (T]/I 2C_SDA
PE3/TIM1_BKIN
PE4
PG7
PG6
PG5
PI5
PI4
Figure 3. LQFP 80-pin pinout
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PI3
PI2
PI1
PI0
PG4
PG3
PG2
PG1/CAN_RX
PG0/CAN_TX
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PC0/ADC_ETR
PE5/SPI_NSS
AIN11/PF3
VREF+
VDDA
VSSA
VREFAIN10/PF0
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
TIM1_ETR/PH4
TIM1_CH3N/PH5
TIM1_CH2N/PH6
TIM1_CH1N/PH7
AIN8/PE7
AIN9/PE6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/ (HS) PA4
UART1_TX/ (HS) PA5
UART1_CK/ (HS) PA6
(HS) PH0
(HS) PH1
PH2
PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4.
CAN_RX and CAN_TX is available on STM8S208xx devices only.
DocID14733 Rev 13
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116
Pinouts and pin description
STM8S207xx STM8S208xx
PD7/TLI
PD6/UART3_RX
PD5/UART3_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD3 (HS)/TIM2_CH2[ADC_ETR]
PD2 (HS)/TIM3_CH1[TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
PE3/TIM1_BKIN
PE4
PG7
PG6
PG5
Figure 4. LQFP 64-pin pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PI0
PG4
PG3
PG2
PG1/CAN_RX
PG0/CAN_TX
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
AIN11/PF3
VREF+
VDDA
VSSA
VREFAIN10/PF0
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
AIN8/PE7
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/ (HS) PA4
UART1_TX/ (HS) PA5
UART1_CK/ (HS) PA6
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
24/117
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4.
CAN_RX and CAN_TX is available on STM8S208xx devices only.
DocID14733 Rev 13
STM8S207xx STM8S208xx
Pinouts and pin description
PD7/TLI
PD6/UART3_RX
PD5/UART3_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
PE3/TIM1_BKIN
Figure 5. LQFP 48-pin pinout
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 2223 24
PG1/CAN_RX
PG0/CAN_TX
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
VDDA
VSSA
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR/AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
AIN8/PE7
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/(HS) PA4
UART1_TX/(HS) PA5
UART1_CK/(HS) PA6
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4.
CAN_RX and CAN_TX is available on STM8S208xx devices only.
DocID14733 Rev 13
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116
Pinouts and pin description
STM8S207xx STM8S208xx
PD7/TLI [TIM1_CH4]
PD6/UART3_RX
PD5/UART3_TX
PD4 (HS)/TIM2_CH1[BEEP]
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
Figure 6. LQFP 44-pin pinout
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
PG1/CAN_RX
PG0/CAN_TX
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
VDDA
VSSA
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
(TIM1_CH1N] AIN0/PB0
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
UART1_RX
UART1_TX/
UART1_CK
26/117
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4.
CAN_RX and CAN_TX is available on STM8S208xx devices only.
DocID14733 Rev 13
STM8S207xx STM8S208xx
Pinouts and pin description
PD7/TLI
PD6/UART3_RX
PD5/UART3_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1[TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
Figure 7. LQFP 32-pin pinout
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 1516
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
VDDA
VSSA
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
VDDIO
AIN12/PF4
1.
(HS) high sink capability.
2.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
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116
Pinouts and pin description
STM8S207xx STM8S208xx
Table 5. Legend/abbreviations for pinout table
Type
I= Input, O = Output, S = Power supply
Level
Input
CM = CMOS
Output
HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input
configuration
Output
Reset state
float = floating, wpu = weak pull-up
T = True open drain, OD = Open drain, PP = Push pull
Bold X (pin state after internal reset release)
Unless otherwise specified, the pin state is the same during the reset phase and
after the internal reset release.
Table 6. Pin description
Main function
(after reset)
1 NRST
I/O
X
2
2
2
2
2 PA1/OSCIN
I/O X
X
3
3
3
3
3 PA2/OSCOUT
I/O X
X
4
4
4
4
- VSSIO_1
S
I/O ground
5
5
5
5
4 VSS
S
Digital ground
6
6
6
6
5 VCAP
S
1.8 V regulator capacitor
7
7
7
7
6 VDD
S
Digital power supply
8
8
8
8
7 VDDIO_1
S
I/O power supply
9
9
9
-
- PA3/TIM2_CH3
I/O X
X
X
O1 X
X Port A3
Timer 2 channel3
10 10 10
9
PA4/UART1_RX
- (1)
I/O X
X
X HS O3 X
X Port A4
UART1
receive
11 11 11 10
- PA5/UART1_TX
I/O X
X
X HS O3 X
X Port A5
UART1
transmit
28/117
PP
1
OD
LQFP32
1
Speed
LQFP44
1
wpu
LQFP48
1
Pin name
floating
LQFP64
Default
alternate
function
LQFP80
High sink
Output
Ext. interrupt
Input
Type
Pin number
Alternate
function
after remap
[option bit]
Reset
X
O1 X
X Port A1
Resonator/
crystal in
O1 X
X Port A2
Resonator/
crystal out
DocID14733 Rev 13
TIM3_CH1
[AFR1]
STM8S207xx STM8S208xx
Pinouts and pin description
Table 6. Pin description (continued)
Main function
(after reset)
Output
I/O X
X
HS O3 X
X Port H0
14
-
-
-
- PH1
I/O X
X
HS O3 X
X Port H1
15
-
-
-
- PH2
I/O X
X
O1 X
X Port H2
16
-
-
-
- PH3
I/O X
X
O1 X
X Port H3
17 13
-
-
- PF7/AIN15
I/O X
X
O1 X
X
Port F7
Analog
input 15
18 14
-
-
- PF6/AIN14
I/O X
X
O1 X
X
Port F6
Analog
input 14
19 15
-
-
- PF5/AIN13
I/O X
X
O1 X
X
Port F5
Analog
input 13
20 16
-
-
8 PF4/AIN12
I/O X
X
O1 X
X
Port F4
Analog
input 12
21 17
-
-
- PF3/AIN11
I/O X
X
O1 X
X
Port F3
Analog
input 11
22 18
-
-
- VREF+
S
ADC positive reference
voltage
9 VDDA
S
Analog power supply
24 20 14 13 10 VSSA
S
Analog ground
25 21
-
-
- VREF-
S
ADC negative reference
voltage
26 22
-
-
- PF0/AIN10
I/O X
X
27 23 15 14
- PB7/AIN7
I/O X
X
28 24 16 15
- PB6/AIN6
I/O X
29 25 17 16 11 PB5/AIN5
30 26 18 17 12 PB4/AIN4
23 19 13 12
PP
- PH0
OD
-
Speed
-
High sink
-
floating
13
Pin name
Type
X HS O3 X
LQFP32
X
LQFP44
I/O X
LQFP48
- PA6/UART1_CK
LQFP64
12 12 12 11
LQFP80
Ext. interrupt
Input
wpu
Pin number
Default
alternate
function
Alternate
function
after remap
[option bit]
UART1
X Port A6 synchronous
clock
O1 X
X
Port F0
Analog
input 10
X
O1 X
X Port B7
Analog
input 7
X
X
O1 X
X Port B6
Analog
input 6
I/O X
X
X
O1 X
X Port B5
Analog
input 5
I2C_SDA
[AFR6]
I/O X
X
X
O1 X
X Port B4
Analog
input 4
I2C_SCL
[AFR6]
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116
Pinouts and pin description
STM8S207xx STM8S208xx
Table 6. Pin description (continued)
Main function
(after reset)
Output
Alternate
function
after remap
[option bit]
X
X
O1 X
X Port B2
Analog
input 2
TIM1_
CH3N
[AFR5]
33 29 21 20 15 PB1/AIN1
I/O X
X
X
O1 X
X Port B1
Analog
input 1
TIM1_
CH2N
[AFR5]
34 30 22 21 16 PB0/AIN0
I/O X
X
X
O1 X
X Port B0
Analog
input 0
TIM1_
CH1N
[AFR5]
35
-
-
-
- PH4/TIM1_ETR
I/O X
X
O1 X
X Port H4
Timer 1 trigger input
36
-
-
-
- PH5/ TIM1_CH3N I/O X
X
O1 X
Timer 1 X Port H5 inverted
channel 3
37
-
-
-
- PH6/ TIM1_CH2N I/O X
X
O1 X
Timer 1 X Port H6 inverted
channel 2
38
-
-
-
- PH7/ TIM1_CH1N I/O X
X
O1 X
Timer 1 X Port H7 inverted
channel 2
-
- PE7/AIN8
I/O X
X
X
O1 X
X Port E7 Analog input 8
- PE6/AIN9
I/O X
X
X
O1 X
X Port E6 Analog input 9
41 33 25 23 17 PE5/SPI_NSS
I/O X
X
X
O1 X
SPI
X Port E5 master/slave
select
42
- PC0/ADC_ETR
I/O X
X
X
O1 X
X Port C0
ADC trigger
input
43 34 26 24 18 PC1/TIM1_CH1
I/O X
X
X HS O3 X
X Port C1
Timer 1 channel 1
44 35 27 25 19 PC2/TIM1_CH2
I/O X
X
X HS O3 X
X Port C2
Timer 1channel 2
45 36 28 26 20 PC3/TIM1_CH3
I/O X
X
X HS O3 X
X Port C3
Timer 1 channel 3
39 31 23
40 32 24 22
-
30/117
-
-
DocID14733 Rev 13
PP
I/O X
OD
32 28 20 19 14 PB2/AIN2
Speed
TIM1_ETR
[AFR5]
High sink
Analog
input 3
floating
X Port B3
Pin name
Type
O1 X
LQFP32
X
LQFP44
X
LQFP48
I/O X
LQFP64
31 27 19 18 13 PB3/AIN3
LQFP80
Ext. interrupt
Input
wpu
Pin number
Default
alternate
function
STM8S207xx STM8S208xx
Pinouts and pin description
Table 6. Pin description (continued)
21 PC4/TIM1_CH4
47 38 30 27 22 PC5/SPI_SCK
Main function
(after reset)
X
X HS O3 X
X Port C5 SPI clock
PP
I/O X
OD
X Port C4
Speed
X HS O3 X
High sink
X
floating
I/O X
Type
LQFP32
Pin name
Output
Ext. interrupt
-
Input
wpu
46 37 29
LQFP44
LQFP48
LQFP64
LQFP80
Pin number
Default
alternate
function
Timer 1 channel 4
48 39 31 28
- VSSIO_2
S
I/O ground
49 40 32 29
- VDDIO_2
S
I/O power supply
50 41 33 30 23 PC6/SPI_MOSI
I/O X
X
X HS O3 X
SPI master
X Port C6 out/
slave in
51 42 34 31 24 PC7/SPI_MISO
I/O X
X
X HS O3 X
X Port C7
SPI master in/
slave out
52 43 35 32
- PG0/CAN_TX(2)
I/O X
X
O1 X
X Port G0
beCAN
transmit
53 44 36 33
- PG1/CAN_RX(2)
I/O X
X
O1 X
X Port G1
beCAN
receive
54 45
-
-
- PG2
I/O X
X
O1 X
X Port G2
55 46
-
-
- PG3
I/O X
X
O1 X
X Port G3
56 47
-
-
- PG4
I/O X
X
O1 X
X Port G4
57 48
-
-
- PI0
I/O X
X
O1 X
X
Port I0
58
-
-
-
- PI1
I/O X
X
O1 X
X
Port I1
59
-
-
-
- PI2
I/O X
X
O1 X
X
Port I2
60
-
-
-
- PI3
I/O X
X
O1 X
X
Port I3
61
-
-
-
- PI4
I/O X
X
O1 X
X
Port I4
62
-
-
-
- PI5
I/O X
X
O1 X
X
Port I5
63 49
-
-
- PG5
I/O X
X
O1 X
X Port G5
64 50
-
-
- PG6
I/O X
X
O1 X
X Port G6
65 51
-
-
- PG7
I/O X
X
O1 X
X Port G7
66 52
-
-
- PE4
I/O X
X
X
O1 X
X Port E4
-
- PE3/TIM1_BKIN
I/O X
X
X
O1 X
X Port E3
- PE2/I2C_SDA
I/O X
X
O1 T(3)
67 53 37
68 54 38 34
DocID14733 Rev 13
Alternate
function
after remap
[option bit]
Timer 1 -
break input
Port E2 I2C data
31/117
116
Pinouts and pin description
STM8S207xx STM8S208xx
Table 6. Pin description (continued)
69 55 39 35
- PE1/I2C_SCL
I/O X
70 56 40 36
- PE0/CLK_CCO
I/O X
X
X HS O3 X
71
-
-
-
- PI6
I/O X
X
O1 X
X
Port I6
72
-
-
-
- PI7
I/O X
X
O1 X
X
Port I7
X
O1 T(3)
Main function
(after reset)
PP
OD
Speed
High sink
Output
Ext. interrupt
wpu
floating
Pin name
Type
Input
LQFP32
LQFP44
LQFP48
LQFP64
LQFP80
Pin number
Default
alternate
function
Alternate
function
after remap
[option bit]
Port E1 I2C clock
X Port E0
Configurable
clock output
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
73 57 41 37 25 PD0/TIM3_CH2
I/O X
X
X HS O3 X
Timer 3 X Port D0
channel 2
74 58 42 38 26 PD1/SWIM(4)
I/O X
X
X HS O4 X
X Port D1
SWIM data
interface
75 59 43 39 27 PD2/TIM3_CH1
I/O X
X
X HS O3 X
X Port D2
Timer 3 channel 1
TIM2_CH3
[AFR1]
76 60 44 40 28 PD3/TIM2_CH2
I/O X
X
X HS O3 X
X Port D3
Timer 2 channel 2
ADC_ETR
[AFR0]
PD4/TIM2_CH1/B
I/O X
EEP
X
X HS O3 X
X Port D4
Timer 2 channel 1
BEEP output
[AFR7]
I/O X
X
X
O1 X
X Port D5
UART3 data
transmit
I/O X
X
X
O1 X
X Port D6
UART3 data
receive
I/O X
X
X
O1 X
X Port D7
Top level
interrupt
77 61 45 41 29
78 62 46 42 30 PD5/ UART3_TX
79 63 47 43 31
PD6/
UART3_RX(1)
80 64 48 44 32 PD7/TLI
TIM1_CH4
[AFR4](5)
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as part
of the bootloader activation process and returned to the floating state before a return from the bootloader.
2. The beCAN interface is available on STM8S208xx devices only
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
5. Available in 44-pin package only. On other packages, the AFR4 bit is reserved and must be kept at 0.
5.2
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
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DocID14733 Rev 13
STM8S207xx STM8S208xx
Pinouts and pin description
remap) option bits. Refer to Section 8: Option bytes on page 47. When the remapping
option is active, the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
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116
Memory and register map
STM8S207xx STM8S208xx
6
Memory and register map
6.1
Memory map
Figure 8. Memory map
0x00 0000
0x00 17FF
0x00 1800
RAM
(up to 6 Kbytes)
1024 bytes stack
Reserved
0x00 3FFF
0x00 4000
Up to 2 Kbytes data EEPROM
0x00 47FF
0x00 4800
0x00 487F
0x00 4900
Option bytes
Reserved
0x00 4FFF
0x00 5000
0x00 57FF
0x00 5800
GPIO and peripheral registers
(see Table 8 and Table 9)
Reserved
0x00 5FFF
0x00 6000
2 Kbytes boot ROM
0x00 67FF
0x00 6800
Reserved
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
CPU/SWIM/debug/ITC
registers (see Table 10)
32 interrupt vectors
Flash program memory
(64 to 128 Kbytes)
0x02 7FFF
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DocID14733 Rev 13
STM8S207xx STM8S208xx
Memory and register map
Table 7 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Table 7. Flash, Data EEPROM and RAM boundary addresses
Memory area
Flash program memory
RAM
Data EEPROM
6.2
Size (bytes)
Start address
End address
128 K
0x00 8000
0x02 7FFF
64 K
0x00 8000
0x01 7FFF
32 K
0x00 8000
0x00 FFFF
6K
0x00 0000
0x00 17FF
4K
0x00 0000
0x00 1000
2K
0x00 0000
0x00 07FF
2048
0x00 4000
0x00 47FF
1536
0x00 4000
0x00 45FF
1024
0x00 4000
0x00 43FF
Register map
Table 8. I/O port hardware register map
Register label
Register name
Reset
status
0x00 5000
PA_ODR
Port A data output latch register
0x00
0x00 5001
PA_IDR
Port A input pin value register
0x00
PA_DDR
Port A data direction register
0x00
0x00 5003
PA_CR1
Port A control register 1
0x00
0x00 5004
PA_CR2
Port A control register 2
0x00
0x00 5005
PB_ODR
Port B data output latch register
0x00
0x00 5006
PB_IDR
Port B input pin value register
0x00
PB_DDR
Port B data direction register
0x00
0x00 5008
PB_CR1
Port B control register 1
0x00
0x00 5009
PB_CR2
Port B control register 2
0x00
0x00 500A
PC_ODR
Port C data output latch register
0x00
0x00 500B
PB_IDR
Port C input pin value register
0x00
PC_DDR
Port C data direction register
0x00
0x00 500D
PC_CR1
Port C control register 1
0x00
0x00 500E
PC_CR2
Port C control register 2
0x00
Address
0x00 5002
0x00 5007
0x00 500C
Block
Port A
Port B
Port C
DocID14733 Rev 13
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116
Memory and register map
STM8S207xx STM8S208xx
Table 8. I/O port hardware register map (continued)
Register label
Register name
Reset
status
0x00 500F
PD_ODR
Port D data output latch register
0x00
0x00 5010
PD_IDR
Port D input pin value register
0x00
PD_DDR
Port D data direction register
0x00
0x00 5012
PD_CR1
Port D control register 1
0x02
0x00 5013
PD_CR2
Port D control register 2
0x00
0x00 5014
PE_ODR
Port E data output latch register
0x00
0x00 5015
PE_IDR
Port E input pin value register
0x00
PE_DDR
Port E data direction register
0x00
0x00 5017
PE_CR1
Port E control register 1
0x00
0x00 5018
PE_CR2
Port E control register 2
0x00
0x00 5019
PF_ODR
Port F data output latch register
0x00
0x00 501A
PF_IDR
Port F input pin value register
0x00
PF_DDR
Port F data direction register
0x00
0x00 501C
PF_CR1
Port F control register 1
0x00
0x00 501D
PF_CR2
Port F control register 2
0x00
0x00 501E
PG_ODR
Port G data output latch register
0x00
0x00 501F
PG_IDR
Port G input pin value register
0x00
PG_DDR
Port G data direction register
0x00
0x00 5021
PG_CR1
Port G control register 1
0x00
0x00 5022
PG_CR2
Port G control register 2
0x00
0x00 5023
PH_ODR
Port H data output latch register
0x00
0x00 5024
PH_IDR
Port H input pin value register
0x00
PH_DDR
Port H data direction register
0x00
0x00 5026
PH_CR1
Port H control register 1
0x00
0x00 5027
PH_CR2
Port H control register 2
0x00
0x00 5028
PI_ODR
Port I data output latch register
0x00
0x00 5029
PI_IDR
Port I input pin value register
0x00
PI_DDR
Port I data direction register
0x00
0x00 502B
PI_CR1
Port I control register 1
0x00
0x00 502C
PI_CR2
Port I control register 2
0x00
Address
0x00 5011
0x00 5016
0x00 501B
0x00 5020
0x00 5025
0x00 502A
36/117
Block
Port D
Port E
Port F
Port G
Port H
Port I
DocID14733 Rev 13
STM8S207xx STM8S208xx
Memory and register map
Table 9. General hardware register map
Address
Block
Register label
0x00 5050 to
0x00 5059
Register name
Reset
status
Reserved area (10 bytes)
0x00 505A
FLASH_CR1
Flash control register 1
0x00
0x00 505B
FLASH_CR2
Flash control register 2
0x00
0x00 505C
FLASH_NCR2
Flash complementary control register 2
0xFF
FLASH _FPR
Flash protection register
0x00
0x00 505E
FLASH _NFPR
Flash complementary protection register
0xFF
0x00 505F
FLASH _IAPSR
Flash in-application programming status
register
0x00
0x00 505D
Flash
0x00 5060 to
0x00 5061
0x00 5062
Reserved area (2 bytes)
Flash
FLASH _PUKR
0x00 5063
0x00 5064
Flash Program memory unprotection
register
0x00
Reserved area (1 byte)
Flash
FLASH _DUKR
0x00 5065 to
0x00 509F
Data EEPROM unprotection register
0x00
Reserved area (59 bytes)
0x00 50A0
EXTI_CR1
External interrupt control register 1
0x00
EXTI_CR2
External interrupt control register 2
0x00
ITC
0x00 50A1
0x00 50A2 to
0x00 50B2
0x00 50B3
Reserved area (17 bytes)
RST
RST_SR
0x00 50B4 to
0x00 50BF
Reset status register
0xXX(1)
Reserved area (12 bytes)
0x00 50C0
CLK_ICKR
Internal clock control register
0x01
CLK_ECKR
External clock control register
0x00
CLK
0x00 50C1
0x00 50C2
Reserved area (1 byte)
0x00 50C3
CLK_CMSR
Clock master status register
0xE1
0x00 50C4
CLK_SWR
Clock master switch register
0xE1
0x00 50C5
CLK_SWCR
Clock switch control register
0xXX
0x00 50C6
CLK_CKDIVR
Clock divider register
0x18
CLK_PCKENR1
Peripheral clock gating register 1
0xFF
0x00 50C8
CLK_CSSR
Clock security system register
0x00
0x00 50C9
CLK_CCOR
Configurable clock control register
0x00
0x00 50CA
CLK_PCKENR2
Peripheral clock gating register 2
0xFF
0x00 50CB
CLK_CANCCR
CAN clock control register
0x00
0x00 50C7
CLK
DocID14733 Rev 13
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116
Memory and register map
STM8S207xx STM8S208xx
Table 9. General hardware register map (continued)
Address
Block
0x00 50CC
Register label
Register name
Reset
status
CLK_HSITRIMR
HSI clock calibration trimming register
0x00
CLK_SWIMCCR
SWIM clock control register
0bXXXX
XXX0
CLK
0x00 50CD
0x00 50CE to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1
WWDG_CR
WWDG control register
0x7F
WWDG_WR
WWDR window register
0x7F
WWDG
0x00 50D2
0x00 50D3 to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
IWDG
0x00 50E2
IWDG_KR
IWDG key register
0xXX(2)
IWDG_PR
IWDG prescaler register
0x00
IWDG_RLR
IWDG reload register
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
AWU
0x00 50F2
0x00 50F3
BEEP
AWU_CSR1
AWU control/status register 1
0x00
AWU_APR
AWU asynchronous prescaler buffer register
0x3F
AWU_TBR
AWU timebase selection register
0x00
BEEP_CSR
BEEP control/status register
0x1F
0x00 50F4 to
0x00 50FF
Reserved area (12 bytes)
0x00 5200
SPI_CR1
SPI control register 1
0x00
0x00 5201
SPI_CR2
SPI control register 2
0x00
0x00 5202
SPI_ICR
SPI interrupt control register
0x00
SPI_SR
SPI status register
0x02
0x00 5204
SPI_DR
SPI data register
0x00
0x00 5205
SPI_CRCPR
SPI CRC polynomial register
0x07
0x00 5206
SPI_RXCRCR
SPI Rx CRC register
0xFF
0x00 5207
SPI_TXCRCR
SPI Tx CRC register
0xFF
0x00 5203
SPI
0x00 5208 to
0x00 520F
Reserved area (8 bytes)
0x00 5211
0x00 5212
I2C control register 1
I2C_CR1
0x00 5210
I2C_CR2
I2C
I
2C
I2C
I2C_FREQR
2C
0x00
control register 2
0x00
frequency register
0x00
0x00 5213
I2C_OARL
I
own address register low
0x00
0x00 5214
I2C_OARH
I2C own address register high
0x00
0x00 5215
38/117
Reserved
DocID14733 Rev 13
STM8S207xx STM8S208xx
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
0x00 5216
Register label
Register name
Reset
status
I2C_DR
I2C data register
0x00
2
0x00 5217
I2C_SR1
I C status register 1
0x00
0x00 5218
I2C_SR2
I2C status register 2
0x00
I2C_SR3
I2
0x00
0x00 5219
I2C
0x00 521A
I2C_ITR
C status register 3
2
I C interrupt control register
0x00
2
0x00 521B
I2C_CCRL
I C clock control register low
0x00
0x00 521C
I2C_CCRH
I2C clock control register high
0x00
0x00 521D
I2C_TRISER
0x00 521E to
0x00 522F
I
2C
TRISE register
0x02
Reserved area (18 bytes)
0x00 5230
UART1_SR
UART1 status register
0xC0
0x00 5231
UART1_DR
UART1 data register
0xXX
0x00 5232
UART1_BRR1
UART1 baud rate register 1
0x00
0x00 5233
UART1_BRR2
UART1 baud rate register 2
0x00
0x00 5234
UART1_CR1
UART1 control register 1
0x00
UART1_CR2
UART1 control register 2
0x00
0x00 5236
UART1_CR3
UART1 control register 3
0x00
0x00 5237
UART1_CR4
UART1 control register 4
0x00
0x00 5238
UART1_CR5
UART1 control register 5
0x00
0x00 5239
UART1_GTR
UART1 guard time register
0x00
0x00 523A
UART1_PSCR
UART1 prescaler register
0x00
0x00 5235
UART1
0x00 523B to
0x00 523F
Reserved area (5 bytes)
0x00 5240
UART3_SR
UART3 status register
C0h
0x00 5241
UART3_DR
UART3 data register
0xXX
0x00 5242
UART3_BRR1
UART3 baud rate register 1
0x00
0x00 5243
UART3_BRR2
UART3 baud rate register 2
0x00
UART3_CR1
UART3 control register 1
0x00
0x00 5245
UART3_CR2
UART3 control register 2
0x00
0x00 5246
UART3_CR3
UART3 control register 3
0x00
0x00 5247
UART3_CR4
UART3 control register 4
0x00
0x00 5244
UART3
0x00 5248
0x00 5249
0x00 524A to
0x00 524F
Reserved
UART3_CR6
UART3 control register 6
0x00
Reserved area (6 bytes)
DocID14733 Rev 13
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116
Memory and register map
STM8S207xx STM8S208xx
Table 9. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5250
TIM1_CR1
TIM1 control register 1
0x00
0x00 5251
TIM1_CR2
TIM1 control register 2
0x00
0x00 5252
TIM1_SMCR
TIM1 slave mode control register
0x00
0x00 5253
TIM1_ETR
TIM1 external trigger register
0x00
0x00 5254
TIM1_IER
TIM1 Interrupt enable register
0x00
0x00 5255
TIM1_SR1
TIM1 status register 1
0x00
0x00 5256
TIM1_SR2
TIM1 status register 2
0x00
0x00 5257
TIM1_EGR
TIM1 event generation register
0x00
0x00 5258
TIM1_CCMR1
TIM1 capture/compare mode register 1
0x00
0x00 5259
TIM1_CCMR2
TIM1 capture/compare mode register 2
0x00
0x00 525A
TIM1_CCMR3
TIM1 capture/compare mode register 3
0x00
0x00 525B
TIM1_CCMR4
TIM1 capture/compare mode register 4
0x00
0x00 525C
TIM1_CCER1
TIM1 capture/compare enable register 1
0x00
0x00 525D
TIM1_CCER2
TIM1 capture/compare enable register 2
0x00
0x00 525E
TIM1_CNTRH
TIM1 counter high
0x00
TIM1_CNTRL
TIM1 counter low
0x00
0x00 5260
TIM1_PSCRH
TIM1 prescaler register high
0x00
0x00 5261
TIM1_PSCRL
TIM1 prescaler register low
0x00
0x00 5262
TIM1_ARRH
TIM1 auto-reload register high
0xFF
0x00 5263
TIM1_ARRL
TIM1 auto-reload register low
0xFF
0x00 5264
TIM1_RCR
TIM1 repetition counter register
0x00
0x00 5265
TIM1_CCR1H
TIM1 capture/compare register 1 high
0x00
0x00 5266
TIM1_CCR1L
TIM1 capture/compare register 1 low
0x00
0x00 5267
TIM1_CCR2H
TIM1 capture/compare register 2 high
0x00
0x00 5268
TIM1_CCR2L
TIM1 capture/compare register 2 low
0x00
0x00 5269
TIM1_CCR3H
TIM1 capture/compare register 3 high
0x00
0x00 526A
TIM1_CCR3L
TIM1 capture/compare register 3 low
0x00
0x00 526B
TIM1_CCR4H
TIM1 capture/compare register 4 high
0x00
0x00 526C
TIM1_CCR4L
TIM1 capture/compare register 4 low
0x00
0x00 526D
TIM1_BKR
TIM1 break register
0x00
0x00 526E
TIM1_DTR
TIM1 dead-time register
0x00
0x00 526F
TIM1_OISR
TIM1 output idle state register
0x00
Address
Block
0x00 525F
TIM1
0x00 5270 to
0x00 52FF
40/117
Reserved area (147 bytes)
DocID14733 Rev 13
STM8S207xx STM8S208xx
Memory and register map
Table 9. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5300
TIM2_CR1
TIM2 control register 1
0x00
0x00 5301
TIM2_IER
TIM2 interrupt enable register
0x00
0x00 5302
TIM2_SR1
TIM2 status register 1
0x00
0x00 5303
TIM2_SR2
TIM2 status register 2
0x00
0x00 5304
TIM2_EGR
TIM2 event generation register
0x00
0x00 5305
TIM2_CCMR1
TIM2 capture/compare mode register 1
0x00
0x00 5306
TIM2_CCMR2
TIM2 capture/compare mode register 2
0x00
0x00 5307
TIM2_CCMR3
TIM2 capture/compare mode register 3
0x00
0x00 5308
TIM2_CCER1
TIM2 capture/compare enable register 1
0x00
0x00 5309
TIM2_CCER2
TIM2 capture/compare enable register 2
0x00
TIM2_CNTRH
TIM2 counter high
0x00
0x00 530B
TIM2_CNTRL
TIM2 counter low
0x00
00 530C0x
TIM2_PSCR
TIM2 prescaler register
0x00
0x00 530D
TIM2_ARRH
TIM2 auto-reload register high
0xFF
0x00 530E
TIM2_ARRL
TIM2 auto-reload register low
0xFF
0x00 530F
TIM2_CCR1H
TIM2 capture/compare register 1 high
0x00
0x00 5310
TIM2_CCR1L
TIM2 capture/compare register 1 low
0x00
0x00 5311
TIM2_CCR2H
TIM2 capture/compare reg. 2 high
0x00
0x00 5312
TIM2_CCR2L
TIM2 capture/compare register 2 low
0x00
0x00 5313
TIM2_CCR3H
TIM2 capture/compare register 3 high
0x00
0x00 5314
TIM2_CCR3L
TIM2 capture/compare register 3 low
0x00
Address
0x00 530A
Block
TIM2
0x00 5315 to
0x00 531F
Reserved area (11 bytes)
0x00 5320
TIM3_CR1
TIM3 control register 1
0x00
0x00 5321
TIM3_IER
TIM3 interrupt enable register
0x00
0x00 5322
TIM3_SR1
TIM3 status register 1
0x00
0x00 5323
TIM3_SR2
TIM3 status register 2
0x00
0x00 5324
TIM3_EGR
TIM3 event generation register
0x00
TIM3_CCMR1
TIM3 capture/compare mode register 1
0x00
0x00 5326
TIM3_CCMR2
TIM3 capture/compare mode register 2
0x00
0x00 5327
TIM3_CCER1
TIM3 capture/compare enable register 1
0x00
0x00 5328
TIM3_CNTRH
TIM3 counter high
0x00
0x00 5329
TIM3_CNTRL
TIM3 counter low
0x00
0x00 532A
TIM3_PSCR
TIM3 prescaler register
0x00
0x00 5325
TIM3
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Memory and register map
STM8S207xx STM8S208xx
Table 9. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 532B
TIM3_ARRH
TIM3 auto-reload register high
0xFF
0x00 532C
TIM3_ARRL
TIM3 auto-reload register low
0xFF
TIM3_CCR1H
TIM3 capture/compare register 1 high
0x00
0x00 532E
TIM3_CCR1L
TIM3 capture/compare register 1 low
0x00
0x00 532F
TIM3_CCR2H
TIM3 capture/compare register 2 high
0x00
0x00 5330
TIM3_CCR2L
TIM3 capture/compare register 2 low
0x00
Address
Block
0x00 532D
TIM3
0x00 5331 to
0x00 533F
Reserved area (15 bytes)
0x00 5340
TIM4_CR1
TIM4 control register 1
0x00
0x00 5341
TIM4_IER
TIM4 interrupt enable register
0x00
0x00 5342
TIM4_SR
TIM4 status register
0x00
TIM4_EGR
TIM4 event generation register
0x00
0x00 5344
TIM4_CNTR
TIM4 counter
0x00
0x00 5345
TIM4_PSCR
TIM4 prescaler register
0x00
0x00 5346
TIM4_ARR
TIM4 auto-reload register
0xFF
0x00 5343
TIM4
0x00 5347 to
0x00 53FF
Reserved area (185 bytes)
0x00 5400
ADC _CSR
ADC control/status register
0x00
0x00 5401
ADC_CR1
ADC configuration register 1
0x00
0x00 5402
ADC_CR2
ADC configuration register 2
0x00
ADC_CR3
ADC configuration register 3
0x00
0x00 5404
ADC_DRH
ADC data register high
0xXX
0x00 5405
ADC_DRL
ADC data register low
0xXX
0x00 5406
ADC_TDRH
ADC Schmitt trigger disable register high
0x00
0x00 5407
ADC_TDRL
ADC Schmitt trigger disable register low
0x00
0x00 5403
ADC2
0x00 5408 to
0x00 541F
Reserved area (24 bytes)
0x00 5420
CAN_MCR
CAN master control register
0x02
0x00 5421
CAN_MSR
CAN master status register
0x02
0x00 5422
CAN_TSR
CAN transmit status register
0x00
CAN_TPR
CAN transmit priority register
0x0C
0x00 5424
CAN_RFR
CAN receive FIFO register
0x00
0x00 5425
CAN_IER
CAN interrupt enable register
0x00
0x00 5426
CAN_DGR
CAN diagnosis register
0x0C
0x00 5427
CAN_FPSR
CAN page selection register
0x00
0x00 5423
beCAN
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Memory and register map
Table 9. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5428
CAN_P0
CAN paged register 0
0xXX(3)
0x00 5429
CAN_P1
CAN paged register 1
0xXX(3)
0x00 542A
CAN_P2
CAN paged register 2
0xXX(3)
0x00 542B
CAN_P3
CAN paged register 3
0xXX(3)
0x00 542C
CAN_P4
CAN paged register 4
0xXX(3)
0x00 542D
CAN_P5
CAN paged register 5
0xXX(3)
0x00 542E
CAN_P6
CAN paged register 6
0xXX(3)
CAN_P7
CAN paged register 7
0xXX(3)
0x00 5430
CAN_P8
CAN paged register 8
0xXX(3)
0x00 5431
CAN_P9
CAN paged register 9
0xXX(3)
0x00 5432
CAN_PA
CAN paged register A
0xXX(3)
0x00 5433
CAN_PB
CAN paged register B
0xXX(3)
0x00 5434
CAN_PC
CAN paged register C
0xXX(3)
0x00 5435
CAN_PD
CAN paged register D
0xXX(3)
0x00 5436
CAN_PE
CAN paged register E
0xXX(3)
0x00 5437
CAN_PF
CAN paged register F
0xXX(3)
Address
Block
0x00 542F
beCAN
0x00 5438 to
0x00 57FF
Reserved area (968 bytes)
1. Depends on the previous reset source.
2. Write only register.
3. If the bootloader is enabled, it is initialized to 0x00.
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Memory and register map
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Table 10. CPU/SWIM/debug module/interrupt controller registers
Register Label
Register Name
Reset
Status
0x00 7F00
A
Accumulator
0x00
0x00 7F01
PCE
Program counter extended
0x00
0x00 7F02
PCH
Program counter high
0x00
0x00 7F03
PCL
Program counter low
0x00
XH
X index register high
0x00
XL
X index register low
0x00
0x00 7F06
YH
Y index register high
0x00
0x00 7F07
YL
Y index register low
0x00
0x00 7F08
SPH
Stack pointer high
0x17(2)
0x00 7F09
SPL
Stack pointer low
0xFF
0x00 7F0A
CCR
Condition code register
0x28
Address
Block
0x00 7F04
0x00 7F05
CPU(1)
0x00 7F0B to
0x00 7F5F
0x00 7F60
Reserved area (85 bytes)
CPU
CFG_GCR
Global configuration register
0x00
0x00 7F70
ITC_SPR1
Interrupt software priority register 1
0xFF
0x00 7F71
ITC_SPR2
Interrupt software priority register 2
0xFF
0x00 7F72
ITC_SPR3
Interrupt software priority register 3
0xFF
ITC_SPR4
Interrupt software priority register 4
0xFF
0x00 7F74
ITC_SPR5
Interrupt software priority register 5
0xFF
0x00 7F75
ITC_SPR6
Interrupt software priority register 6
0xFF
0x00 7F76
ITC_SPR7
Interrupt software priority register 7
0xFF
0x00 7F77
ITC_SPR8
Interrupt software priority register 8
0xFF
0x00 7F73
ITC
0x00 7F78 to
0x00 7F79
0x00 7F80
Reserved area (2 bytes)
SWIM
SWIM_CSR
0x00 7F81 to
0x00 7F8F
SWIM control status register
0x00
Reserved area (15 bytes)
0x00 7F90
DM_BK1RE
DM breakpoint 1 register extended byte
0xFF
0x00 7F91
DM_BK1RH
DM breakpoint 1 register high byte
0xFF
0x00 7F92
DM_BK1RL
DM breakpoint 1 register low byte
0xFF
DM_BK2RE
DM breakpoint 2 register extended byte
0xFF
0x00 7F94
DM_BK2RH
DM breakpoint 2 register high byte
0xFF
0x00 7F95
DM_BK2RL
DM breakpoint 2 register low byte
0xFF
0x00 7F96
DM_CR1
DM debug module control register 1
0x00
0x00 7F97
DM_CR2
DM debug module control register 2
0x00
0x00 7F93
DM
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Memory and register map
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Address
Block
Register Label
Register Name
Reset
Status
DM_CSR1
DM debug module control/status register 1
0x10
DM_CSR2
DM debug module control/status register 2
0x00
DM_ENFCTR
DM enable function register
0xFF
0x00 7F98
0x00 7F99
0x00 7F9A
DM
0x00 7F9B to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
2. Product dependent value, see Figure 8: Memory map.
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Interrupt vector mapping
7
STM8S207xx STM8S208xx
Interrupt vector mapping
Table 11. Interrupt mapping
IRQ
no.
Source
block
RESET
TRAP
Wakeup from
Wakeup from
Halt mode
Active-halt mode
Description
Reset
Vector address
Yes
Yes
0x00 8000
Software interrupt
-
-
0x00 8004
External top level interrupt
-
-
0x00 8008
Yes
0x00 800C
-
0x00 8010
Yes(1)
0x00 8014
0
TLI
1
AWU
Auto wake up from halt
-
2
CLK
Clock controller
(1)
3
EXTI0
Port A external interrupts
Yes
4
EXTI1
Port B external interrupts
Yes
Yes
0x00 8018
5
EXTI2
Port C external interrupts
Yes
Yes
0x00 801C
6
EXTI3
Port D external interrupts
Yes
Yes
0x00 8020
7
EXTI4
Port E external interrupts
Yes
Yes
0x00 8024
8
beCAN
beCAN RX interrupt
Yes
Yes
0x00 8028
9
beCAN
beCAN TX/ER/SC interrupt
-
-
0x00 802C
10
SPI
Yes
Yes
0x00 8030
11
TIM1
TIM1 update/overflow/underflow/
trigger/break
-
-
0x00 8034
12
TIM1
TIM1 capture/compare
-
-
0x00 8038
13
TIM2
TIM2 update /overflow
-
-
0x00 803C
14
TIM2
TIM2 capture/compare
-
-
0x00 8040
15
TIM3
Update/overflow
-
-
0x00 8044
16
TIM3
Capture/compare
-
-
0x00 8048
17
UART1
Tx complete
-
-
0x00 804C
18
UART1
Receive register DATA FULL
-
-
0x00 8050
19
I2C
I2C interrupt
Yes
Yes
0x00 8054
20
UART3
Tx complete
-
-
0x00 8058
21
UART3
Receive register DATA FULL
-
-
0x00 805C
22
ADC2
ADC2 end of conversion
-
-
0x00 8060
23
TIM4
TIM4 update/overflow
-
-
0x00 8064
24
Flash
EOP/WR_PG_DIS
-
-
0x00 8068
End of transfer
0x00 806C to
0x00 807C
Reserved
1. Except PA1
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8
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12. Option bytes
Addr.
4800h
4801h
4802h
4803h
4804h
Option
name
Read-out
protection
(ROP)
User boot
code (UBC)
Alternate
function
remapping
(AFR)
Option
byte no.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
OPT0
ROP[7:0]
00h
OPT1
UBC[7:0]
00h
NUBC[7:0]
FFh
NOPT1
OPT2
NOPT2
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
00h
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
FFh
OPT3
Reserved
LSI
_EN
IWDG
_HW
WWDG
_HW
WWDG
_HALT
00h
4806h
NOPT3
Reserved
NLSI
_EN
NIWDG
_HW
NWWDG
_HW
NWWDG
_HALT
FFh
4807h
OPT4
Reserved
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
00h
NOPT4
Reserved
NEXT
CLK
NCKAWU
SEL
NPR
SC1
NPR
SC0
FFh
4805h
Watchdog
option
Clock option
4808h
4809h
480Ah
HSE clock
startup
480Bh
OPT5
HSECNT[7:0]
00h
NHSECNT[7:0]
FFh
OPT6
Reserved
00h
NOPT6
Reserved
FFh
NOPT5
Reserved
480Ch
480Dh
480Eh
Flash wait
states
487Eh
OPT7
Reserved
Wait state
00h
NOPT7
Reserved
Nwait state
FFh
OPTBL
BL[7:0]
00h
NBL[7:0]
FFh
Bootloader
487Fh
NOPTBL
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Option bytes
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Table 13. Option byte description
Option byte no.
48/117
Description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT1
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Pages 0 to 1 defined as UBC, memory write-protected
0x02: Pages 0 to 3 defined as UBC, memory write-protected
0x03: Pages 0 to 4 defined as UBC, memory write-protected
...
0xFE: Pages 0 to 255 defined as UBC, memory write-protected
0xFF: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM write protection for more details.
OPT2
AFR7Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
AFR6 Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL
AFR5 Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N
AFR4 Alternate function remapping option 4
0: Port D7 alternate function = TLI
1: Port D7 alternate function = TIM1_CH4
AFR3 Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
AFR2 Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1 Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3
AFR0 Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR
DocID14733 Rev 13
STM8S207xx STM8S208xx
Option bytes
Table 13. Option byte description (continued)
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
OPT4
CKAWUSEL: Auto wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for AWU
PRSC[1:0] AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
OPT5
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilization time.
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
OPT6
Reserved
OPT7
WAITSTATE Wait state configuration
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
1 wait state is required if fCPU > 16 MHz.
0: No wait state
1: 1 wait state
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Option bytes
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Table 13. Option byte description (continued)
Option byte no.
OPTBL
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Description
BL[7:0] Bootloader option byte
For STM8S products, this option is checked by the boot ROM code
after reset. Depending on the content of addresses 0x487E, 0x487F,
and 0x8000 (reset vector), the CPU jumps to the bootloader or to
the reset vector. Refer to the UM0560 (STM8L/S bootloader manual)
for more details.
For STM8L products, the bootloader option bytes are on addresses
0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control
whether the bootloader is active or not. For more details, refer to the
UM0560 (STM8L/S bootloader manual) for more details.
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9
Unique ID
Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated
using a custom algorithm.
The unique device identifier is ideally suited:
For use as serial numbers
For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory.
To activate secure boot processes
Table 14. Unique ID registers (96 bits)
Address
0x48CD
0x48CE
0x48CF
Content
description
Unique ID bits
7
6
5
0x48D0
0x48D1
Wafer number
3
1
0
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
0x48D2
U_ID[47:40]
0x48D3
U_ID[55:48]
0x48D4
U_ID[63:56]
0x48D5
2
U_ID[7:0]
X co-ordinate on the
wafer
Y co-ordinate on the
wafer
4
U_ID[71:64]
Lot number
0x48D6
U_ID[79:72]
0x48D7
U_ID[87:80]
0x48D8
U_ID[95:88]
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Electrical characteristics
STM8S207xx STM8S208xx
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 ).
10.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 ).
10.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
10.1.4
Typical current consumption
For typical current consumption measurements, VDD, VDDIO and VDDA are connected
together in the configuration shown in Figure 9.
Figure 9. Supply current measurement conditions
5 V or 3.3 V
A
VDD
VDDA
VDDIO
VSS
VSSA
VSSIO
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Electrical characteristics
10.1.5
Pin loading conditions
10.1.6
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Figure 10. Pin loading conditions
STM8 pin
50 pF
10.1.7
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 11. Pin input voltage
STM8 pin
VIN
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Electrical characteristics
10.2
STM8S207xx STM8S208xx
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 15. Voltage characteristics
Symbol
VDDx - VSS
Ratings
Min
Max
-0.3
6.5
Input voltage on true open drain pins (PE1, PE2)
VSS - 0.3
6.5
Input voltage on any other pin(2)
VSS - 0.3
VDD + 0.3
Supply voltage (including VDDA and VDDIO)(1)
(2)
VIN
|VDDx - VDD| Variations between different power pins
50
|VSSx - VSS| Variations between all the different ground pins
50
VESD
Electrostatic discharge voltage
Unit
V
mV
see Absolute maximum
ratings (electrical
sensitivity) on page 89
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VINP$@
9''>9@
069
Figure 15. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz
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