STO47N60M6

STO47N60M6 Datasheet N-channel 600 V, 70 mΩ typ., 36 A, MDmesh M6 Power MOSFET in a TO‑LL package Features TO-LL type A Drain (TAB) Order code VDS RDS(on) max. ID STO47N60M6 600 V 80 mΩ 36 A • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • • Low gate input resistance 100% avalanche tested Zener-protected Excellent switching performance thanks to the extra driving source pin Applications Gate(1) • Driver source (2) Power source (3, 4, 5, 6, 7,8) N-chG1DS2PS345678DTABZ Switching applications Description The new MDmesh M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STO47N60M6 Product summary Order code STO47N60M6 Marking 47N60M6 Package TO-LL type A Packing Tape and reel DS12393 - Rev 3 - May 2021 For further information contact your local STMicroelectronics sales office. www.st.com STO47N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 36 Drain current (continuous) at TC = 100 °C 23 IDM(1) Drain current (pulsed) 130 A PTOT Total power dissipation at TC = 25 °C 255 W dv/dt(2) Peak diode recovery voltage slope 15 V/ns dv/dt(3) MOSFET dv/dt ruggedness 100 V/ns Tstg Storage temperature range VGS ID TJ Parameter Operating junction temperature range -55 to 150 A °C °C 1. Pulse width limited by safe operating area. 2. ISD ≤ 36 A, di/dt ≤ 400 A/µs, VDS (peak) < V(BR)DSS, VDD = 400 V. 3. VDS ≤ 480 V. Table 2. Thermal data Symbol RthJC RthJB Parameter Thermal resistance, junction-to-case Value Unit 0.49 °C/W Thermal resistance, junction-to-board(1) 43 Thermal resistance, junction-to-board(2) 22 °C/W 1. When mounted on 1 inch² FR-4 pcb, standard footprint 2 Oz copper board. 2. When mounted on 40x40mm FR-4 pcb, 6 cm² 2 Oz copper board. Table 3. Avalanche characteristics Symbol DS12393 - Rev 3 Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max.) 5.3 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 800 mJ page 2/15 STO47N60M6 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. 600 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 18 A VGS = 0 V, VDS = 600 V, TC = 125 Unit V VGS = 0 V, VDS = 600 V IDSS Max. 1 µA 100 µA ±5 µA 4.00 4.75 V 70 80 mΩ Min. Typ. Max. Unit - 2340 - pF - 149 - pF - 3.7 - pF °C(1) 3.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 390 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 1.4 - Ω Qg Total gate charge - 52.2 - nC Qgs Gate-source charge - 16.5 - nC Qgd Gate-drain charge - 23 - nC VDS= 100 V, f = 1 MHz, VGS = 0 V VDD = 480 V, ID = 36 A, VGS = 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12393 - Rev 3 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 300 V, ID = 18 A, - 21.5 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 18.7 - ns Turn-off delay time (see Figure 13. Switching times test circuit for resistive load and Figure 18. Switching time waveform) - 54.6 - ns - 8.1 - ns Fall time page 3/15 STO47N60M6 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) VSD (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 36 A Source-drain current (pulsed) - 130 A 1.6 V Forward on voltage VGS = 0 V, ISD = 36 A - trr Reverse recovery time ISD = 36 A, di/dt = 100 A/µs, - 281 ns Qrr Reverse recovery charge VDD = 60 V - 3.67 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 26 A trr Reverse recovery time ISD = 36 A, di/dt = 100 A/µs, - 424 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 7.2 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 34 A IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 μs, duty cycle 1.5%. DS12393 - Rev 3 page 4/15 STO47N60M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Operation in this area is limited by R DS(on) Figure 2. Thermal impedance K GIPG101220181028SOA tp =1 µs tp =10 µs 10 2 GADG181220181402ZTH 10-1 0.05 10 tp =100 µs 1 tp =1 ms TJ≤150 °C TC=25 °C VGS=10 V single pulse 10 0 10 -1 10 -1 10 0 10 1 tp =10 ms VDS (V) 10 2 10-2 Zth = K*RthJC 10-3 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) VGS =7, 8, 9, 10 V Figure 3. Output characteristics ID (A) Figure 4. Transfer characteristics GIPG101220181057OCH VGS =10 V VGS =9 V 120 100 VGS =8 V 60 VDS =16 V 120 80 60 40 VGS =7 V 20 40 20 VGS =6 V 2 4 6 8 10 12 14 16 VDS (V) Figure 5. Gate charge vs gate-source voltage GIPG101220181058QVG VGS VDS (V) VDD = 480 V, ID = 36 A (V) 600 12 Qg 500 400 GIPG101220181058TCH 100 80 0 0 ID (A) 10 VDS 5 6 7 8 9 VGS (V) Figure 6. Static drain-source on-resistance RDS(on) (mΩ) GIPG101220181055RID VGS =10 V 76 74 8 Qgd Qgs 0 4 72 300 6 200 4 100 2 0 0 DS12393 - Rev 3 10 20 30 40 50 60 0 Qg (nC) 70 68 66 0 6 12 18 24 30 36 ID (A) page 5/15 STO47N60M6 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) GIPG101220181057CVR 10 4 Figure 8. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GIPG101220181029VTH ID = 250 μA 1.1 1.0 10 3 0.9 10 2 0.8 f = 1 MHz 10 1 0.7 10 0 10 -1 10 0 10 1 VDS (V) 10 2 Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GIPG101220181029RON VGS = 10 V 2.2 0.6 -75 V(BR)DSS (norm.) 1.4 1.00 1.0 0.96 0.6 0.92 25 75 125 TJ (°C) Figure 11. Output capacitance stored energy EOSS (µJ) ADG181220181310EOS 125 TJ (°C) ID = 1 mA 0.88 -75 -25 25 75 125 TJ (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GIPG101220181057SDF 1.1 20 75 GIPG101220181055BDV 1.08 1.04 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 1.8 0.2 -75 -25 Tj = -50 °C 1.0 16 Tj = 25 °C 0.9 12 0.8 8 4 0 0 DS12393 - Rev 3 Tj = 150 °C 0.7 0.6 100 200 300 400 500 600 VDS (V) 0.5 0 6 12 18 24 30 36 ISD (A) page 6/15 STO47N60M6 Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD RL + VD VGS 3.3 µF 2200 RL µF VDD IG= CONST VGS RG + pulse width D.U.T. 2200 μF PW D.U.T. 100 Ω 2.7 kΩ VG 47 kΩ GND1 (driver signal) GND2 (power) 1 kΩ GND1 AM15855v1 GND2 GADG180720181011SA Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 16. Unclamped inductive load test circuit A L D G S L=100µH B B D 25Ω VD 3.3 µF B + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG D.U.T. Vi D.U.T. Pw GND2 GND1 GND1 GND2 AM15858v1 AM15857v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD VGS AM01472v1 0 VDS 10% 90% 10% AM01473v1 DS12393 - Rev 3 page 7/15 STO47N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO-LL type A package information Figure 19. TO-LL type A package outline DM00276569_5_type_A DS12393 - Rev 3 page 8/15 STO47N60M6 TO-LL type A package information Table 8. TO-LL type A package mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.40 A1 0.40 0.48 0.60 b 0.70 0.80 0.90 c 0.46 c1 0.15 C 10.28 10.38 10.48 C2 2.35 2.45 2.55 C3 1.16 D 9.80 9.90 10.00 D2 3.30 3.50 3.70 D3 9.30 9.40 9.50 D4 8.20 8.40 8.60 D5 9.50 9.70 9.90 D6 7.40 D7 2.20 e 1.20 E 11.48 E1 4.96 E2 5.54 E3 5.14 E4 0.90 E5 0.72 E6 6.41 E7 6.61 11.88 6.81 1.44 E8 0.50 0.70 0.90 K 1.70 1.90 2.10 K1 2.70 L 0.70 L1 0.44 L2 θ DS12393 - Rev 3 11.68 0.40 0.60 0.80 11° page 9/15 STO47N60M6 TO-LL type A package information Figure 20. TO-LL type A recommended footprint (dimensions are in mm) DM00276569_5_type_A_FP DS12393 - Rev 3 page 10/15 STO47N60M6 TO-LL packing information 4.2 TO-LL packing information Figure 21. Carrier tape outline and dimensions Figure 22. Reel outline and dimensions DS12393 - Rev 3 page 11/15 STO47N60M6 TO-LL packing information Figure 23. TO-LL orientation in tape pocket DS12393 - Rev 3 page 12/15 STO47N60M6 Revision history Table 9. Document revision history Date Version 04-Dec-2017 1 Changes First release. Modified Section 1 Electrical ratings and Section 2 Electrical characteristics. 10-Dec-2018 2 Added Section 2.1 Electrical characteristics (curves). Updated Section 4.1 TO-LL type A package information. Minor text changes. Updated title and Device summary in cover page. 05-May-2021 3 Updated Table 2. Thermal data. Updated Section 4 Package information. Minor text changes. DS12393 - Rev 3 page 13/15 STO47N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-LL type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 TO-LL packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12393 - Rev 3 page 14/15 STO47N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS12393 - Rev 3 page 15/15