STP08CDC596B1

STP08CDC596 8-Bit constant current Led sink driver with full outputs detection General features ■ 8 constant current output channels ■ Adjustable output current through one external resistor ■ Open and short line, short to GND, short to V-LED supply error detection ■ Serial data in/parallel data out ■ Serial out change state on the falling edges of clock ■ Output current: 20-120mA ■ 3.3V micro driver-able ■ 25MHz clock frequency ■ Available in high thermal TSSOP exposed pad. Description o r P e c u d t e l o s b O Order codes SO-16 TSSOP16 TSSOP16 (Exposed pad) c u d ) s t( To perform this functionality mode, the device needs a digital key coming from the Microprocessor. The STP08CDC596 is able to detect: open and short on the LED line, short to GND, short to LED voltage supply. The data mapping of output channels status detection is provided by a feedback from the serial output to the Microprocessor. e t le o r P o s b O - The STP08CDC596 is a monolithic, mediumvoltage, low current power 8-bit shift register designed for LED panel display. The STP08CDC596 contains a 8-bit serial-in, parallelout shift register that feeds a 8-bitD-type storage register. In the output stage, eight regulated current sources were designed to provide 15120mA constant current to drive the LEDs. The STP08CDC596 contains the built-IN error detection feature. The device performs this additional function without any increase of the pin number and any change of the pin function, if compared to the standard device without error detection. Consequently, choosing this device does not mean to change the footprint on the board. (t s) Dip-16 Trough an external resistor, users may adjust the STP08CDC596 output current, controlling the light intensity of LEDs. The STP08CDC596 guarantees 16V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 25 MHz, also satisfies the system requirement of high volume data transmission. The device is offered in DIP-16, SO-16, TSSOP-16 and TSSOP-16 Exposed Pad packages. The STP08CDC596 is well suitable for traffic display signs where the detection feature is strongly required. Part Number Temperature range Package Packaging STP08CDC596B1 -40°C to 125°C DIP-16 25 part per tube STP08CDC596M -40°C to 125°C SO-16 (Tube) 50 parts per tube STP08CDC596MTR -40°C to 125°C SO-16 (Tape & Reel) 2500 parts per reel STP08CDC596TTR -40°C to 125°C TSSOP16 (Tape & Reel) 2500 parts per reel STP08CDC596XTTR -40°C to 125°C TSSOP16 Exposed pad (Tape & Reel) 2500 parts per reel August 2006 Rev 3 1/29 www.st.com 29 Contents STP08CDC596 Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ) s t( 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Equivalent circuit of inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Running the detection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 c u d e t le ) s ( ct Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.2 Phase two: “error detection“ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.3 Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 18 s b O 2/29 u d o r P e Condition in order to get a successfully detection condition . . . . . . . . . . . 19 t e l o 10 12 o s b O - 9.1 9.4 11 o r P Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STP08CDC596 1 Summary description Summary description Table 1. Current accuracy Current accuracy Output voltage Output current Between bits Between ICs (Typ) ±3% ±10% ≥0.7V 1.1 20 to 120mA Pin connection and description Figure 1. Connections diagram c u d e t le ) s ( ct ) s t( o r P o s b O - Table 2. Pin description PIN N° o r P e 1 t e l o O bs du Symbol Name and function GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal 4 LE/DM1 Latch input terminal 5-12 OUT 0-7 Output terminal 13 OE/DM2 Output enable input terminal (active low) 14 SDO 15 R-EXT 16 VDD Serial data out terminal Constant current programming 5V Supply voltage terminal 3/29 Block diagram 2 STP08CDC596 Block diagram Figure 2. Block diagram c u d e t le ) s ( ct u d o r P e t e l o s b O 4/29 o s b O - o r P ) s t( STP08CDC596 3 Maximum rating Maximum rating Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 3.2 Parameter VDD Supply voltage IGND VO Output voltage -0.5 to 16 IO Output current 120 VI Input voltage IGND GND terminal current fCLK Clock frequency 0 to 7 TOPR Operating temperature range TSTG Storage temperature range Thermal data Table 4. Thermal data Parameter r P e t e l o RthJA ) s ( ct Thermal resistance junction-ambient uc Unit ) s t( V V mA -0.4 to VDD+0.4 od V 980 mA 25 MHz -40 to +125 °C -55 to +150 °C Package Value Unit DIP-16 90 SO-16 125 TSSOP-16 140 TSSOP-16 Exposed Pad 38 (1) e t le o s b O - u d o Symbol s b O Value Pr °C/W 1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits. 5/29 Maximum rating 3.3 STP08CDC596 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Test conditions Min Typ Max Unit 5.5 V 16.0 V 120 mA VDD Supply voltage VO Output voltage IO Output current OUTn IOH Output current SERIAL-OUT +1 mA IOL Output current SERIAL-OUT -1 mA VIH Input voltage 0.7VDD VDD+0.3 V VIL Input voltage -0.3 0.3VDD V 3.3 15 twLAT LE/DM1 pulse width 10 20 ns twCLK CLK pulse width 10 20 ns twEN OE/DM2 pulse width (1) 120 uc tSETUP(D) Setup time for DATA VDD = 3.0 to 5.0V e t le tSETUP(L) Setup time for LATCH fCLK Clock frequency (2) 400 ns od 20 ns 4 15 ns 8 15 ns 25 MHz 5 tHOLD(D) Hold time for DATA o s b O - Pr ) s t( 1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please considered the timings carefully. 2. In normal mode the OE/DM2 must remain low at least two clock cycles. ) s ( ct u d o r P e t e l o s b O 6/29 STP08CDC596 4 Electrical characteristics Electrical characteristics Table 6. Electrical characteristics (VDD = 5V, T = 25°C, unless otherwise specified.) Symbol Parameter Test conditions Min Typ Max Unit VIH Input voltage high level 0.7VDD VDD V VIL Input voltage low level GND 0.3VDD V IOH Output leakage current VOH = 16V 10 µA VOL Output voltage (Serial-OUT) IOL = 1mA 0.4 V VOH Output voltage (Serial-OUT) IOH = -1mA IOL1 Output current IOL2 ∆IOL1 ∆IOL2 RSIN(up) Output current error between bit (All Output ON) VDD-0.4V VO = 0.7VREXT = 910 Ω 18.8 20.9 24.00 mA VO = 0.7VREXT = 360 Ω 46.00 51.5 56.5 mA VO = 0.7VREXT = 910 Ω ±2 ±5 % VO = 0.7VREXT = 360 Ω ±1 Pull-up resistor 150 RSIN(down) Pull-down resistor IDD(OFF2) REXT = OPEN Supply current (OFF) IDD(OFF3) IDD(ON1) Pr 100 IDD(OFF1) Supply current (ON) IDD(ON2) V OUT 0 to 7 = OFF e t le uc ) s t( ±4 % 300 600 KΩ 200 400 KΩ 0.45 0.7 3.0 6.0 8.2 12.0 od REXT = 910 Ω OUT 0 to 7 = OFF REXT = 360 Ω OUT 0 to 7 = OFF REXT = 910 Ω OUT 0 to 7 = ON 3.1 6.2 REXT = 360 Ω OUT 0 to 7 = ON 8.4 12.8 ) s ( ct so b O - mA u d o r P e t e l o s b O 7/29 Switching characteristics 5 STP08CDC596 Switching characteristics Table 7. Switching Characteristics (VDD = 3.3V to 5.5V, T = 25°C, unless otherwise specified.) Symbol Parameter Test conditions Min Typ Max Unit tPLH1 Propagation delay time, CLK-OUTn, LE/DM1 = H, OE/DM2 = L 180 280 ns tPLH2 Propagation delay time, LE/DM1-OUTn, OE/DM2 = L 150 280 ns tPLH3 Propagation delay time, OE/DM2-OUTn, LE/DM1 = H 140 280 ns tPLH Propagation delay time, CLK-SDO 25 35 ns tPHL1 Propagation delay time, CLK-OUTn, LE/DM1 = H, OE/DM2 = L 30 60 tPHL2 Propagation delay time, LE/DM1-OUTn, OE/DM2 = L tPHL3 Propagation delay time, OE/DM2-OUTn, LE/DM1 = H tPHL Propagation delay time, CLK-SDO tr Output rise time tf Output fall time VDD = 3V VIL = GND IO = 40mA REXT = 470Ω ) s ( ct u d o r P e t e l o s b O 8/29 VIH = VDD CL = 13pF VL = 3V RL = 65 Ω o s b O - e t le c u d ) s t( ns 30 50 ns 35 70 ns 30 40 ns o r P 220 ns 20 ns STP08CDC596 6 Equivalent circuit of inputs and outputs Equivalent circuit of inputs and outputs Figure 3. OE terminal Figure 4. LE terminal c u d e t le Figure 5. ) s ( ct ) s t( o r P o s b O - u d o CLK, SDI terminal r P e t e l o s b O 9/29 Equivalent circuit of inputs and outputs Figure 6. STP08CDC596 SDO terminal c u d e t le ) s ( ct u d o r P e t e l o s b O 10/29 o s b O - o r P ) s t( STP08CDC596 7 Timing diagram Timing diagram Figure 7. Timing diagram c u d e t le ) s ( ct Note: ) s t( o r P o s b O - In normal mode the OE/DM2 must remain low at least two clock cycles. In case of OE signal enabled (OE = LOW) during no clock activity (clock stopped), after the CLK restarts, 3 full CLK cycles are necessary before disabling the OE signal (OE = High). u d o r P e t e l o s b O 11/29 Timing diagram Figure 8. Figure 9. STP08CDC596 Clock, serial-in, serial-out Clock, serial-in, latch, enable, outputs e t le ) s ( ct u d o r P e t e l o s b O 12/29 o s b O - o r P c u d ) s t( STP08CDC596 Timing diagram Figure 10. Outputs c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 13/29 Test circuit STP08CDC596 8 Test circuit Figure 11. DC characteristics c u d Figure 12. AC characteristics ) s ( ct u d o r P e t e l o s b O 14/29 o s b O - e t le o r P ) s t( STP08CDC596 Test circuit Figure 13. Timing example for open and/or short detection c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 15/29 Running the detection mode STP08CDC596 9 Running the detection mode 9.1 Phase one: “entering in detection mode“ From the “Normal Mode” condition the device can switch to the “Error Mode“ by a logic sequence on the OE/DM2 and LE/DM1 pins as showed in the following table and diagram: Table 8. Entering in detection truth table CLK 1° 2° 3° 4° 5° OE/DM2 H L H H H LE/DM1 L L L H L Table 9. Entering in detection timing diagram c u d e t le ) s ( ct ) s t( o r P o s b O - After these five CLK cycles the device goes into the “Error Detection Mode“ and at the 6th rise front of CLK the SDI data are ready for the sampling. u d o r P e t e l o s b O 16/29 STP08CDC596 9.2 Running the detection mode Phase two: “error detection“ The eight data bits must be set “1“ in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the detection process. When the Micro controller switches the OE/DM2 to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred. Table 10. Detection diagram c u d e t le ) s t( o r P The LEDs status will be detected at least in 2 microseconds and after this time the microcontroller puts OE in HIGH state and the output data detection result will go to the microprocessor via SDO. o s b O - The detection data format is the same of data in normal mode. As soon as all the detection data bits are available on the serial line, the device may go back to normal mode operation. ) s ( ct u d o r P e t e l o s b O 17/29 Running the detection mode 9.3 STP08CDC596 Phase three: “resuming to normal mode” The sequence for re-entering in normal mode is showed in the following Table and diagram: Table 11. Resuming to normal mode timing diagram CLK 1° 2° 3° 4° 5° OE/DM2 H L H H H LE/DM1 L L L L L Table 12. Resuming to normal mode timing diagram c u d e t le Note: o r P For proper device operation the "Entering in detection" sequence must be follow by a "Resume Mode" sequence, isn’t possible to insert consecutive equal sequence. ) s ( ct u d o r P e t e l o s b O 18/29 o s b O - ) s t( STP08CDC596 9.4 Running the detection mode Condition in order to get a successfully detection condition Table 13. Detection condition (VDD = 3.3 to 5 V Temp. Range -40 to 85°C) Note: SW-1 or SW-3b Open line or output short to GND detected SW-2 or SW-3a Short on LED or short ==> VO ≥ 2.4 V to V-LED detected ==> IODEC ≤0.5 x IO No error detected ==> IODEC ≥ 0.5 x IO No error detected ==> VO ≤2.2 V Where: IO = the output current programmed by the REXT , IODEC = the detected output current in detection mode. Figure 14. Detection circuit c u d e t le ) s ( ct o r P e du ) s t( o r P o s b O - STP08CDC596 16 t e l o s b O 19/29 Typical characteristics 10 STP08CDC596 Typical characteristics Figure 15. Output current-REXT resistor Figure 16. Dropout voltage vs output current Figure 17. Power dissipation vs temperature package c u d Figure 18. Output current vs ±∆IOL(%) e t le ) s ( ct u d o r P e t e l o s b O 20/29 ) s t( o s b O - o r P STP08CDC596 11 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 21/29 Package mechanical data STP08CDC596 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 I 5.1 L 0.280 r P e t le 3.3 Z od 0.201 0.130 1.27 ) s ( ct uc ) s t( 0.050 o s b O - u d o r P e t e l o s b O P001C 22/29 STP08CDC596 Package mechanical data SO-16 MECHANICAL DATA mm. DIM. MIN. TYP A inch MAX. MIN. TYP. a1 1.75 MAX. 0.1 0.068 0.25 a2 0.004 0.010 1.64 b 0.35 b1 0.19 C 0.063 0.46 0.013 0.25 0.007 0.5 0.018 0.010 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 G 4.6 5.3 0.181 L 0.5 1.27 0.019 M 0.62 S e t le 8° (max.) ) s ( ct uc ) s t( 0.157 Pr od 0.208 0.050 0.024 o s b O - u d o r P e t e l o s b O 0016020D 23/29 Package mechanical data STP08CDC596 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 1 e 0˚ L 0.45 P e let b A1 u d o r P e 0˚ 0.75 ) s ( ct A2 A 0.0256 BSC 8˚ 0.60 e 0.176 d o r 0.65 BSC K uc 0.018 o s b O c 0.024 K ) s t( 8˚ 0.030 L E D t e l o s b O E1 PIN 1 IDENTIFICATION 1 0080338D 24/29 STP08CDC596 Package mechanical data TSSOP16 EXPOSED PAD MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A 1.2 A1 0.15 A2 0.8 b 1 MIN. TYP. MAX. 0.047 0.004 0.006 0.039 0.041 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5.1 0.193 D1 1.7 E 6.2 6.4 6.6 E1 4.3 4.4 4.5 E2 1.5 5 0.197 0.201 0.244 0.252 0.260 0.169 0.173 0.067 0.65 K 0° L 0.45 d o r 0.059 e ) s ( ct 0.177 0.0256 P e let 8° 0.60 uc ) s t( 0.75 0° 0.018 0.024 8° 0.030 o s b O - u d o r P e t e l o s b O 7419276A 25/29 Package mechanical data STP08CDC596 Tape & Reel TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 22.4 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 P 7.9 8.1 0.311 ) s ( ct u d o r P e t e l o 26/29 o s b O - uc ) s t( 0.161 d o r P e let s b O MAX. 0.319 STP08CDC596 Package mechanical data Tape & Reel SO-16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 330 MAX. 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 22.4 0.882 Ao 6.45 6.65 0.254 0.262 Bo 10.3 10.5 0.406 0.414 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 P 7.9 8.1 0.311 ) s ( ct r P e t le uc ) s t( 0.161 od 0.319 o s b O - u d o r P e t e l o s b O 27/29 Revision history 12 STP08CDC596 Revision history Table 1. Revision history Date Revision Changes 15-Jun-2005 1 First release 11-Oct-2005 2 Minor revision, no content change 2-Aug-2006 3 New template, block diagram Figure 2 on page 4 and equivalent circuit Section 6 on page 9 updated, added TSSOP-16 Exposed Pad package. c u d e t le ) s ( ct u d o r P e t e l o s b O 28/29 o s b O - o r P ) s t( STP08CDC596 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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