STP10N80K5
Datasheet
N-channel 800 V, 0.470 Ω typ., 9 A
MDmesh™ K5 Power MOSFET in a TO-220 package
Features
TAB
1
2
3
TO-220
Order code
VDS
RDS(on ) max.
ID
PTOT
STP10N80K5
800 V
0.600 Ω
9A
130 W
•
Industry’s lowest RDS(on) x area
•
•
•
•
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
D(2, TAB)
Applications
•
G(1)
Switching applications
Description
S(3)
AM01475V1
This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5
technology based on an innovative proprietary vertical structure. The result is a
dramatic reduction in on-resistance and ultra-low gate charge for applications
requiring superior power density and high efficiency.
Product status
STP10N80K5
Product summary
Order code
STP10N80K5
Marking
10N80K5
Package
TO-220
Packing
Tube
DS12512 - Rev 1 - March 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STP10N80K5
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Parameter
VGS
Gate-source voltage
Value
Unit
±30
V
ID
Drain current (continuous) at TC = 25 °C
9
A
ID
Drain current (continuous) at TC = 100 °C
6
A
IDM (1)
Drain current pulsed
36
A
PTOT
Total dissipation at TC = 25 °C
130
W
dv/dt (2)
Peak diode recovery voltage slope
4.5
dv/dt (3)
MOSFET dv/dt ruggedness
50
Tj
Operating junction temperature range
Tstg
Storage temperature range
V/ns
- 55 to 150
°C
1. Pulse width limited by safe operating area.
2. ISD≤ 9 A, di/dt ≤ 100 A/μs; VDS peak ≤ V(BR)DSS
3. VDS ≤ 640 V
Table 2. Thermal data
Symbol
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case
0.96
°C/W
Rthj-amb
Thermal resistance junction-ambient
62.5
°C/W
Table 3. Avalanche characteristics
Symbol
DS12512 - Rev 1
Parameter
IAR
Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax.)
EAS
Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V)
Value
Unit
3
A
130
mJ
page 2/14
STP10N80K5
Electrical characteristics
2
Electrical characteristics
TC = 25 °C unless otherwise specified
Table 4. On/off-state
Symbol
V(BR)DSS
Parameter
Drain-source breakdown
voltage
Test conditions
VGS = 0 V, ID = 1 mA
Min.
Typ.
800
IDSS
1
µA
50
µA
±10
µA
4
5
V
0.470
0.600
Ω
Min.
Typ.
Max.
Unit
-
635
-
pF
-
53
-
pF
-
0.8
-
pF
-
85
-
pF
34
-
pF
VGS = 0 V, VDS = 800 V
TC = 125 °C (1)
IGSS
Gate body leakage current
VDS = 0 V, VGS = ±20 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 100 µA
RDS(on)
Static drain-source onresistance
VGS = 10 V, ID = 4.5 A
Unit
V
VGS = 0 V, VDS = 800 V
Zero gate voltage drain
current
Max.
3
1. Defined by design, no subject to production test.
Table 5. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Co(tr) (1)
Equivalent capacitance time
related
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0 V
VDS = 0 to 640 V, VGS = 0 V
Co(er) (2)
Equivalent capacitance
energy related
Rg
Intrinsic gate resistance
f = 1 MHz , ID = 0 A
-
6
-
Ω
Qg
Total gate charge
VDD = 640 V, ID = 9 A
-
22
-
nC
Qgs
Gate-source charge
VGS = 0 to 10 V
-
5.5
-
nC
Gate-drain charge
(see Figure 15. Test circuit for
gate charge behavior )
-
13.2
-
nC
Qgd
1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
DS12512 - Rev 1
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
Typ.
Max.
Unit
VDD = 400 V, ID = 4.5 A, RG =
4.7 Ω
-
14.5
-
ns
-
11
-
ns
-
35
-
ns
-
14
-
ns
VGS = 10 V (see Figure
14. Test circuit for resistive
load switching times and
Figure 19. Switching time
waveform)
page 3/14
STP10N80K5
Electrical characteristics
Table 7. Source-drain diode
Symbol
ISD
ISDM (1)
(2)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
9
A
Source-drain current (pulsed)
-
36
A
1.5
V
Forward on voltage
ISD = 9 A, VGS = 0 V
-
trr
Reverse recovery time
ISD = 9 A, di/dt = 100 A/µs,
-
370
ns
Qrr
Reverse recovery charge
-
4.58
µC
IRRM
Reverse recovery current
VDD = 60 V, see )Figure
16. Test circuit for inductive
load switching and diode
recovery times
-
25
A
VSD
trr
Reverse recovery time
ISD = 9 A, di/dt = 100 A/µs,
-
520
ns
Qrr
Reverse recovery charge
VDD = 60 V, Tj = 150 °C
-
5.88
µC
IRRM
Reverse recovery current
(see Figure 16. Test circuit for
inductive load switching and
diode recovery times)
-
22.5
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Table 8. Gate-source Zener diode
Symbol
V(BR)GSO
Parameter
Gate-source breakdown
voltage
Test conditions
IGS = ±1 mA, ID = 0 A
Min.
Typ.
Max
Unit
±30
-
-
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for
additional external componentry.
DS12512 - Rev 1
page 4/14
STP10N80K5
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 2. Thermal impedance
GIPG210320181256SOA
ID
(A) Operation in this area is
limited by R DS(on)
10 1
tp =100 µs
tp =1 ms
10 0
TJ≤150 °C
TC=25 °C
single pulse
10 -1
10 -1
10 0
10 1
tp =10 ms
VDS (V)
10 2
Figure 3. Output characteristics
Figure 4. Transfer characteristics
GIPD110811520SMD
ID(A)
VGS=11 V
10 V
20
GIPD110811420SMD
ID
(A)
VDS=20 V
20
9V
16
16
12
12
8V
8
8
7V
4
4
6V
0
0
4
8
12
16
VDS(V)
Figure 5. Gate charge vs. gate-source voltage
0
5
RDS(on)
(Ω)
12
600
0.8
10
500
8
400
6
300
GIPD110811425SMD
VDS
VDS= 640 V
ID= 9 A
4
2
0
200
100
0
DS12512 - Rev 1
4
8
12
16
0
20 Qg(nC)
7
9
8
10
VGS(V)
Figure 6. Static drain-source on-resistance
VDS
(V)
VGS
(V)
6
GIPD110811430SMD
VGS=10 V
0.7
0.6
0.5
0.4
0.3
0
4
8
12
16
ID(A)
page 5/14
STP10N80K5
Electrical characteristics (curves)
Figure 7. Capacitance variations
C
(pF)
Figure 8. Source-drain diode forward characteristics
VSD
(V)
GIPD110811524SMD
1000
Ciss
100
GIPD110811455SMD
0.9
TJ=-50 °C
0.8
TJ=25 °C
Coss
10
0.7
f = 1 MHz
Crss
TJ =150 °C
0.6
1
0.1
0.1
1
10
100
VDS(V)
Figure 9. Normalized gate threshold voltage vs.
temperature
VGS(th)
GIPD110811432SMD
0.5
3
4
5
6
7
8
ISD(A)
Figure 10. Normalized on-resistance vs. temperature
GIPD110811441SMD
RDS(on)
(norm)
(norm)
2.5
1.2
1
1.5
0.8
1
0.5
0.6
0.4
-75
ID= 4.5 A
VGS= 10 V
2
ID=100 µA
0
-75
-25
25
75
125
Figure 11. Normalized V(BR)DSS vs. temperature
GIPD110811447SMD
V(BR)DSS
-25
25
75
125
TJ(°C)
TJ(°C)
(norm)
Figure 12. Maximum avalanche energy vs. starting TJ
EAS (mJ)
GIPD110811545SMD
120
1.1
100
1.05
ID=1mA
80
60
1
40
0.95
0.9
-75
DS12512 - Rev 1
20
0
-25
25
75
125
TJ(°C)
0
20
40
60
80 100 120 140 TJ(°C)
page 6/14
STP10N80K5
Electrical characteristics (curves)
Figure 13. Output capacitance stored energy
Eoss
(µJ)
GIPD110811503SMD
8
6
4
2
0
DS12512 - Rev 1
0
100 200 300 400 500 600 700 VDS(V)
page 7/14
STP10N80K5
Test circuits
3
Test circuits
Figure 14. Test circuit for resistive load switching times
Figure 15. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 16. Test circuit for inductive load switching and
diode recovery times
Figure 17. Unclamped inductive load test circuit
L
D
G
A
D.U.T.
S
25 Ω
A
A
100 µH
fast
diode
B
B
B
VD
3.3
µF
D
G
+
RG
1000
+ µF
2200
+ µF
3.3
µF
VDD
ID
VDD
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
V(BR)DSS
ton
VD
td(on)
IDM
toff
td(off)
tr
90%
tf
90%
10%
ID
VDD
10%
0
VDD
VGS
0
VDS
90%
10%
AM01472v1
AM01473v1
DS12512 - Rev 1
page 8/14
STP10N80K5
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
DS12512 - Rev 1
page 9/14
STP10N80K5
TO-220 type A package information
4.1
TO-220 type A package information
Figure 20. TO-220 type A package outline
0015988_typeA_Rev_21
DS12512 - Rev 1
page 10/14
STP10N80K5
TO-220 type A package information
Table 9. TO-220 type A package mechanical data
Dim.
mm
Min.
Max.
A
4.40
4.60
b
0.61
0.88
b1
1.14
1.55
c
0.48
0.70
D
15.25
15.75
D1
DS12512 - Rev 1
Typ.
1.27
E
10.00
10.40
e
2.40
2.70
e1
4.95
5.15
F
1.23
1.32
H1
6.20
6.60
J1
2.40
2.72
L
13.00
14.00
L1
3.50
3.93
L20
16.40
L30
28.90
øP
3.75
3.85
Q
2.65
2.95
page 11/14
STP10N80K5
Revision history
Table 10. Document revision history
DS12512 - Rev 1
Date
Revision
21-Mar-2018
1
Changes
Initial release. The document status is production data.
page 12/14
STP10N80K5
Contents
Contents
1
Electrical ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
TO-220 type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DS12512 - Rev 1
page 13/14
STP10N80K5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12512 - Rev 1
page 14/14
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