STP12N50M2

STP12N50M2 N-channel 500 V, 0.325 Ω typ.,10 A MDmesh II Plus™ low Qg Power MOSFET in a TO-220 package Datasheet - preliminary data Features 7$% Order code VDS RDS(on) max ID STP12N50M2 500 V 0.38 Ω 10 A • Extremely low gate charge • Lower RDS(on) x area vs previous generation    • Low gate input resistance • 100% avalanche tested 72 • Zener-protected Applications Figure 1. Internal schematic diagram , TAB • Switching applications Description This device is an N-channel Power MOSFET developed using a new generation of MDmesh™ technology: MDmesh II Plus™ low Qg. This revolutionary Power MOSFET associates a vertical structure to the company's strip layout to yield one of the world's lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. AM15572v1 . Table 1. Device summary Order code Marking Package Packaging STP12N50M2 12N50M2 TO-220 Tube June 2014 DocID026516 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/13 www.st.com Contents STP12N50M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 8 DocID026516 Rev 1 STP12N50M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 10 A ID Drain current (continuous) at TC = 100 °C 7 A IDM (1) Drain current (pulsed) 40 A PTOT Total dissipation at TC = 25 °C 85 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Value Unit dv/dt (2) dv/dt(3) Tstg Tj Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area. 2. ISD ≤ 10 A, di/dt ≤ 400 A/μs; VDS peak < V(BR)DSS, VDD=400 V. 3. VDS ≤ 400 V Table 3. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max 1.47 °C/W Rthj-amb Thermal resistance junction-amb max 62.5 °C/W Value Unit Table 4. Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 3.5 A EAS Single pulse avalanche energy (starting Tj=25°C, ID= IAR; VDD=50) 204 mJ DocID026516 Rev 1 3/13 13 Electrical characteristics 2 STP12N50M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS IDSS IGSS Parameter Drain-source breakdown voltage Zero gate voltage drain current Gate-body leakage current Test conditions ID = 1 mA, VGS = 0 Min. Typ. Max. Unit 500 V VGS = 0, VDS = 500 V 1 μA VGS = 0, VDS = 500 V, TC=125 °C 100 μA VDS = 0, VGS = ± 25 V ±10 μA 3 4 V 0.325 0.38 Ω Min. Typ. Max. Unit - 560 - pF - 33 - pF - 1 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 5 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VGS = 0, VDS = 0 to 400 V - 125 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 6.8 - Ω Qg Total gate charge - 15 - nC - 3 - nC - 8.3 - nC Qgs Gate-source charge Qgd Gate-drain charge VGS = 0, VDS = 100 V, f = 1 MHz VDD = 400 V, ID = 10 A, VGS = 10 V (see Figure 15) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/13 DocID026516 Rev 1 STP12N50M2 Electrical characteristics Table 7. Switching times Symbol td(on) Parameter Test conditions Turn-on delay time VDD = 250 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14 and 19) Rise time tr td(off) tf Turn-off delay time Fall time Min. Typ. Max. Unit - 13.5 - ns - 10.5 - ns - 8 - ns - 34.5 - ns Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 10 A ISDM (1) Source-drain current (pulsed) - 40 A VSD (2) Forward on voltage - 1.6 V ISD trr VGS = 0, ISD = 10 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 10 A, di/dt = 100 A/μs VDD = 60 V (see Figure 16) ISD = 10 A, di/dt = 100 A/μs VDD = 60 V, Tj=150 °C (see Figure 16) - 276 ns - 2.4 μC - 17.5 A - 376 ns - 3.4 μC - 18.3 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5% DocID026516 Rev 1 5/13 13 Electrical characteristics 2.1 STP12N50M2 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance *,3*6$ ,' $ LV —V 6 RQ  2S /LP HUD LWH WLRQ G LQ E\ WK P LV D[ DU 5 HD  '  —V  PV PV 7M ƒ& 7F ƒ& 6LQJOHSXOVH     9'69  Figure 4. Output characteristics Figure 5. Transfer characteristics *,3*6$ ,' $ 9*6 9 9    9  9     9     *,3*6$ 9'6 9*6 9 9'6  9'' 9 ,' $  5'6RQ ȍ                    9*69 Figure 7. Static drain-source on-resistance 9      9'69 Figure 6. Gate charge vs gate-source voltage 6/13 9'6 9    *,3*6$ ,' $ *,3*6$ 9*6 9        4JQ&  DocID026516 Rev 1           ,'$ STP12N50M2 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy *,3*6$ & S) *,3*6$ (RVV —-   &LVV   &RVV        Figure 10. Normalized gate threshold voltage vs temperature *,3*6$ 9*6WK   &UVV 9'69 QRUP      9'69 Figure 11. Normalized on-resistance vs temperature *,3*6$ 5'6RQ QRUP 9*6 9 ,' —$                         7-ƒ& Figure 12. Normalized V(BR)DSS vs temperature *,3*6$ 9%5'66 QRUP     7-ƒ&   Figure 13. Source-drain diode forward characteristics *,3*6$ 96'9 ,' P$    7- ƒ&          7- ƒ& 7- ƒ&        7-ƒ& DocID026516 Rev 1        ,6'$ 7/13 13 Test circuits 3 STP12N50M2 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton 9%5'66 tdon 9' toff tr tdoff tf 90% 90% ,'0 10% ,' 9'' 10% 0 9'' VDS 90% VGS $0Y 8/13 0 DocID026516 Rev 1 10% AM01473v1 STP12N50M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026516 Rev 1 9/13 13 Package mechanical data STP12N50M2 Figure 20. TO-220 type A drawing BW\SH$B5HYB7 10/13 DocID026516 Rev 1 STP12N50M2 Package mechanical data Table 9. TO-220 type A mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 DocID026516 Rev 1 11/13 13 Revision history 5 STP12N50M2 Revision history Table 10. Document revision history 12/13 Date Revision 17-Jun-2014 1 Changes First release. DocID026516 Rev 1 STP12N50M2 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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