STP1612PW05

STP1612PW05 16-channel LED driver with 16-bit PWM, 8-bit gain and full LED error detection Preliminary data Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 16 constant current output channels Supply voltage: 3.3 V or 5 V Two PWM selectable counters 12/16-bit of grayscale Selectable enhanced PWM for ghost effect reduction Open and short LED detection 8-bit current gain control by means of 256 steps in two selectable ranges Single resistor to set the current from 3 mA to 60 mA Programmable progressive output delay Thermal protection and thermal flag UVLO Schmitt trigger input Selectable 16-bit or 256-bit serial data-in format Max clock frequency: 30 MHz ESD protection 2.5 kV HBM, 200 V MM Drop-in compatible with STP16CP\S\DP05 series Available in high thermal efficiency TSSOP exposed pad QFN-24 SO-24 TSSOP24 TSSOP24 exposed pad Description The STP1612PW05 is a 16-channel constant current sink LED driver. The maximum output current value for all the 16 channels is set by a single resistor from 3 mA to 60 mA. The device features 8-bit gain (256 steps) for global LED brightness adjustment with two selectable ranges. This function is accessible via a serial interface. The device has an individual adjustable PWM brightness control for each output channel. The PWM counters are selectable via a serial interface with 4096 or 65536 steps (12 or 16 bit). The STP1612PW05 also provides enhanced pulse-width modulation counting algorithms called e-PWM to reduce flickering effects (ghost visual effects) improving the overall image quality. The device has a dual size 16-bit or 256-bit shift register. All the control and the shift register read back data are accessible via serial interface. The STP1612PW05 has the capability to detect open and short LED failure and overtemperature, reporting the status through SPI line. The device guarantees a 20 V output driving capability, allowing the user to connect more LEDs in series. Packaging 4000 parts per reel 1000 parts per reel 2500 parts per reel 2500 parts per reel 1/35 www.st.com 35 Applications ■ ■ ■ Video display LED panels RGB backlighting Special lighting Table 1. Device summary Order code STP1612PW05QTR STP1612PW05MTR STP1612PW05TTR STP1612PW05XTTR December 2009 Package QFN-24 SO-24 TSSOP24 TSSOP24 exposed pad Doc ID 15819 Rev 4 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STP1612PW05 Contents 1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 3.2 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 5 6 7 8 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Definition of configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Grey scales data loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Setting the PWM gray scale counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1 9.2 PWM data synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Synchronization for PWM counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 11 12 13 14 15 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Setting output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Current gain adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Delay time of staggered output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Time-out alert of GCLK disconnection . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/35 Doc ID 15819 Rev 4 STP1612PW05 Contents 16 17 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 15819 Rev 4 3/35 Block diagram STP1612PW05 1 Block diagram Figure 1. Block diagram GND SDI CLK LE SDO VDD R-EXT Dual range gain 7-bit DAC UVLO & POR Serial interface TSD Open/short error detection Shift register dual size mode (16 or 256 bit) PWM data buffer (16x16 bit) PWM and e-PWM 12/16 bit counter and SYNC control PWCLK 4/35 Doc ID 15819 Rev 4 1----------16 CTRL command and CTRL logic 16-bit Configuration Register Gradual outputs delay Constant current output channels STP1612PW05 Summary description 2 Summary description Table 2. Typical current accuracy at 5 V Current accuracy Output voltage Between bits ≥ 1.0 ≥ 0,2 ± 1.5% ± 1.5% Between ICs ± 6% ± 6% 15 to 60 5V 3 to 15 25 °C Output current VDD temp. Table 3. Typical current accuracy at 3.3 V Current accuracy Output current Between bits Between ICs ± 6% ± 6% 15 to 60 3.3 V ± 1.5% 3 to 15 25 °C ± 1.5% VDD temp. Output voltage ≥ 1.0 ≥ 0,3 Doc ID 15819 Rev 4 5/35 Summary description STP1612PW05 2.1 Pin connection and description Figure 2. Pin connection R-EXT PWCLK LE OUT0 OUT1 OUT2 OUT3 OUT4 1 24 2 3 22 21 20 19 18 17 16 15 14 7 8 OUT6 13 9 10 11 12 GND OUT8 OUT7 OUT9 S DO OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 2 3 4 5 6 Note: The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground Table 4. Pin n° 1 2 3 4 5-20 21 22 23 24 Pin description Symbol GND SDI CLK LE OUT 0-15 PWCLK SDO R-EXT VDD Ground terminal Serial data input terminal Clock input terminal used to shift data on rising edge and carries command information when LE is asserted. Data strobe terminal and controlling command with CLK Output terminals Gray scale clock terminal. Reference clock for grey scale PWM counter. Serial data out terminal Input terminal of an external resistor for constant current programing Supply voltage terminal Name and function 6/35 Doc ID 15819 Rev 4 OUT5 VDD CLK SDI STP1612PW05 Electrical ratings 3 3.1 Electrical ratings Absolute maximum ratings Stressing the device above the rating listed in the Table 5 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Symbol VDD VO IO VI IGND fCLK TJ Supply voltage Output voltage Output current Input voltage GND terminal current Clock frequency Junction temperature range (1) Absolute maximum ratings Parameter Value 0 to 7 -0.5 to 20 60 -0.4 to VDD 1300 50 -40 to + 170 Unit V V mA V mA MHz °C 1. Such absolute value is based on the thermal shutdown protection. 3.2 Thermal data Table 6. Symbol TA TJ-OPR TSTG Thermal data Parameter Operating free-air temperature range Operating thermal junction temperature range Storage temperature range SO-24 TSSOP24 Thermal resistance junctionambient (1) Value -40 to +125 -40 to +150 -55 to +150 42.7 55 37.5 55 Unit °C °C °C °C/W °C/W °C/W °C/W RthJA TSSOP24(2) Exposed pad QFN-24 1. According to Jedec standard 51-7B 2. The exposed pad should be soldered directly to the PCB to realize the thermal benefits. Doc ID 15819 Rev 4 7/35 Electrical ratings STP1612PW05 3.3 Recommended operating conditions Table 7. Symbol VDD VO IO IOH IOL VIH VIL twLAT twCLK twEN Recommended operating conditions at 25 °C, VDD = 5 V Parameter Supply voltage Output voltage Output current Output current Output current Input voltage Input voltage LE pulse width CLK pulse width PWCLK pulse width VDD = 3.3 V to 5.0 V OUTn SERIAL-OUT SERIAL-OUT 0.7 VDD GND 20 10 20 5 5 5 Cascade operation (1) Test conditions Min. 3.0 Typ. - Max. 5.5 20 60 +1 -1 VDD 0.3 VDD Unit V V mA mA mA V V ns ns ns ns ns ns 3 - tSETUP(D) Setup time for DATA tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH fCLK Clock frequency 30 MHz 1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please considered the timings carefully. 8/35 Doc ID 15819 Rev 4 STP1612PW05 Electrical characteristics 4 Electrical characteristics TA = 25 °C (Unless otherwise specified) Table 8. Symbol VDD VO IOUT IOH IOL VIH VIL IOH VOL VOH dIOUT1 dIOUT2 Current skew (Channel) Current skew (IC) Output current vs. output voltage regulation Output current vs. supply voltage regulation Input voltage “H” level Input voltage “L” level Output leakage current Output current Electrical characteristics (VDD = 5.0 V) Characteristics Supply voltage Maximum output voltage OUT0 ~ OUT15 VO = 1.2V SDO, TA = - 40 ~ 125 °C SDO, TA = - 40 ~ 125 °C TA = - 40 ~ 125 °C TA = - 40 ~ 125 °C VO = 20 V IOL = + 1.0 mA, TA = - 40 ~ 125 °C IOH = -1.0 mA TA = - 40 ~ 125 °C IOUT = 10 mA VO = 1.0 V, Rext = 69 kΩ IOUT = 10 mA VO = 1.0 V, Rext = 69 kΩ VO within 1.0 V and 3.0 V, Rext = 34.7 kΩ @ 20 mA VDD 0.4 ± 1.5 ± 3.0 ± 3.0 ± 6.0 0.7 * VDD GND 5 Test conditions Min. 4.5 Typ. 5.0 Max. 5.5 20 60 -8 8 VDD 0.3 * VDD 10 0.4 Unit V V mA mA mA V V μA V V % % Output voltage SDO %/dVO ± 0.1 ± 0.5 %/V %/dVDD VO,TH RIN(down) IDD(off) 1 IDD(off) 2 IDD(off) 3 IDD(on) 1 IDD(on) 2 VDD within 4.5 V and 5.5 V ± 1.0 0.15 ± 5.0 0.20 250 13 12 16.5 12.2 14.9 %/V V kΩ Pull-down resistor LE 150 7 6.6 9 6.6 8 200 10 9.5 12.7 9.4 11.5 Rext = Open, OUT0 ~ OUT15 = Off Supply current “Off” IO = 20 mA, OUT0 ~ OUT15 = Off IO = 60 mA, OUT0 ~ OUT15 = Off IO = 20 mA, OUT0 ~ OUT15 = On IO = 60 mA, OUT0 ~ OUT15 = On Doc ID 15819 Rev 4 mA Supply current “On” 9/35 Electrical characteristics Table 9. Symbol VDD VO IOUT IOH IOL VIH VIL IOH VOL Output voltage SDO VOH Input voltage “H” level Input voltage “L” level Output leakage current Output current STP1612PW05 Electrical characteristics (VDD = 3.3 V) Characteristics Supply voltage Sustaining voltage at OUT Ports OUT0 ~ OUT15 VO = 1.2 V SDO, TA = -40 ~ 125 °C SDO TA = -40 ~ 125 °C TA = - 40 ~ 125 °C TA = - 40 ~ 125 °C VO = 17.0 V IOL = +1.0 mA, TA = -40 ~ 125 °C IOH = -1.0 mA TA = -40 ~ 125 °C Current skew (channel) IOUT = 10.5 mA, VO = 1.0 V, Rext = 69 kΩ at 10 mA IOUT = 10.8 mA, VO = 1.0 V, Rext = 69 kΩ at 10 mA 2.9 0.7 * VDD GND 5 Test conditions Min. 3.0 Typ. 3.3 Max. 3.6 20 60 -1.0 1.0 VDD 0.3 * VDD 0.5 0.4 Unit V V mA mA mA V V μA V V dIOUT1 ± 1.5 ± 3.0 % dIOUT2 Current skew (IC) ± 3.0 ± 6.0 % %/dVO Output current vs. VO within 1.0 V and 3.0 V, output voltage regulation Rext = 34.7 kΩ at 20 mA Output current vs. VDD within 3.0 V and 3.6 V LE Rext = Open, OUT0 ~ OUT15 = Off IO = 20 mA, OUT0 ~ OUT15 = Off IO = 60 mA, OUT0 ~ OUT15 = Off IO = 20 mA, OUT0 ~ OUT15 = On Supply current “ON” IO = 60 mA, OUT0 ~ OUT15 = On 150 ± 0.1 ± 0.5 %/V %/dVDD supply voltage regulation RIN(down) Pull-down resistor ± 1.0 200 7.2 8.6 11.7 29 31.2 ± 5.0 250 9.3 11 15.2 37.7 40 %/V kΩ IDD(off) 1 IDD(off) 2 Supply current “OFF” IDD(off) 3 IDD(on) 1 IDD(on) 2 mA 10/35 Doc ID 15819 Rev 4 STP1612PW05 Figure 3. Test circuit for electrical characteristics Electrical characteristics IDD VDD IOUT VIH,VIL V DD SDI CLK LE P WCLK R - EXT GND Logic input waveform VIH=VDD V IL=GND SDO OUT0 Function Generator . . . OUT15 IOL I OH R ext Table 10. Symbol tSU0 tSU1 tSU2 tH0 tH1 tPD0 tPD1 tPD2 tDL1 tDL2 tDL3 tw(L) tw( CLK) tw(PWCLK) tON tOFF tEDD Switching characteristics (VDD = 5.0 V) TA = -40 ~ 125 °C Characteristics Conditions SDI - CLK ↑ Setup time LE ↑ – DCLK ↑ LE ↓ – DCLK ↑ CLK ↑ - SDI Hold time CLK ↑ - LE ↓ CLK - SDO Propagation delay time PWCLK-OUTn4 LE – Stagger delay time SDO(2) (1) Min. 1 1 5 3 7 Typ. Max. Unit ns ns ns ns ns OUTn4 + 1 (1) OUTn4 + 2 (1) OUTn4 +3 LE Pulse width CLK PWCLK Output rise time of output ports Output fall time of output ports Error detection minimum duration (3) (1) VDD = 5.0 V VIH = VDD VIL = GND Rext = 460 Ω VLED = 4.5 V RL = 152 Ω CL = 10 pF C1 = 100 nF C2 = 10 μF IO = 20 mA 30 100 30 40 80 120 5 20 20 10 6 1 40 ns ns 40 ns ns ns ns ns ns ns ns ns µs 1. Refer to the timing waveform, where n = 0, 1, 2, 3. 2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after the falling edge of LE. 3. Refer to Figure 5 on page 13. Doc ID 15819 Rev 4 11/35 Electrical characteristics STP1612PW05 Table 11. Symbol tSU0 tSU1 tSU2 tH0 tH1 tPD0 tPD1 tPD2 tDL1 tDL2 tDL3 tw(L) tw(CLK) tw(PWCLK) tON tOFF tDEC Switching characteristics (VDD = 3.3 V) Characteristics Conditions SDI - DCLK ↑ Setup time LE ↑ – DCLK ↑ LE ↓ – DCLK ↑ CLK ↑ - SDI Hold time CLK ↑ - LE ↓ Min. 1 1 5 3 7 45 120 45 40 80 120 5 20 20 11.6 7 0.5 1 40 40 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns μs CLK - SDO VDD = 3.3 V Propagation delay PWCLK-OUTn4(1) VIH = VDD time VIL = GND LE – SDO(2) Rext = 460 Ω VLED = 4.5 V OUTn4 + 1 (1) RL = 152 Ω Stagger delay OUTn4 + 2 (1) time CL = 10 pF OUTn4 +3 (1) C1 = 100 nF C2 = 10 μF LE Pulse width CLK PWCLK Output rise time of output ports Output fall time of output ports Error detection duration 1. Refer to the timing waveform Figure 4, where n = 0, 1, 2, 3. 2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after the falling edge of LE. Figure 4. Test circuit for switching characteristics IDD V DD C1 I OUT VIH,VIL VDD SDI CLK LE P W CLK R - E XT GND Logic input w aveform VIH=VDD VIL=G ND SDO O UT0 Function Generator . . . RL CL RL CL VL ED C2 O UT 15 Rext CL 12/35 Doc ID 15819 Rev 4 STP1612PW05 Timing waveform 5 Timing waveform Figure 5. Timing waveform PWCLK PWCLK PWCLK Doc ID 15819 Rev 4 13/35 Principle of operation STP1612PW05 6 Principle of operation Table 12. Control command Signals combination Command name Data latch Global latch Read configuration Enable “error detection” Read “error status code” Write configuration Reset to 16-bit shift register length LE High High High High High High High Number of CLK rising edge when LE is asserted 1 2 or 3 4 or 5 6 or 7 8 or 9 10 or 11 12 or 13 Description The action after a falling edge of LE Serial data are transferred to the buffers Buffer data are transferred to the comparators Move out “configuration register” to the shift register Detect the status of each output’s LED Move out “error status code” of 16 outputs to the shift registers Serial data are transferred to the “configuration register” Set to 16-bit the shift register length 14/35 Doc ID 15819 Rev 4 STP1612PW05 Figure 6. Timing diagram Principle of operation Doc ID 15819 Rev 4 15/35 Definition of configuration register STP1612PW05 7 Definition of configuration register Configuration register MSB F E D C B A 9 8 7 6 5 4 3 2 1 LSB 0 Default value MSB F X E 0 D 1 C 11 B A 1 9 8 7 6 5 4 3 2 1 0 LSB 0 0 8’b10101011 Table 13. Bit F Configuration register Definition Shift register length Thermal error flag PWM counter: 16-bit or 12-bit Value Function Attribute Read/Write 0 (default) Shift register length 0 = 16-bit,1 = 256-bit 0 (default) Safe (OK) 1 0 (default) 00 Over temperature (>150 °C typ.) To set the gray scale mode (PWM): 0 = 12-bit 1 = 16-bit 64 times of MSB(1) 6-bit PWM counting plus once of LSB(1) 6-bit PWM counting 16 times of MSB 6-bit PWM counting by 1/4 PWCLK plus once of LSB 6-bit PWM counting 4 times of MSB 6-bit PWM counting by 1/16 PWCLK plus once of LSB 6-bit PWM counting E Read D Read/Write C Read/Write B PWM counting mode selection 01 10 11 (default) PWM counting A Read/Write PWM data synchronization mode Current gain adjustment 0 Auto-synchronization 1 (default) Manual synchronization 00000000 ~ 8’b10101011 (default) 11111111 0 (default) Disable 9~2 Read/Write 1 Read/Write TSD thermal shutdown 1 Enable (2) the output channel turn OFF if TTF > 150 °C 0 Time-out alert of Read/Write PWCLK disconnection 0 (default) Enable (3) 1 Disable 1. Please refer to “setting the PWM counting mode” section. 2. Please refer to “TSD” thermal error flag and thermal shutdown “section. 3. Please refer to “time-out alert of PWCLK disconnection” section. 16/35 Doc ID 15819 Rev 4 STP1612PW05 Grey scales data loading 8 Grey scales data loading The STP1612PW05 is able to manage a gray-scale depth of 12 or 16 bits for each output, exploiting an e-PWM algorithm. The bit D of the configuration register is used to select the grey-scale loading. Its value can be set to “0” for 12 bits or “1” for 16 bits. By default, D is set to “0”. Loading of the data is performed through the serial input on a dedicated buffer and two different methods can be used. With both methods, the first incoming data packet is relative to the output 15; the following packet is relative to the output 14 and so on up to the output 0. If F=”0”, when a data packet has been loaded, the latch signal (LE) must become active for one CLK cycle (data latch). When the last data packet, relative to the output 0, has been loaded, the latch signal must be active for two CLK cycles (global latch) and all the data will be transferred to the e-PWM registers starting from the MSB. If F=”1” all data packets (12 or 16 bits x16) are loaded and then the global latch signal must be active and all the data will be transferred to the e-PWM registers starting from the MSB. Figure 7. Full timing for data loading Doc ID 15819 Rev 4 17/35 Setting the PWM gray scale counter STP1612PW05 9 Setting the PWM gray scale counter STP1612PW05 provides a 12-bit or 16-bit PWM color depth. Each serial data input will be implemented according to the e-PWM algorithm. 9.1 PWM data synchronization STP1612PW05 defines the different counting algorithms that support e-PWM, technology, (scrambled PWM). With e-PWM, the total PWM cycles can be broken down into MSB (most significant bits) and LSB (least significant bits) of gray scale cycles, and the MSB information can be dithered across many refresh cycles to achieve overall same high bit resolution. STP1612PW05 also allows changing different counting algorithms and provides the best output linearity when there are fewer transitions of output. Figure 8. 12-bit e-PWM operation example PWCLK PWCLK PWCLK PWCLK PWCLK 18/35 Doc ID 15819 Rev 4 STP1612PW05 Setting the PWM gray scale counter 9.2 Synchronization for PWM counting The data synchronization between the incoming data flow and the output channels is managed through the bit A within the configuration register. If the bit A is set to “0” the device performs itself the data synchronization: when all the new data are loaded with a “global latch”, the device wait until all the PWM counter completes the counting cycle before updating them with the new data, at the next CLK rising edge. Conversely, if bit A is set to “1” (default), the data synchronization is not performed by the device and is managed by the microcontroller, which has to take care of the data and signals. If this is not done, there might be artefacts on the output image. Figure 9. Synchronization for PWM counting CLK PWCLK Figure 10. Without synchronization for PWM counting CLK PWCLK Doc ID 15819 Rev 4 19/35 Error detection conditions STP1612PW05 10 Error detection conditions The STP1612PW05 can detect open channels (OD) and LED short-circuits (SD). The detection circuitry performs open- and short-circuit detection simultaneously and the image quality will not be impacted since the test duration is short (0.5 µs typ). To perform the open-circuit, short-circuit error detection a channel must be on, the command “enable error detection” starts the detection. After 0.5 µs (typ) the command “read error status code” allows to get the status from the serial output (SDO). Table 14. Detection conditions (VDD = 3.3 to 5 V temp. range -40 to 125 °C) Open line or output short to GND detected Short on LED or short to V-LED detected ==> IODEC ≤ 0.5 x IO ==> VO ≥ 2.3 V SW-1 or SW-3b SW-2 or SW-3a Note: Where: IO = the output current programmed by the REXT, IODEC = the detected output current in detection mode Figure 11. Detection circuit 16 STP1612PW05 20/35 Doc ID 15819 Rev 4 STP1612PW05 Setting output current 11 Setting output current The output current (IOUT) is set by an external resistor, Rext. It is calculated from the equation: VR-EXT = 1.24 x G; IOUT = (VR-EXT/Rext) x 560 Whereas Rext is the resistance of the external resistor connected to R-EXT terminal and VR-EXT is its voltage. G is the digital current gain, which is set by the bit9 – bit2 of the configuration register. The default value of G is 1. For your information, the output current is about 20 mA when Rext = 34.70 kΩ and 10 mA when Rext = 69.6 kΩ if G is set to default value 1. The formula and setting for G are described in next section. Figure 12. Rext vs output current 275 250 225 200 175 150 125 100 75 50 25 0 3 5 10 20 30 50 60 80 Iout (mA) Table 15. Rext vs output current (1) Iout (mA) 3 5 10 20 30 50 60 80 Rext (kΩ) 238.2 142.2 69.6 34.70 22.94 13.72 11.40 8.63 1. TA = 25 °C, Vdd = 3.3 V; 5.0 V, VLed = 3.0 V, Vdrop = 1.5 V, HC = 0101011 (default) Rext (kOhm) Doc ID 15819 Rev 4 21/35 Current gain adjustment STP1612PW05 12 Current gain adjustment Figure 13. Gain vs DA6 - DA0 The bit 9 to bit 2 of the configuration register set the gain of output current, i.e., G. Being 8bit in total, ranging from 8’b00000000 to 8’b11111111, these bits allow the user to set the output current gain up to 256 levels. These bits can be further defined in the configuration register as follows: Configuration register MSB F E D C B A 9 HC 8 DA6 7 DA5 6 DA4 5 DA3 4 DA2 3 DA1 2 DA0 1 LSB 0 - 1. 2. Bit 9 is HC bit. The setting is in the low current range when HC=0, and in the high current range when HC=1. Bit 8 to bit 2 are DA6 ~ DA0. The relationship between these bits and current gain G is: HC = 1, D = (256G-128)/3 HC = 0, D = (1024G-128)/3 and D in the above decimal numeration can be converted to its equivalent in binary form by the following equation: D = DA6x26 + DA5x25 + DA4x24 + DA3x23 + DA2x22 + DA1x21 + DA0x20 In other words, these bits can be looked as a floating number with 1-bit exponent HC and 7bit mantissa DA6~DA0. 22/35 Doc ID 15819 Rev 4 STP1612PW05 For example, HC = 1, G = 1.25, D = (256x1.25-128)/3 = 64 the D in binary form would be: D = 64 = 1x26+0x25+0x24+0x23+0x22+0x21+0x20 Delay time of staggered output The bit 9 to bit 2 of the configuration register are set to 8’b1100,0000. 13 Delay time of staggered output This feature prevents large inrush current from the power line and reduces the bypass capacitors. The outputs are organized in four groups OUT4n, OUT4n+1, OUTn4+2, OUT4n+3 and each group has 40 ns delay between the previous one. E.g.: OUT4n has no delay, OUTn4+1 has 40ns delay, OUTn4+2 has 80ns delay, OUTn4+3 has 120 ns delay. 14 Thermal protection Thermal flag provides an indication about the status of the junction temperature. When the junction temperature reaches 150 °C the bit E of the configuration register is set to “1”, signaling dangerous operating condition. This flag is useful when thermal shutdown function is disabled. The thermal shutdown function, if activated by configuration register, turns-off all output channels if the junction exceeds 150 °C. As soon as the junction temperature is below 140 °C the outputs channels will be turned ON. In thermal shutdown mode, the digital core is active and data flow is guaranteed. Doc ID 15819 Rev 4 23/35 Time-out alert of GCLK disconnection STP1612PW05 15 Time-out alert of GCLK disconnection When the PWCLK signal is disconnected for around 1 second, all output ports will be turned off automatically. This function will protect the LED display system from staying ON indefinitely and prevent excessive current from damaging the power system. The default is set to ‘enable” when bit “0” is 0. When the PWCLK is active again and new serial data are moved in, the driver resumes to work after resetting the internal counters and comparators. Figure 14. Time-out alert application scheme PWCLK 500K STP1612PW05 STP1612PW05 STP1612PW05 STP1612PW05 24/35 Doc ID 15819 Rev 4 STP1612PW05 Package mechanical data 16 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 16. Dim. Min. A A1 A2 b c D E e H K L 6.25 0° 0.50 0.19 0.09 7.7 4.3 0.65 BSC 6.5 8° 0.70 0.246 0° 0.020 0.05 0.9 0.30 0.20 7.9 4.5 0.0075 0.0035 0.303 0.169 0.0256 BSC 0.256 8° 0.028 Typ Max. 1.1 0.15 0.002 0.035 0.0118 0.0079 0.311 0.177 Min. Typ. Max. 0.043 0.006 TSSOP24 mechanical data mm. inch Figure 15. TSSOP24 package dimensions Doc ID 15819 Rev 4 25/35 Package mechanical data Table 17. Dim. Min. A C D N T Ao Bo Ko Po P 6.8 8.2 1.7 3.9 11.9 12.8 20.2 60 Typ 22.4 7 8.4 1.9 4.1 12.1 0.268 0.323 0.067 0.153 0.468 Max. 330 13.2 0.504 0.795 2.362 Min. Typ. - STP1612PW05 TSSOP24 tape and reel mm. inch Max. 12.992 0.519 0.882 0.276 0.331 0.075 0.161 0.476 Figure 16. TSSOP24 reel dimensions 26/35 Doc ID 15819 Rev 4 STP1612PW05 Table 18. Dim. Min. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 0.291 0.020 °(max.) 8 15.60 10.65 0.35 0.23 0.5 45°(typ.) 0.598 0.393 0.1 Typ Max. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.004 Min. Package mechanical data SO-24 mechanical data mm. inch Typ. Max. 0.104 0.008 0.096 0.019 0.012 0.020 0.614 0.419 0.050 0.550 0.300 0.050 Doc ID 15819 Rev 4 27/35 Package mechanical data Figure 17. SO-24 package dimensions STP1612PW05 28/35 Doc ID 15819 Rev 4 STP1612PW05 Table 19. Dim. Min. A C D N T Ao Bo Ko Po P 10.8 15.7 2.9 3.9 11.9 12.8 20.2 60 Typ 30.4 11.0 15.9 3.1 4.1 12.1 0.425 0.618 0.114 0.153 0.468 Max. 330 13.2 0.504 0.795 2.362 Min. Package mechanical data SO-24 tape and reel mm. inch Typ. 1.197 0.433 0.626 0.122 0.161 0.476 Max. 12.992 0.519 Figure 18. SO-24 reel dimensions Doc ID 15819 Rev 4 29/35 Package mechanical data Table 20. Dim. Min. A A1 Typ. Max. 1.2 0.15 0.004 Min. Typ. STP1612PW05 TSSOP24 exposed pad mm inch Max. 0.047 0.006 A2 b c D D1 E E1 E2 e K L 0.8 0.19 0.09 7.7 4.7 6.2 4.3 2.9 1 1.05 0.30 0.20 0.031 0.007 0.004 0.303 0.185 0.244 0.169 0.114 0.039 0.041 0.012 0.0089 7.8 5.0 6.4 4.4 3.2 0.65 7.9 5.3 6.6 4.5 3.5 0.307 0.197 0.252 0.173 0.126 0.0256 0.311 0.209 0.260 0.177 0.138 0° 0.45 0.60 8° 0.75 0° 0.018 0.024 8° 0.030 Figure 19. TSSOP24 package dimensions 30/35 Doc ID 15819 Rev 4 STP1612PW05 Package mechanical data Table 21. Dim. QFN24 (4x4) mechanical data mm. Min. Typ Max. 1.00 0.00 0.18 3.9 2.6 3.9 2.6 0.50 0.40 0.60 15.7 0.05 0.30 4.1 2.8 4.1 2.8 0.0 7.1 153.5 76.8 153.5 76.8 19.7 23.6 Min. mils Typ. Max. 39.4 2.0 11.8 161.4 88.6 161.4 88.6 A A1 b D D2 E E2 e L Doc ID 15819 Rev 4 31/35 Package mechanical data Figure 20. QFN24 (4x4) mechanical drawing STP1612PW05 32/35 Doc ID 15819 Rev 4 STP1612PW05 Package mechanical data Tape & Reel QFNxx/DFNxx (4x4) MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 4.35 4.35 1.1 4 8 12.8 20.2 99 101 14.4 0.171 0.171 0.043 0.157 0.315 TYP MAX. 330 13.2 0.504 0.795 3.898 3.976 0.567 MIN. TYP. MAX. 12.992 0.519 inch Doc ID 15819 Rev 4 33/35 Revision history STP1612PW05 17 Revision history Table 22. Date 17-Jun-2009 10-Aug-2009 29-Oct-2009 18-Dec-2009 Document revision history Revision 1 2 3 4 Initial release. Updated Section 9.2 on page 19 and Table 12 on page 14 Updated: Figure 2 on page 6 and Table 21 on page 31 Added: Figure 14 on page 24 Updated Section 11 on page 21 Changes 34/35 Doc ID 15819 Rev 4 STP1612PW05 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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