STP16CPS05M

STP16CPS05 Low voltage 16-bit constant current LED sink driver with auto power saving Datasheet - production data Description The STP16CPS05 is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The STP16CPS05 contains a 16-bit serial-in, parallel-out shift register that feeds a 16-bit, D-type storage register. In the output stage, sixteen regulated current sources provide from 5 mA to 100 mA constant current to drive the LEDs. The auto power shut-down and auto power-ON feature allows the device to save power without any external intervention. The output current setup time is 40 ns (typ.), thus improving the system performance. The LEDs' brightness can be controlled by using an external resistor to adjust the STP16CPS05 output current. The STP16CPS05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, makes the device suitable for high data rate transmission. The 3.3 V voltage supply is useful in applications that interface with a 3.3 V microcontroller. Features          Low voltage power supply down to 3 V 16 constant current output channels Adjustable output current through external resistor Serial data IN/parallel data OUT Auto power-saving feature minimizes the quiescent current if no active data is detected on the latches Can be driven by a 3.3 V microcontroller Output current: 5-100 mA Max clock frequency 30 MHz ESD protection: 2 kV HBM, 200 V MM Table 1: Device summary Order code Package Packing STP16CPS05MTR SO-24 1000 parts per reel STP16CPS05TTR TSSOP24 2500 parts per reel STP16CPS05XTTR TSSOP24 exposed pad 2500 parts per reel STP16CPS05PTR QSOP-24 2500 parts per reel March 2017 DocID12569 Rev 8 This is information on a product in full production. 1/31 www.st.com Contents STP16CPS05 Contents 1 Summary description ...................................................................... 3 1.1 2 Pin connection and description ......................................................... 3 Electrical ratings ............................................................................. 4 2.1 Absolute maximum ratings ................................................................ 4 2.2 Thermal data ..................................................................................... 4 2.3 Recommended operating conditions ................................................. 5 3 Electrical characteristics ................................................................ 6 4 Equivalent circuit and outputs ....................................................... 8 5 Timing diagrams ............................................................................ 11 6 Typical characteristics .................................................................. 14 7 Test circuit ..................................................................................... 18 8 Package information ..................................................................... 20 8.1 QSOP-24 package information ....................................................... 21 8.2 SO-24 package information ............................................................ 23 8.3 TSSOP24 package information ....................................................... 24 8.4 TSSOP24 exposed pad package information ................................. 26 8.5 TSSOP24, TSSOP24 exposed pad and ............................................ SO-24 packing information .............................................................. 28 9 2/31 Revision history ............................................................................ 30 DocID12569 Rev 8 STP16CPS05 1 Summary description Summary description Table 2: Typical current accuracy Current accuracy Output voltage Between bits Between ICs ± 1.5 % ±5% ≥ 1.3 V 1.1 Output current VDD Temperature 20 to 100 mA 3.3 V to 5 V 25 °C Pin connection and description Figure 1: Pin connection The exposed pad should be electrically connected to a metal land electrically isolated or connected to GND. Table 3: Pin description Pin n° Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal 4 LE Latch input terminal 5-20 OUT 0-15 21 OE Input terminal of output enable (active low) 22 SDO Serial data out terminal 23 R-EXT 24 VDD Output terminal Input terminal for an external resistor for constant current programming Supply voltage terminal DocID12569 Rev 8 3/31 Electrical ratings STP16CPS05 2 Electrical ratings 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 4: Absolute maximum ratings Symbol Parameter Value Unit VDD Supply voltage 0 to 7 V VO Output voltage -0.5 to 20 V IO Output current 100 mA VI Input voltage IGND GND terminal current fCLK Clock frequency TJ Junction temperature range(1) -0.4 to VDD V 1600 mA 50 MHz -40 to +170 °C Value Unit -40 to + 125 °C Notes: (1) 2.2 Such absolute value is achieved according the thermal shutdown. Thermal data Table 5: Thermal data Symbol Parameter TOPR Operating temperature range TSTG Storage temperature range RthJA Thermal resistance junction-ambient(1) -55 to + 150 SO-24 42.7 °C/W TSSOP24 55 °C/W 37.5 °C/W 55 °C/W TSSOP24(2) exposed pad QSOP-24 Notes: 4/31 (1) According to jedec standard 51-7B. (2) The exposed pad should be soldered directly to the PCB to realize the thermal benefits. DocID12569 Rev 8 °C STP16CPS05 2.3 Electrical ratings Recommended operating conditions Table 6: Recommended operating conditions at 25 °C Symbol Parameter Test conditions Min. 3.0 Typ. Max. Unit 5.5 V 20 V 100 mA VDD Supply voltage VO Output voltage IO Output current OUTn IOH Output current SERIAL-OUT +1 mA IOL Output current SERIAL-OUT -1 mA VIH Input voltage 0.7 VDD VDD V VIL Input voltage -0.3 0.3 VDD V 5 twLAT LE pulse width 10 ns twCLK CLK pulse width 8 ns 100 ns twEN OE pulse width VDD = 3.0 V to 5.0 V tSETUP(D) Setup time for DATA 14 ns tHOLD(D) Hold time for DATA 5 ns tSETUP(L) Setup time for LATCH 15 ns fCLK Clock frequency Cascade operation (1) 30 MHz Notes: (1) If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully. DocID12569 Rev 8 5/31 Electrical characteristics 3 STP16CPS05 Electrical characteristics Table 7: Electrical characteristics (VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified) Symbol VIH Parameter Test conditions Input voltage high level Min. Typ. Max. Unit 0.7 VDD VDD V GND 0.3 VDD V VIL Input voltage low level IOH Output leakage current VOH = 20 V 10 μA VOL Output voltage (serial-OUT) IOL = 1 mA 0.4 V VOH Output voltage (serial-OUT) IOH = -1 mA VDD-0.4V V VO = 0.3 V, Rext = 3.9 kΩ 4.25 5 5.75 VO = 0.3 V, Rext = 970 Ω 19 20 21 IOL3 VO = 1.3 V, Rext = 190 Ω 96 100 104 ΔIOL1 VO = 0.3 V, Rext = 3.9 kΩ ±5 ±8 VO = 0.3 V, Rext = 970 Ω ± 1.5 ±3 VO = 1.3 V, Rext = 190 Ω ± 1.2 ±3 IOL1 IOL2 ΔIOL2 Output current Output current error between bit (all output ON) ΔIOL3 mA % Pull-up resistor 150 300 600 kΩ RSIN(down) Pull-down resistor 100 200 400 kΩ Shut-down current all latched data = L VDD = 3.3 V 120 170 IDD(SH) VDD = 5 V 140 200 RSIN(up) Rext = 970 OUT 0 to 15 = OFF 5 IDD(OFF2) Rext = 240 OUT 0 to 15 = OFF 12.5 IDD(ON1) Rext = 970 OUT 0 to 15 = ON 5.5 Rext = 240 OUT 0 to 15 = ON 13 IDD(OFF1) Supply current (OFF) Supply current (ON) IDD(ON2) Thermal 6/31 Thermal protection mA 170 DocID12569 Rev 8 μA °C STP16CPS05 Electrical characteristics Table 8: Switching characteristics Symbol Parameter Test conditions Typ. Max. 35 55 VDD = 5 V 17.5 26 Propagation delay time, VDD = 3.3 V 33.5 52 LE- OUTn , OE = L VDD = 5 V 17 20 Propagation delay time, VDD = 3.3 V 53.5 84.5 OE - OUTn , LE = H VDD = 5 V 28.5 40.5 VDD = 3.3 V 19 27.5 VDD = 5 V 13 18.5 VDD = 3.3 V 13 19 VDD = 5 V 8.5 Propagation delay time, tPLH1 VDD = 3.3 V CLK- OUTn , LE = H, OE = L tPLH2 tPLH3 tPLH Propagation delay time, CLK-SDO Propagation delay time, tPHL1 CLK- OUTn , LE = H, OE = L Propagation delay time, tPHL2 tPHL3 Min. VIH = VDD VIL = GND CL = 10 pF IO = 20 mA VL = 3.0 V Rext = 1 KΩ RL = 60 Ω VDD = 3.3 V 10 14.5 VDD = 5 V 6.5 9 Propagation delay time, VDD = 3.3 V 10.5 15 VDD = 5 V 7.5 10.5 23 33 Propagation delay time, CLK-SDO VDD = 3.3 V VDD = 5 V 15.5 21.5 Output rise time 10~90% of voltage waveform VDD = 3.3 V 23.5 31.5 tON 9 10.5 tOFF Output fall time 90~10% of voltage waveform VDD = 3.3 V 4.6 5.5 VDD = 5 V 3.5 5 tf VDD = 5 V CLK rise time (1) CLK fall time ns ns ns ns tPHL tr ns 12 LE -OUTn , OE = L OE - OUTn , LE = H Unit (1) ns ns ns ns ns 5000 ns 5000 ns Notes: (1) In order to achieve high cascade data transfer, please consider tr/tf timings carefully. DocID12569 Rev 8 7/31 Equivalent circuit and outputs 4 STP16CPS05 Equivalent circuit and outputs Figure 2: OE/DM2 terminal Figure 3: LE/DM1 terminal 8/31 DocID12569 Rev 8 STP16CPS05 Equivalent circuit and outputs Figure 4: CLK, SDI terminal Figure 5: SDO terminal DocID12569 Rev 8 9/31 Equivalent circuit and outputs STP16CPS05 Figure 6: Block diagram 10/31 DocID12569 Rev 8 STP16CPS05 5 Timing diagrams Timing diagrams Table 9: Truth table CLOCK LE OE SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO _|¯ H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 _|¯ L L Dn + 1 No change Dn - 14 _|¯ H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X H Dn + 3 OFF Dn - 13 OUTn = ON when Dn = H OUTn = OFF when Dn = L. Figure 7: Timing diagram 1 Latch and output enable terminals are Level-sensitive and are not synchronized with rising or falling edge of CLK signal. 2 When LE terminal is at low level, the latch circuit holds previous set of data. 3 When LE terminal is at high level, the latch circuit refreshes new set of data from SDI chain. 4 When OE is at low level the output terminals Out 0 to Out 15 respond to data in the latch circuits, either '1' for ON or '0' for OFF. 5 When OE is at high level, all output terminals are switched OFF. DocID12569 Rev 8 11/31 Timing diagrams STP16CPS05 Table 10: Truth table CLOCK LE SDI0 ........... SDI7 ............ SDI15 SH Auto power-up OUTn _|¯ H All = L Active Not active OFF _|¯ L No change No change No change No change _|¯ H One or more = H Not active Active X At the power-up the device starts in shut-down mode. Figure 8: Clock, serial-in, serial-out 12/31 DocID12569 Rev 8 STP16CPS05 Timing diagrams Figure 9: Clock, serial-in, latch, enable, outputs Figure 10: Outputs DocID12569 Rev 8 13/31 Typical characteristics 6 STP16CPS05 Typical characteristics Figure 11: Output current-R-EXT resistor Table 11: Output current-R-EXT resistor 14/31 R-EXT (Ω) Output current (mA) 976 20 780 25 652 30 560 35 488 40 433 45 389 50 354 55 325 60 300 65 278 70 259 75 241 80 229 85 215 90 DocID12569 Rev 8 STP16CPS05 Typical characteristics Figure 12: Output current vs ± ΔIOL(%) Figure 13: ISET vs drop out voltage (Vdrop) DocID12569 Rev 8 15/31 Typical characteristics STP16CPS05 Figure 14: IDD ON\OFF Figure 15: Auto power saving Auto power-saving feature minimizes the quiescent current if no active data is detected on the latches and auto-power-up the device at fist active data latched. 16/31 DocID12569 Rev 8 STP16CPS05 Typical characteristics Figure 16: First output ON after switching from auto power saving to normal mode operating condition When the device goes from auto power saving to normal operative condition, the first output that switch ON shows TON condition as seen in the plot above. DocID12569 Rev 8 17/31 Test circuit 7 STP16CPS05 Test circuit Figure 17: DC characteristic Figure 18: AC characteristic 18/31 DocID12569 Rev 8 STP16CPS05 Test circuit Figure 19: Typical application schematic VL will be determined by the VF of the LEDs. Figure 20: Turn ON output current characteristics(1) Figure 21: Turn OFF output current characteristics(2) Notes: (1) Reference level for the TON characteristics is 50 % of OE signal to 90 % of output current. (2) Reference level for the TOFF characteristics is 50 % of OE signal to 10 % of output current. DocID12569 Rev 8 19/31 Package information 8 STP16CPS05 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 20/31 DocID12569 Rev 8 STP16CPS05 8.1 Package information QSOP-24 package information Figure 22: QSOP-24 package outline DocID12569 Rev 8 21/31 Package information STP16CPS05 Table 12: QSOP-24 mechanical data mm Dim. Min. Typ. Max. A 1.54 1.62 1.73 A1 0.10 0.15 0.25 A2 1.47 b 0.20 0.31 c 0.17 0.254 D 8.56 8.66 8.76 E 5.80 6.00 6.20 E1 3.80 3.91 4.01 e 22/31 0.635 L 0.40 0.635 0.89 h 0.25 0.33 0.41 < 0° DocID12569 Rev 8 8° STP16CPS05 8.2 Package information SO-24 package information Figure 23: SO-24 package outline DocID12569 Rev 8 23/31 Package information STP16CPS05 Table 13: SO-24 mechanical data mm Dim. Min. Typ. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 15.20 15.60 E 7.40 e 7.60 1.27 H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 k 0 8 ddd 8.3 0.10 TSSOP24 package information Figure 24: TSSOP24 package outline 24/31 Max. DocID12569 Rev 8 STP16CPS05 Package information Table 14: TSSOP24 mechanical data mm Dim. Min. Typ. A A1 Max. 1.1 0.05 A2 0.15 0.9 b 0.19 0.30 c 0.09 0.20 D 7.7 7.9 E 4.3 4.5 e 0.65 BSC H 6.25 6.5 K 0° 8° L 0.50 0.70 DocID12569 Rev 8 25/31 Package information 8.4 STP16CPS05 TSSOP24 exposed pad package information Figure 25: TSSOP24 exposed pad package outline 26/31 DocID12569 Rev 8 STP16CPS05 Package information Table 15: TSSOP24 exposed pad mechanical data mm Dim. Min. Typ. Max. A 1.20 A1 0.15 A2 0.80 1.00 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.80 7.90 D1 4.80 5.00 5.2 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 E2 3.00 3.20 3.40 e L 0.65 0.45 L1 k 060 075 1.00 0° aaa 8° 0.10 DocID12569 Rev 8 27/31 Package information 8.5 STP16CPS05 TSSOP24, TSSOP24 exposed pad and SO-24 packing information Figure 26: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline Table 16: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm Dim. Min. A Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T 28/31 Typ. - 22.4 Ao 6.8 - 7 Bo 8.2 - 8.4 Ko 1.7 - 1.9 Po 3.9 - 4.1 P 11.9 - 12.1 DocID12569 Rev 8 STP16CPS05 Package information Table 17: SO-24 tape and reel mechanical data mm Dim. Min. A Typ. Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T - 30.4 Ao 10.8 - 11.0 Bo 15.7 - 15.9 Ko 2.9 - 3.1 Po 3.9 - 4.1 P 11.9 - 12.1 DocID12569 Rev 8 29/31 Revision history 9 STP16CPS05 Revision history Table 18: Document revision history Date Revision 28-Jul-2006 1 First release 22-Dec-2006 2 Final datasheet 17-May-2007 3 Updated Table 8 on page 8 10-Jul-2007 4 Updated Table 9: Truth table on page 11 28-Feb-2008 5 Updated Table 19: TSSOP24 exposed pad on page 25 Added QSOP-24 package information Table 14 and Figure 20 on page 21 19-Jan-2010 6 Updated Table 6 on page 6 7 Updated Section 8: Package mechanical data. Added Section 9: Packaging mechanical data. Minor text changes. 8 Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in, serialout", Figure 9: "Clock, serial-in, latch, enable, outputs" and Section 8.1: "QSOP-24 package information". Minor text changes. 17-Jun-2014 24-Mar-2017 30/31 Changes DocID12569 Rev 8 STP16CPS05 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID12569 Rev 8 31/31