STP16DPS05

STP16DPS05 Low voltage 16-bit constant current LED sink driver with outputs error detection Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low voltage power supply down to 3 V 16 constant current output channels Adjustable output current through external resistor Short and open output error detection Serial data IN/Parallel data OUT 3.3 V micro driver-able Output current: 20-85 mA 30 MHz clock frequency Available in high thermal efficiency TSSOP exposed pad ESD protection 2.0 kV HBM, 200 V MM TSSOP24 TSSOP24 (exposed pad) QSOP-24 SO-24 The data detection results are loaded in the shift register and shifted out via the serial line output. The detection functionality is implemented without increasing the pin count number, through a secondary function of the LATCH and output enable pin (DM1 and DM2 respectively), a dedicated logic sequence allows the device to enter or leave from detection mode. Through an external resistor, users can adjust the STP16DPS05 output current, controlling in this way the light intensity of LEDs, in addition, user can adjust LED’s brightness intensity from 0% to 100% via OE/DM2 pin. The STP16DPS05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, makes the device suitable for high data rate transmission. The 3.3 V voltage supply is well useful for applications that interface any 3.3V micro. Compared with a standard TSSOP package, the TSSOP exposed pad increases heat dissipation capability by a 2.5 factor. Packaging 1000 parts per reel 2500 parts per reel 2500 parts per reel 2500 parts per reel Description The STP16DPS05 is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The device contains a 16-bit serial-in, parallel-out shift register that feeds a 16-bit D-type storage register. In the output stage, sixteen regulated current sources were designed to provide 5-100 mA constant current to drive the LEDs. The STP16DP05 features open and short LED detections on the outputs.The STP16DP05 is backward compatible with STP16C/L596.The detection circuit checks 3 different conditions that can occur on the output line: short to GND, short to VO or open line. Table 1. Device summary Order codes STP16DPS05MTR STP16DPS05TTR STP16DPS05XTTR STP16DP05PTR Package SO-24 (tape and reel) TSSOP24 (tape and reel) TSSOP24 exposed pad (tape and reel) QSOP-24 January 2010 Doc ID 16538 Rev 2 1/34 www.st.com 34 Contents STP16DPS05 Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4 5 6 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 7.2 7.3 7.4 7.5 Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 16 Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 19 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Auto power-saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/34 Doc ID 16538 Rev 2 STP16DPS05 Summary description 1 Summary description Table 2. Typical current accuracy Current accuracy Output voltage Between bits ≥ 1.3 V ±1.5% Between ICs ±5% 20 to 100 mA 3.3 V to 5 V 25 °C Output current VDD Temperature 1.1 Pin connection and description Figure 1. Pin connection LE/DM1 Note: The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground. Table 3. Pin n° 1 2 3 4 5-20 21 22 23 24 Pin description Symbol GND SDI CLK LE/DM1 OUT 0-15 OE/DM2 SDO R-EXT VDD Ground terminal Serial data input terminal Clock input terminal Latch input terminal - detect mode 1 (see operation principle) Output terminal Input terminal of output enable (active low) - detect mode 1 (see operation principle) Serial data out terminal Input terminal of an external resistor for constant current programing Supply voltage terminal Name and function Doc ID 16538 Rev 2 3/34 Electrical ratings STP16DPS05 2 2.1 Electrical ratings Absolute maximum ratings Stressing the device above the rating listed in the Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Symbol VDD VO IO VI IGND fCLK TJ Supply voltage Output voltage Output current Input voltage GND terminal current Clock frequency Junction temperature range (1) Absolute maximum ratings Parameter Value 0 to 7 -0.5 to 20 100 -0.4 to VDD 1600 50 -40 to +170 Unit V V mA V mA MHz °C 1. Such absolute value is achieved according the thermal shutdown 2.2 Thermal data Table 5. Symbol TOPR TSTG Thermal data Parameter Operating temperature range Storage temperature range SO-24 TSSOP24 Thermal resistance junctionambient (1) Value -40 to +125 -55 to +150 42.7 55 37.5 55 Unit °C °C °C/W °C/W °C/W °C/W RthJA TSSOP24 exposed pad QSOP-24 (2) 1. According with JEDEC JESD51-7 2. The exposed pad should be soldered directly to the PCB to realize the thermal benefits. 4/34 Doc ID 16538 Rev 2 STP16DPS05 Electrical ratings 2.3 Recommended operating conditions Table 6. Symbol VDD VO IO IOH IOL VIH VIL twLAT twCLK twEN Recommended operating conditions Parameter Supply voltage Output voltage Output current Output current Output current Input voltage Input voltage LE/DM1 pulse width CLK pulse width OE/DM2 pulse width VDD = 3.0 V to 5.0 V OUTn SERIAL-OUT SERIAL-OUT 0.7VDD -0.3 6 8 100 10 5 10 Cascade operation (1) Test conditions Min. 3.0 Typ. - Max. 5.5 20 100 +1 -1 VDD+0.3 0.3 VDD Unit V V mA mA mA V V ns ns ns ns ns ns 5 - tSETUP(D) Setup time for DATA tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH fCLK Clock frequency 30 MHz 1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully. Doc ID 16538 Rev 2 5/34 Electrical characteristics STP16DPS05 3 Electrical characteristics VDD = 5 V, T = 25 °C, unless otherwise specified Table 7. Symbol VIH VIL IOH VOL VOH IOL1 IOL2 IOL3 ΔIOL1 ΔIOL2 ΔIOL3 RSIN(up) Electrical characteristics Parameter Input voltage high level Input voltage low level Output leakage current Output voltage (Serial-OUT) Output voltage (Serial-OUT) VOH = 20 V IOL = 1 mA IOH = -1 mA VO = 0.3 V, Rext = 3.9 kΩ Output current VO = 0.3 V, Rext = 970 Ω VO = 1.3 V, Rext = 190 Ω Output current error between bit (all output ON) Pull-up resistor VO = 0.3 VREXT = 3.9 kΩ VO = 0.3 VREXT = 970 Ω VO = 1.3 VREXT =190 Ω 150 100 REXT = 970 OUT 0 to 15 = OFF Supply current (OFF) REXT = 240 OUT 0 to 15 = OFF REXT = 970 OUT 0 to 15 = ON Supply current (ON) REXT = 240 OUT 0 to 15 = ON Thermal protection (1) VOH -VDD = -0.4 V 4.25 19 96 5 20 100 ±5 ± 1.5 ± 1.2 300 200 5 13 6 13.5 170 5.75 21 104 ±8 ±3 ±3 600 400 6 14 mA 7 14.5 °C KΩ KΩ % mA Test conditions Min. 0.7VDD GND Typ. Max. VDD 0.3VDD 1 0.4 Unit V V μA V V RSIN(down) Pull-down resistor IDD(OFF1) IDD(OFF2) IDD(ON1) IDD(ON2) Thermal 1. Guaranteed by design (not tested) The thermal protection switches OFF only the outputs current 6/34 Doc ID 16538 Rev 2 STP16DPS05 VDD = 5 V, T = 25 °C, unless otherwise specified Table 8. Symbol tPLH1 Electrical characteristics Switching characteristics Parameter Propagation delay time, CLK-OUTn, LE/DM1 = H, OE/DM2 = L Propagation delay time, LE/DM1 -OUTn, OE/DM2 = L Propagation delay time, OE/DM2-OUTn, LE/DM1 = H Propagation delay time, CLK-SDO Propagation delay time, CLK-OUTn, LE/DM1 = H, VIH = VDD OE/DM2 = L VIL = GND Propagation delay time, IO = 20 mA LE/DM1 -OUTn, REXT = 1 KΩ OE/DM2 = L Propagation delay time, OE/DM2-OUTn, LE/DM1 = H Propagation delay time, CLK-SDO Output rise time 10~90% of voltage waveform Output fall time 90~10% of voltage waveform CLK rise time (1) CLK fall time (1) Test conditions VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V CL = 10 pF VL = 3.0 V RL = 60 Ω VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V Min. - Typ. 40 to 44 20 to 44 51 32 49 to 57 27 to 32 21.5 to 22 14.5 to 15 15 to 18 11 to 13 13 to 18 9 to 12 11.5 to 12 8.5 to 10 25.5 17.5 to 20.5 34 to 20 12.5 to 9 Max. 44 Unit ns 44 77 ns 47 57 to 77 ns 32 to 41 32 ns 21.5 25 ns 14.5 to 16 18 to 25 ns 12.5 to 15 12 to 18 ns 9.7 to 12 38 ns 25 24 to 53.5 ns 9 to 18.5 ns tPLH2 tPLH3 tPLH tPHL1 tPHL2 tPHL3 tPHL tON 5.5 to 3.3 3.3 to 8.5 4.5 to 2.8 2.8 to 6.5 5000 5000 ns ns tOFF tr tf 1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully. Doc ID 16538 Rev 2 7/34 Equivalent circuit and outputs STP16DPS05 4 Equivalent circuit and outputs Figure 2. OE/DM2 terminal Figure 3. LE/DM1 terminal Figure 4. CLK, SDI terminal 8/34 Doc ID 16538 Rev 2 STP16DPS05 Figure 5. SDO terminal Equivalent circuit and outputs Figure 6. Block diagram Doc ID 16538 Rev 2 9/34 Timing diagrams STP16DPS05 5 Timing diagrams Table 9. CLOCK Truth table LE/DM1 H L H X X OE/DM2 L L L L H SERIAL-IN Dn Dn + 1 Dn + 2 Dn + 3 Dn + 3 OUT0 ............. OUT7 ................ OUT15 Dn ..... Dn - 7 ..... Dn -15 No change Dn + 2 ..... Dn - 5 ..... Dn -13 Dn + 2 ..... Dn - 5 ..... Dn -13 OFF SDO Dn - 15 Dn - 14 Dn - 13 Dn - 13 Dn - 13 Note: OUTn = ON when Dn = H OUTn = OFF when Dn = L Figure 7. Timing diagram Note: 1 2 3 4 5 Latch and output enable are level sensitive and ARE NOT synchronized with rising-or-falling edge of CLK signal. When LE/DM1 terminal is low level, the latch circuits hold previous set of data When LE/DM1 terminal is high level, the latch circuits refresh new set of data from SDI chain. When OE/DM2 terminal is at low level, the output terminals - Out0 to Out15 respond to data in the latch circuits, either '1' for ON or '0' for OFF When OE/DM2 terminal is at high level, all output terminals will be switched OFF. Doc ID 16538 Rev 2 10/34 STP16DPS05 Figure 8. Clock, serial-in, serial-out Timing diagrams Doc ID 16538 Rev 2 11/34 Timing diagrams Figure 9. Clock, serial-in, latch, enable, outputs STP16DPS05 LE/DM1 OE/DM2 Figure 10. Outputs 12/34 Doc ID 16538 Rev 2 STP16DPS05 Typical characteristics 6 Typical characteristics Figure 11. Output current-REXT resistor Table 10. Output current-REXT resistor Rext (Ω) 976 780 652 560 488 433 389 354 325 300 278 259 241 229 Output current (mA) 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Doc ID 16538 Rev 2 13/34 Typical characteristics STP16DPS05 Conditions: Temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA. Figure 12. ISET vs drop out voltage (Vdrop) 800 700 600 500 400 300 200 100 0 0 20 40 Iset mA) 60 80 Vdrop (mV) Avg @ 3.0V Avg @ 5.0V Table 11. ISET vs drop out voltage (Vdrop) Iout (mA) 3 5 10 20 50 80 Avg @ 3.0 V 19.33 36.67 77.33 158.67 406 692 Avg @ 5.0 V 22.66 40.33 80 157.33 406 668 14/34 Doc ID 16538 Rev 2 STP16DPS05 Typical characteristics Figure 13. IDD ON/OFF 14 12 10 Idd (mA) 8 6 4 2 0 0 10 20 30 40 50 Iset (mA) 60 70 80 90 IddON Avg @ 5.5V IddON Avg @ 3.6V IddOFF Avg @ 5.5V IddOFF Avg @ 3.6V Doc ID 16538 Rev 2 15/34 Detection mode functionality STP16DPS05 7 7.1 Detection mode functionality Phase one: “entering in detection mode“ From the “normal mode” condition the device can switch to the “error mode” by a logic sequence on the OE/DM2 and LE/DM1 pins as showed in the following table and diagram: Table 12. CLK OE/DM2 LE/DM1 Entering in detection truth table 1° H L 2° L L 3° H L 4° H H 5° H L Figure 14. Entering in detection timing diagram After these five CLK cycles the device goes into the “error detection mode” and at the 6th rise front of CLK the SDI data are ready for the sampling. 16/34 Doc ID 16538 Rev 2 STP16DPS05 Detection mode functionality 7.2 Phase two: “error detection” The 16 data bits must be set “1” in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the detection process. When the microcontroller switches the OE/DM2 to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred. Figure 15. Detection diagram The LEDs status will be detected at least in 1 microsecond and after this time the microcontroller sets OE/DM2 in HIGH state and the output data detection result will go to the microprocessor via SDO. Detection mode and normal mode use both the same format data. As soon as all the detection data bits are available on the serial line, the device may go back to normal mode of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode. Doc ID 16538 Rev 2 17/34 Detection mode functionality Figure 16. Timing example for open and/or short detection STP16DPS05 18/34 Doc ID 16538 Rev 2 STP16DPS05 Detection mode functionality 7.3 Phase three: “resuming to normal mode” The sequence for re-entering in normal mode is showed in the following table and diagram: Figure 17. Resuming to normal mode timing diagram CLK OE/DM2 LE/DM1 1° H L 2° L L 3° H L 4° H L 5° H L Note: For proper device operation the “Entering in detection” sequence must be follow by a “resume mode” sequence, it is not possible to insert consecutive equal sequence. 7.4 Error detection conditions VDD = 3.3 to 5 V temperature range -40 to 125 °C Table 13. SW-1 or SW-3b SW-2 or SW-3a Detection conditions Open line or output ==> IODEC ≤ 0.5 x IO short to GND detected Short on LED or short ==> VO ≥ 2.4 V to V-LED detected No error detected ==> IODEC ≥ 0.5 x IO ==> VO ≤ 2.2 V No error detected Note: Where: IO = the output current programmed by the REXT, IODEC = the detected output current in detection mode Figure 18. Detection circuit 16 STP16DP05 Doc ID 16538 Rev 2 19/34 Detection mode functionality Figure 19. Error detection sequence 16 CLK pulse are required to load the data setting 1 into shift register During During the error detection are necessary at least 2 CLK signal plus oneat the end STP16DPS05 Every CLK pulse shows the results of single Output results:Out15;14; 13 etc. etc LE/DM1 and OE/DM2 Key Sequence necessary to Enter in EDM The LE/DM1 pulse latch the data loaded during the previous state After OE/DM2 signal turn High the SDO pin show the results of Error Detection (Open or Short in this case) The OE/DM2 Pulse put the the device from EDM to Normal Mode 20/34 Doc ID 16538 Rev 2 STP16DPS05 Typical schematic used to perform the error detection: Figure 20. Error detection typical schematic Vdd Detection mode functionality Vled IDEC Iset Out REXT Rload DUT GND Using the follow formula is possible measure the Iodec IODEC = (Vled-Vload) / Rload The tables below shows the IODEC average value at 3.3 V and 5.0 V of power supply voltage. The IODEC is the current value recognized by the devices output open error detection Table 14. IODEC average value at 3.3 V Iset (mA) 5 10 3.3 20 50 80 Rext (Ω) 4270 2056 1006 382 251 Iout AVG (mA) 2.097 6.79 10.46 26.92 35.03 Vdd (V) Table 15. IODEC average value at 5 V Iset (mA) 5 10 5 20 50 80 Rext (Ω) 4270 2056 1006 382 251 Iout AVG (mA) 1.98 6.09 9.67 25.54 38.9 Vdd (V) Doc ID 16538 Rev 2 21/34 Detection mode functionality STP16DPS05 7.5 Auto power-saving The auto power-saving feature minimizes the quiescent current if no active data is detected on the latches and auto powers-up the device as the first active data is latched. Figure 21. Auto power-saving feature Conditions: Temp. = 25 °C, Vdd = 3.3 V, Vin = Vdd, VLed = 3.0 V, Iset = 20 mA Ch1 (Yellow) = IDD, Ch2 (Blue) = SDI, Ch3 (Purple) = LE/DM1, Ch4 (Green) = CLK Idd consumption: Idd (normal operation) = 5.15 mA Idd (shutdown condition) = 163 µA 22/34 Doc ID 16538 Rev 2 STP16DPS05 Figure 22. Delay LE-OUT Detection mode functionality After 16 clock cycles without data change, device will enter in Auto power save mode as expected. Delay TLE-OUT = 1.053 µs Conditions: Temp. = 25 °C, Vdd = 3.3 V, Vin = Vdd, VLed = 3.0 V, Iset = 20 mA Ch1 (Yellow) = CLK, Ch2 (Blue) = SDI, Ch3 (Purple) = LE/DM1, Ch4 (Green) = IOUT Doc ID 16538 Rev 2 23/34 Detection mode functionality Figure 23. Behaviour auto power saving STP16DPS05 Note: When the device goes from auto power-saving to normal operating condition, the first output that switches ON shows the TON condition as seen in the plot above. Temp. = 25°C, Vdd = 3.3 V, Vin = Vdd, VLed = 3.0 V, Iset = 20 mA Ch1 (Yellow) = IDD, Ch2 (Blue) = SDI, Ch3 (Purple) = LE/DM1, Ch4 (Green) = CLK 24/34 Doc ID 16538 Rev 2 STP16DPS05 Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark . Table 16. Dim. Min. A A1 A2 b c D E E1 e L h < 0.4 0.25 8° 0.31 0.254 8.56 5.8 3.8 1.54 0.1 Typ. 1.62 0.15 1.47 0.2 0.17 8.66 6 3.91 0.635 0.635 0.33 0° 0.89 0.41 0.016 0.010 8.76 6.2 4.01 0.012 0.010 0.337 0.228 0.150 Max. 1.73 0.25 Min. 0.061 0.004 Typ. 0.064 0.006 0.058 0.008 0.007 0.341 0.236 0.154 0.025 0.025 0.013 0.035 0.016 0.345 0.244 0.158 Max. 0.068 0.010 QSOP-24 mechanical data mm. inch Doc ID 16538 Rev 2 25/34 Package mechanical data Figure 24. QSOP-24 package dimensions STP16DPS05 26/34 Doc ID 16538 Rev 2 STP16DPS05 Package mechanical data Table 17. Dim. QSOP-24 tape and reel mm. Min Typ 13 330 100 16.4 1.5 2 2.5 0.591 Max 13.5 Min 5.039 inch Typ 5.118 129.921 39.37 6.457 0.787 0.984 Max 5.315 R1 R2 R3 eint e1 12.8 Table 18. QSOP-24 tape and reel dimensions 4.0+/-0.1 0.3+/-0.05 1.5+1/0 2.0+/-0.1 1.75+/-0.1 7.5+/-0.1 2.1 +/-0.1 10.3 +/-0.1 10.3 +/-0.1 16 +/-0.3 8 +/-0.1 6.5 +/- 0.1 1.6 +1/-0.1 7217811_C Doc ID 16538 Rev 2 27/34 Package mechanical data Table 19. Dim. Min. A A1 A2 b c D E e H K L 6.25 0° 0.50 0.19 0.09 7.7 4.3 0.65 BSC 6.5 8° 0.70 0.246 0° 0.020 0.05 0.9 0.30 0.20 7.9 4.5 0.0075 0.0035 0.303 0.169 Typ. Max. 1.1 0.15 0.002 0.035 Min. Typ. STP16DPS05 TSSOP24 mechanical data mm. inch Max. 0.043 0.006 0.0118 0.0079 0.311 0.177 0.0256 BSC 0.256 8° 0.028 Figure 25. TSSOP24 package dimensions 28/34 Doc ID 16538 Rev 2 STP16DPS05 Package mechanical data Table 20. Dim. TSSOP24 tape and reel mm. Min. Typ. 12.8 20.2 60 6.8 8.2 1.7 3.9 11.9 22.4 7 8.4 1.9 4.1 12.1 0.268 0.323 0.067 0.153 0.468 Max. 330 13.2 0.504 0.795 2.362 Min. inch Typ. 0.882 0.276 0.331 0.075 0.161 0.476 Max. 12.992 0.519 A C D N T Ao Bo Ko Po P Figure 26. Reel dimensions Doc ID 16538 Rev 2 29/34 Package mechanical data Table 21. Dim. Min. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 0.291 0.020 °(max.) 8 15.60 10.65 0.35 0.23 0.5 45°(typ.) 0.598 0.393 0.050 0.550 0.1 Typ. Max. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 Min. Typ. STP16DPS05 SO-24 mechanical data mm. inch Max. 0.104 0.008 0.096 0.019 0.012 0.614 0.419 0.300 0.050 Figure 27. SO-24 package dimensions 30/34 Doc ID 16538 Rev 2 STP16DPS05 Table 22. Dim. Min. A C D N T Ao Bo Ko Po P 10.8 15.7 2.9 3.9 11.9 12.8 20.2 60 Typ. 30.4 11.0 15.9 3.1 4.1 12.1 0.425 0.618 0.114 0.153 0.468 Max. 330 13.2 0.504 0.795 2.362 Min. Package mechanical data SO-24 tape and reel mm. inch Typ. 1.197 0.433 0.626 0.122 0.161 0.476 Max. 12.992 0.519 Figure 28. Reel dimensions Doc ID 16538 Rev 2 31/34 Package mechanical data Table 23. Dim. Min. A A1 Typ. Max. 1.2 0.15 0.004 Min. Typ. STP16DPS05 TSSOP24 exposed pad mm inch Max. 0.047 0.006 A2 b c D D1 E E1 E2 e K L 0.8 0.19 0.09 7.7 4.7 6.2 4.3 2.9 1 1.05 0.30 0.20 0.031 0.007 0.004 0.303 0.185 0.244 0.169 0.114 0.039 0.041 0.012 0.0089 7.8 5.0 6.4 4.4 3.2 0.65 7.9 5.3 6.6 4.5 3.5 0.307 0.197 0.252 0.173 0.126 0.0256 0.311 0.209 0.260 0.177 0.138 0° 0.45 0.60 8° 0.75 0° 0.018 0.024 8° 0.030 Figure 29. TSSOP24 dimensions 32/34 Doc ID 16538 Rev 2 STP16DPS05 Revision history 9 Revision history Table 24. Date 23-Oct-2009 22-Jan-2010 Document revision history Revision 1 2 First release Updated Table 5 on page 4 Changes Doc ID 16538 Rev 2 33/34 STP16DPS05 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 34/34 Doc ID 16538 Rev 2