STP16NK65Z

STP16NK65Z STB16NK65Z-S N-CHANNEL 650V - 0.38Ω - 13A TO-220 / I2SPAK Zener - Protected SuperMESH™ MOSFET Figure 1: Package Table 1: General Features TYPE VDSS RDS(on) ID Pw STP16NK65Z STB16NK65Z-S 650 V 650 V < 0.50 Ω < 0.50 Ω 13 A 13 A 190 W 190 W ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.38Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY 3 12 3 1 e t le ) s t( I²SPAK c u d TO-220 DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. ) s ( ct 2 o r P Figure 2: Internal Schematic Diagram o s b O - APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ IDEAL FOR OFF-LINE POWER SUPPLIES u d o r P e t e l o Table 2: Order Codes s b O SALES TYPE MARKING PACKAGE PACKAGING STP16NK65Z P16NK65Z TO-220 TUBE STB16NK65Z-S B16NK65Z I²SPAK TUBE Rev. 3 September 2005 1/12 STP16NK65Z - STB16NK65Z-S Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 650 V Drain-gate Voltage (RGS = 20 kΩ) 650 V Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 13 A ID Drain Current (continuous) at TC = 100°C 8.19 A 52 A IDM (*) Drain Current (pulsed) PTOT Total Dissipation at TC = 25°C 190 W Derating Factor 1.51 W/°C Gate source EDS (HBM-C=100pF, R=1.5kΩ) 6000 V 4.5 V/ns -55 to 150 °C VESD(G-S) dv/dt (1) Tj Tstg Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature (*) Pulse width limited by safe operating area (1) ISD ≤ 13 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS,T j ≤ T JMAX c u d Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max Tl 0.66 e t le Table 5: Avalanche Characteristics Symbol so Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) ) s ( ct o r P 62.5 Maximum Lead Temperature For Soldering Purpose b O - ) s t( °C/W °C/W 300 °C Max. Value Unit 13 A 350 mJ Table 6: Gate-Source Zener Diode Symbol BVGSO du Parameter o r P e Gate-Source Breakdown Voltage t e l o Test Condition Min. Igs=± 1mA (Open Drain) 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied fromgate to source. In this respect the Zener voltage ia appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. s b O 2/12 STP16NK65Z - STB16NK65Z-S ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off Symbol Parameter Test Conditions Min. Typ. Max. 650 Unit Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 100 µA 3.75 4.5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 6.5 A 0.38 0.50 Ω Typ. Max. Unit V(BR)DSS 3 V Table 8: Dynamic Symbol gfs (1) Parameter Test Conditions Min. Forward Transconductance VDS = 15 V, ID = 6.5 A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, f = 1 MHz, VGS = 0 Equivalent Output Capacitance VGS = 0V, VDS = 6.5 V to 520 V td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 325 V, ID = 6.5 A RG = 4.7Ω VGS = 10 V (see Figure 17) Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 520 V, ID = 13 A, VGS = 10 V (see Figure 20) Ciss Coss Crss Coss eq. (*) ) s ( ct Table 9: Source Drain Diode 12 2750 275 60 S c u d ro P e let o s b O - 188 pF 25 25 68 17 ns ns ns ns 89 18 45 nC nC nC Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 13 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 13 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 25°C (see Figure 18) 500 5.2 21 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 13 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150°C (see Figure 18) 615 7 22.5 ns µC A trr Qrr t e l o r P e IRRM trr Qrr s b O IRRM Min. pF pF pF Symbol u d o Test Conditions ) s t( Typ. Max. Unit 13 52 A A 1.6 V (1) Pulsed: Pulse duration = 300µs, duty cycle 1.5% (2) Pulse width limited by safe operating area (*) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 3/12 STP16NK65Z - STB16NK65Z-S Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics c u d e t le Figure 5: Transconductance u d o ) s ( ct r P e t e l o s b O 4/12 ) s t( o r P o s b O - Figure 8: Static Drain-source On Resistance STP16NK65Z - STB16NK65Z-S Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature c u d e t le ) s ( ct o r P o s b O - Figure 11: Dource-Drain Diode Forward Characteristics u d o ) s t( Figure 14: Normalized BVdss vs Temperature r P e t e l o s b O 5/12 STP16NK65Z - STB16NK65Z-S Figure 15: Avalanche Energy vs Starting Tj j c u d e t le ) s ( ct u d o r P e t e l o s b O 6/12 o s b O - o r P ) s t( STP16NK65Z - STB16NK65Z-S Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform Figure 17: Switching Times Test Circuit For Resistive Load Figure 20: Gate Charge Test Circuit c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times t e l o s b O 7/12 STP16NK65Z - STB16NK65Z-S In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com c u d e t le ) s ( ct u d o r P e t e l o s b O 8/12 o s b O - o r P ) s t( STP16NK65Z - STB16NK65Z-S I2SPAK MECHANICAL DATA mm. DIM. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 A1 2.49 2.69 0.098 0.181 0.106 B 0.70 0.93 0.027 0.037 B2 1.14 1.70 0.045 0.067 C 0.45 0.60 0.018 0.024 C2 1.23 1.36 0.048 0.053 0.368 D 8.95 9.35 0.352 E 10.00 10.40 0.394 0.409 G 4.88 5.28 0.192 0.208 ) s t( L 16.7 17.5 0.657 0.689 L2 1.27 1.4 0.05 0.055 L3 13.82 14.42 0.544 0.568 e t le ) s ( ct c u d o r P o s b O - u d o r P e t e l o s b O 9/12 STP16NK65Z - STB16NK65Z-S TO-220 MECHANICAL DATA mm. DIM. MIN. A TYP MAX. MIN. 4.40 4.60 0.173 0.181 TYP. MAX. 0.034 b 0.61 0.88 0.024 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 28.90 3.85 Q 2.65 2.95 u d o r P e t e l o s b O 0.551 0.147 o s b O - P e let 0.104 uc d o r 1.137 3.75 ) s t( 0.107 0.645 øP ) s ( ct 10/12 inch 0.154 0.151 0.116 STP16NK65Z - STB16NK65Z-S Table 10: Revision History Date Revision 06-Aug-2004 02-Sep-2004 06-Sep-2005 1 2 3 Description of Changes First Release. Complete Version Inserted Ecopack indication c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 11/12 STP16NK65Z - STB16NK65Z-S c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. t e l o s b O The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 12/12