STP17N80K5

STP17N80K5 N-channel 800 V, 0.29 Ω typ., 14 A MDmesh™ K5 Power MOSFET in a TO-220 package Datasheet - production data Features      Order code VDS RDS(on) max. ID STP17N80K5 800 V 0.34 Ω 14 A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STP17N80K5 17N80K5 TO-220 Tube May 2016 DocID027702 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents STP17N80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220 type A package information................................................ 10 Revision history ............................................................................ 12 DocID027702 Rev 2 STP17N80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 14 A ID Drain current (continuous) at TC = 100 °C 9 A (1) IDM Drain current (pulsed) 56 A PTOT W Total dissipation at TC = 25 °C 170 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 TJ Operating junction temperature range Tstg Storage temperature range V/ns - 55 to 150 °C Notes: (1) Pulse width limited by safe operating area (2) ISD ≤ 14 A, di/dt = 100 A/μs; VDS peak < V(BR)DSS,VDD= 640 V (3) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 0.74 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 4.7 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 340 mJ DocID027702 Rev 2 3/13 Electrical characteristics 2 STP17N80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 800 Typ. Max. Unit V VGS = 0 V, VDS = 800 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V (1) TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDD = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 7 A 0.29 0.34 Ω Min. Typ. Max. Unit - 866 - pF - 64 - pF - 0.42 - pF - 142 - pF - 51 - pF 3 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance (1) Co(tr) (2) Co(er) Test conditions Equivalent capacitance time related Equivalent capacitance energy related VDS = 0 to 640 V, VGS = 0 V Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 5 - Ω Qg Total gate charge - 26 - nC Qgs Gate-source charge - 7.2 - nC Qgd Gate-drain charge VDD = 640 V, ID = 14 A VGS= 10 V (see Figure 15: "Test circuit for gate charge behavior") - 15.2 - nC Notes: (1) Co(tr) is a constant capacitance value that gives the same charging time as Coss while V DS is rising from 0 to 80% VDSS. (2) Co(er) is a constant capacitance value that gives the same stored energy as Coss while V DS is rising from 0 to 80% VDSS. 4/13 DocID027702 Rev 2 STP17N80K5 Electrical characteristics Table 7: Switching times Symbol td(on) tr Parameter Turn-on delay time Rise time td(off) tf Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD= 400 V, ID =7 A, RG = 4.7 Ω VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 14.8 - ns - 10.8 - ns - 84.3 - ns - 10.1 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions Source-drain current - 14 A (1) Source-drain current (pulsed) - 56 A (2) Forward on voltage - 1.6 V ISD ISDM VSD ISD = 14 A, VGS = 0 V trr Reverse recovery time Qrr Reverrse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 439 ns - 6.37 µC - 29 A - 626 ns - 8.36 µC - 26.7 A Notes: (1) (2) Pulse width limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ± 1 mA, ID= 0 A Min. Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID027702 Rev 2 5/13 Electrical characteristics 2.2 STP17N80K5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*Rthj-c δ= tp/Ƭ 0.01 Single pulse 10 -2 10 -5 6/13 10 -4 10 tp -3 10 -2 Ƭ 10 -1 tP (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027702 Rev 2 STP17N80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting TJ DocID027702 Rev 2 7/13 Test circuits 3 8/13 STP17N80K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID027702 Rev 2 STP17N80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID027702 Rev 2 9/13 Package information 4.1 STP17N80K5 TO-220 type A package information Figure 20: TO-220 type A package outline 10/13 DocID027702 Rev 2 STP17N80K5 Package information Table 10: TO-220 type A mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95 DocID027702 Rev 2 11/13 Revision history 5 STP17N80K5 Revision history Table 11: Document revision history Date Revision 03-Apr-2015 1 First release. 2 Modified: Table 2: "Absolute maximum ratings", Table 3: "Thermal data" Added: Section 3.1: "Electrical characteristics (curves)" Minor text changes 19-May-2016 12/13 Changes DocID027702 Rev 2 STP17N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID027702 Rev 2 13/13