STP1N120

STP1N120 N-channel 1200V - 30Ω - 500mA - TO-220 Zener - protected SuperMESH™ Power MOSFET PRELIMINARY DATA General features Type STP1N120 ■ ■ ■ ■ ■ VDSS 1200V RDS(on) < 38Ω ID 500mA PW 45W 100% avalanche tested Extremely high dv/dt capability ESD improved capability New high voltage benchmark Gate charge minimized 1 3 2 TO-220 Description The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage Power MOSFETs including revolutionary MDmesh™ products. Internal schematic diagram Applications ■ Switching application Order codes Part number STP1N120 Marking P1N120 Package TO-220 Packaging Tube September 2006 Rev 1 1/10 www.st.com 10 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STP1N120 Contents 1 2 3 4 5 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuit ................................................ 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2/10 STP1N120 Electrical ratings 1 Electrical ratings Table 1. Symbol VDS VGS ID ID IDM (1) Absolute maximum ratings Parameter Drain-source voltage (VGS=0) Gate-source voltage Drain current (continuous) at TC = 25°C Drain current (continuous) at TC = 100°C Drain current (pulsed) Derating factor Value 1200 ± 30 500 315 2 0.36 45 Tbd -55 to 150 Unit V V mA mA A W/°C W V/ns °C PTOT dv/dt (2) Tj Tstg Total dissipation at TC = 25°C Peak diode recovery voltage slope Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area 2. ISD ≤1A, di/dt ≤200A/µs, VDD ≤960 Table 2. Symbol Rthj-case Thermal data Parameter Thermal resistance junction-case max Value 2.78 62.5 300 Unit °C/W °C/W °C Rthj-amb (1) Thermal resistance junction-amb max Tl Maximum lead temperature for soldering purpose 1. When mounted on 1inch² FR-4 board, 2 oz Cu Table 3. Symbol IAS EAS Avalanche characteristics Parameter Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj=25°C, ID=IAS, VDD= 50V) Max value Tbd Tbd Unit A mJ 3/10 Electrical characteristics STP1N120 2 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On/off states Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1mA, VGS= 0 VDS = Max rating, VDS = Max rating,Tc=125°C VGS = ±20V VDS= VGS, ID = 50µA VGS= 10V, ID= 0.25A 3 3.75 30 Min. 1200 1 50 ±10 4.5 38 Typ. Max. Unit V µA µA µA V Ω Table 5. Symbol Ciss Coss Crss Qg Qgs Qgd Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions Min. Typ. 130 22 3 7 Tbd Tbd Max. Unit pF pF pF nC nC nC VDS =25V, f=1MHz, VGS=0 VDD=960V, ID = 500mA VGS =10V (see Figure 2) 4/10 STP1N120 Electrical characteristics Table 6. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Tbd Tbd Tbd Tbd Max. Unit ns ns ns ns Tbd Table 7. Symbol ISD ISDM VSD(1) trr Qrr IRRM trr Qrr IRRM 1. Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD=1A, VGS=0 ISD=1A, VDD=100V di/dt = 50A/µs,Tj=25°C (see Figure 6) ISD=1A,VDD=100V di/dt=50A/µs,Tj=150°C (see Figure 6) Tbd Tbd Tbd Tbd Tbd Tbd Test conditions Min Typ. Max 500 2 Tbd Unit mA A V ns nC A ns nC A Pulsed: pulse duration = 300µs, duty cycle 1.5% Table 8. Symbol Gate-source zener diode Parameter Test conditions Min 30 Typ. Max Unit V BVGSO (1) Gate-source breakdown voltage Igs ± 1mA, (open drain) 1. The built-in-back zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possibile voltage transients that may occasionally be applied from gate to source. In this respect the zener voltage is appropriate to achieve an efficient and osteffective intervention to protect the device’s integrity. These integrated zener diodes thus avoid the usage of external components. 5/10 Test circuit STP1N120 3 Figure 1. Test circuit Switching times test circuit for resistive load Figure 2. Gate charge test circuit Figure 3. Test circuit for inductive load Figure 4. switching and diode recovery times Unclamped inductive load test circuit Figure 5. Unclamped inductive waveform Figure 6. Switching time waveform 6/10 STP1N120 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 7/10 Package mechanical data STP1N120 TO-220 MECHANICAL DATA DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154 øP Q 8/10 STP1N120 Revision history 5 Revision history Table 9. Date 14-Sep-2006 Revision history Revision 1 First release Changes 9/10 STP1N120 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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