STP24DP05

STP24DP05 24-bit constant current LED sink driver with output error detection Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low voltage power supply down to 3 V 8 x 3 constant current output channels Adjustable output current through external resistors Short and open output error detection Serial data IN/Parallel data OUT Shift register data flow registers control Accepts 3.3 V and 5 V micro driver Output current: 5-80 mA 25 MHz clock frequency High thermal efficiency package TQFP48 The data detection results are loaded in the shift registers and shifted out via the serial line output. The detection functionality is activated with a dedicated pin or as alternative, through a logic sequence that allows the user to enter or exit from detection mode. Through three external resistors, users can adjust the output current for each 8-channel group, controlling in this way the light intensity of LEDs. The STP24DP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 25 MHz, makes the device suitable for high data rate transmission. The 3.3 V of voltage supply is useful for applications that interface any micro from 3.3 V. Description The STP24DP05 is a monolithic, low voltage, low current power 24-bit shift register designed for LED panel displays. The device contains a 8 x 3-bit serial-in, parallel-out shift register that feeds a 8 x 3-bit D-type storage register. In the output stage, twenty-four regulated current sources were designed to provide 5-80 mA constant current to drive the LEDs. The 8x3 shift registers data flow sequence order can be managed with two dedicated pins. The STP24DP05 has a dedicated pin to activate the outputs with a sequential delay, that will prevent inrush current during outputs turn-ON. The device detection circuit checks 3 different conditions that can occur on the output line: short to GND, short to VO or open line. Table 1. Device summary Order code STP24DP05BTR Package TQFP48 Packaging Tape and reel May 2008 Rev 1 1/26 www.st.com 26 Contents STP24DP05 Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 4 5 6 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 7.2 7.3 7.4 7.5 7.6 7.7 DG: gradual outputs delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Error detection condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Phase one: “entering in detection mode” . . . . . . . . . . . . . . . . . . . . . . . . . 16 Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 18 Shift registers data flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 EFLAG/TFLAG - output detection and overtemperature monitoring . . . . 19 8 9 10 11 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/26 STP24DP05 Summary description 1 Summary description Table 2. Current accuracy Typical current accuracy Output voltage Between bits ≥ 1.0 V ≥ 0.2 V ±3% ±6% Between ICs ±6% ±6% ≥ 15 to 80 mA 5 to 15 mA 3.3 V to 5 V 25 °C Output current VDD Temperature 1.1 Pin connection and description Figure 1. Pin connection TQFP48 exposed pad 3/26 Summary description Table 3. Pin description Symbol GND SDI SDO CLK LE\DM DM R1 - 8 TF EF DG B1 - 8 OE-B OE-G OE-R\DM REXTR REXTG REXTB G1 - 8 DF0 DF1 VDD Ground terminal Serial data input Serial data output Clock for serial data Data latch in both SH register Detection mode pin 8 channel LED driver outputs Thermal flag (open drain) Error detection flag (open drain) Gradual delay 8 channel LED driver outputs Output enable for B1 - 8 Output enable for G1 - 8 Output enable for R1 - 8 Control outputs R1 - 8 Control outputs G1 - 8 Control outputs B1 - 8 8 channel LED driver outputs Data banks flow bit 0 Data banks flow bit 1 Supply voltage terminal Name and function STP24DP05 Pin N° 1, 7, 12, 25, 30, 36 2 35 4 3 5 13, 16, 19, 22, 39, 42, 45, 48 8 29 9 15, 17, 20, 23, 37, 40, 43, 46 32 33 34 28 27 26 14, 18, 21, 24, 38, 41, 44, 48 10 11 31 4/26 STP24DP05 Electrical ratings 2 2.1 Electrical ratings Absolute maximum ratings Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality documents. Table 4. Symbol VDD VO VTF and VER IO VI IGND fCLK Absolute maximum ratings Parameter Supply voltage - digital Output voltage - LED driver Open drain absolute voltage Output current - LED driver Input voltage - digital GND terminal current Clock frequency Value 0 to 7 -0.5 to 20 0 to 7 80 -0.4 to VDD+0.4 2000 30 Unit V V V mA V mA MHz 2.2 Thermal data Table 5. Symbol TOPR TSTG RthJC Thermal data Parameter Operating temperature range Storage temperature range Thermal resistance junction-case Value -40 to 125 -40 to 150 25 Unit °C °C °C/W 5/26 Electrical ratings STP24DP05 2.3 Recommended operating conditions Table 6. Symbol VDD VO IO IOH IOL VIH VIL twLAT twCLK twEN Recommended operating conditions Parameter Supply voltage Output voltage Output current Output current Output current Input voltage Input voltage LE pulse width CLK pulse width OE pulse width VDD = 3.0 V to 5.0 V OUTn SERIAL-OUT SERIAL-OUT 0.7VDD -0.3 15 15 150 15 5 10 Cascade operation (1) Test conditions Min 3.0 Typ Max 5.5 20 Unit V V mA mA mA 5 +10 -10 80 VDD+0.3 0.3VDD V V ns ns ns ns ns ns tSETUP(D) Setup time for DATA tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH fCLK Clock frequency 25 MHz 1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully. 6/26 STP24DP05 Electrical characteristics 3 Table 7. Symbol VIH VIL IOH VOL VOH IOL1 IOL2 IOL3 ∆IOL1 ∆IOL2 ∆IOL3 RSIN(up) RSIN(down) LE(up) DG(up) OE-R\ DM (up) OE-G (up) OE-B (up) DF0 DF1 IDD(OFF1) Electrical characteristics Electrical characteristics (VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.) Parameter Input voltage high level Input voltage low level Output leakage current Output voltage (Serial-OUT) Output voltage (Serial-OUT) VOH = 20 V IOL = 1 mA IOH = -1 mA VO = 0.3 V, REXT = 2 kΩ, IO = 10 mA Output current VO = 0.3 V, REXT = 1 kΩ, IO = 20 mA VO = 0.3V, REXT = 250 Ω, IO = 80 mA VO = 0.3 V, REXT = 2 kΩ, IO = 10 mA Output current error among VO = 0.3 V, REXT = 1 kΩ, the channels IO = 20 mA (All outputs ON) VO = 0.3V, REXT = 250 Ω, IO = 80 mA Pull-up resistor Pull-down resistor 300 300 VDD-0.4V 20 80 80 ±2 ±2 ±2 600 400 ±3 ±3 ±3 800 500 Test conditions Min 0.7VDD GND Typ Max VDD 0.3VDD 10 0.4 Unit V V µA V V mA mA mA % % % kΩ kΩ Pull-up resistor 300 400 500 kΩ REXT = 1 kΩ OUT 0 to 15 = OFF Supply current (OFF) REXT = 250 Ω OUT 0 to 15 = OFF REXT = 1 kΩ OUT 0 to 15 = ON Supply current (ON) REXT = 250 Ω OUT 0 to 15 = ON 9 32 13 35 12 40 mA 18 40 IDD(OFF2) IDD(ON1) IDD(ON2) 7/26 Electrical characteristics Table 7. Symbol Thermal VTF ITF VEF IEF STP24DP05 Electrical characteristics (VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.) Parameter Thermal protection Output voltage Output current Output voltage Output current VEF @ 1 V 20 VTF @ 1 V 20 5 Test conditions Min Typ 170 5 Max Unit °C V mA V mA Table 8. Symbol tPLH1 Switching characteristics (VDD = 5 V, T = 25 °C, unless otherwise specified.) Parameter Propagation delay time, CLK-OUTn, LE = H, OE = L Propagation delay time, LE-OUTn, OE = L Propagation delay time, OE-OUTn, LE = H Propagation delay time, CLK-SDO Propagation delay time, CLK-OUTn, LE = H, OE = L Propagation delay time, LE-OUTn, OE = L Propagation delay time, OE-OUTn, LE = H Propagation delay time, CLK-SDO Output rise time 10~90% of voltage waveform Output fall time 90~10% of voltage waveform CLK rise time (1) CLK fall time (1) Test conditions VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 3.3 V VIL = GND IO = 20 mA REXT = 1 kΩ VIH = VDD CL = 10 pF VL = 3.0 V RL = 60 Ω VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V 15 9 14 9 Min Typ 62 38 67 44 65 38 22 14 46 39 51 46 41 33 24 15 33 17 24 25 Max 100 ns 60 107 ns 60 83 ns 45 36 ns 23 70 ns 50 76 ns 55 45 ns 39 38 ns 24 57 ns 27 34 ns 37 5000 5000 ns ns Unit tPLH2 tPLH3 tPLH tPHL1 tPHL2 tPHL3 tPHL tON tOFF tr tf 1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully. 8/26 STP24DP05 Block diagram 4 Figure 2. Block diagram Block diagram 9/26 Equivalent circuit and outputs STP24DP05 5 Equivalent circuit and outputs Figure 3. OExx terminal Figure 4. LE\DM terminal Figure 5. CLK, SDI terminal 10/26 STP24DP05 Figure 6. SDO terminal Equivalent circuit and outputs Figure 7. TF and EF 11/26 Timing diagrams STP24DP05 6 Timing diagrams Figure 8. Timing diagram Note: 1 2 3 The latches circuit holds data when the LE terminal is low. When LE\DML terminal is at high level, latch circuit hold the data it passes from the input to the output. When either OE-R\DM, OE-G, OE-B terminals are at low level, output terminals R\G\B1 to R\G\B8 respond to the data, either ON or OFF. When either OE-R\DM, OE-G, OE-B terminals are at high level, it switches off all the data on the output terminal R\G\B1 to R\G\B8. 12/26 STP24DP05 Figure 9. Clock, serial-in, serial-out Timing diagrams 13/26 Timing diagrams Figure 10. Clock, serial-in, latch, enable, outputs STP24DP05 Figure 11. Outputs 14/26 STP24DP05 Feature description 7 7.1 Feature description DG: gradual outputs delay This feature prevents large inrush current and reduces the bypass capacitors. The fixed delay time can be activated with DG = LOW and the typical output delay is 20 ns for each group of 8 outputs R, G, B. Eg: R1, G1, B1 has no delay, R2, G2, B2 has 20 ns delay and R3, G3, B3, has 40 ns delay, etc. Table 9. Typical gradual delay time table Delay time (ns) from ↓OExx DG = 0 DG = 1 R1 G1 B1 0 R2 G2 B2 30 0 R3 G3 B3 60 0 R4 G4 B4 90 0 R5 G5 B5 120 0 R6 G6 B6 150 0 R7 G7 B7 180 0 R8 G8 B8 200 0 7.2 Error detection condition Table 10. Detection conditions (VDD = 3.3 to 5 V, IO = 20 mA, tA = 25 °C) => IODEC ≤ 0.4 x IO No error detected No error detected => IODEC ≥ 0.35 x IO SW-1 Open Open line or output short or SW-3b to GND detected SW-2 Closed or SW-3a Short on LED or short to V-LED detected => VO ≥ 2.6 V => VO ≤ 2.4 V Note: IO = the output current programmed by the REXT IODEC = the detected output current in detection mode Table 11. Typical current threshold values to detect LED open line Rext (Ω) 3920 1960 980 386 241 Typ. out current detection (mA) 1.28 2.45 7.4 17 27 Iset (mA) 5 10 20 50 80 15/26 Feature description Figure 12. Detection circuit STP24DP05 23 STP24DP05 24 16 7.3 Phase one: “entering in detection mode” From the “normal mode” condition the device can switch to the “error detection mode“ by a DM PIN set to LOW or a logic sequence on the OE-R/DM and LE/DM pins as showed in the following table and diagram: Figure 13. EDM timing diagram using DM pin Table 12. CLK OE-R/DM LE/DM SPI sequence to enter in detection mode - truth table 1° H L 2° L L 3° H L 4° H H 5° H L 16/26 STP24DP05 Feature description Figure 14. SPI sequence to enter in detection mode - time diagram OE-R/DM LE/DM After these five CLK cycles the device goes into the “error detection mode“ and at the 6th rise front of CLK the SDI data are ready for the sampling. 7.4 Phase two: “error detection” The eight data bits must be set “1“ in order to set ON all the outputs during the detection. The data are latched by LE/DM and after that the outputs are ready for the detection process. When the micro controller switches the OE-R/DM to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred. Figure 15. Detection diagram The LEDs status will be detected at least in 1 microsecond and after this time the microcontroller sets OE-R/DM in HIGH state and the output data detection result will go to the microprocessor via SDO. Detection mode and normal mode use both the same format data. As soon as all the detection data bits are available on the serial line, the device may go back to normal mode of operation. 17/26 Feature description STP24DP05 7.5 Phase three: “resuming to normal mode” In order to re-enter in normal mode either the LE\DML pin or the sequence showed in the following table and diagram can be used: Table 13. CLK OE-R/DM LE/DM SPI sequence to resume in normal mode - truth table 1° H L 2° L L 3° H L 4° H L 5° H L Note: For proper device operation the "entering in detection" sequence must be followed by a "resume mode" sequence, it is not possible to insert consecutive equal sequence. 7.6 Shift registers data flow control The 8x3 shift registers have a default RGB sequence serial data flow as showed on block diagram Figure 2. The data can be redirected by DF0 and DF1 pins, these pins change the order of the data flow according to the following table: Table 14. Shifter register data flow control Sequence BGR BGR RGB GBR DF0 1 0 1 0 DF1 1 1 0 0 18/26 STP24DP05 Feature description 7.7 EFLAG/TFLAG - output detection and overtemperature monitoring The open-drain output EFLAG and TFLAG are used to report the STP24DP05 error flags. During normal operating conditions, the voltage on EFLAG/TFLAG is pulledup through an external resistor. When an error is detected, the internal switch is turned on, to GND. Figure 16. TF and EF test circuit 19/26 Typical application schematic STP24DP05 8 Typical application schematic Figure 17. Typical application schematic 20/26 STP24DP05 Typical characteristics 9 Typical characteristics Figure 18. Typical external resistor values vs output current capabilities 4500 4000 External Resistance (Ohm) 3500 3000 2500 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 Output Current (mA) Temp. = 25°C Vdd = 5.0V Iset = 5mA; 10mA; 20mA; 50mA; 80mA Table 15. Typical external resistor values vs output current capabilities Iset 5 mA 4210 10 mA 2050 20 mA 1000 50 mA 400 80 mA 249 Rext (Ω) Figure 19. Typical dropout voltage vs output current Table 16. Iset 5 10 20 50 80 Typical dropout voltage vs output current Rext (Ω) 4210 2050 1000 400 249 Avg (mV) @ 3.3 V 59 130 201 500 810 Avg (mV) @ 5.0 V 41 90 180 480 790 21/26 Package mechanical data STP24DP05 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 22/26 STP24DP05 Figure 20. TQFP48 mechanical data Package mechanical data TQFP48 MECHANICAL DATA mm. DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0˚ 0.45 0.05 1.35 0.17 0.09 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 3.5˚ 7˚ 0˚ 0.75 0.018 1.40 0.22 TYP MAX. 1.6 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.0035 0.354 0.276 0.216 0.020 0.354 0.276 0.216 0.024 0.039 3.5˚ 7˚ 0.030 0.055 0.009 MIN. TYP. MAX. 0.063 0.006 0.057 0.011 0.0079 inch 0110596/C 23/26 Package mechanical data Figure 21. TQFP48 tape and reel STP24DP05 Tape & Reel TQFP48 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 9.5 9.5 2.1 3.9 11.9 12.8 20.2 60 22.4 9.7 9.7 2.3 4.1 12.1 0.374 0.374 0.083 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.382 0.382 0.091 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 24/26 STP24DP05 Revision history 11 Revision history Table 17. Date 19-Apr-2008 Document revision history Revision 1 First release Changes 25/26 STP24DP05 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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