STP24DP05
24-bit constant current LED sink driver with output error detection
Features
■
Low-voltage power supply down to 3 V
■
8 x 3 constant current output channels
■
Adjustable output current through external
resistors
■
Short and open output error detection
■
Serial data IN/parallel data OUT
■
Shift register data flow register control
■
Accepts 3.3 V and 5 V micro driver
■
Output current: 5-80 mA
■
25 MHz clock frequency
■
High thermal efficiency package
TQFP48-EP
The detection functionality is activated with a
dedicated pin or alternatively, through a logic
sequence that allows the user to enter or exit
detection mode.
Through three external resistors, the user can
adjust the output current for each 8-channel
group, therefore controlling the light intensity
of LEDs.
Description
The STP24DP05 is a monolithic, low-voltage, low
current power 24-bit shift register designed for
LED panel displays. The device contains an
8 x 3-bit serial-IN, parallel-OUT shift register that
feeds a 8 x 3-bit D-type storage register. In the
output stage, twenty four regulated current
sources were designed to provide 5-80 mA
constant current to drive the LEDs.
The STP24DP05 guarantees a 20 V output
driving capability, allowing the user to connect
more LEDs in series.
The high clock frequency, 25 MHz, makes the
device suitable for high data rate transmission.
The 3.3 V of voltage supply is useful for
applications that interface any microcontroller
from 3.3 V.
The 8 x 3 shift register data flow sequence order
can be managed through two dedicated pins.
The STP24DP05 has a dedicated pin to activate
the outputs with a sequential delay, that prevents
inrush current during output turn-ON.
The device detection circuit checks 3 different
conditions that can occur on the output line: short
to GND, short to VO, or open line.
The data detection results are loaded in the shift
registers and shifted out via the serial line output.
Table 1.
Device summary
Order code
Package
Packaging
STP24DP05BTR
TQFP48-EP (1)
Tape and reel
1. Thermal pad size: 3.5 mm x 3.5 mm.
February 2012
Doc ID 14714 Rev 5
1/27
www.st.com
27
Contents
STP24DP05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Features description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
DG: gradual output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2
Error detection condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3
Phase one: “entering detection mode” . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4
Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5
Phase three: “resuming normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6
Shift register data flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7
EFLAG/TFLAG - output detection and overtemperature monitoring . . . . 19
8
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
Doc ID 14714 Rev 5
STP24DP05
1
Summary description
Summary description
Table 2.
Current accuracy
Typical current accuracy
Output voltage
Output current
Between bits
1.1
VDD
Temperature
3.3 V to 5 V
25 °C
Between ICs
≥ 1.0 V
± 3%
± 6%
≥ 15 to 80 mA
≥ 0.2 V
± 6%
± 6%
5 to 15 mA
Pin connection and description
Figure 1.
Pin connection
TQFP48 exposed pad
Note:
The exposed pad should be electrically connected to a PCB metal dissipation area
electrically isolated or connected to ground.
Doc ID 14714 Rev 5
3/27
Summary description
Table 3.
4/27
STP24DP05
Pin description
Pin N°
Symbol
Name and function
1, 7, 12, 25, 30, 36
GND
Ground terminal
2
SDI
Serial data input
35
SDO
Serial data output
4
CLK
Clock for serial data
3
LE\DM
5
DM
13, 16, 19, 22,
39, 42, 45, 48
R1 - 8
8
TF
Thermal flag (open drain)
29
EF
Error detection flag (open drain)
9
DG
Gradual delay
15, 18, 21, 24
37, 40, 43, 46
B1 - 8
8-channel LED driver outputs
32
OE-B
Output enable for B1 - 8
33
OE-G
Output enable for G1 - 8
34
OE-R\DM
Output enable for R1 - 8
28
REXTR
Control outputs R1 - 8
27
REXTG
Control outputs G1 - 8
26
REXTB
Control outputs B1 - 8
14, 17, 20, 23
38, 41, 44, 48
G1 - 8
8-channel LED driver outputs
10
DF0
Data banks flow bit 0
11
DF1
Data banks flow bit 1
31
VDD
Supply voltage terminal
Data latch in both SH registers
Detection mode pin
8-channel LED driver outputs
Doc ID 14714 Rev 5
STP24DP05
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in Table 4 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 4.
Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
0 to 7
V
VDD
Supply voltage - digital
VO
Output voltage - LED driver
-0.5 to 20
V
VTF and
VER
Open drain absolute voltage
0 to 7
V
IO
Output current - LED driver
80
mA
VI
Input voltage - digital
-0.4 to VDD+0.4
V
IGND
GND terminal current
2000
mA
fCLK
Clock frequency
30
MHz
Value
Unit
-40 to 125
°C
-40 to 150
°C
33
°C/W
Thermal data
Table 5.
Symbol
Thermal data
Parameter
TOPR
Operating temperature range
TSTG
Storage temperature range
RthJA
Thermal resistance junction-ambient
(1) (2)
1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.
2. Packages tested on multi-layer (1S2P) JEDEC compliant test boards.
Doc ID 14714 Rev 5
5/27
Electrical ratings
2.3
STP24DP05
Recommended operating conditions
Table 6.
Symbol
Recommended operating conditions
Parameter
Test conditions
Min.
Typ.
Max.
Unit
5.5
V
20
V
80
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
Serial-OUT
+10
mA
IOL
Output current
Serial-OUT
-10
mA
VIH
Input voltage
0.7 VDD
VDD+0.3
V
VIL
Input voltage
-0.3
0.3 VDD
V
twLAT
LE pulse width
15
ns
twCLK
CLK pulse width
15
ns
twEN
OE pulse width
150
ns
15
ns
5
ns
10
ns
3.0
5
VDD = 3.0 V to 5.0 V
tSETUP(D) Setup time for DATA
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
fCLK
Clock frequency
Cascade operation
(1)
25
MHz
1. If the device is connected in cascade, it may not be possible to achieve the maximum data transfer. Please
consider the timings carefully.
6/27
Doc ID 14714 Rev 5
STP24DP05
3
Electrical characteristics
Electrical characteristics
T = 25 °C, unless otherwise specified.
Table 7.
Symbol
Electrical characteristics (VDD = 3.3 V to 5 V)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIH
Input voltage high level
0.7 VDD
VDD
V
VIL
Input voltage low level
GND
0.3 VDD
V
IOH
Output leakage current
VOH = 20 V
10
μA
VOL
Output voltage
(Serial-OUT)
IOL = 1 mA
0.4
V
VOH
Output voltage
(Serial-OUT)
IOH = -1 mA
IOL1
IOL2
Output current
IOL3
ΔIOL1
ΔIOL2
ΔIOL3
RSIN(up)
VDD-0.4 V
V
VO = 0.3 V, REXT = 2 kΩ,
IO = 10 mA
10
mA
VO = 0.3 V, REXT = 1 kΩ,
IO = 20 mA
20
mA
VO = 0.3 V, REXT = 250 Ω,
IO = 80 mA
80
mA
VO = 0.3 V, REXT = 2 kΩ,
IO = 10 mA
±2
±3
%
±2
±3
%
±2
±3
%
Output current error among
VO = 0.3 V, REXT = 1 kΩ,
the channels
IO = 20 mA
(All outputs ON)
VO = 0.3 V, REXT = 250 Ω,
IO = 80 mA
Pull-up resistor
300
600
800
kΩ
RSIN(down)
Pull-down resistor
300
400
500
kΩ
LE(up)
DG(up)
OE-R\
DM (up)
OE-G (up)
OE-B (up)
DF0
DF1
Pull-up resistor
300
400
500
kΩ
REXT = 1 kΩ
OUT 0 to 15 = OFF
9
12
IDD(OFF2)
REXT = 250 Ω
OUT 0 to 15 = OFF
32
40
IDD(ON1)
REXT = 1 kΩ
OUT 0 to 15 = ON
13
18
REXT = 250 Ω
OUT 0 to 15 = ON
35
40
IDD(OFF1)
Supply current (OFF)
mA
Supply current (ON)
IDD(ON2)
Doc ID 14714 Rev 5
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Electrical characteristics
Table 7.
Electrical characteristics (VDD = 3.3 V to 5 V) (continued)
Symbol
Parameter
Thermal
Thermal protection
VTF
Output voltage
ITF
Output current
VEF
Output voltage
IEF
Output current
Table 8.
STP24DP05
Test conditions
Min.
Max.
170
°C
5
VTF @ 1 V
V
20
mA
5
VEF @ 1 V
Unit
V
20
mA
Switching characteristics (VDD = 3.3 V, 5 V)
Symbol
Parameter
tPLH1
Propagation delay time,
CLK-OUTn, LE = H, OE = L
tPLH2
Propagation delay time,
LE-OUTn, OE = L
tPLH3
Propagation delay time,
OE-OUTn, LE = H
tPLH
Propagation delay time,
CLK-SDO
tPHL1
Propagation delay time,
CLK-OUTn, LE = H,
OE = L
tPHL2
Propagation delay time,
LE-OUTn, OE = L
tPHL3
Propagation delay time,
OE-OUTn, LE = H
tPHL
Propagation delay time,
CLK-SDO
tON
Output rise time
10~90% of voltage
waveform
tOFF
Output fall time
90~10% of voltage
waveform
Test conditions
VIH = VDD
VIL = GND
IO = 20 mA
REXT = 1 kΩ
Min.
Typ.
Max.
VDD = 3.3 V
62
100
VDD = 5 V
38
60
VDD = 3.3 V
67
107
VDD = 5 V
44
60
VDD = 3.3 V
65
83
VDD = 5 V
38
45
Unit
ns
ns
ns
VDD = 3.3 V
14
22
36
VDD = 5 V
9
14
23
VDD = 3.3 V
46
70
VDD = 5 V
39
50
VDD = 3.3 V
51
76
VDD = 5 V
46
55
VDD = 3.3 V
41
45
VDD = 5 V
33
39
ns
ns
CL = 10 pF
VL = 3.0 V
RL = 60 Ω
ns
ns
VDD = 3.3 V
15
24
38
VDD = 5 V
9
15
24
VDD = 3.3 V
33
57
VDD = 5 V
17
27
VDD = 3.3 V
24
34
VDD = 5 V
25
37
ns
ns
ns
tr
CLK rise time (1)
5000
ns
tf
CLK fall time (1)
5000
ns
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
8/27
Typ.
Doc ID 14714 Rev 5
STP24DP05
Block diagram
4
Block diagram
Figure 2.
Block diagram
Doc ID 14714 Rev 5
9/27
Equivalent circuit and outputs
5
10/27
STP24DP05
Equivalent circuit and outputs
Figure 3.
OExx terminal
Figure 4.
LE\DM terminal
Figure 5.
CLK, SDI terminal
Doc ID 14714 Rev 5
STP24DP05
Equivalent circuit and outputs
Figure 6.
SDO terminal
Figure 7.
TF and EF
Doc ID 14714 Rev 5
11/27
Timing diagrams
6
Timing diagrams
Figure 8.
Note:
12/27
STP24DP05
Timing diagram
1
Latch and output enable are level sensitive and are not synchronized with rising-or-falling
edge of CLK signal.
2
When LE\DM terminal is low level, the latch circuit holds the previous set of data.
3
When LE\DM terminal is high level, the latch circuit refreshes the new set of data
from the SDI chain.
4
When either OE-R\DM, OE-G, or OE-B terminals are at low level, output terminals R\G\B1
to R\G\B8 respond to the data, either ON or OFF.
5
When either OE-R\DM, OE-G, or OE-B terminals are at high level, all the data on the output
terminal R\G\B1 to R\G\B8 is switched off.
6
This device can customize the RGB sequence serial data flow by means of setting DF0 and
DF1 (refer to Table 14.).
Doc ID 14714 Rev 5
STP24DP05
Timing diagrams
Figure 9.
Clock, serial-IN, serial-OUT
Doc ID 14714 Rev 5
13/27
Timing diagrams
STP24DP05
Figure 10. Clock, serial-IN, latch, enable, outputs
Figure 11. Outputs
14/27
Doc ID 14714 Rev 5
STP24DP05
Features description
7
Features description
7.1
DG: gradual output delay
This feature prevents large inrush current and reduces the bypass capacitors.
The fixed delay time can be activated with DG = LOW and the typical output delay is 30 ns
for each group of 8 outputs, R, G, and B. E.g.: R1, G1, B1 has no delay, R2, G2, B2 has 30
ns delay and R3, G3, B3, has 60 ns delay, etc.
Table 9.
Typical gradual delay time table
Delay time (ns) from ↓OExx
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R7
G7
B7
R8
G8
B8
DG = 0
0
30
60
90
120
150
180
210
0
0
0
0
0
0
0
DG = 1
7.2
Error detection condition
Table 10.
Detection conditions (VDD = 3.3 to 5 V, IO = 20 mA, tA = 25 °C)
SW-1 Open Open line or output short
or SW-3b to GND detected
SW-2
Closed or
SW-3a
Note:
Short on LED or short to
V-LED detected
=> IODEC ≤ 0.4 x IO
No error
detected
=> IODEC ≥ 0.35 x IO
=> VO ≥ 2.6 V
No error
detected
=> VO ≤ 2.4 V
IO = the output current programmed by the REXT
IODEC = the detected output current in detection mode
Table 11.
Typical current threshold values to detect LED open line
Iset (mA)
Rext (Ω)
Typ. out current detection (mA)
5
3920
1.28
10
1960
2.45
20
980
7.4
50
386
17
80
241
27
Doc ID 14714 Rev 5
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Features description
STP24DP05
Figure 12. Detection circuit
23
24
STP24DP05
16
7.3
Phase one: “entering detection mode”
From the “normal mode” condition the device can switch to the “error detection mode”
through a DM PIN set to LOW or a logic sequence on the OE-R\DM and LE\DM pins as
shown in Figure 13, 14 and Table 12:
Figure 13. EDM timing diagram using a DM pin
OE-R\DM
Table 12.
16/27
SPI sequence to enter detection mode - truth table
CLK
1°
2°
3°
4°
5°
OE-R\DM
H
L
H
H
H
LE\DM
L
L
L
H
L
Doc ID 14714 Rev 5
STP24DP05
Features description
Figure 14. SPI sequence to enter detection mode - time diagram
OE-R\DM
LE\DM
After these five CLK cycles the device goes into “error detection mode” and at the 6th rise
front of CLK, the SDI data are ready for the sampling.
7.4
Phase two: “error detection”
The eight data bits must be set “1” in order to set all the outputs ON during detection. The
data are latched by LE\DM and after that the outputs are ready for the detection process.
When the microcontroller switches the OE-R\DM to LOW, the device drives the LEDs in
order to analyze if an OPEN or SHORT condition has occurred.
Figure 15. Detection diagram
The LED status is detected after at least 1 microsecond and after this time the
microcontroller sets OE-R\DM in HIGH state and the output data detection result goes to the
microprocessor via the SDO pin.
Detection mode and normal mode both use the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal
operation mode. The result of the error detection is shifted out of the SDO pin providing 24
clock pulses. A faulty output is indicated as “0”, whereas a good output is indicated as “1”.
The result is shifted out according to the selected data flow (DF0 and DF1 status, see
Section 7.6).
Doc ID 14714 Rev 5
17/27
Features description
7.5
STP24DP05
Phase three: “resuming normal mode”
In order to re-enter normal mode, either the LE\DM pin or the sequence shown in the
following table can be used:
Table 13.
SPI sequence to resume in normal mode - truth table
CLK
1°
2°
3°
4°
5°
OE-R\DM
H
L
H
H
H
LE\DM
L
L
L
L
L
Note:
For proper device operation the “entering detection” sequence must be followed by a
“resume mode” sequence, it is not possible to insert a consecutive equal sequence.
7.6
Shift register data flow control
The 8x3 shift registers have a default RGB sequence serial data flow as show in the block
diagram of Figure 2.
The data can be redirected by the DF0 and DF1 pins, these pins change the order of the
data flow according to the following table:
Table 14.
Shifter register data flow control
Sequence
DF0
DF1
BGR
1
1
BRG
0
1
RGB
1
0
GRB
0
0
The status of pins DF0 and DF1 also influences the sequence of the error detection result
shifted out of the SDO pin.
Note:
18/27
If the DF0 and DF1 pins are left floating, they are pulled-up to Vdd by internal pull-up
resistors. In such conditions, the shift register sequence is set to BGR.
Doc ID 14714 Rev 5
STP24DP05
7.7
Features description
EFLAG/TFLAG - output detection and overtemperature
monitoring
The open drain output EFLAG and TFLAG are used to report the STP24DP05 status flags.
During normal operating conditions, the EFLAG/TFLAG pins should be pulled up through an
external resistor. The EFLAF is turned on (shorted to GND) while the error detection is
running. The TFLAG is turned on (shorted to GND) when the silicon temperature exceeds
180 °C.
Figure 16. TF and EF test circuit
Doc ID 14714 Rev 5
19/27
Typical application schematic
8
STP24DP05
Typical application schematic
Figure 17. Typical application schematic
20/27
Doc ID 14714 Rev 5
STP24DP05
Typical characteristics
Figure 18. Typical external resistor values vs. output current capabilities
4500
4000
External Resistance (Ohm)
9
Typical characteristics
3500
Temp. = 25°C
Vdd = 5.0V
Iset = 5mA; 10mA; 20mA; 50mA; 80mA
3000
2500
2000
1500
1000
500
0
0
10
20
30
40
50
60
70
80
90
Output Current (mA)
Table 15.
Typical external resistor values vs. output current capabilities
Iset
5 mA
10 mA
20 mA
50 mA
80 mA
Rext (Ω)
4210
2050
1000
400
249
Figure 19. Typical dropout voltage vs. output current
Table 16.
Typical dropout voltage vs. output current
Iset
Rext (Ω)
Avg (mV) @ 3.3 V
Avg (mV) @ 5.0 V
5
4210
59
41
10
2050
130
90
20
1000
201
180
50
400
500
480
80
249
810
790
Doc ID 14714 Rev 5
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Package mechanical data
10
STP24DP05
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
22/27
Doc ID 14714 Rev 5
STP24DP05
Package mechanical data
Table 17.
TQFP48-EP mechanical data
Dim.
Min.
Typ.
A
Max
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
b
0.17
0.22
0.27
c
0.09
D
8.80
9.00
9.20
D1
6.80
7.00
7.20
0.20
D2
3.50
D3
5.50
E
8.80
9.00
9.20
E1
6.80
7.00
7.20
E2
3.50
E3
5.50
e
0.50
L
0.45
L1
k
0.60
0.75
1.00
0
ccc
3.5
7
0.08
Doc ID 14714 Rev 5
23/27
Package mechanical data
STP24DP05
Figure 20. TQFP48-EP mechanical data
24/27
Doc ID 14714 Rev 5
STP24DP05
Package mechanical data
Figure 21. Tape and reel TQFP48-EP
Tape & Reel TQFP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
22.4
0.519
0.882
Ao
9.5
9.7
0.374
0.382
Bo
9.5
9.7
0.374
0.382
Ko
2.1
2.3
0.083
0.091
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
Doc ID 14714 Rev 5
25/27
Revision history
11
STP24DP05
Revision history
Table 18.
26/27
Document revision history
Date
Revision
Changes
19-Apr-2008
1
First release
12-Jan-2009
2
Updated package to TQFP48-EP
04-Mar-2009
3
Updated Table 3 on page 4
13-Nov-2009
4
Updated Table 3 on page 4
21-Feb-2012
5
– Modified: Section 6, 7.4 and 7.7
– Modified: Table 14
– Modified: Figure 8
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