STP35N60DM2

STP35N60DM2 N-channel 600 V, 0.094 Ω typ., 28 A MDmesh™ DM2 Power MOSFET in a TO-220 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STP35N60DM2 600 V 0.110 Ω 28 A 210 W       Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Figure 1: Internal schematic diagram Applications  Switching applications Description This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1: Device summary Order code Marking Package Packing STP35N60DM2 35N60DM2 TO-220 Tube September 2015 DocID028348 Rev 1 This is information on a product in full production. 1/13 www.st.com Contents STP35N60DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220 type A package information................................................ 10 Revision history ............................................................................ 12 DocID028348 Rev 1 STP35N60DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS ID (1) IDM PTOT Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 28 Drain current (continuous) at Tcase = 100 °C 17 Drain current (pulsed) 112 A W A Total dissipation at Tcase = 25 °C 210 dv/dt (2) Peak diode recovery voltage slope 50 dv/dt (3) MOSFET dv/dt ruggedness 50 Tstg Tj Storage temperature Operating junction temperature V/ns -55 to 150 °C Notes: (1) Pulse width is limited by safe operating area. (2) ISD ≤ 28 A, di/dt=900 A/μs; VDS peak < V(BR)DSS,VDD = 400. (3) VDS ≤ 480 V. Table 3: Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case 0.6 Rthj-amb Thermal resistance junction-amb 62.5 Unit °C/W Table 4: Avalanche characteristics Symbol IAR (1) EAS Parameter Avalanche current, repetitive or not repetitive Single pulse avalanche energy Value Unit 6 A 650 mJ Notes: (1) starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID028348 Rev 1 3/13 Electrical characteristics 2 STP35N60DM2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 10 VGS = 0 V, VDS = 600 V, Tcase = 125 °C 100 Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 14 A 0.094 0.11 Ω Min. Typ. Max. Unit - 2400 - - 110 - - 2.8 - IDSS Zero gate voltage drain current IGSS 3 µA Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 190 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 4.3 - Ω Qg Total gate charge - 54 - Qgs Gate-source charge - 14.6 - Qgd Gate-drain charge - 24.2 - Coss eq. (1) VDD = 480 V, ID = 28 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 4/13 pF DocID028348 Rev 1 nC STP35N60DM2 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off delay time tf Test conditions VDD = 300 V, ID = 14 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") Fall time Min. Typ. Max. Unit - 21.2 - - 17 - - 68 - - 10.7 - Min. Typ. Max. Unit ns Table 8: Source-drain diode Symbol ISD (1) ISDM (2) VSD Parameter Test conditions Source-drain current - 28 A Source-drain current (pulsed) - 112 A - 1.6 V Forward on voltage VGS = 0 V, ISD = 28 A trr Reverse recovery time Qrr Reverse recovery charge IRRM - 120 ns - 572 nC Reverse recovery current - 10.2 A trr Reverse recovery time - 215 ns Qrr Reverse recovery charge - 1.89 µC IRRM Reverse recovery current - 17.7 A ISD = 28 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ISD = 28 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = ±250 µA, ID = 0 A ±30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID028348 Rev 1 5/13 Electrical characteristics 2.1 STP35N60DM2 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*Rthj-c δ= tp/Ƭ 0.01 Single pulse 10 -2 10 -5 6/13 10 -4 10 tp -3 10 -2 Ƭ 10 -1 t P (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028348 Rev 1 STP35N60DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID028348 Rev 1 7/13 Test circuits 3 STP35N60DM2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/13 DocID028348 Rev 1 Figure 19: Switching time waveform STP35N60DM2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID028348 Rev 1 9/13 Package information 4.1 STP35N60DM2 TO-220 type A package information Figure 20: TO-220 type A package outline 10/13 DocID028348 Rev 1 STP35N60DM2 Package information Table 10: TO-220 type A mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95 DocID028348 Rev 1 11/13 Revision history 5 STP35N60DM2 Revision history Table 11: Document revision history 12/13 Date Revision 10-Sep-2015 1 DocID028348 Rev 1 Changes Initial version STP35N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID028348 Rev 1 13/13