STP40N03L-20
N - CHANNEL ENHANCEMENT MODE ”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR
PRELIMINARY DATA TYPE ST P40N03L-20
s s s s s s s
V DSS 30 V
R DS(on) < 0.02 Ω
ID 40 A
TYPICAL RDS(on) = 0.016 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED HIGH CURRENT CAPABILITY 175oC OPERATING TEMPERATURE HIGH dV/dt CAPABILITY APPLICATION ORIENTED CHARACTERIZATION TO-220
1
2
3
APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s POWER MOTOR CONTROL s DC-DC & DC-AC CONVERTERS s SYNCRONOUS RECTIFICATION
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID I DM ( • ) P to t Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω) Gate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) Total Dissipation at T c = 25 C Derating Factor dV/dt( 1 ) T st g Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature
o o o
Value 30 30 ± 15 40 28 160 90 0.6 6 -65 to 175 175
Unit V V V A A A W W/ C V/ns
o o o
C C
( •) Pulse width limited by safe operating area
March 1996
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STP40N03L-20
THERMAL DATA
R t hj-ca se R t hj- amb R thc- si nk Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Case-sink Maximum Lead T emperature For Soldering Purpose Max Max Typ 1.66 62.5 0.5 300
o o
C/W C/W o C/W o C
AVALANCHE CHARACTERISTICS
Symb ol I AR E AS E AR I AR Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) Single Pulse Avalanche Energy o (starting Tj = 25 C, ID = I AR , V DD = 25 V) Repetitive Avalanche Energy (pulse width limited by Tj max, δ < 1%) Avalanche Current, Repetitive or Not-Repetitive o (T c = 100 C, pulse width limited by Tj max, δ < 1%) Max Valu e 40 300 75 28 Unit A mJ mJ A
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 µA VGS = 0 Min. 30 250 1000 ± 100 Typ . Max. Un it V µA µA nA
Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating x 0.8 T c = 125 o C Gate-body Leakage Current (V DS = 0) V GS = ± 1 5 V
ON (∗)
Symb ol V GS(th) R DS( on) Parameter Gate T hreshold Voltage V DS = VGS Static Drain-source On Resistance On State Drain Current Test Cond ition s ID = 250 µ A T c = 100 o C 0.019 40 Min. 1 Typ . 1.6 0.016 Max. 2 0.02 0.04 0.023 Un it V Ω Ω Ω A
V GS = 10V I D = 20 A V GS = 10V ID = 20 A V GS = 5V I D = 20 A V DS > I D(on) x R DS(on) max V GS = 10 V
ID(o n)
DYNAMIC
Symb ol g fs ( ∗ ) C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Cond ition s V DS > I D(on) x R DS(on) max V DS = 25 V f = 1 MHz I D = 20 A VGS = 0 Min. 15 Typ . 22 1800 450 180 2300 580 230 Max. Un it S pF pF pF
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STP40N03L-20
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symb ol t d(on) tr (di/dt) on Parameter Turn-on T ime Rise Time Turn-on Current Slope Test Cond ition s V DD = 15 V ID = 10 A VGS = 5 V R G = 4.7 Ω (see test circuit, figure 3) V DD = 24 V ID = 20 A R G = 50 Ω V GS = 5 V (see test circuit, figure 5) V DD = 24 V ID = 20 A V GS = 5 V Min. Typ . 20 80 200 Max. 30 100 Un it ns ns A/ µ s
Qg Q gs Q gd
Total Gate Charge Gate-Source Charge Gate-Drain Charge
40 10 20
60
nC nC nC
SWITCHING OFF
Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall T ime Cross-over T ime Test Cond ition s V DD = 24 V I D = 20 A R G = 4.7 Ω V GS = 5 V (see test circuit, figure 5) Min. Typ . 42 45 76 Max. 55 60 100 Un it ns ns ns
SOURCE DRAIN DIODE
Symb ol I SD I SDM (• ) V SD ( ∗ ) t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward O n Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 40 A V GS = 0 65 0.12 4 I SD = 20 A di/dt = 100 A/µ s o Tj = 150 C V DD = 24 V (see test circuit, figure 5) Test Cond ition s Min. Typ . Max. 40 160 1.5 Un it A A V ns µC A
( ∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % ( •) Pulse width limited by safe operating area ( 1) ISD ≤ 40 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
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STP40N03L-20
PSPICE PARAMETERS SUBCIRCUIT COMPONENTS
Symb ol S1 S2 LD LG LS RDRAIN RG ATE CG D CGS ALFA RG N Parameter (V14_16
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