STP40N65M2

STI40N65M2, STP40N65M2 N-channel 650 V, 0.087 Ω typ., 32 A MDmesh™ M2 Power MOSFET in I²PAK and TO-220 packages Datasheet - production data Features TAB TAB Order code STI40N65M2 STP40N65M2 I²PAK 1 2 3 1 2 3 TO-220 • • • • VDS RDS(on) max. ID 650 V 0.099 Ω 32 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram • Switching applications D(2, TAB) Description These devices are N-channel Power MOSFETs developed using MDmesh™ M2 technology. Thanks to their strip layout and improved vertical structure, the devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1_tab Table 1: Device summary Order code STI40N65M2 STP40N65M2 February 2015 Marking 40N65M2 DocID027478 Rev 1 This is information on a product in full production. Package I²PAK TO-220 Packaging Tube 1/14 www.st.com Contents STI40N65M2, STP40N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.2 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/14 4.1 I²PAK package information ............................................................... 9 4.2 TO-220 type A package information................................................ 11 Revision history ............................................................................ 13 DocID027478 Rev 1 STI40N65M2, STP40N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 32 A ID Drain current (continuous) at TC= 100 °C 20 A (1) IDM Drain current (pulsed) 128 A PTOT Total dissipation at TC = 25 °C 250 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns Tstg Tj Storage temperature - 55 to 150 Max. operating junction temperature 150 °C Notes: (1) Pulse width limited by safe operating area. (2) ISD ≤ 32 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V (3) VDS ≤ 520 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max Value Unit 0.5 °C/W 62.50 °C/W Value Unit Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 3 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 820 mJ DocID027478 Rev 1 3/14 Electrical characteristics 2 STI40N65M2, STP40N65M2 Electrical characteristics (TC= 25 °C unless otherwise specified) Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min . Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 16 A 0.087 0.099 Ω Min. Typ. Max. Unit - 2355 - pF - 102 - pF - 2.7 - pF 2 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance VDS = 0 V to 520 V, VGS = 0 V - 380 - pF RG Intrinsic gate resistance f = 1 MHz, open drain - 4.5 - Ω Qg Total gate charge - 56.5 - nC Qgs Gate-source charge - 8 - nC Qgd Gate-drain charge - 24 - nC Coss eq. (1) VDD = 520 V, ID = 32 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/14 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 325 V, ID = 16 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 15 - ns - 10 - ns - 96.5 - ns - 12 - ns DocID027478 Rev 1 STI40N65M2, STP40N65M2 Electrical characteristics Table 8: Source drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 32 A (1) Source-drain current (pulsed) - 128 A (2) Forward on voltage VGS = 0 V, ISD = 32 A - 1.6 V trr Reverse recovery time - 468 ns Qrr Reverse recovery charge - 8.7 µC IRRM Reverse recovery current ISD = 32 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") - 37.5 A - 610 ns - 11.7 µC - 39 A ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 32 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area Pulse test: pulse duration = 300 µs, duty cycle 1.5% DocID027478 Rev 1 5/14 Electrical characteristics 2.2 STI40N65M2, STP40N65M2 Electrical characteristics (curves) Figure 2: Safe operating area ID (A) Figure 3: Thermal impedance GIPG090220151652ALS GC20540 K δ=0.5 100 1 0.1 DS (o n) 10 O p lim era ite tio d ni by n m this ax a R r ea is 0.2 0.1 0.1 10µs 100µs 1ms 0.02 Zth= K*Rthj-c δ= tp/Ƭ Tj = 150 °C Tc = 25 °C Single pulse 0.01 Single pulse VDS(V) 100 Figure 4: Output characteristics ID (A) 70 0.05 10ms 10 1 10-1 GIPG300120151500ALS VGS = 6,7,8,9,10 V 10-4 tp 10-3 10-2 Ƭ 10-1 tP(s) Figure 5: Transfer characteristics ID (A) GIPG300120151715ALS 70 VGS = 5 V 60 10-2 10-5 60 50 50 40 40 30 VGS = 4 V VGS = 20 V 30 20 20 10 10 0 0 0 0 4 8 12 16 20 24 VDS (V) Figure 6: Normalized gate threshold voltage vs temperature 6/14 DocID027478 Rev 1 2 4 6 8 VGS (V) Figure 7: Normalized V(BR)DSS vs temperature STI40N65M2, STP40N65M2 Electrical characteristics Figure 8: Static drain-source on-resistance Figure 9: Normalized on-resistance vs. temperature Figure 10: Gate charge vs. gate-source voltage Figure 11: Capacitance variations Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID027478 Rev 1 7/14 Test circuits 3 STI40N65M2, STP40N65M2 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VDD 47 k Ω 12 V 1 kΩ 100 nF I G = CONST Vi ≤ V GS 100 Ω D.U.T. 2.7 k Ω 2200 μ F VG 47 k Ω PW 1 kΩ AM01469v 1 Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 17: Unclamped inductive load test circuit A D G S 25 Ω L=100 µH 3.3 µF B 1000 µF D G RG VDD D.U.T. S AM01470v1 Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform toff t on V(BR)DSS t d(on) tr t d(off) tf VD 90% 90% I DM 10% ID VDD 10% 0 VDD VGS AM01472v 1 8/14 DocID027478 Rev 1 0 10% VDS 90% AM01473v 1 STI40N65M2, STP40N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 I²PAK package information Figure 20: I²PAK package outline 0004982_Rev_H DocID027478 Rev 1 9/14 Package information STI40N65M2, STP40N65M2 Table 9: I²PAK mechanical data mm Dim. 10/14 Min. Typ. Max. A 4.40 – 4.60 A1 2.40 – 2.72 b 0.61 – 0.88 b1 1.14 – 1.70 c 0.49 – 0.70 c2 1.23 – 1.32 D 8.95 – 9.35 e 2.40 – 2.70 e1 4.95 – 5.15 E 10 – 10.40 L 13 – 14 L1 3.50 – 3.93 L2 1.27 – 1.40 DocID027478 Rev 1 STI40N65M2, STP40N65M2 4.2 Package information TO-220 type A package information Figure 21: TO-220 type A package outline DocID027478 Rev 1 11/14 Package information STI40N65M2, STP40N65M2 Table 10: TO-220 type A mechanical data mm Dim. Min. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 12/14 Typ. 28.90 øP 3.75 3.85 Q 2.65 2.95 DocID027478 Rev 1 STI40N65M2, STP40N65M2 5 Revision history Revision history Table 11: Document revision history Date Revision 09-Feb-2014 1 DocID027478 Rev 1 Changes First release. 13/14 STI40N65M2, STP40N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 14/14 DocID027478 Rev 1