STP70NF3LL

STB70NF3LL STP70NF3LL N-CHANNEL 30V - 0.0075 Ω - 70A D²PAK/TO-220 LOW GATE CHARGE STripFET™ II POWER MOSFET TYPE STB70NF3LL STP70NF3LL s s s s VDSS 30 V 30 V RDS(on) < 0.0095 Ω < 0.0095 Ω ID 70 A 70 A TYPICAL RDS(on) = 0.0075 Ω @ 10 V OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5 V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 3 1 3 1 2 DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS s SWITCHING APPLICATIONS D2PAK TO-263 (Suffix “T4”) TO-220 INTERNAL SCHEMATIC DIAGRAM Ordering Information SALES TYPE STB70NF3LLT4 STP70NF3LL MARKING B70NF3LL@ P70NF3LL@ PACKAGE D2PAK TO-220 PACKAGING TAPE & REEL TUBE ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(•) ID IDM(••) Ptot dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Operating Junction Temperature Value 30 30 ± 16 70 50 280 100 0.67 5.5 500 -55 to 175 (1) ISD ≤70A, di/dt ≤350A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX (2) Starting T j = 25 oC, ID = 35A, VDD = 25V Unit V V V A A A W W/°C V/ns mJ °C (•) Current limited by the package (••) Pulse width limited by safe operating area. October 2003 1/10 NEW DATASHEET ACCORDING TO PCN DSG/CT/2C13 MARKING: P70NF3LL@ B70NF3LL@ STB70NF3LL STP70NF3LL THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 1.5 62.5 300 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125°C VGS = ± 16 V Min. 30 1 10 ±100 Typ. Max. Unit V µA µA nA ON (*) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 µA ID = 35 A ID = 18 A Min. 1 0.0075 0.010 0.0095 0.012 Typ. Max. Unit V Ω Ω DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15 V ID = 35 A Min. Typ. 25 1650 540 130 Max. Unit S pF pF pF VDS = 25V f = 1 MHz VGS = 0 2/10 STB70NF3LL STP70NF3LL ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 35 A VDD = 15 V RG = 4.7 Ω VGS = 4.5 V (Resistive Load, Figure 3) VDD= 15V ID= 70A VGS= 4.5V Min. Typ. 23 156 24 8.5 12 33 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 35 A VDD = 15 V RG = 4.7Ω, VGS = 4.5 V (Resistive Load, Figure 3) Min. Typ. 27 28 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (•) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current 1.5 %. Test Conditions Min. Typ. Max. 70 280 Unit A A V ns nC A ISD = 70 A VGS = 0 40 50 2.5 1.3 di/dt = 100A/µs ISD = 70 A VDD = 25 V Tj = 150°C (see test circuit, Figure 5) (*)Pulsed: Pulse duration = 300 µs, duty cycle (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/10 STB70NF3LL STP70NF3LL Output Characteristics Transfer Characteristics Source-drain Diode Forward Characteristics Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/10 STB70NF3LL STP70NF3LL Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Normalized Breakdown Voltage vs Temperature. . . 5/10 STB70NF3LL STP70NF3LL Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/10 STB70NF3LL STP70NF3LL D2PAK MECHANICAL DATA DIM. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0° 4.88 15 1.27 1.4 2.4 0.4 8° 0° 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.591 0.050 0.055 0.094 0.015 8° mm. MIN. 4.4 2.49 0.03 0.7 1.14 0.45 1.21 8.95 8 10.4 0.394 0.334 0.208 0.624 0.055 0.069 0.126 TYP. MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.028 0.045 0.018 0.048 0.352 0.315 0.409 inch. TYP. TYP. 0.181 0.106 0.009 0.037 0.067 0.024 0.054 0.368 7/10 STB70NF3LL STP70NF3LL TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 F1 D G1 E Dia. L5 L7 L6 L4 P011C L9 8/10 F2 F G H2 STB70NF3LL STP70NF3LL D2PAK FOOTPRINT TUBE SHIPMENT (no suffix)* TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 24.4 100 30.4 BASE QTY 1000 26.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.795 0.960 3.937 1.197 BULK QTY 1000 1.039 0.520 MIN. inch MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 D D1 E F K0 P0 P1 P2 R T W mm MIN. 10.5 15.7 1.5 1.59 1.65 11.4 4.8 3.9 11.9 1.9 50 0.25 23.7 0.35 24.3 MAX. 10.7 15.9 1.6 1.61 1.85 11.6 5.0 4.1 12.1 2.1 MIN. 0.413 0.618 0.059 0.062 0.065 0.449 0.189 0.153 0.468 0075 1.574 .0.0098 0.933 0.0137 0.956 inch MAX. 0.421 0.626 0.063 0.063 0.073 0.456 0.197 0.161 0.476 0.082 * on sales type 9/10 STB70NF3LL STP70NF3LL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. ® 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 10/10