STP7N105K5

STP7N105K5, STU7N105K5, STW7N105K5 N-channel 1050 V, 1.4 Ω typ., 4 A MDmesh™ K5 Power MOSFETs in TO-220, IPAK and TO-247 packages Datasheet - production data TAB Features TAB Order code IPAK TO-220 1 2 1 2 3 VDS RDS(on) max. ID PTOT 1050 V 2Ω 4A 110 W STP7N105K5 STU7N105K5 STW7N105K5 3 3 TO-247      Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected 2 1 Applications Figure 1: Internal schematic diagram D(2, TAB)  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM01476v1 Table 1: Device summary Order code Marking STP7N105K5 STU7N105K5 Packaging TO-220 7N105K5 STW7N105K5 October 2016 Package IPAK Tube TO-247 DocID026183 Rev 2 This is information on a product in full production. 1/18 www.st.com Contents STP7N105K5, STU7N105K5, STW7N105K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/18 4.1 TO-220 package information ........................................................... 11 4.2 IPAK package information ............................................................... 13 4.3 TO-247 package information ........................................................... 15 Revision history ............................................................................ 17 DocID026183 Rev 2 STP7N105K5, STU7N105K5, STW7N105K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate- source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 4 A ID Drain current (continuous) at TC = 100 °C 3 A IDM(1) Drain current (pulsed) 16 A PTOT Total dissipation at TC = 25 °C 110 W IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.5 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID=IAR, VDD= 50 V) 132 mJ dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area. ≤ 4 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS ; VSD ≤ 840 V DS ≤ 840 V Table 3: Thermal data Value Symbol Parameter Unit TO-220 Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-amb max DocID026183 Rev 2 IPAK TO-247 1.14 62.5 100 °C/W 50 °C/W 3/18 Electrical characteristics 2 STP7N105K5, STU7N105K5, STW7N105K5 Electrical characteristics (TCASE = 25 °C unless otherwise specified). Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS= 0, ID = 1 mA Min. Typ. Max. 1050 Unit V VGS = 0, VDS = 1050 V 1 µA VGS = 0, VDS = 1050 V, Tc=125 °C(1) 50 µA Gate body leakage current VDS = 0, VGS = ± 20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID= 2 A 1.4 2 Ω Min. Typ. Max. Unit - 380 - pF - 40 - pF - 0.65 - pF - 47 - pF - 17 - pF IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Test conditions VDS =100 V, f=1 MHz, VGS=0 Equivalent capacitance time related VGS = 0, VDS = 0 to 840 V Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1MHz open drain - 7 - Ω Qg Total gate charge - 11 - nC Qgs Gate-source charge - 2.8 - nC Qgd Gate-drain charge VDD = 840 V, ID = 4 A VGS =10 V Figure 18: "Test circuit for gate charge behavior" - 5.6 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS 4/18 DocID026183 Rev 2 STP7N105K5, STU7N105K5, STW7N105K5 Electrical characteristics Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 525V, ID = 2 A, RG=4.7 Ω, VGS=10 V (see Figure 17: "Test circuit for resistive load switching times" and Figure 22: "Switching time waveform") - 17.5 - ns - 7 - ns - 43 - ns - 25 - ns Min. Typ. Max. Unit 4 A 16 A 1.6 V tr td(off) tf Rise time Turn-off delay time Fall time Table 7: Source drain diode Symbol Parameter ISD Source-drain current ISDM Source-drain current (pulsed) VSD(1) Test conditions - Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD= 4 A, VGS=0 - ISD= 4 A, VDD= 60 V di/dt = 100 A/µs, Figure 19: "Test circuit for inductive load switching and diode recovery times" - 370 ns - 3 µC - 16.5 A ISD= 4 A,VDD= 60 V di/dt=100 A/µs, Tj=150 °C Figure 19: "Test circuit for inductive load switching and diode recovery times" - 600 ns - 4.4 µC - 14.5 A Notes: (1)Pulsed: pulse duration = 300µs, duty cycle 1.5% Table 8: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ± 1mA, ID=0 Min Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID026183 Rev 2 5/18 Electrical characteristics 2.1 STP7N105K5, STU7N105K5, STW7N105K5 Electrical characteristics (curves) Figure 2: Safe operating area for TO-220 and TO-247 Figure 3: Thermal impedance for TO-220 and TO-247 CG20930 K δ = 0.5 δ = 0.2 δ = 0.1 µ Ronlimit -1 10 Z Zthth == kk R Rthj-C thj-C δδ == ttp // ƬƬ p δ = 0.05 δ = 0.02 δ = 0.01 tp SINGLE PULSE 10-2 10-5 6/18 10-4 10-3 10-2 ƬƬ 10-1 tp(s) Figure 4: Safe operating area for IPAK Figure 5: Thermal impedance for IPAK Figure 6: Output characteristics Figure 7: Transfer characteristics DocID026183 Rev 2 STP7N105K5, STU7N105K5, STW7N105K5 Figure 8: Gate charge vs gate-source voltage Electrical characteristics Figure 9: Static drain-source on-resistance Ω Figure 10: Capacitance variations Figure 11: Source-drain diode forward characteristics Figure 12: Normalized gate threshold voltage vs temperature Figure 13: Normalized on-resistance vs temperature µ DocID026183 Rev 2 7/18 Electrical characteristics STP7N105K5, STU7N105K5, STW7N105K5 Figure 14: Normalized V(BR)DSS vs temperature Figure 15: Maximum avalanche energy vs starting Tj GIPG210320141421S A EAS (mJ) 120 ID=1.5 A VDD=50 V 100 80 60 40 20 0 0 20 40 Figure 16: Output capacitance stored energy µ 8/18 DocID026183 Rev 2 60 80 100 120 140 TJ(°C) STP7N105K5, STU7N105K5, STW7N105K5 3 Test circuits Test circuits Figure 18: Test circuit for gate charge behavior Figure 17: Test circuit for resistive load switching times Figure 19: Test circuit for inductive load switching and diode recovery times Figure 20: Unclamped inductive load test circuit Figure 21: Unclamped inductive waveform DocID026183 Rev 2 Figure 22: Switching time waveform 9/18 Package information 4 STP7N105K5, STU7N105K5, STW7N105K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/18 DocID026183 Rev 2 STP7N105K5, STU7N105K5, STW7N105K5 4.1 Package information TO-220 package information Figure 23: TO-220 type A package outline DocID026183 Rev 2 11/18 Package information STP7N105K5, STU7N105K5, STW7N105K5 Table 9: TO-220 type A mechanical data mm Dim. Min. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 D1 12/18 Typ. 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95 DocID026183 Rev 2 STP7N105K5, STU7N105K5, STW7N105K5 4.2 Package information IPAK package information Figure 24: IPAK (TO-251) type A package outline DocID026183 Rev 2 13/18 Package information STP7N105K5, STU7N105K5, STW7N105K5 Table 10: IPAK (TO-251) type A package mechanical data mm Dim. Min. Typ. A 2.20 2.40 A1 0.90 1.10 b 0.64 0.90 b2 b4 0.95 5.20 B5 5.40 0.30 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 E 6.40 6.60 e e1 2.28 4.40 H 14/18 Max. 4.60 16.10 L 9.00 9.40 L1 0.80 1.20 L2 0.80 V1 10° DocID026183 Rev 2 1.00 STP7N105K5, STU7N105K5, STW7N105K5 4.3 Package information TO-247 package information Figure 25: TO-247 package outline DocID026183 Rev 2 15/18 Package information STP7N105K5, STU7N105K5, STW7N105K5 Table 11: TO-247 package mechanical data mm Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 16/18 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID026183 Rev 2 3.65 5.50 5.50 5.70 STP7N105K5, STU7N105K5, STW7N105K5 5 Revision history Revision history Table 12: Document revision history Date Revision Changes 07-Apr-2014 1 First release. 17-Oct-2016 2 Updated Figure 8: "Gate charge vs gate-source voltage" and Table 5: "Dynamic". Minor text changes. DocID026183 Rev 2 17/18 STP7N105K5, STU7N105K5, STW7N105K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 18/18 DocID026183 Rev 2