STB80N20M5, STP80N20M5
Datasheet
N-channel 200 V, 15 mΩ, 65 A, MDmesh™ M5 Power MOSFETs
in D2PAK and TO‑220 packages
Features
Order codes
TAB
TAB
STB80N20M5
1
STP80N20M5
3
D2PAK
TO-220
1
2
3
VDS
RDS(on) max.
ID
200 V
20 mΩ
65 A
•
Extremely low RDS(on)
•
•
•
Low gate charge and input capacitance
Excellent switching performance
100% avalanche tested
D(2, TAB)
Applications
•
Switching applications
G(1)
Description
S(3)
AM01475v1_noZen
These devices are N-channel Power MOSFETs based on the MDmesh™ M5
innovative vertical process technology combined with the well-known PowerMESH™
horizontal layout. The resulting products offer extremely low on-resistance, making
them particularly suitable for applications requiring high power and superior
efficiency.
Product status links
STB80N20M5
STP80N20M5
Product summary
Order code: STB80N20M5
Marking
80N20M5
Package
D2PAK
Packing
Tape and reel
Order code: STP80N20M5
Marking
80N20M5
Package
TO-220
Packing
Tube
DS6286 - Rev 3 - January 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STB80N20M5, STP80N20M5
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Value
Unit
Gate-source voltage
±25
V
Drain current (continuous) at TC = 25 °C
65
A
Drain current (continuous) at TC = 100 °C
41
A
IDM(1)
Drain current (pulsed)
232
A
PTOT
Total power dissipation at TC = 25 °C
190
W
IAR
Avalanche current, repetitive or non-repetitive (pulse width limited by TJmax)
20
A
EAS
Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V)
500
mJ
Peak diode recovery voltage slope
15
V/ns
-55 to 150
°C
VGS
ID
dv/dt(2)
Tj
Tstg
Parameter
Operating junction temperature range
Storage temperature range
1. Pulse width limited by safe operating area
2. ISD ≤ 65 A, di/dt ≤ 400 A/μs, VDS(peak) < V(BR)DSS
Table 2. Thermal data
DS6286 - Rev 3
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-amb
Thermal resistance junction-ambient
Rthj-pcb
Thermal resistance junction-pcb
Value
D2PAK
TO-220
0.66
°C/W
62.5
30
Unit
°C/W
°C/W
page 2/17
STB80N20M5, STP80N20M5
Electrical characteristics
2
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 3. On/off states
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown voltage
ID = 1 mA, VGS = 0 V
Min.
Typ.
200
Zero gate voltage drain current
1
µA
100
µA
100
nA
4
5
V
15
20
mΩ
Typ.
Max.
Unit
-
pF
VGS = 0 V, VDS = 200 V,
TC = 125 °C(1)
IGSS
Gate-body leakage current
VDS = 0 V, VGS = ±25 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on resistance
VGS = 10 V, ID = 32.5 A
3
Unit
V
VGS = 0 V, VDS = 200 V
IDSS
Max.
1. Defined by design, not subject to production test.
Table 4. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Co(tr)(1)
Co(er)(2)
Time-related equivalent
capacitance
Energy-related equivalent
capacitance
Test conditions
VDS = 50 V, f = 1 MHz,
VGS = 0 V
4080
-
290
50
-
740
-
pF
-
295
-
pF
-
2
-
Ω
-
nC
VDS = 0 to 160 V, VGS = 0 V
Rg
Gate input resistance
f = 1 MHz open drain
Qg
Total gate charge
VDD = 160 V, ID = 32.5 A,
Qgs
Gate-source charge
VGS = 0 to 10 V
Gate-drain charge
(see Figure 14. Test circuit for gate
charge behavior)
Qgd
Min.
108
-
23
62
1. Co(tr) is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to
80% VDSS.
2. Co(er) is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to
80% VDSS.
Table 5. Switching times
Symbol
Test conditions
Min.
Typ.
td(v)
Voltage delay time
VDD = 160 V, ID = 65 A,
83
tr(v)
Voltage rise time
RG = 4.7 Ω, VGS = 10 V
26
Current fall time
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times and
Figure 18. Switching time
waveform)
tf(i)
tc(off)
DS6286 - Rev 3
Parameter
Crossing time
-
46
Max.
Unit
-
ns
77
page 3/17
STB80N20M5, STP80N20M5
Electrical characteristics
Table 6. Source drain diode
Symbol
ISD
Parameter
Test conditions
Source-drain current
Typ.
Source-drain current (pulsed)
VSD(2)
Forward on voltage
ISD = 65 A, VGS = 0 V
trr
Reverse recovery time
ISD = 65 A, di/dt = 100 A/µs,
Qrr
Reverse recovery charge
VDD = 60 V
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
trr
Reverse recovery time
ISD = 65 A, di/dt = 100 A/µs,
Qrr
Reverse recovery charge
VDD = 60 V, Tj = 150 °C
IRRM
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
232
-
-
-
Max.
65
-
ISDM(1)
IRRM
Min.
1.6
Unit
A
V
178
ns
1.4
µC
16
A
219
ns
2.1
µC
20
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
DS6286 - Rev 3
page 4/17
STB80N20M5, STP80N20M5
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
ID
(A)
102
Figure 2. Thermal impedance
GADG090120191248SOA
Operation in this area
is limited by RDS(on)
tp = 10 μs
101
tp = 100 μs
Single pulse,
TC = 25 °C,
TJ ≤ 150 °C
100
10-1
10-1
100
tp = 1 ms
101
tp = 10 ms
VDS (V)
102
Figure 3. Output characteristics
ID
(A)
Figure 4. Transfer characteristics
ID
(A)
GADG110120191128OCH
VGS = 10 V
200
200
VGS = 9 V
160
GADG110120191128TCH
160
VGS = 8 V
120
VDS = 10 V
120
80
80
VGS = 7 V
40
0
0
40
VGS = 6 V
2
4
6
8
10
VDS (V)
Figure 5. Gate charge vs gate-source voltage
VGS
(V)
GADG090120191537QVG VDS
(V)
12
10
8
VDS
160
120
4
80
2
40
20
40
60
80
5
100
120
0
Qg (nC)
6
7
8
9
VGS (V)
Figure 6. Static drain-source on-resistance
RDS(on)
(mΩ)
GADG090120191258RID
15.8
200
6
0
0
DS6286 - Rev 3
240
VDD = 160 V
ID = 32.5 A
0
4
VGS = 10 V
15.4
15.0
14.6
14.2
0
10
20
30
40
50
60
ID (A)
page 5/17
STB80N20M5, STP80N20M5
Electrical characteristics (curves)
Figure 7. Capacitance variations
C
(pF)
Figure 8. Output capacitance stored energy
EOSS
(µJ)
GADG090120191254CVR
GADG090120191254EOS
6
10 4
5
CISS
4
10 3
3
f = 1 MHz
COSS
10 2
10 1
10 -1
10 0
10 1
10 2
CRSS
1
VDS (V)
0
0
Figure 9. Normalized gate threshold voltage vs
temperature
AM07101v1
VGS(th)
(norm)
1.10
2
50
VDS (V)
AM07102v1
R DS(on)
(norm)
2.1
ID =250 µA
150
Figure 10. Normalized on-resistance vs temperature
1.00
1.7
0.90
1.3
VGS = 10 V
0.9
0.80
0.70
-50
100
-25
0
25
50
75 100
TJ (°C)
Figure 11. Normalized V(BR)DSS vs temperature
AM10399v1
V(BR)DS S
(norm)
0.5
-50 -25
25
0
50
75
100
TJ (°C)
Figure 12. Source-drain diode forward characteristics
AM07104v1
VSD
(V)
TJ =-50°C
1.2
1.08
ID = 1mA
1.06
TJ =25°C
1.0
1.04
0.8
1.02
1.00
0.6
0.98
0.4
0.96
0.2
0.94
0.92
-50 -25
DS6286 - Rev 3
TJ =150°C
0
25
50
75 100
TJ (°C)
0
0
10
20
30
40
50 ISD (A)
page 6/17
STB80N20M5, STP80N20M5
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 14. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 15. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
B
L
A
B
3.3
µF
D
G
+
VD
100 µH
fast
diode
B
Figure 16. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 17. Unclamped inductive waveform
V(BR)DSS
Figure 18. Switching time waveform
Concept waveform for Inductive Load Turn-off
Id
VD
90%Vds
90%Id
Tdelay -off
IDM
Vgs
90%Vgs
on
ID
Vgs(I(t ))
VDD
VDD
10%Vds
10%Id
Vds
Trise
AM01472v1
DS6286 - Rev 3
Tfall
Tcross --over
AM05540v2
page 7/17
STB80N20M5, STP80N20M5
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
DS6286 - Rev 3
page 8/17
STB80N20M5, STP80N20M5
D²PAK (TO-263) type A2 package information
4.1
D²PAK (TO-263) type A2 package information
Figure 19. D²PAK (TO-263) type A2 package outline
0079457_A2_25
DS6286 - Rev 3
page 9/17
STB80N20M5, STP80N20M5
D²PAK (TO-263) type A2 package information
Table 7. D²PAK (TO-263) type A2 package mechanical data
Dim.
mm
Min.
Typ.
Max.
A
4.40
4.60
A1
0.03
0.23
b
0.70
0.93
b2
1.14
1.70
c
0.45
0.60
c2
1.23
1.36
D
8.95
9.35
D1
7.50
7.75
8.00
D2
1.10
1.30
1.50
E
10.00
E1
8.70
8.90
9.10
E2
7.30
7.50
7.70
e
10.40
2.54
e1
4.88
5.28
H
15.00
15.85
J1
2.49
2.69
L
2.29
2.79
L1
1.27
1.40
L2
1.30
1.75
R
V2
0.40
0°
8°
Figure 20. D²PAK (TO-263) recommended footprint (dimensions are in mm)
Footprint
DS6286 - Rev 3
page 10/17
STB80N20M5, STP80N20M5
D²PAK packing information
4.2
D²PAK packing information
Figure 21. D²PAK tape outline
DS6286 - Rev 3
page 11/17
STB80N20M5, STP80N20M5
D²PAK packing information
Figure 22. D²PAK reel outline
T
40mm min.
access hole
at slot location
B
D
C
N
A
G measured
at hub
Tape slot
in core for
tape start
2.5mm min.width
Full radius
AM06038v1
Table 8. D²PAK tape and reel mechanical data
Tape
Dim.
DS6286 - Rev 3
Reel
mm
mm
Dim.
Min.
Max.
Min.
A0
10.5
10.7
A
B0
15.7
15.9
B
1.5
D
1.5
1.6
C
12.8
D1
1.59
1.61
D
20.2
E
1.65
1.85
G
24.4
F
11.4
11.6
N
100
K0
4.8
5.0
T
Max.
330
13.2
26.4
30.4
P0
3.9
4.1
P1
11.9
12.1
Base quantity
1000
P2
1.9
2.1
Bulk quantity
1000
R
50
T
0.25
0.35
W
23.7
24.3
page 12/17
STB80N20M5, STP80N20M5
TO-220 type A package information
4.3
TO-220 type A package information
Figure 23. TO-220 type A package outline
0015988_typeA_Rev_22
DS6286 - Rev 3
page 13/17
STB80N20M5, STP80N20M5
TO-220 type A package information
Table 9. TO-220 type A package mechanical data
Dim.
mm
Min.
Max.
A
4.40
4.60
b
0.61
0.88
b1
1.14
1.55
c
0.48
0.70
D
15.25
15.75
D1
DS6286 - Rev 3
Typ.
1.27
E
10.00
10.40
e
2.40
2.70
e1
4.95
5.15
F
1.23
1.32
H1
6.20
6.60
J1
2.40
2.72
L
13.00
14.00
L1
3.50
3.93
L20
16.40
L30
28.90
øP
3.75
3.85
Q
2.65
2.95
page 14/17
STB80N20M5, STP80N20M5
Revision history
Table 10. Document revision history
Date
Version
Changes
01-Jul-2009
1
First release
03-Jul-2010
2
Document status promoted from preliminary data to datasheet
Updated title, features and internal schematic diagram on cover page.
16-Jan-2019
3
Updated Section 1 Electrical ratings, Section 2 Electrical characteristics and
Section 4.1 D²PAK (TO-263) type A2 package information.
Minor text changes.
DS6286 - Rev 3
page 15/17
STB80N20M5, STP80N20M5
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
D²PAK (TO-263) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
TO-220 type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DS6286 - Rev 3
page 16/17
STB80N20M5, STP80N20M5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS6286 - Rev 3
page 17/17
