STP80NF03L
N-CHANNEL 30V - 0.004 Ω - 80A TO-220
STripFET™ II MOSFET
TYPE
STP80NF03L
VDSS
RDS(on)
ID
30 V
< 0.0045 Ω
80 A
TYPICAL RDS(on) = 0.004 Ω
EXCEPTIONAL dv/dt CAPABILITY
100% AVALANCHE TESTED
LOW THRESHOLD DRIVE
■
■
■
■
3
1
2
TO-220
DESCRIPTION
This Power MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” stripbased process. The resulting transistor shows extremely high packing density for low on-resistance,
rugged avalance characteristics and less critical
alignment steps therefore a remarkable manufacturing reproducibility.
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INTERNAL SCHEMATIC DIAGRAM
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APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS
■ AUTOMOTIVE ENVIRONMENT
(INJECTION,ABS, AIR-BAG ,LAMPDRIVERS
Etc.)
)
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ORDERING INFORMATION
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SALES TYPE
MARKING
PACKAGE
PACKAGING
STP80NF03L
P80NF03L
TO-220
TUBE
.
January 2004
1/8
STP80NF03L
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
VDGR
Parameter
Value
Unit
Drain-source Voltage (VGS = 0)
30
V
Drain-gate Voltage (RGS = 20 kΩ)
30
V
VGS
Gate-source Voltage
± 20
V
ID (#)
Drain Current (continuous) at TC = 25°C
80
A
ID (#)
Drain Current (continuous) at TC = 100°C
80
A
Drain Current (pulsed)
320
A
Total Dissipation at TC = 25°C
300
W
Derating Factor
2.0
W/°C
Peak Diode Recovery Voltage Slope
2.0
V/ns
–65 to 175
°C
175
°C
IDM ()
PTOT
dv/dt (1)
Tstg
Tj
Storage Temperature
Max. Operating Junction Temperature
(#) Current Limited by Package.
( ) Pulse width limited by safe operating area.
(1) ISD ≤ 80A, di/dt ≤ 240 A/µs, VDD = 24V ; T j ≤ TJMAX.
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THERMAL DATA
Rthj-case
Thermal Resistance Junction-case Max
Rthj-amb
Thermal Resistance Junction-ambient Max
Tl
AVALANCHE CHARACTERISTICS
Symbol
Parameter
ro
0.5
P
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let
Maximum Lead Temperature For Soldering Purpose Typ
)
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°C/W
62.5
°C/W
300
°C
Max Value
Unit
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
40
A
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 20 V)
2.3
J
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ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF/ON
Symbol
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V(BR)DSS
Test Conditions
Min.
Typ.
Max.
ID = 250 µA, VGS = 0
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
1
µA
VDS = Max Rating, TC = 125 °C
10
µA
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20V
±100
nA
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
1.5
2.5
V
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V, ID = 40 A
VGS = 4.5 V, ID = 40 A
0.004
0.0045
0.0045
0.0065
Ω
Ω
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IGSS
30
Unit
Drain-source
Breakdown Voltage
IDSS
2/8
Parameter
1
V
STP80NF03L
ELECTRICAL CHARACTERISTICS (CONTINUED)
DYNAMIC
Symbol
gfs (1)
Parameter
Test Conditions
Forward Transconductance
Min.
Max.
Unit
50
S
5500
pF
Output Capacitance
1670
pF
Reverse Transfer
Capacitance
290
pF
Ciss
Input Capacitance
Coss
Crss
VDS =15 V, ID = 15 A
Typ.
VDS = 25V, f = 1 MHz, VGS = 0
SWITCHING ON
Symbol
td(on)
tr
Parameter
Test Conditions
Typ.
VDD = 15 V, ID = 40 A
RG = 4.7Ω VGS = 4.5 V
(Resistive Load, Figure 3)
Turn-on Delay Time
Rise Time
Qg
Qgs
Qgd
Min.
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 24V, ID = 80A,
VGS = 4.5V
Parameter
ns
270
ns
85
23
40
Test Conditions
td(off)
tf
Turn-off-Delay Time
Fall Time
VDD = 15 V, ID = 40 A,
RG = 4.7Ω, VGS = 4.5V
(Resistive Load, Figure 3)
tr(Voff)
tf
tc
Off-Voltage Rise Time
Fall Time
Cross-over Time
Vclamp = 24 V, ID = 80 A,
RG = 4.7Ω, VGS = 4.5V
(Inductive Load, Figure 5)
SOURCE DRAIN DIODE
Symbol
ISD
Parameter
t
c
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Source-drain Current (pulsed)
VSD (2)
Forward On Voltage
trr
Qrr
IRRM
(s)
Source-drain Current
ISDM (1)
od
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
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Min.
110
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Typ.
Test Conditions
Min.
)
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Max.
Unit
110
95
ns
ns
125
75
125
ns
ns
ns
Typ.
ISD = 80 A, VGS = 0
ISD = 80 A, di/dt = 100 A/µs,
VDD = 20 V, Tj = 150°C
(see test circuit, Figure 5)
nC
nC
nC
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Unit
30
SWITCHING OFF
Symbol
Max.
75
0.15
4
Max.
Unit
80
A
320
A
1.5
V
ns
µC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
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STP80NF03L
Safe Operating Area
Thermal Impedance
Output Characteristics
Transfer Characteristics
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Transconductance
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Static Drain-source On Resistance
)
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STP80NF03L
Gate Charge vs Gate-source Voltage
Capacitance Variations
Normalized Gate Threshold Voltage vs Temp.
Normalized On Resistance vs Temperature
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Source-drain Diode Forward Characteristics
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NormalizedBreakdownVoltage vs Temperature
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5/8
STP80NF03L
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
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Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
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STP80NF03L
TO-220 MECHANICAL DATA
mm.
DIM.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
b
0.61
0.88
0.024
0.034
b1
1.15
1.70
0.045
0.066
c
0.49
0.70
0.019
0.027
D
15.25
15.75
0.60
0.620
E
10
10.40
0.393
0.409
e
2.40
2.70
0.094
0.106
e1
4.95
5.15
0.194
0.202
0.052
F
1.23
1.32
0.048
H1
6.20
6.60
0.244
0.256
J1
2.40
2.72
0.094
0.107
L
13
14
0.511
0.551
L1
3.50
3.93
0.137
0.154
L20
16.40
0.645
L30
28.90
1.137
øP
3.75
3.85
0.147
Q
2.65
2.95
0.104
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0.151
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7/8
STP80NF03L
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
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© 2004 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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