STP80NF10FP

N-CHANNEL 100V - 0.012Ω - 80A TO-220/TO-220FP LOW GATE CHARGE STripFET™II POWER MOSFET TYPE STP80NF10 STP80NF10FP s s s s STP80NF10 STP80NF10FP VDSS 100 V 100 V RDS(on) < 0.015 Ω < 0.015 Ω ID 80 A 38 A TYPICAL RDS(on) = 0.012Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION TO-220 3 1 2 1 2 3 TO-220FP DESCRIPTION This Power MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements. APPLICATIONS s HIGH-EFFICIENCY DC-DC CONVERTERS s UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(*) ID IDM (l) PTOT dv/dt (1) EAS (2) VISO Tstg Tj Parameter INTERNAL SCHEMATIC DIAGRAM Value STP80NF10 STP80NF10FP 100 100 ±20 80 66 320 300 2 9 360 – 55 to 175 (1) I SD ≤80A, di/dt ≤300A/µs, VDD ≤ V (BR)DSS, Tj ≤ T JMAX. (2) Starting T j = 25°C, I D = 80A, VDD = 50V Unit V V V 38 27 152 45 0.3 A A A W W/°C V/ns mJ 2500 V °C Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature (q) Pulse width limited by safe operating area (*) Limited by Package September 2002 1/9 STP80NF10/STP80NF10FP THERMAL DATA TO-220 Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.5 62.5 300 TO-220FP 3.33 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ±20V Min. 100 1 10 ±100 Typ. Max. Unit V µA µA nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250µA VGS = 10V, ID = 40 A Min. 2 Typ. 3 0.012 Max. 4 0.015 Unit V Ω DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS =25V , ID =40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 80 4300 600 230 Max. Unit S pF pF pF 2/9 STP80NF10/STP80NF10FP ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 50V, ID = 40A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 80V, ID = 80A, VGS = 10V Min. Typ. 40 145 140 23 51 189 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions VDD = 50V, ID = 40A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 3) Min. Typ. 134 115 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80A, VGS = 0 ISD = 80A, di/dt = 100A/µs, VDD = 50V, Tj = 150°C (see test circuit, Figure 5) 155 0.85 11 Test Conditions Min. Typ. Max. 80 320 1.3 Unit A A V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 STP80NF10/STP80NF10FP Thermal Impedence for TO-220 Thermal Impedence for TO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STP80NF10/STP80NF10FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP80NF10/STP80NF10FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP80NF10/STP80NF10FP TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 D F1 G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/9 STP80NF10/STP80NF10FP TO-220FP MECHANICAL DATA mm. MIN. 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 28.6 9.8 2.9 15.9 9 3 30.6 10.6 3.6 16.4 9.3 3.2 1.126 .0385 0.114 0.626 0.354 0.118 TYP MAX. 4.6 2.7 2.75 0.7 1 1.7 1.7 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.141 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409 DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7 Ø A B L3 L6 L7 F1 D F G1 H F2 L2 L5 E 123 L4 8/9 G STP80NF10/STP80NF10FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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