STPCC01

® STPC CONSUMER PC Compatible Embeded Microprocessor s s s s s s s s s s s s s s s s s s s POWERFUL X86 PROCESSOR 64-BIT BUS ARCHITECTURE 64-BIT DRAM CONTROLLER SVGA GRAPHICS CONTROLLER UMA ARCHITECTURE VIDEO SCALER DIGITAL PAL/NTSC ENCODER VIDEO INPUT PORT CRT CONTROLLER 135MHz RAMDAC 3 LINE FLICKER FILTER SCAN CONVERTER PCI MASTER / SLAVE / ARBITER CTRL ISA MASTER/SLAVE INTERFACE IDE CONTROLLER DMA CONTROLLER INTERRUPT CONTROLLER TIMER / COUNTERS POWER MANAGEMENT PCI m/s PBGA388 Figure 1. Logic Diagram ISA BUS x86 Core Host I/F ISA m/s IPC STPC CONSUMER OVERVIEW The STPC Consumer integrates a standard 5th generation x86 core, a DRAM controller, a graphics subsystem, a video pipeline and support logic including PCI, ISA and IDE controllers to provide a single Consumer orientated PC compatible subsystem on a single device. The device is based on a tightly coupled Unified Memory Architecture (UMA), sharing the same memory array between the CPU main memory and the graphics and video frame buffers. Extra facilities are implemented to handle video streams. Features include smooth scaling and color space conversion of the video input stream and mixing with graphics data. The chip also includes a built-in digital TV encoder and anti-flicker filters that allow stable, high-quality display on standard PAL or NTSC television sets without additional components. The STPC Consumer is packaged in a 388 Plastic Ball Grid Array (PBGA). EIDE EIDE PCI m/s VIP PCI BUS CCIR Input TV Output D igital PAL/ NTSC AntiFlicker C olor Space C onverter Video pipeline 2D SVGA Color Key Chroma Key H W C ursor Monitor CRTC DRAM CTRL SYNC Output 8/2/00 Issue 1.2 1/51 STPC CONSUMER s s s s s s s s s s s s s s s s s X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GBytes of external memory. 8KByte unified instruction and data cache with write back and write through capability. Parallel processing integral floating point unit, with automatic power down. Clock core speeds up to of 100 MHz. Fully static design for dynamic clock control. Low power and system management modes. Optimized design for 3.3V operation. DRAM Controller Integrated system memory and graphic frame memory. Supports up to 128 MBytes system memory in 4 banks and down to as little as 2Mbytes. Supports 4MB, 8MB, 16MB, 32MB singlesided and double-sided DRAM SIMMs. Four quad-word write buffers for CPU to DRAM and PCI to DRAM cycles. Four 4-word read buffers for PCI masters. Supports Fast Page Mode & EDO DRAM. Programmable timing for DRAM parameters including CAS pulse width, CAS pre-charge time and RAS to CAS delay. 60, 70, 80 & 100ns DRAM speeds. Memory hole between 1 MByte & 8 MByte supported for PCI/ISA busses. Hidden refresh. s s s s s s s s s s s VGA Controller Integrated 135MHz triple RAMDAC allowing for 1280 x 1024 x 75Hz display. Requires external frequency synthesizer and reference sources. 8-, 16-, 24-bit pixels. Interlaced or non-interlaced output. Video Input port Accepts video inputs in CCIR 601/656 or ITU-R 601/656, and stream decoding. Optional 2:1 decimator Stores captured video in off setting area of the onboard frame buffer. Video pass through to the onboard PAL/ NTSC encoder for full screen video images. HSYNC and B/T generation or lock onto external video timing source. Video Pipeline Two-tap interpolative horizontal filter. Two-tap interpolative vertical filter. Color space conversion (RGB to YUV and YUV to RGB). Programmable window size. Chroma and color keying for integrated video overlay. Programmable two tap filter with gamma correction or three tap flicker filter. Progressive to interlaced scan converter. Digital NTSC/PAL encoder NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy programmable video outputs. CCIR601 encoding with programmable color subcarrier frequencies. Line skip/insert capability Interlaced or non-interlaced operation mode. 625 lines/50Hz or 525 lines/60Hz 8 bit multiplexed CB-Y-CR digital input. CVBS and R,G,B simultaneous analog outputs through 10-bit DACs. Cross color reduction by specific trap filtering on luma within CVBS flow. Power down mode available on each DAC. s s s s s s s s s s s s s s s s s s s s To check if your memory device is supported by the STPC, please refer to Table 9-3 in the Programming Manual. s s s s s s s s Graphics Engine 64-bit windows accelerator. Backward compatibility to SVGA standards. Hardware acceleration for text, bitblts, transparent blts and fills. Up to 64 x 64 bit graphics hardware cursor. Up to 4MB long linear frame buffer. 8-, 16-, and 24-bit pixels. Drivers for Windows and other operating systems. 2/51 Issue 1.2 STPC CONSUMER s s s s s s s PCI Controller Fully compliant with PCI 2.1 specification. Integrated PCI arbitration interface. Up to 3 masters can connect directly. External PAL allows for greater than 3 masters. Translation of PCI cycles to ISA bus. Translation of ISA master initiated cycle to PCI. Support for burst read/write from PCI master. 0.33X and 0.5X CPU clock PCI clock. ISA master/slave Interface Generates the ISA clock from either 14.318MHz oscillator clock or PCI clock Supports programmable extra wait state for ISA cycles Supports I/O recovery time for back to back I/O cycles. Fast Gate A20 and Fast reset. Supports the single ROM that C, D, or E. blocks shares with F block BIOS ROM. Supports flash ROM. Supports ISA hidden refresh. Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI and Host bus. NSP compliant. IDE Interface Supports PIO Supports up to Mode 5 Timings Transfer Rates to 22 MBytes/sec Supports up to 4 IDE devices s s s s s s s s s s s s s s s s s s Concurrent channel operation (PIO modes) 4 x 32-Bit Buffer FIFOs per channel Support for PIO mode 3 & 4. Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers. Individual drive timing for all four IDE devices Supports both legacy & native IDE modes Supports hard drives larger than 528MB Support for CD-ROM and tape peripherals Backward compatibility with IDE (ATA-1). Drivers for Windows and other Operating Systems Integrated peripheral controller 2X8237/AT compatible 7-channel DMA controller. 2X8259/AT compatible interrupt Controller. 16 interrupt inputs - ISA and PCI. Three 8254 compatible Timer/Counters. Co-processor error support logic. Power Management Four power saving modes: On, Doze, Standby, Suspend. Programmable system activity detector Supports SMM and APM. Supports STOPCLK. Supports IO trap & restart. Independent peripheral time-out timer to monitor hard disk, serial & parallel ports. Supports RTC, interrupts and DMAs wake-up s s s s s s s s s s s s s s s s s s 3/51 Issue 1.2 STPC CONSUMER 4/51 Issue 1.2 U PDATE HISTORY FOR OVERVIEW. 0.1 UPDATE HISTORY FOR OVERVIEW. The following changes have been made to the Electrical Specification Chapter on the 02/02/2000. Section Change Added Text To check if your memory device is supported by the STPC, please refer to Table 9-3 Host Address to MA Bus Mappingin the Programming Manual. 5/51 Issue 1.2 GENERAL DESCRIPTION 1. GENERAL DESCRIPTION At the heart of the STPC Consumer is an advanced processor block, dubbed the 5ST86. The 5ST86 includes a powerful x86 processor core along with a 64-bit DRAM controller, advanced 64bit accelerated graphics and video controller, a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus) and EIDE controller. The STPC Consumer has in addition to the 5ST86, a Video subsystem and high quality digital Television output. The STMicroelectronics x86 processor core is embedded with standard and application specific peripheral modules on the same silicon die. The core has all the functionality of the STMicroelectronics standard x86 processor products, including the low power System Management Mode (SMM). System Management Mode (SMM) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. While running in isolated SMM address space, the SMM interrupt routine can execute without interfering with the operating system or application programs. Further power management facilities include a suspend mode that can be initiated from either hardware or software. Because of the static nature of the core, no internal data is lost. The STPC Consumer makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buffer. This significantly reduces total system memory with system performances equal to that of a comparable solution with separate frame buffer and system memory. In addition, memory bandwidth is improved by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional PCI bus. The 64-bit wide memory array provides the system with 320MB/s peak bandwidth, double that of an equivalent system using 32 bits. This allows for higher screen resolutions and greater color depth. The processor bus runs at the speed of the processor (DX devices) or half the speed (DX2 devices). The ‘standard’ PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated with the x86 processor core. The PCI bus is the main data communication link to the STPC Consumer chip. The STPC Consumer translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports the generation of Configuration cycles on the PCI bus. The STPC Consumer, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devices. The STPC Consumer integrates an ISA bus controller. Peripheral modules such as parallel and serial communications ports, keyboard controllers and additional ISA devices can be accessed by the STPC Consumer chip set through this bus. An industry standard EIDE (ATA 2) controller is built in to the STPC Consumer and connected internally via the PCI bus. Graphics functions are controlled by the on-chip SVGA controller and the monitor display is managed by the 2D graphics display engine. This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost. It performs limited graphics drawing operations, which include hardware acceleration of text, bitblts, transparent blts and fills. These operations can act on off-screen or on-screen areas. The frame buffer size ranges up to 4 Mbytes anywhere in the physical main memory. The graphics resolution supported is a maximum of 1280x1024 in 65536 colours at 75Hz refresh rate and is VGA and SVGA compatible. Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate the above display resolution. STPC Consumer provides several additional functions to handle MPEG or similar video streams. The Video Input Port accepts an encoded digital video stream in one of a number of industry standard formats, decodes it, optionally decimates it by a factor of 2:1, and deposits it into an off screen area of the frame buffer. An interrupt request can be generated when an entire field or frame has been captured. 6/51 Issue 1.2 GENERAL DESCRIPTION The video output pipeline incorporates a videoscaler and color space converter function and provisions in the CRT controller to display a video window. While repainting the screen the CRT controller fetches both the video as well as the normal non-video frame buffer in two separate internal FIFOs (256-Bytes each). The video stream can be color-space converted (optionally) and smooth scaled. Smooth interpolative scaling in both horizontal and vertical directions are implemented. Color and Chroma key functions are also implemented to allow mixing video stream with non-video frame buffer. The video output passes directly to the RAMDAC for monitor output or through another optional color space converter (RGB to 4:2:2 YCrCb) to the programmable anti-flicker filter. The flicker filter is configured as either a two line filter with gamma correction (primarily designed for DOS type text) or a 3 line flicker filter (primarily designed for Windows type displays). The flicker filter is optional and can be software disabled for use with video on large screen areas. The Video output pipeline of the STPC Consumer interfaces directly to the internal digital TV encoder. It takes a 24 bit RGB non-interlaced pixel stream and converts to a multiplexed 4:2:2 YCrCb 8 bit output stream, the logic includes a progressive to interlaced scan converter and logic to insert appropriate CCIR656 timing reference codes into the output stream. It facilitates the high quality display of VGA or full screen video streams received via the Video input port to standard NTSC or PAL televisions. The STPC Consumer core is compliant with the Advanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal computers. The Power Management Unit module (PMU) controls the power consumption by providing a comprehensive set of features that control the power usage and supports compliance with the United States Environmental Protection Agency’s Energy Star Computer Program. The PMU provides following hardware structures to assist the software in managing the power consumption by the system. - System Activity Detection. - 3 power-down timers detecting system inactivity: - Doze timer (short durations). - Stand-by timer (medium durations). - Suspend timer (long durations). - House-keeping activity detection. - House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - Peripheral activity detection. - Peripheral timer detecting peripheral inactivity - SUSP# modulation to adjust the system performance in various power down states of the system including full power on state. - Power control outputs to disable power from different planes of the board. Lack of system activity for progressively longer period of times is detected by the three power down timers. These timers can generate SMI interrupts to CPU so that the SMM software can put the system in decreasing states of power consumption. Alternatively, system activity in a power down state can generate SMI interrupt to allow the software to bring the system back up to full power on state. The chip-set supports up to three power down states: Doze state, Stand-by state and Suspend mode. These correspond to decreasing levels of power savings. Power down puts the STPC Consumer into suspend mode. The processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. During the suspend mode, internal clocks are stopped. Removing power down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. A reference design for the STPC Consumer is available including the schematics and layout files, the design is a PC ATX motherboard design. The design is available as a demonstration board for application and system development. The STPC Consumer is supported by several BIOS vendors, including the super I/O device used in the reference design. Drivers for 2D accelerator, video features and EIDE are availaible on various operating systems. The STPC Consumer has been designed using modern reusable modular design techniques, it is possible to add or remove the standard features of the STPC Consumer or other variants of the 5ST86 family. Contact your local STMicroelectonics sales office for further information. 7/51 Issue 1.2 GENERAL DESCRIPTION Figure 1-1 Functionnal description x86 Core Host I/F ISA IPC ISA BUS PCI m/s EIDE EIDE PCI m/s PCI BUS VIP CCIR Input TV Output Digital PAL/ Anti-Flicker Video pipeline 2D SVGA CRTC DRAM Color Key Chroma HW Cursor Color Space Monitor SYNC Output 8/51 Issue 1.2 GENERAL DESCRIPTION Figure 1-2 Typical Application Super I/O RTC Keyboard / Mouse Serial Ports Parallel Port Floppy Flash ISA DMUX MUX 2x EIDE IRQ MUX Monitor SVGA DMA.REQ TV S-VHS RGB PAL NTSC STPC Consumer DMA.ACK DMUX Video CCIR601 CCIR656 PCI 4x 16-bit EDO DRAMs 9/51 Issue 1.2 PIN DESCRIPTION 2. PIN DESCRIPTION 2.1 INTRODUCTION The STPC Consumer integrates most of the functionalities of the PC architecture. As a result, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Consumer. This offers improved performance due to the tight coupling of the processor core and these peripherals. As a result many of the external pin connections are made directly to the on-chip peripheral functions. Figure 2-1 shows the STPC Consumer’s external interfaces. It defines the main busses and their function. Table 2-1 describes the physical implementation listing signal types and their functionalities. Table 2-2 provides a full pin listing and description. Table 2-3 provides a full listing of the STPC Consumer pin locations of package by physical connection. Please refer to the pin allocation drawing for reference. Table 2-1. Signal Description Group name Basic Clocks reset & Xtal(SYS) DRAM Controller PCI interface (PCI) ISA / IDE / IPC combined interface Video Input (VIP) TV Output VGA Monitor interface Grounds VDD Analog specific VCC/VDD Reserved Total Pin Count Qty 12 89 58 88 9 10 10 69 26 12 5 388 Note: Several interface pins are multiplexed with other functions, refer to the Pin Description section for further details Figure 2-1. STPC Consumer External Interfaces x86 STPC Consumer NORTH DRAM VGA VIP TV PCI SYS SOUTH ISA/IDE IPC 89 10 9 10 58 13 77 11 10/51 Issue 1.2 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name BASIC CLOCKS AND RESETS SYSRSTI# XTALI XTALO HCLK DEV_CLK GCLK2X DCLK PCI_CLKI PCI_CLKO SYSRSTO# ISA_CLK ISA_CLK2X MEMORY INTERFACE MA[11:0] RAS#[3:0] CAS#[7:0] MWE# MD[63:0] PCI INTERFACE AD[31:0] CBE[3:0] FRAME# TRDY# IRDY# STOP# DEVSEL# PAR SERR# LOCK# PCIREQ#[2:0] PCIGNT#[2:0] PCI_INT[3:0] VDD5 Dir I I I/O O O I/O I/O I O O O O Description System Reset / Power good 14.3MHz Crystal Input 14.3MHz Crystal Output - External Oscillator Input Host Clock (Test) 24MHz Peripheral Clock (floppy drive) 80MHz Graphics Clock 135MHz Dot Clock 33MHz PCI Input Clock 33MHz PCI Output Clock (from internal PLL) Reset Output to System ISA Clock Output - Multiplexer Select Line For IPC ISA Clock x 2 Output - Multiplexer Select Line For IPC Qty 1 1 1 1 1 1 1 1 1 1 1 1 I/O O O O I/O Memory Address Row Address Strobe Column Address Strobe Write Enable Memory Data 12 4 8 1 64 I/O I/O I/O I/O I/O I/O I/O I/O O I I O I I PCI Address / Data Bus Commands / Byte Enables Cycle Frame Target Ready Initiator Ready Stop Transaction Device Select Parity Signal Transactions System Error PCI Lock PCI Request PCI Grant PCI Interrupt Request 5V Power Supply for PCI ESD protection 32 4 1 1 1 1 1 1 1 1 3 3 4 4 ISA AND IDE COMBINED ADDRESS/DATA LA[23:22] / SCS3#,SCS1# I/O Unlatched Address (ISA) / Secondary Chip Select (IDE) LA[21:20] / PCS3#,PCS1# I/O Unlatched Address (ISA) / Primary Chip Select (IDE) LA[19:17] / DA[2:0] O Unlatched Address (ISA) / Address (IDE) RMRTCCS# / DD[15] I/O ROM/RTC Chip Select / Data Bus bit 15 (IDE) KBCS# / DD[14] I/O Keyboard Chip Select / Data Bus bit 14 (IDE) RTCRW# / DD[13] I/O RTC Read/Write / Data Bus bit 13 (IDE) RTCDS# / DD[12] I/O RTC Data Strobe / Data Bus bit 12 (IDE) SA[19:8] / DD[11:0] SA[7:0] SD[15:0] I/O I/O I/O Latched Address (ISA) / Data Bus (IDE) Latched Address (IDE) Data Bus (ISA) 2 2 3 1 1 1 1 16 4 16 11/51 Issue 1.2 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name ISA/IDE COMBINED CONTROL IOCHRDY / DIORDY ISA CONTROL OSC14M ALE BHE# MEMR#, MEMW# SMEMR#, SMEMW# IOR#, IOW# MASTER# MCS16#, IOCS16# REF# AEN ZWS# IOCHCK# ISAOE# RTCAS# GPIOCS# IDE CONTROL PIRQ SIRQ PDRQ SDRQ PDACK# SDACK# PIOR# PIOW# SIOR# SIOW# Dir Description Qty I/O I/O Channel Ready (ISA) - Busy/Ready (IDE) 1 O O I/O I/O O I/O I I O O I I O O I/O ISA bus synchronisation clock Address Latch Enable System Bus High Enable Memory Read and Memory Write System Memory Read and Memory Write I/O Read and Write Add On Card Owns Bus Memory/IO Chip Select16 Refresh Cycle. Address Enable Zero Wait State I/O Channel Check. Bidirectional OE Control Real Time Clock Address Strobe General Purpose Chip Select 1 1 1 2 2 2 1 2 1 1 1 1 1 1 1 I I I I O O I/O O I/O O Primary Interrupt Request Secondary Interrupt Request Primary DMA Request Secondary DMA Request Primary DMA Acknowledge Secondary DMA Acknowledge Primary I/O Read Primary I/O Write Secondary I/O Read Secondary I/O Write 1 1 1 1 1 1 1 1 1 1 IPC IRQ_MUX[3:0] DREQ_MUX[1:0] DACK_ENC[2:0] TC MONITOR INTERFACE RED, GREEN, BLUE VSYNC HSYNC VREF_DAC RSET COMP DDC[1:0] SCL / DDC[1] I I O O Multiplexed Interrupt Request Multiplexed DMA Request DMA Acknowledge ISA Terminal Count 4 2 3 1 O O O I I I I/O I/O Red, Green, Blue Vertical Sync Horizontal Sync DAC Voltage reference Resistor Set Compensation Display Data Channel Serial Link I C Interface - Clock / Can be used for VGA DDC[1] signal 3 1 1 1 1 1 2 1 12/51 Issue 1.2 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name SDA / DDC[0] COL_CMP VIDEO INPUT VCLK VIN DIGITAL TV OUTPUT RED_TV, GREEN_TV, BLUE_TV VCS ODD_EVEN CVBS IREF1_TV VREF1_TV IREF2_TV VREF2_TV VSSA_TV VDDA_TV MISCELLANEOUS SPKRD SCAN_ENABLE Dir I/O O Description I C Interface - Data / Can be used for VGA DDC[0] signal Color Compare Output. Qty 1 I I Pixel Clock YUV Video Data Input CCIR 601 or 656 1 8 O O O O I I I I I I Analog video outputs synchronized with CVBS Composite Synch or Horizontal line SYNC output Frame Synchronisation Analog video composite output (luminance / chrominance) Reference current of 9bit DAC for CVBS Reference voltage of 9bit DAC for CVBS Reference current of 8bit DAC for R,G,B Reference voltage of 8bit DAC for R,G,B Analog Vss for DAC Analog Vdd for DAC 3 1 1 1 1 1 1 1 1 1 O I Speaker Device Output Reserved (Test pin) 1 1 13/51 Issue 1.2 PIN DESCRIPTION 2.2 SIGNAL DESCRIPTIONS 2.2.1 BASIC CLOCKS AND RESETS SYSRSTI System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply’s power good signal. SYSRSTI is asynchronous to all clocks, and acts as a negative active reset. The reset circuit initiates a hard reset on the rising edge of SYSRSTI. SYSRSTO# Reset Output to System. This is the system reset signal and is used to reset the rest of the components (not on Host bus) in the system. The ISA bus reset is an externally inverted buffered version of this output and the PCI bus reset is an externally buffered version of this output. XTALI 14.3MHz Crystal Input XTALO 14.3MHz Crystal Output. These pins are the 14.318 MHz crystal input; This clock is used as the reference clock for the internal frequency synthesizer to generate the HCLK, CLK24M, GCLK2X and DCLK clocks. A 14.318 MHz Series Cut Quartz Crystal should be connected between these two pins. Balance capacitors of 15 pF should also be added. In the event of an external oscillator providing the master clock signal to the STPC Consumer device, the TTL signal should be provided on XTALO. HCLK Host Clock. This is the host 1X clock. Its frequency can vary from 25 to 75 MHz. All host transactions and PCI transactions are synchronized to this clock. The DRAM controller to execute the host transactions is also driven by this clock. In normal mode, this output clock is generated by the internal pll. GCLK2X 80MHz Graphics Clock. This is the Graphics 2X clock, which drives the graphics engine and the DRAM controller to execute the graphics and display cycles. Normally GCLK2X is generated by the internal frequency synthesizer, and this pin is an output. By setting a bit in Strap Register 2, this pin can be made an input so that an external clock can replace the internal frequency synthesizer. PCI_CLKI 33MHz PCI Input Clock This signal is the PCI bus clock input and should be driven from the PCI_CLKO pin. PCI_CLKO 33MHz PCI Output Clock. This is the master PCI bus clock output. DCLK 135MHz Dot Clock. This is the dot clock, which drives graphics display cycles. Its frequency can go from 8MHz (using internal PLL) up to 135 MHz, and it is required to have a worst case duty cycle of 60-40. This signal is either driven by the internal pll (VGA) or an external 27MHz oscillator (when the composite video output is enabled). The direction can be controlled by a strap option or an internal register bit. ISA_CLK ISA Clock Output (also Multiplexer Select Line For IPC). This pin produces the Clock signal for the ISA bus. It is also used with ISA_CLK2X as the multiplexor control lines for the Interrupt Controller Interrupt input lines. This is a divided down version of either the PCICLK or OSC14M. ISA_CLKX2 ISA Clock Output (also Multiplexer Select Line For IPC). This pin produces a signal that is twice the frequency of the ISA bus Clock signal. It is also used with ISA_CLK as the multiplexor control lines for the Interrupt Controller input lines. DEV_CLK 24MHz Peripheral Clock Output. This 24MHZ signal is provided as a convenience for the system integration of a Floppy Disk driver function in an external chip. OSC14M ISA bus synchronisation clock Output. This is the buffered 14.318 Mhz clock to the ISA bus. 2.2.2 MEMORY INTERFACE MA[11:0] Memory Address Output. These 12 multiplexed memory address pins support external DRAM with up to 4K refresh. These include all 16M x N and some 4M x N DRAM modules. The address signals must be externally buffered to support more than 16 DRAM chips. The timing of these signals can be adjusted by software to match the timings of most DRAM modules. 14/51 Issue 1.2 PIN DESCRIPTION MD[63:0] Memory Data I/O. This is the 64-bit memory data bus. If only half of a bank is populated, MD63-32 is pulled high, data is on MD31-0. MD[40-0] are read by the device strap option registers during rising edge of SYSRSTI. RAS#[3:0] Row Address Strobe Output. There are 4 active low row address strobe outputs, one for each bank of the memory. Each bank contains 4 or 8-Bytes of data. The memory controller allows half of a bank (4-bytes) to be populated to enable memory upgrade at finer granularity. The RAS# signals drive the SIMMs directly without any external buffering. These pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the RAS# signals at the pins. CAS#[7:0] Column Address Strobe Output. There are 8 active low column address strobe outputs, one each for each byte of the memory. The CAS# signals drive the SIMMs either directly or through external buffers. These pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the CAS# signals at the pins. MWE# Write Enable Output. Write enable specifies whether the memory access is a read (MWE# = H) or a write (MWE# = L). This single write enable controls all the DRAM. It can be externally buffered to boost the maximum number of loads (DRAM chips) supported. The MWE# signals drive the SIMMs directly without any external buffering. 2.2.3 VIDEO INTERFACE VCLK Pixel Clock Input. VIN[7:0] YUV Video Data Input CCIR 601 or 656. Time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input levels). This bus interfaces with an MPEG video decoder output port and typically carries a stream of Cb,Y,Cr,Y digital video at VCLK frequency, clocked on the rising edge (by default) of VCLK. A 54-Mbit/s ‘double’ Cb, Y, Cr, Y input multiplex is supported for double encoding application (rising and falling edge of CKREF are operating). 2.2.4 TV OUTPUT RED_TV / C_TV Analog video outputs synchronized with CVBS. This output is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is the Chrominance Output. GREEN_TV / Y_TV Analog video outputs synchronized with CVBS. This output is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is the Luminance Output. BLUE_TV / CVBSAnalog video outputs synchronized with CVBS. This output is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is a second composite output. VCS Line synchronisation Output. This pin is an input in ODDEV+HSYNC or VSYNC + HSYNC or VSYNC slave modes and an output in all other modes (master/slave) The signal is synchronous to rising edge of CKREF. The default polarity uses a negative pulse ODD_EVEN Frame Synchronisation Ourput. This pin supports the Frame synchronisation signal. It is an input in slave modes, except when sync is extracted from YCrCb data, and an output in master mode and when sync is extracted from YCrCb data The signal is synchronous to rising edge of DCLK. The default polarity for this pin is: - odd (not-top) field : LOW level - even (bottom) field : HIGH level IREF1_TV Ref. current for CVBS 10-bit DAC. VREF1_TV Ref. voltage for CVBS 10-bit DAC. IREF2_TV Reference current for RGB 9-bit DAC. VREF2_TV Reference voltage for RGB 9-bit DAC. VSSA_TV Analog VSS for DAC VDDA_TV Analog VDD for DAC CVBS Analog video composite output (luminance/ chrominance). CVBS is current-driven and must be connected to analog ground over a load resistor (R LOAD). Following the load resistor, a simple analog low pass filter is recommended. 2.2.5 PCI INTERFACE AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data bus of the PCI. This bus is driven by the master during the address phase and data phase of write transactions. It is 15/51 Issue 1.2 PIN DESCRIPTION driven by the target during data phase of read transactions. CBE#[3:0] Bus Commands/Byte Enables. These are the multiplexed command and byte enable signals of the PCI bus. During the address phase they define the command and during the data phase they carry the byte enable information. These pins are inputs when a PCI master other than the STPC Consumer owns the bus and outputs when the STPC Consumer owns the bus. FRAME# Cycle Frame. This is the frame signal of the PCI bus. It is an input when a PCI master owns the bus and is an output when STPC Consumer owns the PCI bus. TRDY# Target Ready. This is the target ready signal of the PCI bus. It is driven as an output when the STPC Consumer is the target of the current bus transaction. It is used as an input when STPC Consumer initiates a cycle on the PCI bus. IRDY# Initiator Ready. This is the initiator ready signal of the PCI bus. It is used as an output when the STPC Consumer initiates a bus cycle on the PCI bus. It is used as an input during the PCI cycles targeted to the STPC Consumer to determine when the current PCI master is ready to complete the current transaction. STOP# Stop Transaction. Stop is used to implement the disconnect, retry and abort protocol of the PCI bus. It is used as an input for the bus cycles initiated by the STPC Consumer and is used as an output when a PCI master cycle is targeted to the STPC Consumer. DEVSEL# I/O Device Select. This signal is used as an input when the STPC Consumer initiates a bus cycle on the PCI bus to determine if a PCI slave device has decoded itself to be the target of the current transaction. It is asserted as an output either when the STPC Consumer is the target of the current PCI transaction or when no other device asserts DEVSEL# prior to the subtractive decode phase of the current PCI transaction. PAR Parity Signal Transactions. This is the parity signal of the PCI bus. This signal is used to guarantee even parity across AD[31:0], CBE#[3:0], and PAR. This signal is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. (Its assertion is identical to that of the AD bus delayed by one PCI clock cycle) SERR# System Error. This is the system error signal of the PCI bus. It may, if enabled, be asserted for one PCI clock cycle if target aborts a STPC Consumer initiated PCI transaction. Its assertion by either the STPC Consumer or by another PCI bus agent will trigger the assertion of NMI to the host CPU. This is an open drain output. LOCK# PCI Lock. This is the lock signal of the PCI bus and is used to implement the exclusive bus operations when acting as a PCI target agent. PCIREQ#[2:0] PCI Request. This pin are the three external PCI master request pins. They indicates to the PCI arbiter that the external agents desire use of the bus. PCIGNT#[2:0] PCI Grant. These pins indicate that the PCI bus has been granted to the master requesting it on its PCIREQ#. 2.2.6 ISA/IDE COMBINED ADDRESS/DATA LA[23]/SCS3# Unlatched Address (ISA)/Secondary Chip Select (IDE). This pin has two functions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pins is ISA Bus unlatched address bit 23 for 16-bit devices. When ISA bus is accessed by any cycle initiated from PCI bus, this pin is in output mode. When an ISA bus master owns the bus, this pins is in input mode. When the IDE bus is active, this signals is used as the active high secondary slave IDE chip select signal. This signal is to be externally NANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. 16/51 Issue 1.2 PIN DESCRIPTION LA[22]/SCS1# Unlatched Address (ISA)/Secondary Chip Select (IDE) This pin has two functions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pins is ISA Bus unlatched address bit 22 for 16-bit devices. When ISA bus is accessed by any cycle initiated from PCI bus, this pin is in output mode. When an ISA bus master owns the bus, this pins is in input mode. When the IDE bus is active, this signals is used as the active high secondary slave IDE chip select signal. This signal is to be externally ANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. LA[21]/PCS3# Unlatched Address (ISA)/Primary Chip Select (IDE). This pin has two functions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pins is ISA Bus unlatched address bit 21 for 16-bit devices. When ISA bus is accessed by any cycle initiated from PCI bus, this pin is in output mode. When an ISAbus master owns the bus, this pins is in input mode. When the IDE bus is active, this signals is used as the active high primary slave IDE chip select signal. This signal is to be externally NANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. LA[20]/PCS1# Unlatched Address (ISA)/Primary Chip Select (IDE). This pin has two functions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pins is ISA Bus unlatched address bit 20 for 16-bit devices. When ISA bus is accessed by any cycle initiated from PCI bus, this pin is in output mode. When an ISA bus master owns the bus, this pins is in input mode. When the IDE bus is active, this signals is used as the active high primary slave IDE chip select signal. This signal is to be externally NANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. LA[19:17]/DA[2:0] Unlatched Address (ISA)/Address (IDE). These pins are multi-function pins. They are used as the ISA bus unlatched address bits [19:17] for ISA bus or the three address bits for the IDE bus devices. When used by the ISA bus, these pins are ISA Bus unlatched address bits 19-17 on 16-bit devices. When ISA bus is accessed by any cycle initiated from the PCI bus, these pins are in output mode. When an ISA bus master owns the bus, these pins are tristated. For IDE devices, these signals are used as the DA[2:0] and are connected to DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals are to be masked during ISA bus cycles, they can be externally ORed before being connected to the IDE devices. SA[19:8]/DD[11:0] Unlatched Address (ISA)/Data Bus (IDE). These are multifunction pins. When the ISA bus is active, they are used as the ISA bus system address bits 19-8. When the IDE bus is active, they serve as IDE signals DD[11:0]. These pins are used as an input when an ISA bus master owns the bus and are outputs at all other times. IDE devices are connected to SA[19:8] directlyand ISA bus is connected to these pins through two LS245 transceivers. The OE of the transceivers are connected to ISAOE # and DIR is connected to MASTER#. A bus signals of the transceivers are connected to CPC and IDE DD bus and B bus signals are connected to ISA SA bus. DD[15:12] Databus (IDE). The high 4 bits of the IDE databus are combined with several of the Xbus lines. Refer to the following section for X-bus pins for further information. SA[7:0] ISA Bus address bits [7:0]. These are the 8 low bits of the system address bus of ISA on 8bit slot. These pins are used as an input when an ISA bus master owns the bus and are outputs at all other times. SD[15:0] I/O Data Bus (ISA). These pins are the external databus to the ISA bus. 17/51 Issue 1.2 PIN DESCRIPTION 2.2.7 ISA/IDE COMBINED CONTROL IOCHRDY/DIORDY Channel Ready (ISA)/Busy/ Ready (IDE). This is a multi-function pin. When the ISA bus is active, this pin is IOCHRDY. When the IDE bus is active, this serves as IDE signal DIORDY. IOCHRDY is the IO channel ready signal of the ISA bus and is driven as an output in response to an ISA master cycle targeted to the host bus or an internal register of the STPC Consumer. The STPC Consumer monitors this signal as an input when performing an ISA cycle on behalf of the host CPU, DMA master or refresh. ISA masters which do not monitor IOCHRDY are not guaranteed to work with the STPC Consumer since the access to the system memory can be considerably delayed due to CRT refresh or a write back cycle. 2.2.8 ISA CONTROL ALE Address Latch Enable. This is the address latch enable output of the ISA bus and is asserted by the STPC Consumer to indicate that LA23-17, SA19-0, AEN and SBHE# signals are valid. The ALE is driven high during refresh, DMA master or an ISA master cycles by the STPC Consumer. ALE is driven low after reset. BHE# System Bus High Enable. This signal, when asserted, indicates that a data byte is being transferred on SD15-8 lines. It is used as an input when an ISA master owns the bus and is an output at all other times. MEMR# Memory Read. This is the memory read command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. The MEMR# signal is active during refresh. MEMW# Memory Write. This is the memory write command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. SMEMR# System Memory Read. The STPC Consumer generates SMEMR# signal of the ISA bus only when the address is below one megabyte or the cycle is a refresh cycle. SMEMW# System Memory Write. The STPC Consumer generates SMEMW# signal of the ISA bus only when the address is below one megabyte. This signal is multiplexed with COL_CMP on the VGA Interface. The signal is selected by setting Strap Option MD[0] as described in Section 3. IOR# I/O Read. This is the IO read command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. IOW# I/O Write. This is the IO write command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. MASTER# Add On Card Owns Bus. This signal is active when an ISA device has been granted bus ownership. MCS16# Memory Chip Select16. This is the decode of LA23-17 address pins of the ISA address bus without any qualification of the command signal lines. MCS16# is always an input. The STPC Consumer ignores this signal during IO and refresh cycles. IOCS16# IO Chip Select16. This signal is the decode of SA15-0 address pins of the ISA address bus without any qualification of the command signals. The STPC Consumer does not drive IOCS16# (similar to PC-AT design). An ISA master access to an internal register of the STPC Consumer is executed as an extended 8-bit IO cycle. REF# Refresh Cycle. This is the refresh command signal of the ISA bus. It is driven as an output when the STPC Consumer performs a refresh cycle on the ISA bus. It is used as an input when an ISA master owns the bus and is used to trigger a refresh cycle. The STPC Consumer performs a pseudo hidden refresh. It requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. The host bus is then relinquished while the refresh cycle continues on the ISA bus. AEN Address Enable. Address Enable is enabled when the DMA controller is the bus owner to indicate that a DMA transfer will occur. The enabling of the signal indicates to IO devices to ignore the IOR#/IOW# signal during DMA transfers. ZWS# Zero Wait State. This signal, when asserted by addressed device, indicates that current cycle can be shortened. IOCHCK# IO Channel Check. IO Channel Check is enabled by any ISA device to signal an error condition that can not be corrected. NMI signal becomes active upon seeing IOCHCK# active if the corresponding bit in Port B is enabled. 18/51 Issue 1.2 PIN DESCRIPTION ISAOE# Bidirectional OE Control. This signal controls the OE signal of the external transceiver that connects the IDE DD bus and ISA SA bus. GPIOCS# I/O General Purpose Chip Select 1. This output signal is used by the external latch on ISA bus to latch the data on the SD[7:0] bus. The latch can be use by PMU unit to control the external peripheral devices to power down or any other desired function. This pin is also serves as a strap input during reset. 2.2.9 IDE CONTROL PIRQ Primary Interrupt Request. Interrupt request from primary IDE channel. SIRQ Secondary Interrupt Request. Interrupt request from secondary IDE channel. PDRQ Primary DMA Request. DMA request from primary IDE channel. SDRQ Secondary DMA Request. DMA request from secondary IDE channel. PDACK# Primary DMA Acknowledge. DMA acknoledge to primary IDE channel. SDACK# Secondary DMA Acknowledge. DMA acknoledge to secondary IDE channel. PIOR# Primary I/O Read. Primary channel read. Active low output. PIOW# Primary I/O Write. Primary channel write. Active low output. SIOR# Secondary I/O Read Secondary channel read. Active low output. SIOW# Secondary I/O Write Secondary channel write. Active low output. 2.2.10 IPC IRQ_MUX[3:0] Multiplexed Interrupt Request. These are the ISA bus interrupt signals. They are to be encoded before connection to the STPC Consumer using ISACLK and ISACLKX2 as the input selection strobes. Note that IRQ8B, which by convention is connected to the RTC, is inverted before being sent to the interrupt controller, so that it may be connected directly to the IRQ pin of the RTC. PCI_INT[3:0] PCI Interrupt Request. These are the PCI bus interrupt signals. They are to be encoded before connection to the STPC Consumer using ISACLK and ISACLKX2 as the input selection strobes. DREQ_MUX[1:0] ISA Bus Multiplexed DMA Request. These are the ISA bus DMA request signals. They are to be encoded before connection to the STPC Consumer using ISACLK and ISACLKX2 as the input selection strobes. DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Consumer before output and should be decoded externally using ISACLK and ISACLKX2 as the control strobes. TC ISA Terminal Count. This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the byte count expires. SPKRD Speaker Drive. This the output to the speaker and is AND of the counter 2 output with bit 1 of Port 61, and drives an external speaker driver. This output should be connected to 7407 type high voltage driver. 2.2.11 X-Bus Interface pins / IDE Data RMRTCCS# / DD[15] ROM/Real Time clock chip select. This pin is a multi-function pin. When ISAOE# is active, this signal is used as RMRTCCS#. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access the ROM. During a IO cycle, this signal is asserted if access to the Real Time Clock (RTC) is decoded. It should be combined with IOR or IOW# signals to properly access the real time clock. When ISAOE# is inactive, this signal is used as IDE DD[15] signal. This signal must be ORed externally with ISAOE# and is then connected to ROM and RTC. An LS244 or equivalent function can be used if OE# is connected to ISAOE# and the output is provided with a weak pull-up resistor. KBCS# / DD[14] Keyboard Chip Select. This pin is a multi-function pin. When ISAOE# is active, this signal is used as KBCS#. This signal is asserted if a keyboard access is decoded during a I/O cycle. When ISAOE# is inactive, this signal is used as IDE DD[14] signal. This signal must be ORed externally with ISAOE# and is then connected to keyboard. An LS244 or equivalent function can be used if OE# is connect- 19/51 Issue 1.2 PIN DESCRIPTION ed to ISAOE# and the output is provided with a weak pull-up resistor. RTCRW# / DD[13] Real Time Clock RW. This pin is a multi-function pin. When ISAOE# is active, this signal is used as RTCRW#. This signal is asserted for any I/O write to port 71H. When ISAOE# is inactive, this signal is used as IDE DD[13] signal. This signal must be ORed externally with ISAOE# and then connected to the RTC. An LS244 or equivalent function can be used if OE is connected to ISAOE# and the output is provided with a weak pull-up resistor. RTCDS# / DD[12] Real Time Clock DS. This pin is a multi-function pin. When ISAOE# is active, this signal is used as RTCDS. This signal is asserted for any I/O read to port 71H. When ISAOE# is inactive, this signal is used as IDE DD[12] signal. This signal must be ORed externally with ISAOE# and is then connected to RTC. An LS244 or equivalent function can be used if OE# is connected to ISAOE# and the output is provided with a weak pull-up resistor. RTCAS# Real time clock address strobe. This signal is asserted for any I/O write to port 70H. 2.2.12 Monitor Interface RED, GREEN, BLUE RGB Video Outputs. These are the 3 analog color outputs from the RAMDACs VSYNC Vertical Synchronisation Pulse. This is the vertical synchronization signal from the VGA controller. HSYNC Horizontal Synchronisation Pulse. This is the horizontal synchronization signal from the VGA controller. VREF_DAC DAC Voltage reference. An external voltage reference is connected to this pin to bias the DAC. RSET Resistor Current Set. This is reference current input to the RAMDAC is used to set the fullscale output of the RAMDAC. COMP Compensation. This is the RAMDAC compensation pin. Normally, an external capacitor (typically 10nF) is connected between this pin and VDD to damp oscillations. DDC[1:0] Direct Data Channel Serial Link. These bidirectional pins are connected to CRTC register 3Fh to implement DDC capabilities. They conform to I2C electrical specifications, they have opencollector output drivers which are internally connected to VDD through pull-up resistors. They can instead be used for accessing I C devices on board. DDC1 and DDC0 correspond to SCL and SDA respectively. COL_CMP Color Compare Output. Allows access to the video signal which flags when there is a color compare hit. This signal is multiplexed with SMEMEW# on the ISA Bus. The signal is selected by setting Strap Option MD[0] as described in Section 3. 2.2.13 MISCELLANEOUS SCAN_ENABLE Reserved . The pins are reserved for Test and Miscellaneous functions) 20/51 Issue 1.2 PIN DESCRIPTION Table 2-3. Pinout. Pin # AF3 A3 C4 G23 F25 AF15 AF9 AD15 AF16 AC15 AE17 AD16 AF17 AC17 AE18 AD17 AF18 AE19 AF19 AD18 AE20 AC19 AF20 AE21 AC20 AF21 AD20 AE22 AF22 AD21 AE23 AC22 AF23 AE24 AF24 AD25 AC25 AC26 AB24 AA25 AA24 Y25 Y24 V23 W24 V26 V24 U23 Pin name SYSRSTI XTALI XTALO HCLK DEV_CLK GCLK2X DCLK MA[0] MA[1] MA[2] MA[3] MA[4] MA[5] MA[6] MA[7] MA[8] MA[9] MA[10] MA[11] RAS#[0] RAS#[1] RAS#[2] RAS#[3] CAS#[0] CAS#[1] CAS#[2] CAS#[3] CAS#[4] CAS#[5] CAS#[6] CAS#[7] MWE# MD[0] MD[1] MD[2] MD[3] MD[4] MD[5] MD[6] MD[7] MD[8] MD[9] MD[10] MD[11] MD[12] MD[13] MD[14] MD[15] Pin # U24 R26 P25 P26 N25 N26 M25 M26 M24 M23 L24 J25 J26 H26 G25 G26 AD22 AD23 AE26 AD26 AC24 AB25 AB26 Y23 AA26 Y26 W25 W26 V25 U25 U26 T25 R25 T24 R23 R24 N23 P24 N24 L25 L26 K25 K26 K24 H25 J24 H23 H24 F24 Pin name MD[16] MD[17] MD[18] MD[19] MD[20] MD[21] MD[22] MD[23] MD[24] MD[25] MD[26] MD[27] MD[28] MD[29] MD[30] MD[31] MD[32] MD[33] MD[34] MD[35] MD[36] MD[37] MD[38] MD[39] MD[40] MD[41] MD[42] MD[43] MD[44] MD[45] MD[46] MD[47] MD[48] MD[49] MD[50] MD[51] MD[52] MD[53] MD[54] MD[55] MD[56] MD[57] MD[58] MD[59] MD[60] MD[61] MD[62] MD[63] PCI_CLKI Pin # D25 A20 C20 B19 A19 C19 B18 A18 B17 C18 A17 D17 B16 C17 B15 A15 C16 D15 A14 C15 B13 D13 A13 C14 C13 A12 B11 C12 A11 D12 B10 C11 A10 D10 C10 A9 B8 A8 B7 D8 A7 C8 B6 D7 A6 C21 A21 B20 C22 Pin name PCI_CLKO AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] CBE[0] CBE[1] CBE[2] CBE[3] FRAME# TRDY# IRDY# STOP# DEVSEL# PAR SERR# LOCK# PCI_REQ#[0] PCI_REQ#[1] PCI_REQ#[2] PCI_GNT#[0] 21/51 Issue 1.2 PIN DESCRIPTION Pin # B21 D20 A5 C6 B4 D5 F2 G4 F3 F1 G2 G3 H2 J4 H1 H3 J2 J1 K2 J3 K1 K4 L2 K3 L1 M2 M1 L3 N2 M4 N1 M3 P4 P3 R2 N3 P1 R1 T2 R3 T1 R4 U2 T3 U1 U4 V2 U3 Pin name PCI_GNT#[1] PCI_GNT#[2] PCI_INT[0] PCI_INT[1] PCI_INT[2] PCI_INT[3] LA[17]/DA[0] LA[18]/DA[1] LA[19]/DA[2] LA[20]/PCS1# LA[21]/PCS3# LA[22]/SCS1# LA[23]/SCS3# SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8]/DD[0] SA[9]/DD[1] SA[10]/DD[2] SA[11]/DD[3] SA[12] / DD[4] SA[13] / DD[5] SA[14] / DD[6] SA[15] / DD[7] SA[16] / DD[8] SA[17] / DD[9] SA[18] / DD[10] SA[19] / DD[11] RTCDS / DD[12] RTCRW# / DD[13] KBCS# / DD[14] RMRTCCS# / DD[15] SD[0] SD[1] SD[2] SD[3] SD[4] SD[5] SD[6] SD[7] SD[8] SD[9] SD[10] Pin # V1 W2 W1 V3 Y2 Y1 AE4 AD4 AE5 AF8 W3 AC9 AA2 Y4 AA1 Y3 AB2 AA3 AC2 AB4 AC1 AB3 AD2 AC3 AD1 AF2 A4 AE3 B1 C2 C1 D2 D3 D1 E2 E4 E3 E1 E23 D26 E24 C25 A24 B23 C23 Pin name SD[11] SD[12] SD[13] SD[14] SD[15] IOCHRDY SYSRSTO# ISA_CLK ISA_CLK2X OSC14M ALE ZWS# BHE# MEMR# MEMW# SMEMR# SMEMW#/COL_CMP IOR# IOW# MASTER# MCS16# IOCS16# REF# AEN IOCHCK# ISAOE# RTCAS# GPIOCS# PIRQ SIRQ PDRQ SDRQ PDACK# SDACK# PIOR# PIOW# SIOR# SIOW# IRQ_MUX[0] IRQ_MUX[1] IRQ_MUX[2] IRQ_MUX[3] DREQ_MUX[0] DREQ_MUX[1] DACK_ENC[0] Pin # A23 B22 D22 C5 AE6 AD6 AF6 AD5 AC5 AD7 AE8 AF5 C7 B5 AC12 AE13 AD14 AD12 AE14 AC14 AF14 AD13 AE15 AF10 AC10 AF11 AE10 AD9 AD11 AD8 AE9 AE11 AD10 B3 AF12 AC7 AF4 AD19 AF13 F26 G24 A16 B12 B9 Pin name DACK_ENC[1] DACK_ENC[2] TC SPKRD RED GREEN BLUE VSYNC HSYNC VREF_DAC RSET COMP SDA / DDC[0] SCL / DDC[1] VCLK VIN[0] VIN[1] VIN[2] VIN[3] VIN[4] VIN[5] VIN[6] VIN[7] RED_TV GREEN_TV BLUE_TV VCS ODD_EVEN CVBS IREF1_TV VREF1_TV IREF2_TV VREF2_TV SCAN_ENABLE VDDA_TV VDD_DAC1 VDD_DAC2 VDD_GCLK_PLL VDD_DCLK_PLL VDD_HCLK_PLL VDD_DEVCLK_PLL VDD5 VDD5 VDD5 22/51 Issue 1.2 PIN DESCRIPTION Pin # D18 A22 B14 C9 D6 D11 D16 D21 F4 F23 G1 K23 L4 L23 P2 T4 T23 T26 W4 AA4 AA23 AB1 AB23 AC6 AC11 AC16 AC21 AE12 AE7 AF7 E25 E26 A1:2 A26 B2 B25:26 C3 C24 D4 D9 D14 D19 D23 H4 J23 L11:16 M11:16 N4 Pin name VDD5 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSSA_TV VSS_DAC1 VSS_DAC2 VSS_DLL VSS_DLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin # N11:16 P11:16 P23 R11:16 T11:16 V4 W23 AC4 AC8 AC13 AC18 AC23 AD3 AD24 AE1:2 AE16 AE25 AF1 AF25 AF26 C26 D24 B24 A25 Pin name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RESERVED RESERVED RESERVED RESERVED 23/51 Issue 1.2 PIN DESCRIPTION 24/51 Issue 1.2 U pdate History for Pin Description chapter 2.4 Update History for Pin Description chapter The following changes have been made to the Pin Description Chapter on 08/02/2000 Section 2.2 Change Added Text Color Compare Signal The following changes have been made to the Pin Description Chapter on 13/01/2000 Section 2.2 Change Added Text “to a minimum of 8MHz” 25/51 Issue 1.2 Update History for Pin Description chapter 26/51 Issue 1.2 STRAP OPTION 3. STRAP OPTION This chapter defines the STPC Consumer Strap Options and their location Memory Data Note Lines MD0 1 MD1 MD2 2 MD3 2 MD4 2 MD5 2 MD6 2 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 2 2 2 2 2 2 2 2 2 Actual Settings Refer to Designation Location Index 4A, Bit 0 Index 4A, bit 2 Index 4A, bit 3 Index 4A,bit 4 Index 4A,bit 5 Index 4A,bit 6 Index 4A, bit 7 Index4B,bit0 Index4B,bit1 Index 4B,bit 2 Index 4B,bit 3 Index 4B,bit 4 Index 4B,bit 5 Index 4B, bit 6 Index 4B,bit 7 Index 4C,bit 0 Index 4C,bit 1 Index 4C,bit 2 Index 4C,bit 3 Index 4C, bit4 Index 5F, bit 0 Index 5F, bit 1 Index 5F,bit 2 Index 5F,bit 3 Index 5F,bit 4 Index 5F,bit 5 Set to ’0’ Set to ’1’ SMEMW# 60 ns FPM 60 ns FPM 60 ns FPM 60 ns FPM HCLK / 3 25 MHz 33 MHz 40 MHz 50 MHz 60 MHz 66 MHz 75 MHz 80 MHz - DRAM Bank 1 DRAM Bank 0 Reserved Speed Speed Type Speed Speed Type Reserved Reserved Speed Speed Type Speed Speed Type Reserved PCI_CLKO Divisor Reserved Reserved Reserved Reserved Reserved Reserved HCLK PLL Speed User defined COLOR_KEY User defined 70 ns Pull up User defined EDO User defined 70 ns Pull up User defined Pull up User defined Pull up User defined User defined Pull up User defined Pull up User defined Pull up Pull up Pull up Pull up Pull up Pull up User defined User defined User defined User defined User defined User defined User defined User defined Pull down Pull down Pull down Pull down Pull down Pull down Pull down Pull down Pull down Pull up Pull up EDO 70 ns EDO 70 ns EDO HCLK / 2 000 001 010 011 100 101 110 111 - DRAM Bank 3 DRAM Bank 2 PCI Clock HCLK MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - 27/51 Issue 1.2 STRAP OPTION Memory Data Note Lines MD38 MD39 MD40 MD41 MD42 MD43 Actual Settings Pull up Pull up User defined Pull down Pull up Pull down Refer to CPU - Designation Reserved Reserved CPU Mode Reserved Reserved Reserved Location - Set to ’0’ DX1 - Set to ’1’ DX2 - Note; 1) This Strap Option selects between two different functional blocks, the first is the ISA (SMEMW#) and the other is the VGA block (Color_Key). 2) Setting of Strap Options MD [2:15] have no effect on the DRAM Controller but are purely meant for software issues. i.e. Readable in a register. 3.1 STRAP REGISTER DESCRIPTION 3.1.1 STRAP (STRAP0) REGISTER 0 INDEX 4AH 3.1.2 STRAP (STRAP1) REGISTER 1 INDEX 4BH Bits 7-0 of this register reflect the status of pins MD[15:8] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Bits 7-0 of this register reflect the status of pins MD[7:0] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Bit Sampled Bit 7 Bits 6-5 Bit 4 Bits 3-2 Description SIMM 2 dram type SIMM 2 speed SIMM 3 dram type SIMM 3 speed Bit Sampled Bit 7 Bits 6-5 Bit 4 Bits 3-2 Bits 1-0 Description SIMM 0 dram type SIMM 0 speed SIMM 1 dram type SIMM 1 speed Reserved Note that the SIMM speed and type information read here is meant only for thesoftware and is not used by the hardware. The software must program the Host and graphics dram controller configuration registers appropriately based on these bits. This register defaults to the values sampled on MD[15:8] pins after reset. 3.1.3 STRAP (STRAP2) REGISTER 2 INDEX 4CH Note that the SIMM speed and type information read here is meant only for the software and is not used by the hardware. The software must program the Host and graphics dram controller configuration registers appropriately based on these bits. This register defaults to the values sampled on MD[7:0] pins after reset. Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the status of pin MD[23]. Bit 4 is writeable, writes to other bits in this register have no effect. They are use by the chip as follows: Bit 4-2; Reserved 28/51 Issue 1.2 STRAP OPTION Bit 1 This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows: 0: PCI clock output = HCLK / 2 1: PCI clock output = HCLK / 3 Bit 0; Reserved Strap Options [39:27] are reserved. This register defaults to the values sampled on MD[23] & MD[20:16] pins after reset. 3.1.4 HCLK PLL STRAP REGISTER 0 INDEX 5FH (HCLK_STRAP0) Bits 5-0 of this register reflect the status of pins MD[26:21] respectively. They are use by the chip as follows: 3.1.5 486 CLOCK PROGRAMMING (486_CLK) The bit MD[40] is used to set the clock multiplication factor of the 486 core. With the MD[40] pin pulled low the 486 will run in DX (x1) mode, while with the MD[40] pin pulled high the 486 will run in DX2 (x2) mode. The default value of the resistor on this strap input should be a resister to ground (DX mode). Strap options MD[43:41] are reserved. Bits 5-3; These pins reflect the value sampled on MD[26:24] pins respectively and control the Host clock frequency synthesizer. Bit 2-0; Reserved This register defaults to the values sampled on above pins after reset. 29/51 Issue 1.2 ELECTRICAL SPECIFICATIONS 4. ELECTRICAL SPECIFICATIONS 4.1 Introduction The electrical specifications in this chapter are valid for the STPC Consumer. 4.2 Electrical Connections 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Consumer, it is necessary to install and test this device using standard high frequency techniques. The high clock frequencies used in the STPC Consumer and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VSS and VDD pins. 4.2.2 Unused Input Pins All inputs not used by the designer and not listed in the table of pin connections in Chapter 3 should be connected either to VDD or to VSS. Connect active-high inputs to VDD through a 20 kΩ (±10%) pull-down resistor and active-low inputs to VSS and connect active-low inputs to VCC through a Table 4-1. Absolute Maximum Ratings Symbol VDDx VI , VO TSTG TOPER PTOT Parameter DC Supply Voltage Digital Input and Output Voltage Storage Temperature Operating Temperature Total Power Dissipation Value -0.3, 4.0 -0.3, VDD + 0.3 -40, +150 0, +70 4.8 Units V V °C °C W 20 kΩ (±10%) pull-up resistor to prevent spurious operation. 4.2.3 Reserved Designated Pins Pins designated reserved should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 Absolute Maximum Ratings The following table lists the absolute maximum ratings for the STPC Consumer device. Stresses beyond those listed under Table 4-1 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those specified in section ”Operating Conditions”. Exposure to conditions beyond Table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 4-1) may also result in reduced useful life and reliability. 30/51 Issue 1.2 ELECTRICAL SPECIFICATIONS 4.4 DC Characteristics Table 4-2. DC Characteristics Recommended Operating conditions : VDD = 3.3V Symbol VDD PDD H CLK VREF_D AC ±0.3V, Tcase = 0 to 100°C unless otherwise specified Min 3.0 Typ 3.3 3.2 Max 3.6 3.9 75 1.255 0.5 2.4 -0.3 -0.3 2.1 2.35 -5 0.8 0.9 VDD+0.3 VDD+0.3 5 Unit V W Mhz V V V V V V V µA pF pF pF Parameter Operating Voltage Supply Power Internal Clock DAC Voltage Reference Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Output Capacitance Clock Capacitance Test conditio ns VDD = 3.3V, HCLK = 66Mhz (Note 1) 1.215 ILoad =1.5 to 8mA depending of the pin ILoad =-0.5 to -8mA depending of the pin Except XTALI XTALI Except XTALI XTALI Input, I/O (Note 2) (Note 2) (Note 2) 1.235 VOL VOH VIL VIH ILK C IN C OUT C CLK Notes: 1. MHz ratings refer to CPU clock frequency. 2. Not 100% tested. 4.5 AC Characteristics Table 4-4 through Table 4-9 list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1 . The rising clock edge reference level VREF , and other reference levels are shown in Table 4-3 below for the STPC Consumer. Input or output signals must cross these levels during testing. Figure 4-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. Table 4-3. Drive Level and Measurement Points for Switching Characteristics Symbol VREF VIHD V ILD Value 1.5 3.0 0.0 Units V V V Note: Refer to Figure 4-1. 31/51 Issue 1.2 ELECTRICAL SPECIFICATIONS Figure 4-1 Drive Level and Measurement Points for Switching Characteristics Tx VIHD CLK: A B MIN VRef Valid Output n+1 MAX VRef VILD OUTPUTS: Valid Output n C D VIHD INPUTS: Valid Input VRef VILD LEGEND: A B C D - Maximum Output Delay Specification - Minimum Output Delay Specification - Minimum Input Setup Specification - Minimum Input Hold Specification Figure 4-2 CLK Timing Measurement Points T1 T2 VIH (MIN) VRef CLK VIL (MAX) T5 T3 T4 LEGEND: T1 - One Clock Cycle T2 - Minimum Time at VIH T3 - Minimum Time at VIL T4 - Clock Fall Time T5 - Clock Rise Time NOTE; All sIgnals are sampled on the rising edge of the CLK. Note; The above timings are generic timings and are not specific to the interfaces defined below 32/51 Issue 1.2 ELECTRICAL SPECIFICATIONS 4.5.1 AC Timing parameters Table 4-4. PCI Bus AC Timing Name t1 t2 t3 t4 t5 T6 T7 T8 T9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 Parameter PCI_CLKI to AD[31:0] valid PCI_CLKI to FRAME# valid PCI_CLKI to CBE#[3:0] valid PCI_CLKI to PAR valid PCI_CLKI to TRDY# valid PCI_CLKI to IRDY# valid PCI_CLKI to STOP# valid PCI_CLKI to DEVSEL# valid PCI_CLKI to PCI_GNT# valid AD[31:0] bus setup to PCI_CLKI AD[31:0] bus hold from PCI_CLKI PCI_REQ#[2:0] setup to PCI_CLKI PCI_REQ#[2:0] hold from PCI_CLKI CBE#[3:0] setup to PCI_CLKI CBE#[3:0] hold to PCI_CLKI IRDY# setup to PCI_CLKI IRDY# hold to PCI_CLKI FRAME# setup to PCI_CLKI FRAME# hold from PCI_CLKI Min 2 2 2 2 2 2 2 2 2 7 0 7 4 7 0 7 0 7 0 Max 11 11 11 11 11 11 11 11 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 4-5. DRAM Bus AC Timing Name t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 Parameter HCLK to RAS#[3:0] valid HCLK to CAS#[7:0] bus valid HCLK to MA[11:0] bus valid HCLK to MWE# valid HCLK to MD[63:0] bus valid MD[63:0] Generic setup GCLK2X to RAS#[3:0] valid GCLK2X to CAS#[7:0] valid GCLK2X to MA[11:0] bus valid GCLK2X to MWE# valid GCLK2X to MD[63:0] bus valid MD[63:0] Generic hold Min Max 19 19 19 17 20 19 19 19 17 20 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns 13 Table 4-6. IDE Bus AC Timing Name t20 t21 Parameter DD[15:0] setup to PIOR#/SIOR# falling DD[15:0} hold to PIOR#/SIOR# falling Min 15 0 Max Unit ns ns 33/51 Issue 1.2 ELECTRICAL SPECIFICATIONS Table 4-7. Video Input AC Timing Name t35 t36 t37 t38 t39 t40 t41 t42 Parameter VIN[7:0] setup to VCLK VIN[7:0] hold from VCLK VCLK to ODD_EVEN valid VCLK to VCS valid ODD_EVEN setup to VCLK ODD_EVEN hold from VCLK VCS setup to VCLK VCS hold from VCLK Min 5 4 Max Unit ns ns ns ns ns ns ns ns 15 15 10 5 10 5 Table 4-8. Graphics Adapter (VGA) AC Timing Name t43 t44 Parameter DCLK to VSYNC valid DCLK to HSYNC valid Min Max 30 30 Unit ns ns Table 4-9. ISA Bus AC Timing Name t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 Parameter XTALO to LA[23:17] bus active XTALO to SA[19:0] bus active XTALO to BHE# valid XTALO to SD[15:0] bus active PCI_CLKI to ISAOE# valid XTALO to GPIOCS# valid XTALO to ALE valid XTALO to MEMW# valid XTALO to MEMR# valid XTALO to SMEMW# valid XTALO to SMEMR# valid XTALO to IOR# valid XTALO to IOW# valid Min Max 60 60 62 35 28 60 62 50 50 50 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 34/51 Issue 1.2 U pdate History for Electrical Specification chapter 4.10 Update History for Electrical Specification chapter The following changes have been made to the Electrical Specification Chapter on the 07/02/2000. Section 4.5 Change Revued Text Timings t35 - t42 The following changes have been made to the Electrical Specification Chapter on the 20/10/99. Section 4.5 Change Revued Text Timings T1-10, T12, T14, T16, T18, T26, T32, T35, T39-42 &T54 The following changes have been made to the Electrical Specification Chapter on the 16/08/99. Section 18 Change Removed Text Figure 4-2 CLK Timing Measurement Points. 35/51 Issue 1.2 Update History for Electrical Specification chapter 36/51 MECHANICAL DATA 5. MECHANICAL DATA 5.1 388-Pin Package Dimension The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View Dimensions are shown in Figure 5-2, Table 5-1 and Figure 5-3, Table 5-2. 1 2 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 37/51 Issue 1.2 M ECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A B A E F D Detail CG Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols A B C D E F G Min 34.95 1.22 0.58 1.57 0.15 0.05 0.75 mm Typ 35.00 1.27 0.63 1.62 0.20 0.10 0.80 Max 35.05 1.32 0.68 1.67 0.25 0.15 0.85 Min 1.375 0.048 0.023 0.062 0.006 0.002 0.030 inches Typ 1.378 0.050 0.025 0.064 0.008 0.004 0.032 Max 1.380 0.052 0.027 0.066 0.001 0.006 0.034 38/51 Issue 1.2 MECHANICAL DATA Figure 5-3. 388-pin PBGA Package - Dimensions C F D E Solderball Solderball after collapse B A G Table 5-2. 388-pin PBGA Package - Dimensions Symbols A B C D E F G Min 0.50 1.12 0.60 0.52 0.63 0.60 mm Typ 0.56 1.17 0.76 0.53 0.78 0.63 30.0 Max 0.62 1.22 0.92 0.54 0.93 0.66 Min 0.020 0.044 0.024 0.020 0.025 0.024 inches Typ 0.022 0.046 0.030 0.021 0.031 0.025 11.8 Max 0.024 0.048 0.036 0.022 0.037 0.026 39/51 Issue 1.2 M ECHANICAL DATA 5.2 388-Pin Package thermal data 388-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Structure in shown in Figure 5-4. Thermal dissipation options are illustrated in Figure 5-5 and Figure 5-6. Signal layers Power & Ground layers Thermal balls Figure 5-5. Thermal dissipation without heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 6 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 125 The PBGA is centered on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17µm for internal layers - 34µm for external layers Airflow = 0 Board temperature taken at the center balls Ambient Rja = 13 °C/W 40/51 Issue 1.2 MECHANICAL DATA Figure 5-6. Thermal dissipation with heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 3 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 50 The PBGA is centered on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17µm for internal layers - 34µm for external layers Airflow = 0 Board temperature taken at the center balls Heat sink is 11.1°C/W Ambient Rja = 9.5 ° C/W 41/51 Issue 1.2 M ECHANICAL DATA 42/51 Issue 1.2 B OARD LAYOUT 6. BOARD LAYOUT 6.1 THERMAL DISSIPATION Thermal dissipation of the STPC depends mainly on supply voltage. As a result, when the system does not need to work at 3.3V, it may be to reduce the voltage to 3.15V for example. This may save few 100’s of mW. The second area that can be concidered is unused interfaces and functions. Depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. Clock speed dynamic adjustment is also a solution that can be used along with the integrated power management unit. The standard way to route thermal balls to internal ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. With such configuration the Plastic BGA 388 package dissipates 90% of the heat through the ground balls, and especially the central thermal balls which are directly connected to the die, the remaining 10% is dissipated through the case. Adding a heat sink reduces this value to 85%. As a result, some basic rules have to be applied when routing the STPC in order to avoid thermal problems. First of all, the whole ground layer acts as a heat sink and ground balls must be directly connected to it as illustrated in Figure 6-1. If one ground layer is not enough, a second ground plane may be added on the solder side. Figure 6-1. Ground routing Pad for ground ball Thru hole to ground layer Top L ayer : Sign Grou als nd la yer Powe r laye r Botto mLa yer : signa ls + l ocal g round layer (if ne eded ) Note: For better visibility, ground balls are not all routed. 43/51 Issue 1.2 BOARD LAYOUT When considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The use of a 8-mil wire results in a thermal resistance of 105°C/W assuming copper is used (418 W/ m.°K). This high value is due to the thickness (34 µm) of the copper on the external side of the PCB. Considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9°C/W. This can be easily improved by using four 10 mil wires to connect to the four vias around the ground pad link as in Figure 6-3. This gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.6°C/W. The use of a ground plane like in Figure 6-4 is even better. To avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (NSMD pad), this gives a diameter of 33 mil for a 25 mil ground pad. To obtain the optimum ground layout, place the vias directly under the ball pads. In this case no local boar d distortion is tolerated. The thickness of the copper on PCB layers is typically 34 µm for external layers and 17 µm for internal layers. This means thermal dissipation is not good and temperature of the board is concentrated around the devices and falls quickly with increased distance. When it is possible to place a metal layer inside the PCB, this improves dramatically the heat spreading and hence thermal dissipation of the board. Figure 6-2. Recommended 1-wire ground pad layout Pad for ground ball (diameter = 25 mil) Solder Mask (4 mil) Connection Wire (width = 10 mil) Via (diameter = 24 mil) il . 34 Figure 6-3. Recommended 4-wire ground pad layout 5 m Hole to ground layer (diameter = 12 mil) 1 mil = 0.0254 mm 4 via pads for each ground ball 44/51 Issue 1.2 B OARD LAYOUT Figure 6-4. Optimum layout for central ground ball Clearance = 6mil External diameter = 37 mil Via to Ground layer hole diameter = 14 mil Solder mask diameter = 33 mil Pad for ground ball diameter = 25 mil connections = 10 mil The PBGA Package also dissipates heat through peripheral ground balls. When a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipation through the peripheral ground balls. The more via pads are connected to each ground ball, the more heat is dissipated . The only limitation is the risk of lossing routing channels. Figure 6-5 shows a routing with a good trade off between thermal dissipation and number of routing channels. Figure 6-5. Global ground layout for good thermal dissipation Via to ground layer Ground pad 45/51 Issue 1.2 BOARD LAYOUT Figure 6-6. Bottom side layout and decoupling Ground plane for thermal dissipation Via to ground layer A local ground plane on opposite side of the board as shown in Figure 6-6 improves thermal dissipation. It is used to connect decoupling capacitances but can also be used for connection to a heat sink or to the system’s metal box for better dissipation. This possibility of using the whole system’s box for thermal dissipation is very usefull in case of high temperature inside the system and low temperature outside. In that case, both sides of the PBGA should be thermally connected to the metal chassis in order to propagate the heat through the metal. Figure 6-7 illustrates such an implementation. Figure 6-7. Use of metal plate for thermal dissipation Die Board Metal planes Thermal conductor 46/51 Issue 1.2 B OARD LAYOUT 6.2 HIGH SPEED SIGNALS Some Interfaces of the STPC run at high speed and have to be carefully routed or even shielded. Here is the list of these interfaces, in decreasing speed order: - Memory Interface. - Graphics and video interfaces - PCI bus - 14MHz oscillator stage Figure 6-8. Shielding signals All the clocks have to be routed first and shielded for speeds of 27MHz or more. The high speed signals have the same contrainsts as some of the memory interface control signals. The next interfaces to be routed are Memory, Video/graphics, and PCI. All the analog noise sensitive signals have to be routed in a separate area and hence can be routed indepedently. ground ring shielded signal line ground pad ground pad shielded signal lines 47/51 Issue 1.2 ORDERING DATA 7. ORDERING DATA 7.1 Ordering Codes ST STMicroelectronics Prefix Product Family PC: PC Compatible Product ID C01: Consumer Core Speed 66: 66MHz 75: 75MHz 80: 80MHz 10: 100MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial 0 to +70°C Tcase = 0 to +100°C I: Industrial -40 to +85°C Tcase = -40 to +100°C Operating Voltage 3 : 3.3V ± 0.3V PC C01 66 BT C 3 48/51 Issue 1.2 ORDERING DATA 7.2 Available Part Numbers Part Number STPCC0166BTC3 STPCC0180BTC3 STPCC0110BTC3 STPCC0166BTI3 STPCC0180BTI3 Core Frequency (MHz) 66 80 100 66 80 CPU Mode DX DX DX2 DX DX Tcase Range (C) 0°C to +100° C 3.3V ± 0.3V -40°C to +100°C Operating Voltage (V) 49/51 Issue 1.2 ORDERING DATA 50/51 Issue 1.2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics. © 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 51 Issue 1.2