STPM33TR

STPM32, STPM33, STPM34 Datasheet ASSP for metering applications with up to four independent 24-bit 2nd order sigma-delta ADCs, 4 MHz OSF and 2 embedded PGLNA Features • • • • • • • • Active power accuracy: – < 0.1% error over 5000 : 1 dynamic range – < 0.5% error over 10000 : 1 dynamic range Exceeds 50-60 Hz EN 50470-x, IEC 62053-2x, ANSI12.2x standard requirements for AC watt meters Reactive power accuracy: – < 0.1% error over 2000 : 1 dynamic range Dual mode apparent energy calculation Instantaneous and averaged power RMS and instantaneous voltage and current Under and overvoltage detection (sag and swell) and monitoring Overcurrent detection and monitoring UART and SPI serial interface with programmable CRC polynomial verification Programmable LED and interrupt outputs • • • • Four independent 24-bit 2nd order sigma-delta ADCs Two programmable gain chopper stabilized low-noise and low-offset amplifiers Bandwidth 3.6 kHz at -3 dB Vcc supply range 3.3 V ± 10% • Supply current Icc 4.3 mA (STPM32) • • Input clock frequency 16 MHz, Xtal or external source Twin precision voltage reference: 1.18 V with independent programmable TC, 30 ppm/°C typ. Internal low drop regulator at 3 V (typ.) QFN packages Operating temperature from -40 °C to +105 °C • • Product status link STPM32 STPM33 STPM34 • • • Product label Description The STPM3x is an ASSP family designed for high accuracy measurement of power and energies in power line systems using the Rogowski coil, current transformer or shunt current sensors. The STPM3x provides instantaneous voltage and current waveforms and calculates RMS values of voltage and currents, active, reactive and apparent power and energies. The STPM3x is a mixed signal IC family consisting of an analog and a digital section. The analog section consists of up to two programmable gain low-noise low-offset amplifiers and up to four 2nd order 24-bit sigma-delta ADCs, two bandgap voltage references with independent temperature compensation, a low drop voltage regulator and DC buffers. The digital section consists of digital filtering stage, a hardwired DSP, DFE to the input and a serial communication interface (UART or SPI). The STPM3x is fully configurable and allows a fast digital system calibration in a single point over the entire current dynamic range. DS10272 - Rev 12 - July 2022 For further information contact your local STMicroelectronics sales office. www.st.com STPM32, STPM33, STPM34 Schematic diagram 1 Schematic diagram Figure 1. STPM34 block diagram CLKOUT/ ZCR LED1 LED2 INT1 INT2 VIP1 VIN1 VIP2 2nd ordΣΔ modulator Decimation Phase Compensation 2nd ordΣΔ modulator Decimation Phase Compensation EN VIN2 Filters IIP1 PLNA 2nd ordΣΔ modulator PLNA 2nd ordΣΔ modulator Decimation Phase Compensation Decimation Phase Compensation IIN1 IIP2 IIN2 DSP VDDD VrefC2 LDR 1.2V VOLTAGE REFERENCE VRefV2 VRefC1 VCC LDR 3.0V VOLTAGE REFERENCE VDDA DS10272 - Rev 12 VRefV1 VREF2 VREF1 OSC 16MHz SPI/UART XTAL1XTAL2 SCS MISO/ MOSI/ SCL SYN TXD RXD page 2/91 STPM32, STPM33, STPM34 Schematic diagram Figure 2. STPM33 block diagram CLKOUT/ ZCR VIP1 2nd ordΣΔ modulator LED1 LED2 INT1 Decimation Phase Compensation Decimation Phase Compensation Decimation Phase Compensation INT2 EN VIN1 IIP1 PLNA 2nd ordΣΔ modulator IIN1 IIP2 PLNA 2nd ordΣΔ modulator Filters DSP IIN2 VDDD VRefC2 VOLTAGE REFERENCE LDR 1.2V VRefV2 VRefC1 VCC VOLTAGE REFERENCE LDR 3.0V OSC 16MHz SPI/UART XTAL1 XTAL2 SCS MISO/ MOSI/ SCL SYN TXD RXD VRefV1 VDDA VREF2 VREF1 Figure 3. STPM32 block diagram CLKOUT/ ZCR VIP1 2nd ordΣΔ modulator Decimation LED1 LED2 INT1 INT2 EN Phase Compensation VIN1 Filters IIP1 PLNA 2nd ordΣΔ modulator Decimation IIN1 DSP Phase Compensation VDDD LDR 1.2V VRefC1 VCC VOLTAGE REFERENCE LDR 3.0V OSC 16MHz SPI/UART XTAL1 XTAL2 SCS MISO/ MOSI/ SCL SYN TXD RXD VRefV1 VDDA DS10272 - Rev 12 VREF1 page 3/91 STPM32, STPM33, STPM34 Pin configuration 2 Pin configuration 25 GNDD 26 GNDD 27 VDDD 28 SYN 29 SCS 30 SCL 31 MOSI/RXD 32 MISO/TXD Figure 4. STPM34 pinout (top view), QFN32L 5x5x1 CLKOUT/ZCR 1 24 NC CLKIN/XTAL2 2 23 VCC 22 GND_REG XTAL1 3 LED1 4 21 VDDA STPM34 LED2 5 20 GNDA INT1 6 19 VREF2 INT2 7 18 GND_REF EN 8 VIP2 16 VIN2 15 IIP2 14 IIN2 13 IIN1 12 IIP1 11 VIN1 10 VIP1 9 17 VREF1 26 GNDD 27 VDDD 28 SYN 29 SCS 30 SCL 25 NC NC CLKOUT/ZCR 1 24 CLKIN/XTAL2 2 23 VCC XTAL1 3 22 GND_REG LED1 4 21 VDDA LED2 5 20 GNDA INT1 6 19 VREF2 INT2 7 18 GND_REF EN 8 17 VREF1 NC 16 NC 15 IIP2 14 IIN2 13 IIN1 12 IIP1 11 VIN1 10 9 STPM33 VIP1 DS10272 - Rev 12 31 MOSI/RXD 32 MISO/TXD Figure 5. STPM33 pinout (top view), QFN32L 5x5x1 page 4/91 STPM32, STPM33, STPM34 Pin configuration 19 VDDD 20 SYN 21 SCS 22 SCL 23 MOSI/RXD 24 MISO/TXD Figure 6. STPM32 pinout (top view), QFN24L 4x4x1 CLKOUT/ZCR 1 18 CLKIN/XTAL2 2 17 VCC XTAL1 3 LED1 4 LED2 5 14 GNDA INT1 6 13 GND_REF 16 GND_REG 9 10 11 12 VIP1 VIN1 IIP1 IIN1 VREF1 15 VDDA 8 7 STPM32 EN GNDD Table 1. STPM34, STPM33, STPM32 pin description DS10272 - Rev 12 STPM34 STPM33 STPM32 Name 1 1 1 CLKOUT/ZCR 2 2 2 CLKIN/XTAL2 3 3 3 XTAL1 4 4 4 LED1 5 5 5 LED2 6 6 6 INT1 7 7 - INT2 8 8 7 EN 9 9 8 10 10 11 12 Description and multiplexed function -Zero-crossing output Voltage range Functional section From 0 to VCC Multifunctional From 0 to VCC Oscillator From 0 to VCC Oscillator From 0 to VCC Multifunctional From 0 to VCC Multifunctional From 0 to VCC Multifunctional From 0 to VCC Multifunctional Enable pin From 0 to VCC Signal VIP1 Positive voltage primary input From -0.3 V to 0.3 V Signal 9 VIN1 Negative voltage primary input From -0.3 V to 0.3 V Signal 11 10 IIP1 Positive current primary input From -0.3 V to 0.3 V Signal 12 11 IIN1 Negative current primary input From -0.3 V to 0.3 V Signal -System clock output -Input of external clock -External crystal input 2 -External crystal input 1 -Pulse output 1 -Primary current SD bitstream -Pulse output 2 -Secondary current SD bitstream -Interrupt 1 -Primary voltage SD bitstream -Interrupt 2 -Secondary voltage SD bitstream page 5/91 STPM32, STPM33, STPM34 Pin configuration Voltage range Functional section Negative current secondary input From -0.3 V to 0.3 V Signal IIP2 Positive current secondary input From -0.3 V to 0.3 V Signal - VIN2 Negative voltage secondary input From -0.3 V to 0.3 V Signal - - VIP2 Positive voltage secondary input From -0.3 V to 0.3 V Signal 17 17 12 VREF1 Output of voltage reference 1 From 1.16 V to 1.18 V Power 18 18 13 GND_REF Analog ground of VREF - Power 19 19 - VREF2 Output of voltage reference 2 From 1.16 V to 1.18 V Power 20 20 14 GNDA Analog ground (shield) - Power 21 21 15 VDDA Output of voltage regulator 3.0 V Power 22 22 16 GND_REG Ground - Power 23 23 17 VCC Voltage supply From 3.0 V to 3.6 V Power - NC Not connected - - STPM34 STPM33 STPM32 Name 13 13 - IIN2 14 14 - 15 - 16 24 DS10272 - Rev 12 15, 16, 24, 25 Description and multiplexed function 25, 26 26 18 GNDD Digital ground - Power 27 27 19 VDDD Output of voltage regulator 1.2 V Power 28 28 20 SYN Synchronization pin From 0 to VCC SPI/UART 29 29 21 SCS From 0 to VCC SPI/UART 30 30 22 SCL From 0 to VCC SPI 31 31 23 MOSI/RXD From 0 to VCC SPI/UART 32 32 24 MISO/TXD From 0 to VCC SPI/UART Chip-select SPI/UART select SPI clock SPI master OUT slave IN UART RX SPI master IN slave OUT UART TX page 6/91 STPM32, STPM33, STPM34 Absolute maximum ratings 3 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Value Unit -0.3 to 4.2 V -0.3 to VCC+0.3 V -0.7 to 0.7 V Human body model (all pins) ±2 kV Current injection latch-up immunity 100 mA Junction temperature 125 °C -40 to 150 °C VCC DC input voltage VID Any pin input voltage VIA Analog pin input voltage (VIP, VIN, IIP, IIN) ESD ILATCH Tj TSTG Note: Parameter Storage temperature range absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 3. Thermal data Symbol RthJA Note: Parameter Thermal resistance junction-ambient Package Value QFN32L 5x5x1 30 QFN24L 4x4x1 35 Unit °C/W this value is referred to single-layer PCB, JEDEC standard test board. DS10272 - Rev 12 page 7/91 STPM32, STPM33, STPM34 Electrical characteristics 4 Electrical characteristics VCC= 3.3 V, CL= 1 μF between VDDA and GNDA, CL= 4.7 μF between VDDD and GNDD, CL= 1 μF between VCC and GND, CL = 100 nF between VREF1, 2 and GNDREF, FCLK = 16 MHz, TAMB = 25 °C, EN = VCC, SPI/UART not used, unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit General section TOP Operating junction temperature range - -40 - 105 °C VCC Operating supply voltage - 2.95 3.3 3.65 V STPM32 - 4.3 - STPM33 - 5.0 - STPM34 - 5.9 - - 4.5 - - 4.0 - STPM34 ICC Primary channel ON: ENVREF1 = 1, enV1 = enC1 = 1 Operating current Secondary channel OFF: ENVREF2 = 0, enV2 = enC2 = 0 mA STPM34 Primary current channel ON only: ENVREF1 = 1, enV1 = 0, enC1 = 1 Secondary channel OFF: ENVREF2 = 0, enV2 = enC2 = 0 FCLK t_comm Nominal frequency - - 16 - MHz Interface selection timing - 125 - - ns Duty cycle of CLKIN signal - 40 - 60 % Rise time (10% to 90%) of CLKIN signal - - - 3 ns Maximum critical crystal gm - - - 0.46 mA/V Drive level - - 100 - uW Internal capacitance of oscillator inputs - - 4 - pF External Clock Duty cycle t_rise Source(1) Crystal Oscillator(1) Gm_crit_ma x DL COSC_IN Power management (VDDA, VDDD, GNDA, GNDD, GND_REG, EN) VPOR Power-on-reset on VCC - - 2.5 - V ISTBY Standby current consumption EN = GND -