STPTIC-82F1M6

STPTIC Parascan™ tunable integrated capacitor Datasheet - production data Applications ST PT IC • Cellular Antenna open loop tunable matching network in multi-band GSM/WCDMA/LTE mobile phone ST PT IC • Open loop tunable RF filters µQFN Description Flip Chip The ST integrated tunable capacitor, offers excellent RF performance, low power consumption and high linearity required in adaptive RF tuning applications. The fundamental building block of PTIC is a tunable material called Parascan, which is a version of barium strontium titanate (BST) developed by Paratek microwave. Features • High power capability (+36 dBm) • High tuning range (3.5/1) • High quality factor (Q) • High linearity device • Low leakage current • Capacitor bias is DC blocked • Frequency of operation from DC to 3 GHz • 8 values available: 1.2 pF, 2.7 pF, 3.3 pF, 3.9 pF, 4.7 pF, 5.6 pF, 6.8 pF and 8.2 pF BST capacitances are tunable capacitances intended for use in mobile phone application, and dedicated to RF tunable applications. These tunable capacitances are controlled through a bias voltage ranging from 2 to 20 V. The use of BST tunable capacitance in mobile phones enables significant improvement in terms of radiated performances making the performance almost insensitive to the external environment. • Analog control voltage • Compatible with high voltage control IC (STHVDAC series) • Available in plastic molded package: – µQFN package 1.2 x 1.6 x 0.9 mm – Flip Chip 0.65 x 1.0 x 0.3 mm – Flip Chip 0.65 x 1.2 x 0.3 mm • ECOPACK®2 compliant component Benefit • RF tunable passive implementation in mobile phones to optimize antenna radiated performances. February 2015 This is information on a product in full production. TM: Parascan is a trade mark of Paratek microwave Inc. DocID023772 Rev 4 1/13 www.st.com Functional characteristics 1 STPTIC Functional characteristics Figure 1. PTIC functional block diagram DC Bias A1 A2 NC RF2 B1 B2 RF1 RF2 C1 C2 RF1 Table 1. Signal descriptions 2/13 Ball/Pad number Pin name A1 DC BIAS DC bias voltage B1 RF2 RF input / output C1 RF2 RF input / output A2 NC Not connected B2 RF1 RF input / output C2 RF1 RF input / output DocID023772 Rev 4 Description STPTIC 2 Electrical characteristics Electrical characteristics Table 2. Absolute maximum ratings (limiting values) Symbol PIN Parameter Input peak power RFIN (CW mode)/all RF ports VESD(HBM) Human body model, JESD22-A114-B, all I/O VESD(MM) Rating Unit +36 dBm STPTIC-12 500 STPTIC-27 400(1) STPTIC-33 400(1) STPTIC-39 500 STPTIC-47 500 STPTIC-56 500 STPTIC-68 500 STPTIC-82 500 V Machine model, JESD22-A114-B, all I/O 100 V Tdevice Device temperature +125 Tstg Storage temperature -55 to +150 Vx Bias voltage °C 25 V 1. Currently failing around 400 V, improvement on going to withstand 500 V on 2p7 and 3p3. Table 3. Recommended operating conditions Rating Symbol Parameter Unit Min. PIN RF input power (50% duty cycle mode) RFIN (LB) RFIN (HB) FOP Operating frequency Tdevice Device temperature TOP Vx 700 Typ. Max. +35 +33 dBm 3000 MHz +100 °C Operating temperature Bias voltage DocID023772 Rev 4 -30 +85 2 20 V 3/13 13 Electrical characteristics STPTIC Table 4. Representative performances (Tamb = 25 °C) Value Symbol C2V Parameter Conditions Unit Min Typ Max STPTIC-12 1.08 1.20 1.32 pF STPTIC-27 2.43 2.7 2.97 pF STPTIC-33 2.97 3.3 3.63 pF STPTIC-39 3.51 3.9 4.29 pF STPTIC-47 4.23 4.7 5.17 pF STPTIC-56 5.04 5.6 6.16 pF STPTIC-68 6.12 6.8 7.48 pF STPTIC-82 7.38 8.2 9.02 Capacitance at 2V bias IL Leakage current Measured with Vbias = 20 V ΔC Tuning range Ratio between C 2V/C20V measured at 100 kHz QLB Quality factor Measured at 900 MHz 65 QHB Quality factor Measured at 1800 MHz 45 V(1) 60 dBm Vbias = 20 V(1) and (3) 70 dBm V(2) -65 dBm -65 dBm -45 dBm Vbias = 20 V(2) and (3) -45 dBm (4) 135 µs 100 µs IP3 H2 Third order intercept point Second harmonic Vbias = 2 Vbias = 2 Vbias = 20 H3 tT Third harmonic Transition time Vbias = 2 and and V(2) V(2) (3) (3) (3) From C min to Cmax From C max to 3/1 (3) and and 100 Cmin(4) 3.5/1 1. F1 = 894 MHz, F2 = 849 MHz, P1 = 20 dBm, P2 = -15 dBm, 2f1 - f2 = 939 MHz 2. 894 MHz, P in = 34 dBm 3. IP3 and harmonics are measured in the shunt/series configuration in a 50 Ω environment 4. One or both of RFin and RFout must be connected to DC ground 4/13 DocID023772 Rev 4 nA STPTIC Package information • Epoxy meets UL94, V0 • Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 2. µQFN-6L package dimension 1.2 mm ± 0.05 mm 0.7 mm A2 B2 B1 C2 C1 0.425 mm 0.9 mm ± 0.1 mm C2 A1 0.5 mm 27 1.6 mm ± 0.05 mm 3 Package information C1 0.25 mm ± 0.03 mm 0.35 mm ± 0.03 mm Figure 3. Recommended PCB land pattern for µQFN-6L package 600 µm Bias NC NC RF2 RF1 RF2 RF1 300 µm 200 µm Solder mask opening 250 µm Top Metal 300 µm DocID023772 Rev 4 550 µm 5/13 13 Package information STPTIC Figure 4. Flip Chip dimensions (size for 1p5) 200 ± 20 µm 190 µm 780 ± 30 µm 400 µm 190 µm UBM pads 160 x 100 µm 660 ± 30 µm 440 µm 300 ± 40 µm 110 µm 110 µm Figure 5. Flip Chip dimensions (size for 2p7, 3p3, 3p9, and 4p7) 200 ± 20 µm 360µm 500µm 1000 ± 30 µm 140µm UBM pads 160 x 100 µm 650 ± 30 µm 440 µm 105 µm 290 ± 30 µm 105 µm Figure 6. Flip Chip dimensions (size for 5p6, 6p8, 8p2) UBM pads 160 x 100 µm 650 ± 30 µm 200 ± 20 µm 1200 ± 30 µm 140 µm 350 µm 350 µm 360 µm 440 µm 290 ± 30 µm 105 µm 105 µm 6/13 DocID023772 Rev 4 STPTIC Package information Figure 7. Recommended PCB land pattern for Flip Chip package (metal defined pads, solder mask 25 µm larger) 225 µm 250 x 230 µm 200 x 180 µm 250 x 500 µm 170 µm 200 x 750 µm Solder mask Metal defined pads 260 µm Figure 8. Recommended PCB land pattern for Flip Chip PTIC (die size 650 x 1200) 250 x 230 µm PTIC die size 650 X 1200 µm 250 x 800 µm Solder mask Metal defined pads DocID023772 Rev 4 7/13 13 Package information STPTIC Figure 9. µQFN-6L tape and reel specification Dot identifying bump A1 location Ø 1.55 2.0 1.75 4.0 8.0 3.5 1.85 0.25 27 27 27 4.0 1.45 1.05 User direction of unreeling Typical dimensions in mm Figure 10. Flip Chip tape and reel specification A1 location Ø 1.55 2.0 4.0 8.0 A0 3.5 1.75 0.25 0.36 0.76 2.0 User direction of unreeling Typical dimensions in mm A0 = 1.12 mm for 2n7, 3p3, 3p9, and 4p7 A0 = 1.32 mm for 5p6, 6p8, and 8p2 8/13 DocID023772 Rev 4 STPTIC Package information Figure 11. µQFN marking 27 Figure 12. Flip Chip marking (bump side view) Die identifier On bump side 2 1 DIE A B C DocID023772 Rev 4 9/13 13 Reflow profile 4 STPTIC Reflow profile Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Table 5. Recommended values for soldering reflow Value Profile Temperature gradient in preheat (T = 70-180 °C) Temperature gradient (T = 200-225 °C) Peak temperature in reflow Time above 220 °C Temperature gradient in cooling Time from 50 to 220 °C 10/13 Typical Max. 0.9 °C/s 3 °C/s 2 °C/s 3 °C/s 240-245 °C 260 °C 60 s 90 s -2 to -3 °C/s -6 °C/s 160 to 220 s DocID023772 Rev 4 STPTIC 5 Ordering information Ordering information Figure 14. Ordering information scheme ST PTIC - 27 F 1 M6 STMicroelectronics Parascan tunable integrated capacitor Capacitor value 27 = 2.7 pF Design version Tolerance 1 = ± 10% Package M6 = µQFN-6L H5 = Flip Chip Table 6. Ordering information Part Number Marking Weight Base Qty Delivery Mode STPTIC-12F1M6 12 4.8 mg 3000 Tape and reel STPTIC-27F1M6 27 4.8 mg 3000 Tape and reel STPTIC-33F1M6 33 4.8 mg 3000 Tape and reel STPTIC-39F1M6 39 4.8 mg 3000 Tape and reel STPTIC-47F1M6 47 4.8 mg 3000 Tape and reel STPTIC-56F1M6 56 4.8 mg 3000 Tape and reel STPTIC-68F1M6 68 4.8 mg 3000 Tape and reel STPTIC-82F1M6 82 4.8 mg 3000 Tape and reel STPTIC-12G1H5 TBD 0.7 mg 15000 Tape and reel STPTIC-27G1H5 I1x 0.7 mg 15000 Tape and reel STPTIC-33G1H5 I3x 0.7 mg 15000 Tape and reel STPTIC-39G1H5 I2x 0.7 mg 15000 Tape and reel STPTIC-47G1H5 I5x 0.7 mg 15000 Tape and reel STPTIC-56G1H5 I4x 0.7 mg 15000 Tape and reel STPTIC-68G1H5 I7x 0.7 mg 15000 Tape and reel STPTIC-82G1H5 I6x 0.7 mg 15000 Tape and reel DocID023772 Rev 4 11/13 13 Revision history 6 STPTIC Revision history Table 7. Document revision history 12/13 Date Revision Changes 02-Nov-2012 1 Initial release. 03-Jul-2013 2 Removed 6-pad 650 x 1000 Flip-Chip package. 10-Jan-2014 3 updated: Features, Table 2, Table 4, Table 6 and added new Figure 4. 13-Feb-2014 4 Updated Applications. DocID023772 Rev 4 STPTIC IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID023772 Rev 4 13/13 13