STQ2LN60K3-AP

STQ2LN60K3-AP N-channel 600 V, 4 Ω typ., 0.6 A MDmesh™ K3 Power MOSFET in a TO-92 package Datasheet - production data Features Order code VDS RDS(on) max ID PTOT STQ2LN60K3-AP 600 V 4.5 Ω 0.6 A 2.5 W     3 2 1 TO-92 ammopack  Figure 1: Internal schematic diagram 100% avalanche tested Extremely high dv/dt capability Very low intrinsic capacitance Improved diode reverse recovery characteristics Zener-protected Applications D(2)  Switching applications Description This MDmesh™ K3 Power MOSFET is the result of improvements applied to STMicroelectronics’ MDmesh™ technology, combined with a new optimized vertical structure. This device boasts an extremely low on-resistance, superior dynamic performance and high avalanche capability, rendering it suitable for the most demanding applications. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STQ2LN60K3-AP 2LN60K3 TO-92 Ammopack February 2017 DocID023499 Rev 3 This is information on a product in full production. 1/13 www.st.com Contents STQ2LN60K3-AP Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 4.1 5 2/13 TO-92 ammopack package information .......................................... 10 Revision history ............................................................................ 12 DocID023499 Rev 3 STQ2LN60K3-AP 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 600 V VGS Gate-source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 0.6 A ID Drain current (continuous) at TC = 100 °C 0.38 A Drain current (pulsed) 2.4 A Total dissipation at TC = 25 °C 2.5 W Peak diode recovery voltage slope 12 V/ns -55 to 150 °C Value Unit IDM (1) PTOT (2) dv/dt Tstg Tj Storage temperature range Operating junction temperature range Notes: (1)Pulse (2)I SD width limited by safe operating area. ≤ 2 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 50 °C/W Rthj-amb Thermal resistance junction-ambient 120 °C/W Value Unit Table 4: Avalanche characteristics Symbol Parameter IAS Single pulse avalanche current (pulse width limited by Tjmax) 2 A EAS Single pulse avalanche energy (starting TJ=25 °C, ID=IAR, VDD=50 V) 80 mJ DocID023499 Rev 3 3/13 Electrical characteristics 2 STQ2LN60K3-AP Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 5: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V IDSS Zero gate voltage drain current IGSS Min. Typ. Max. 600 V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, TC= 125 °C (1) 50 Gate-body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 1 A Unit µA ±10 µA 3.75 4.5 V 4 4.5 Ω Min. Typ. Max. Unit - 235 - pF - 22 - pF - 3.5 - pF - 14 - pF - 10 - 12 - nC - 1.8 - nC - 7.7 - nC - 7 - Ω 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Co(er)(2) Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 V Eq. capacitance time related Eq. capacitance energy related VGS = 0 V, VDS = 0 to 480 V Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 480 V, ID = 1 A, VGS = 0 to 10 V (see Figure 16: "Test circuit for gate charge behavior") RG Gate input resistance f=1 MHz, ID=0 A pF Notes: (1)C oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS (2)C oss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS 4/13 DocID023499 Rev 3 STQ2LN60K3-AP Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 1 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") - 10 - ns - 8.5 - ns - 23.5 - ns - 21 - ns Min. Typ. Max. Unit 0.6 A Table 8: Source-drain diode Symbol Parameter Test conditions ISD(1) Source-drain current - ISDM(1) Source-drain current (pulsed) - VSD(2) Forward on voltage ISD = 2 A, VGS = 0 V - ISD = 2 A, di/dt = 100 A/µs VDD = 60 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 200 ns - 800 nC - 8 A ISD = 2 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 230 ns - 950 nC - 8.5 A Min. Typ. Max. Unit 30 - - V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 2.4 1.5 A V Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ±1 mA, ID= 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID023499 Rev 3 5/13 Electrical characteristics 2.1 STQ2LN60K3-AP Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics AM13054v1 ID (A) VGS=10V AM13055v1 ID (A) VDS=15V 2.5 2.0 2.0 6V 1.5 1.5 1.0 1.0 0.5 0.5 5V 0 0 2 4 8 6 Figure 6: Gate charge vs gate-source voltage VGS (V) AM13056v1 VDS VDD=480V ID=2A 12 (V) 500 VDS 10 0 0 VDS(V) 400 8 2 4 8 6 VGS(V) Figure 7: Static drain-source on-resistance AM13057v1 RDS(on) (W) VGS=10V 4.2 4.0 3.8 300 3.6 6 200 4 100 2 0 0 6/13 5 10 0 Qg(nC) 3.4 3.2 3.0 DocID023499 Rev 3 0 0.2 0.4 0.6 0.8 1.0 1.2 ID(A) STQ2LN60K3-AP Electrical characteristics Figure 8: Capacitance variations Figure 9: Source-drain diode forward characteristics AM13063v1 AM13058v1 C (pF) VSD (V) TJ=-50°C 0.9 TJ=25°C Ciss 0.8 0.7 100 TJ=150°C 0.6 0.5 0.4 10 Coss Crss 0.3 0.2 0.1 1 0.1 1 100 10 Figure 10: Normalized gate threshold voltage vs temperature AM13060v1 VGS(th) (norm) 0 VDS(V) 0 1 4 5 ISD(A) Figure 11: Normalized on-resistance vs temperature AM13061v1 RDS(on) (norm) ID=50µA 3 2 ID=1A VGS=10V 1.10 2.5 2.0 1.00 1.5 0.90 1.0 0.80 0.5 0.70 -75 -25 25 75 125 Figure 12: Normalized V(BR)DSS vs temperature AM13062v1 V(BR)DSS (norm) 0 -75 TJ(°C) ID=1mA 1.10 -25 25 75 125 TJ(°C) Figure 13: Output capacitance stored energy AM13059v1 Eoss (µJ) 1.5 1.05 1 1.00 0.5 0.95 0.90 -75 -25 25 75 125 TJ(°C) DocID023499 Rev 3 0 0 100 200 300 400 500 600 VDS(V) 7/13 Electrical characteristics STQ2LN60K3-AP Figure 14: Maximum avalanche energy vs temperature AM13064v1 EAS(mJ) 90 ID=2 A VDD=50 V 80 70 60 50 40 30 20 10 0 0 8/13 20 40 60 80 100 120 140 TJ(°C) DocID023499 Rev 3 STQ2LN60K3-AP 3 Test circuits Test circuits Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID023499 Rev 3 9/13 Package information 4 STQ2LN60K3-AP Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-92 ammopack package information Figure 21: TO-92 ammopack package outline T A1 T2 H1 T1 delta H H H3 H0 d L W2 l1 W W0 W1 F1 F2 F3 P2 D0 t P0 0050910_Rev_22 10/13 DocID023499 Rev 3 STQ2LN60K3-AP Package information Table 10: TO-92 ammopak mechanical data mm Dim. Min. Typ. Max. A1 4.80 T 3.80 T1 1.60 T2 2.30 d 0.45 0.47 0.48 P0 12.50 12.70 12.90 P2 5.65 6.35 7.05 F1, F2 2.40 2.50 2.94 F3 4.98 5.08 5.48 delta H -2.00 W 17.50 18.00 19.00 W0 5.50 6.00 6.50 W1 8.50 9.00 9.25 18.50 21.00 16.00 18.20 25.00 27.00 2.00 W2 0.50 H H0 15.50 H1 H3 0.50 1.00 2.00 D0 3.80 4.00 4.20 t 0.90 L 11.00 I1 3.00 delta P -1.00 DocID023499 Rev 3 1.00 11/13 Revision history 5 STQ2LN60K3-AP Revision history Table 11: Document revision history 12/13 Date Revision Changes 19-Jul-2012 1 First release. 24-Jan-2017 2 Modified title, features and description on cover page Modified Table 2: "Absolute maximum ratings", Table 5: "On/off states" and Table 9: "Gate-source Zener diode" Modified: Figure 11: "Normalized on-resistance vs temperature" Updated Section 4.1: "TO-92 ammopack package information" Minor text changes 01-Feb-2017 3 Modified Figure 2: "Safe operating area". Minor text changes. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID023499 Rev 3 13/13