STR71xF
ARM7TDMI™ 16/32-BIT MCU WITH FLASH, USB, CAN 5 TIMERS, ADC, 10 COMMUNICATIONS INTERFACES
PRELIMINARY DATA
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Memories – Up to 256+16 Kbytes Flash memory (100,000 cycles endurance, 20 yrs retention) – Up to 64 Kbytes RAM – External Memory Interface (EMI) for up to 4 banks of SRAM, Flash, ROM. – Multi-boot capability Clock, Reset and Supply Management – 3.3V application supply and I/O interface – Internal 1.8V voltage regulator for core supply – 0 to 16 MHz external main oscillator – 32 kHz external backup oscillator – Embedded PLL for CPU clock – Up to 50 MHz CPU operating frequency when executing from Flash – Realtime Clock for clock-calendar function – 4 power saving modes: SLOW, WAIT, STOP and STANDBY modes Nested interrupt controller – Fast interrupt handling with multiple vectors – 32 vectors with 16 IRQ priority levels – 2 maskable FIQ sources Up to 48 I/O ports – 30/32/48 multifunctional bidirectional I/O lines – 14 ports with interrupt capability 5 Timers – 16-bit watchdog timer – 4 16-bit timers with: 2 input captures, 2 output compares, PWM and pulse counter modes
TQFP64 10 x 10
TQFP144 20 x 20
LFBGA64 8 x 8 x 1.7 LFBGA64 8 x 8 x 1.7
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LFBGA144 10 x 10 x 1.7
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10 Communications Interfaces – 2 I2C interfaces (1 multiplexed with SPI) – 4 UART asynchronous serial interfaces – Smart Card ISO7816-3 interface on UART1 – 2 BSPI synchronous serial interfaces – CAN interface (2.0B Active) – USB v 2.0 Full Speed (12Mbit/s) Device Function with Suspend and Resume support – HDLC synchronous communications 4-channel 12-bit A/D Converter – Conversion time: – 4 channels: up to 500 Hz (2 ms) – 1 channel: up to 1 kHz (1 ms) – Conversion range: 0 to 2.5V Development Tools Support – JTAG with debug mode trigger request
Table 1. Device Summary
Features FLASH - Kbytes RAM - Kbytes Peripheral Functions Operating Voltage Operating Temp. Packages T=TQFP144 20 x 20 H=LFBGA144 10 x10 STR710FZ 1 2 128+16 256+16 32 64 CAN, EMI, USB, 48 I/Os STR711FR STR712FR 0 1 2 0 1 2 64+16 128+16 256+16 64+16 128+16 256+16 16 32 USB, 30 I/Os 64 16 32 CAN, 32 I/Os 64 STR715FR 0 64+16 16 32 I/Os
3.0 to 3.6V (optional 1.8V for core) -40 to +85°C T=TQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7
Rev. 6
April 2005 1/49
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 Pin Description for 144-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 Pin Description for 64-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5 External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.7 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 LVD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6 nRSTIN Input Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 Oscillator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.8 PLL Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.9 Flash Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.10 External Memory Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.11 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 ORDER CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Note: For detailed information on the STR71xF Microcontroller memory, registers and peripherals. please refer to the STR71xF Reference Manual.
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1
STR71xF - INTRODUCTION
1 INTRODUCTION
This Preliminary Data provides the STR71x Ordering Information, Mechanical and Electrical Device Characteristics. For complete information on the STR71xF Microcontroller memory, registers and peripherals. please refer to the STR71xF Reference Manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference Manual. 1.1 Overview ARM® core with embedded Flash & RAM The STR71xF series is a family of ARM-powered 16/32-bit Microcontrollers with embedded Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. The STR71xF family has an embedded ARM core and is therefore compatible with all ARM tools and software. For information on the ARM Realview Developer Kit for ST and third-party development tools, please refer to the http://www.st.com website Package Choice: Low Pin-Count 64-pin or Feature-Rich 144-pin TQFP or BGA The STR71xF family is available in 4 main versions. The 144-pin versions have the full set of all features including CAN, USB and External Memory Interface.
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STR710F: 144-pin BGA or TQFP with CAN, USB and EMI
The three 64-pin versions (BGA or TQFP) do not include External Memory Interface.
• • •
STR715F: 64-pin BGA or TQFP without CAN or USB STR711F: 64-pin BGA or TQFP with USB STR712F: 64-pin BGA or TQFP with CAN
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1
STR71xF - INTRODUCTION
Optional External Memory (STR710F) The non-multiplexed 16-bit data/24-bit address bus available on the STR710F (144-pin) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Figure 1 shows the general block diagram of the device family. Flexible Power Management To minimize power consumption, you can program the STR71xF to switch to SLOW, WAIT FOR INTERRUPT, STOP or STANDBY mode depending on the current system activity in the application. Flexible Clock Control Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 50 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. Voltage Regulators The STR71xF requires an external 3.0-3.6V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is switched off and the Low Power VR switched on when the application puts the STR71xF in Standby or Low Power Wait for Interrupt (LPWFI) mode. Low Voltage Detectors Each voltage regulator has an embedded LVD that monitors the internal 1.8V supply. If the voltage drops below a certain threshold, the LVD will reset the STR71xF. On-Chip Peripherals CAN Interface (STR710F and STR712F) The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. USB Interface (STR710F and STR711F) The full-speed USB interface is USB V2.0 compliant and provides up to 8 bidirectional/16 unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer and USB Suspend/Resume functions.
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1
STR71xF - INTRODUCTION
Standard Timers Each of the four timers have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. Realtime Clock (RTC) The RTC provides a set of continuously running counters driven by a low power 32kHz internal oscillator. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR71xF is in Standby mode the RTC can be kept running, powered by the low power voltage regulator and driven by the 32kHz internal oscillator. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 625 kb/s. Smart Card Interface UART1 is configurable to function either as a general purpose UART or as an asynchronous Smart Card interface as defined by ISO 7816-3. It includes Smart Card clock generation and provides support features for synchronous cards. Buffered Serial Peripheral Interfaces (BSPI) Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5Mb/s in Master mode and 4 Mb/s in Slave mode. I2C Interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may be used at a time. HDLC interface The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ, NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator. A/D Converter The Analog to Digital Converter, converts in single channel or up to 4 channels in single-shot or continuous conversion modes. Resolution is 12-bit with a sample rate of 0.5 kHz (1 kHz in single channel mode). The input voltage range is 0-2.5V.
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STR71xF - INTRODUCTION
Watchdog The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O Ports The 48 I/O ports are programmable as Inputs or Outputs. External Interrupts Up to 14 external interrupts are available for application use or to wake-up the application from STOP mode.
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STR71xF - INTRODUCTION
Figure 1. STR71xF Block Diagram
A[19:0] D[15:0] RDN WEN[1:0]
A[23:20] CS[3:0)
CK CKOUT RSTIN
PRCCU/PLL
EXT. MEM. INTERFACE (EMI) FLASH MEMORY 64/128/256K 16K RWW FLASH RAM 16/32/64K APB BRIDGE 1
ARM7TDMI CPU JTDI JTCK JTMS JTRST JTDO DBGRQS BOOTEN
ARM7 NATIVE BUS
JTAG
V18[1:0] V33[6:0] VSS[9:0] V18BKP AVDD AVSS
POWER SUPPLY VREG
APB BRIDGE 2 I2C0 2 AF 2 AF 4 AF 4 AF 2 AF 3 AF 2 AF 2 AF 3 AF USBDP USBDN 1 AF
INTERRUPT CTL(EIC) 4 AF A/D TIMER0 4 AF 2 AF 4 AF OSC 14 AF TIMER1
APB BUS
I2C1 BSPI0 BSPI1 UART0 UART1 / SMART CARD UART2 UART3 HDLC
TIMER2 TIMER3 RTC
APB BUS
STDBY RTCXTO RTCXTI WAKEUP
EXT INT (XTI) WATCHDOG
USB P0[15:0] P1[15:0] P2[15:0] I/O PORT 0 I/O PORT 1 CAN I/O PORT 2
2 AF
AF: alternate function on I/O port pin
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STR71xF - INTRODUCTION
1.2 Related Documentation Available from www.arm.com: ARM7TDMI Technical Reference Manual Available from http://www.st.com: STR71x Reference Manual STR7 Flash Programming Reference Manual AN1774 - Getting Started with STR71xF Software development AN1775 - Getting Started with STR71xF Hardware development AN1776 - STR71xF Enhanced Interrupt Controller AN1777 - STR71xF Memory Mapping AN1778 - STR71xF Multi-ICE Setup AN1780 - Real Time Clock with STR71xF AN1781 - Four 7 Segment Display Drive Using the STR71xF The above is a selected list only, a full list STR71x application notes can be viewed at http://www.st.com.
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STR71xF - INTRODUCTION
1.3 Pin Description for 144-Pin Packages Figure 2. STR710 TQFP Pinout
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V33 WEn.0 WEn.1 A.19 A.18 A.17 A.16 A.15 A.14 V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX A.13 A.12 A.11 A.10 A.9 A.8 A.7 A.6 A.5 V33 VSS P1.15/HTXD N.C. N.C. P0.10/U1.RX/U1.TX/SCDATA RDn P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS V33 P2.0/CSn.0 P2.1/CSn.1 P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA P2.2/CSn.2 P2.3/CSn.3 P2.4/A.20 P2.5/A.21 P2.6/A.22 BOOTEN P2.7/A.23 P2.8 N.C. N.C. VSS V33 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 JTDI JTMS JTCK JTDO JTRSTn NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TQFP144
P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 V33 VSS A.4 A.3 A.2 A.1 A.0 D.15 D.14 D.13 D.12 D.11 D.10 USBDN USBDP P1.12/CANTX P1.11/CANRX N.C. P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL D.9 D.8 D.7 D.6 D.5 P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2
N.C. TEST N.C. V33IO-PLL N.C. VSSIO-PLL N.C. DBGRQS CKOUT CK P0.15/WAKEUP N.C. RTCXTI RTCXTO STDBYn RSTINn N.C. VSSBKP V18BKP N.C. N.C. V18 VSS18 N.C. D.0 D.1 D.2 D.3 D.4 AVDD AVSS N.C. N.C. N.C. P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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STR71xF - INTRODUCTION
Table 2. STR710 BGA Ball Connections
A 1 2 3 4 5 6 7 8 9 10 11 12 P0.10 VSS V33 P0.6 A.19 P0.3 P0.2 A.9 VSS A.8 A.7 A.12 B P2.0 RDn P0.9 P0.7 WEn.1 A.15 P0.1 A.10 V33 N.C. N.C. A.4 C P2.1 P0.11 P0.12 P0.8 WEn.0 A.16 P0.4 A.11 A.5 P1.15 P1.14 A.3 D VSS V33 P0.13 P0.14 P0.5 A.17 VSS18 A.13 A.6 P1.13 P1.10 P1.9 E P2.2 P2.3 P2.4 P2.5 P2.7 A.18 V18 P0.0 V33 VSS A.2 A.1 F P2.6 P2.8 VSS N.C. N.C. V33 A.14 A.0 D.15 D.14 D.13 N.C. G BOOT EN P2.9 P2.10 P2.11 P2.14 V18 D.12 H P2.12 JTMS JTCK JTDO nc N.C. J P2.13 JTRSTn NU CK K P2.15 TEST V33 CKOUT L JTDI TEST N.C. VSSIOPLL nc M N.C. N.C. DBG RQS N.C. P0.15
RTCXRTCXTI TO N.C. D.0 N.C. D.9 D.8 D.5 P1.6 V18BKP nc AVSS P1.0 P1.5 P1.4 D.7
D.1 P1.12/ D.11 CANTX D.10 P1.8 USBDN P1.7 USBDP VSS P1.11/ V33IOCANRX PLL
VSS STDBYn BKP VSS18 RSTINn D.3 N.C. P1.1 P1.3 D.6 D.2 N.C. D.4 AVDD P1.2
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STR71xF - INTRODUCTION
Legend / Abbreviations for Table 3: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.8V / 2V with input trigger TT= TTL 0.3VDD/0.7VDD with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: – Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100kΩ weak pull-up is enabled. pd = in reset state, the internal 100kΩ weak pull-down is enabled. – Output: OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant.
Table 3. STR710 Pin Description
Active in Stdby Pin n° TQFP144 Type BGA144 Input Reset State1) Input Input Level interrupt Output Capability
OD
PP
Pin Name
Main function (after reset)
Alternate function
UART1: Receive Data input 1 A1 P0.10/U1.RX/ U1.TX/ SC.DATA I/O pd CT X 4mA T Port 0.10
UART1: Transmit data output.
Note: This pin may be used for Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress
2
B2
RD P0.11/ BOOT.1/ U1.TX
O
X
External Memory Interface: Active low read signal for external memory. It maps to the OE_N input of the external components. Port 0.11 Port 0.12 Select Boot Con- UART1: Transmit data figuration input output. Smartcard reference clock output
3 4 5 6
C2 C3 D1 D2
I/O pd CT
4mA X 4mA
X
P0.12/SC.CLK I/O pd CT VSS V33 P2.0/CS.0 S S
Ground voltage for digital I/Os Supply voltage for digital I/Os External Memory Interface: Select Memory Bank 0 output Note: This pin is forced to output mode at reset to allow boot from external memory External Memory Interface: Select Memory Bank 1 output UART2: Receive Data input Timer2: Output Compare A output
7
B1
I/O pu CT pu I/O 2) CT I/O pu CT I/O pu CT pu I/O 2) CT
8mA X
X
Port 2.0
8 9 10 11
C1 D3 D4 E1
P2.1/CS.1 P0.13/U2.RX/ T2.OCMPA P0.14/U2.TX/ T2.ICAPA P2.2/CS.2
8mA X X 4mA X 4mA X 8mA X
X X X X
Port 2.1 Port 0.13 Port 0.14 Port 2.2
UART2: Transmit Timer2: Input Capture A data output input External Memory Interface: Select Memory Bank 3 output
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STR71xF - INTRODUCTION
Table 3. STR710 Pin Description
Active in Stdby Pin n° TQFP144 Type BGA144 Input Reset State1) Input Input Level interrupt Output Capability
OD
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
E2 E3 E4 F1
P2.3/CS.3 P2.4/A.20 P2.5/A.21 P2.6/A.22
pu I/O 2) CT pd I/O 3) CT pd I/O 3) CT pd I/O 3) CT I I/O 3) pd CT CT
PP
Pin Name
Main function (after reset)
Alternate function
8mA X 8mA X 8mA X 8mA X
X X X X
Port 2.3 Port 2.4
External Memory Interface: Select Memory Bank 4 output
Port 2.5 External Memory Interface: address bus Port 2.6 Boot control input. Enables sampling of BOOT[1:0] pins
G1 BOOTEN E5 F2 F4 F5 F3 F6 P2.7/A.23 P2.8 N.C. N.C. VSS V33
8mA X X 4mA X
X X
Port 2.7 External Memory Interface: address bus Port 2.8 External interrupt INT2 Not connected (not bonded) Not connected (not bonded)
I/O pu CT
S S I/O pu CT I/O pu CT I/O pu CT I/O pu CT I/O pu CT I/O pu CT I/O pu CT I I I O I TT TT TT C 8mA X X 4mA X X 4mA X X 4mA X 4mA X 4mA X 4mA X 4mA X X X X X X X X
Ground voltage for digital I/Os Supply voltage for digital I/Os Port 2.9 External interrupt INT3 Port 2.10 Port 2.11 Port 2.12 Port 2.13 Port 2.14 Port 2.15 JTAG Data input. External pull-up required. JTAG Mode Selection Input. External pull-up required. JTAG Clock Input. External pull-up or pull-down required. JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. Reserved, must be forced to ground. Reserved, must be forced to ground. Not connected (not bonded) Reserved, must be forced to ground. Not connected (not bonded) External interrupt INT4 External interrupt INT5
G2 P2.9 G3 P2.10 G4 P2.11 H1 J1 P2.12 P2.13
G5 P2.14 K1 L1 H2 H3 H4 J2 J3 K2 L3 L2 P2.15 JTDI JTMS JTCK JTDO JTRST NU TEST N.C. TEST
M1 N.C.
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STR71xF - INTRODUCTION
Table 3. STR710 Pin Description
Active in Stdby Pin n° TQFP144 Type BGA144 Input Reset State1) Input Input Level interrupt Output Capability
OD
PP
Pin Name
Main function (after reset)
Alternate function
40 41 42 43 44 45 46 47 48 49 50
K3
V33IO-PLL
S
Supply voltage for digital I/O circuitry and for PLL reference Not connected (not bonded) Ground voltage for digital I/O circuitry and for PLL reference Not connected (not bonded) CT 8mA C pu TT X 4mA X X Debug Mode request input (active high) Clock output (fPCLK2) Note: Enabled by CKDIS register in APB Bridge 2 Reference clock input Port 0.15 Wakeup from Standby mode input.
M2 N.C. L4 VSSIO-PLL S
M4 N.C. M3 DBGRQS K4 J4 CKOUT CK I O I I
P0.15/WAKEM5 UP L5 K5 J5 N.C. RTCXTI RTCXTO
Not connected (not bonded) Realtime Clock input and input of 32 kHz oscillator amplifier circuit Output of 32 kHz oscillator amplifier circuit Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode.
51
M6 STDBY
I/O
CT
4mA X
Output: Standby mode active low output following SoftX ware Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby
52 53 54
M7 RSTIN J6 L6 N.C. VSSBKP
I
CT S
X Reset input Not connected (not bonded) X Stabilisation for low power voltage regulator. Stabilisation for low power voltage regulator. Requires external capacitors of at least 1µF between V18BKP and X VSS18BKP. See Figure 5. Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. Not connected (not bonded) Not connected (not bonded) Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. Stabilisation for main voltage regulator. Not connected (not bonded)
55
K6
V18BKP
S
56 57 58 59 60
H5 H6
N.C. N.C. S S
G6 V18 L7 K7 VSS18 N.C.
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STR71xF - INTRODUCTION
Table 3. STR710 Pin Description
Active in Stdby Pin n° TQFP144 Type BGA144 Input Reset State1) Input Input Level interrupt Output Capability
OD
61 62 63 64
J7 H7 L8
D.0 D.1 D.3
I/O I/O I/O I/O I/O S S
8mA 8mA 8mA 8mA 8mA Supply voltage for A/D Converter Ground voltage for A/D Converter Not connected (not bonded) Not connected (not bonded) Not connected (not bonded) Timer 3: Output Compare B External Memory Interface: data bus
M8 D.2
65 M10 D.4 66 M11 VDDA 67 68 69 70 71 K8 J8 L9 VSSA N.C. N.C. P1.0/T3.OCMPB/AIN.0
M9 N.C. K9 I/O pu CT I/O pu CT 4mA X 4mA X 4mA X 4mA X X X X X
PP
Pin Name
Main function (after reset)
Alternate function
Port 1.0
ADC: Analog input 0
P1.1/T3.ICA72 L10 PA/T3.EXTCLK/AIN.1 73 M12
Timer 3: Input Port 1.1 Capture A or Ex- ADC: Analog input 1 ternal Clock input Port 1.2 Port 1.3 Timer 3: Output Compare A Timer 3: Input Capture B Timer 1: Input Capture A Timer 1: Input Capture B Timer 1: Output Compare B ADC: Analog input 2 ADC: Analog input 3 Timer 1: External Clock input
P1.2/T3.OCMI/O pu CT PA/AIN.2 I/O pu CT
P1.3/ 74 L11 T3.ICAPB/ AIN.3 P1.4/T1.ICA75 K11 PA/T1.EXTCLK 76 K10 77 J12 P1.5/ T1.ICAPB P1.6/T1.OCMPB
I/O pu CT I/O pu CT I/O pu CT I/O I/O I/O I/O I/O S S
4mA X 4mA X 4mA X 8mA 8mA 8mA 8mA 8mA
X X X
Port 1.4 Port 1.5 Port 1.6
78 J11 D.5 79 L12 D.6 80 K12 D.7 81 J10 D.8 82 J9 D.9
External Memory Interface: data bus
83 H12 V33IO-PLL 84 H11 VSSIO-PLL 85 H10 86 H9
Supply voltage for digital I/O circuitry and for PLL reference Ground voltage for digital I/O circuitry and for PLL reference 4mA X 4mA X X X Port 1.7 Port 1.8 Not connected (not bonded) Timer 1: Output Compare A
P1.7/T1.OCMI/O pu CT PA P1.8 I/O pd CT
87 F12 N.C.
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STR71xF - INTRODUCTION
Table 3. STR710 Pin Description
Active in Stdby Pin n° TQFP144 Type BGA144 Input Reset State1) Input Input Level interrupt Output Capability
OD
PP
Pin Name
Main function (after reset)
Alternate function
88 G12 P1.11/CANRX 89 H8 P1.12/CANTX
I/O pu CT X 4mA X I/O pu CT X 4mA X
X X
Port 1.11 Port 1.12
CAN: receive data input Note: On STR710 and STR712 only CAN: Transmit data output Note: On STR710 and STR712 only
USB bidirectional data (data +). Reset state = HiZ 90 G11 USBDP I/O CT Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA Ground voltage for digital I/O circuitry Supply voltage for digital I/O circuitry 4mA X 4mA X X X X X Port 1.9 Port 1.10 Port 1.13 Port 1.14 USB: 48 MHZ clock input HDLC: reference clock input HDLC: Receive data input I2C clock I2C serial data External Memory Interface: address bus External Memory Interface: data bus
91 G10 USBDN 92 93 94 G9 D.10 G8 D.11 G7 D.12
I/O I/O I/O I/O I/O I/O I/O O O O O O S S
CT
95 F11 D.13 96 F10 D.14 97 98 F9 F8 D.15 A.0
99 E12 A.1 100 E11 A.2 101 C12 A.3 102 B12 A.4 103 E10 VSS 104 E9 V33 P1.10/USBCLK P1.13/HCLK/ I0.SCL P1.14/HRXD/ I0.SDA 105 D12 P1.9 106 D11 107 D10 108 C11
I/O pd CT I/O pu C/T
I/O pu CT X 4mA X I/O pu CT X 4mA X
109 B11 N.C. 110 B10 N.C. 111 C10 P1.15/HTXD 112 A9 113 B9 VSS V33 I/O pu CT X 4mA X S S X
Not connected (not bonded) Not connected (not bonded) Port 1.15 HDLC: Transmit data output
Ground voltage for digital I/O circuitry Supply voltage for digital I/O circuitry
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STR71xF - INTRODUCTION
Table 3. STR710 Pin Description
Active in Stdby Pin n° TQFP144 Type BGA144 Input Reset State1) Input Input Level interrupt Output Capability
OD
114 C9 115 D9
A.5 A.6
O O O O O O O O O
8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA SPI0 Master in/ Slave out data 4mA X X UART3 Transmit data output External Memory Interface: address bus
116 A11 A.7 117 A10 A.8 118 A8 119 B8 120 C8 122 D8 A.9 A.10 A.11 A.13
121 A12 A.12
123 E8
P0.0/S0.MISO/ I/O pu CT U3.TX
PP
Pin Name
Main function (after reset)
Alternate function
Port 0.0 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master out/Slave in data UART3: Receive Data input
124 B7
P0.1/S0.MOSI/ I/O pu CT X 4mA X U3.RX
X
Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Serial Clock I2C1: Serial clock
125 A7
P0.2/ S0.SCLK/ I1.SCL
I/O pu CT X 4mA X
X
Port 0.2 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data
126 A6
P0.3/S0.SS/ I1.SDA
I/O pu CT
4mA X
X
Port 0.3
Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.
127 C7 128 D7 129 E7 130 F7 131 B6 132 C6 133 D6 134 E6 135 A5
P0.4/S1.MISO VSS18 V18 A.14 A.15 A.16 A.17 A.18 A.19
I/O pu CT S S O O O O O O
4mA X
X
Port 0.4 SPI1: Master in/Slave out data Stabilisation for main voltage regulator. Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5.
8mA 8mA 8mA 8mA 8mA 8mA External Memory Interface: address bus
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STR71xF - INTRODUCTION
Table 3. STR710 Pin Description
Active in Stdby Pin n° TQFP144 Type BGA144 Input Reset State1) Input Input Level interrupt Output Capability
OD
PP
Pin Name
Main function (after reset)
Alternate function
136 B5 137 C5 138 A3 139 A2 140 D5 141 A4 142 B4
WE.1 WE.0 V33 VSS P0.5/S1.MOSI P0.7/S1.SS
O O S S
8mA 8mA
External Memory Interface: active low MSB write enable output External Memory Interface: active low LSB write enable output Supply voltage for digital I/Os Ground voltage for digital I/Os X X X Port 0.5 SPI1: Master out/Slave In data Port 0.6 SPI1: Serial Clock Port 0.7 SPI1: Slave Select input active low Port 0.8 UART0: Receive Data input UART0: Transmit data output.
I/O pu CT 4mA X P0.6/S1.SCLK I/O pu CT X 4mA X I/O pu CT 4mA X
143 C4
P0.8/U0.RX/ U0.TX
I/O pd CT
X 4mA T
Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Con- UART0: Transmit data figuration input output
144 B3
P0.9/U0.TX/ BOOT.0
I/O pd CT
4mA X
1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7, “Port Bit Configuration Table,” on page 26. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,” on page 26) to be used by the External Memory Interface. 3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address 0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,” on page 26).
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STR71xF - INTRODUCTION
1.4 Pin Description for 64-Pin Packages Figure 3. STR712F/STR715F TQFP64 Pinout
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TQFP64
P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10 P1.9 VSS P1.12/CANTX1) P1.11/CANRX1) P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2
1)
CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.
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V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO nSTDBY nRSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
STR71xF - INTRODUCTION
Figure 4. STR711F TQFP64 Pinout
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TQFP64
P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 VSS USBDN USBDP P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2
V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO nSTDBY nRSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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STR71xF - INTRODUCTION
Table 4. STR711F BGA Ball Connections
1 2 3 4 5 6 7 8 A P0.10 P0.9 P0.5 VSS18 P0.2 V33 VSS P1.15 B P0.11 VSS P0.7 VSS P0.4 P0.1 P0.0 P1.14 C P0.12 P0.13 BOOTEN P0.8 V18 P0.3 P1.10 VSS D P0.14 VSS JTDI JTDO P0.6 P1.13 USBDN P1.8 E V33 JTMS NU AVDD P1.9 USBDP P1.7 V33IO-PLL F JTCK JTRSTn STDBYn V18BKP P1.0 VSSIO-PLL P1.6 P1.4 G TEST P0.15 RTCXTI RSTINn V18 AVSS P1.5 P1.3 H V33IO-PLL VSSIO-PLL CK RTCXTO VSSBKP VSS18 P1.1 P1.2
Table 5. STR712F/715F BGA Ball Connections
1 2 3 4 5 6 7 8 A P0.10 P0.9 P0.5 VSS18 P0.2 V33 VSS P1.15 B P0.11 VSS P0.7 VSS P0.4 P0.1 P0.0 P1.14 C P0.12 P0.13 BOOTEN P0.8 V18 P0.3 P1.10 VSS D P0.14 VSS JTDI JTDO P0.6 P1.13 P1.12/ CANTX1) P1.8 E V33 JTMS NU AVDD P1.9 P1.11/ CANRX1) P1.7 V33IO-PLL F JTCK JTRSTn STDBYn V18BKP P1.0 VSSIO-PLL P1.6 P1.4 G TEST P0.15 RTCXTI RSTINn V18 AVSS P1.5 P1.3 H V33IO-PLL VSSIO-PLL CK RTCXTO VSSBKP VSS18 P1.1 P1.2
1)CANTX
and CANRX in STR712F only, in STR715F they are general purpose I/Os.
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STR71xF - INTRODUCTION
Legend / Abbreviations for Table 3: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.8V / 2V with input trigger TT= TTL 0.3VDD/0.7VDD with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: – Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100kΩ weak pull-up is enabled. pd = in reset state, the internal 100kΩ weak pull-down is enabled. – Output: OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant.
Table 6. STR711/STR712/STR715 Pin Description
Active in Stdby Pin n° Type TQFP64 Input Reset State1) Input Input Level interrupt Output Capability
BGA64
OD
PP
Pin Name
Main function (after reset)
Alternate function
UART1: Receive Data input 1 P0.10/U1.RX/ A1 U1.TX/ SC.DATA I/O pd CT X 4mA T Port 0.10
UART1: Transmit data output.
Note: This pin may be used for Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress Select Boot Con- UART1: Transmit data figuration input output. Smartcard reference clock output
2 3 4 5 6 7 8 9
P0.11/ B1 BOOT.1/ U1.TX
I/O pd CT
4mA X 4mA
X
Port 0.11 Port 0.12 Port 0.13 Port 0.14
C1 P0.12/SC.CLK I/O pd CT B2 VSS P0.13/U2.RX/ C2 T2.OCMPA D1 P0.14/U2.TX/ T2.ICAPA S I/O pu CT I/O pu CT I S S I I I O I TT TT TT C CT
Ground voltage for digital I/Os X 4mA X 4mA X X X UART2: Receive Data input Timer2: Output Compare A output
UART2: Transmit Timer2: Input Capture A data output input
C3 BOOTEN D2 VSS E1 V33
Boot control input. Enables sampling of BOOT[1:0] pins Ground voltage for digital I/Os Supply voltage for digital I/Os JTAG Data input. External pull-up required. JTAG Mode Selection Input. External pull-up required. JTAG Clock Input. External pull-up or pull-down required. 8mA X JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. Reserved, must be forced to ground.
10 D3 JTDI 11 E2 JTMS 12 F1 JTCK
13 D4 JTDO 14 F2 JTRST 15 E3 NU
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STR71xF - INTRODUCTION
Table 6. STR711/STR712/STR715 Pin Description
Active in Stdby Pin n° Type TQFP64 Input Reset State1) Input Input Level interrupt Output Capability
BGA64
OD
16 G1 TEST 17 H1 V33IO-PLL 18 H2 VSSIO-PLL 19 H3 CK P0.15/WAKE20 G2 UP 21 G3 RTCXTI 22 H4 RTCXTO S S I I C pu TT X 4mA
PP
Pin Name
Main function (after reset)
Alternate function
Reserved, must be forced to ground. Supply voltage for digital I/O circuitry and for PLL reference Ground voltage for digital I/O circuitry and for PLL reference Reference clock input Port X 0.15 Wakeup from Standby mode input.
Realtime Clock input and input of 32 kHz oscillator amplifier circuit Output of 32 kHz oscillator amplifier circuit Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode.
23
F3 STDBY
I/O
CT
4mA X
Output: Standby mode active low output following SoftX ware Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby
24 G4 RSTIN 25 H5 VSSBKP
I
CT S
X Reset input X Stabilisation for low power voltage regulator. Stabilisation for low power voltage regulator. Requires external capacitors of at least 1µF between V18BKP and X VSS18BKP. See Figure 5. Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. Stabilisation for main voltage regulator. Supply voltage for A/D Converter Ground voltage for A/D Converter 4mA X 4mA X 4mA X 4mA X X X X X Port 1.0 Timer 3: Output Compare B ADC: Analog input 0
26
F4 V18BKP
S
27 G5 V18 28 H6 VSS18 29 E4 VDDA 30 G6 VSSA 31 F5 P1.0/T3.OCMPB/AIN.0
S S S S I/O pu CT I/O pu CT
P1.1/T3.ICA32 H7 PA/T3.EXTCLK/AIN.1 33 H8
Timer 3: Input Port 1.1 Capture A or Ex- ADC: Analog input 1 ternal Clock input Port 1.2 Port 1.3 Timer 3: Output Compare A Timer 3: Input Capture B ADC: Analog input 2 ADC: Analog input 3
P1.2/T3.OCMI/O pu CT PA/AIN.2 I/O pu CT
P1.3/ 34 G8 T3.ICAPB/ AIN.3
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STR71xF - INTRODUCTION
Table 6. STR711/STR712/STR715 Pin Description
Active in Stdby Pin n° Type TQFP64 Input Reset State1) Input Input Level interrupt Output Capability
BGA64
OD
35
P1.4/T1.ICAF8 PA/T1.EXTCLK P1.5/ T1.ICAPB P1.6/T1.OCMPB
PP
Pin Name
Main function (after reset)
Alternate function
I/O pu CT I/O pu CT I/O pu CT S S
4mA X 4mA X 4mA X
X X X
Port 1.4 Port 1.5 Port 1.6
Timer 1: Input Capture A Timer 1: Input Capture B Timer 1: Output Compare B
Timer 1: External Clock input
36 G7 37 F7
38 E8 V33IO-PLL 39 F6 VSSIO-PLL
Supply voltage for digital I/O circuitry and for PLL reference Ground voltage for digital I/O circuitry and for PLL reference 4mA X 4mA X X X X X Port 1.7 Port 1.8 Port 1.11 Port 1.12 CAN: receive data input Note: On STR710 and STR712 only CAN: Transmit data output Note: On STR710 and STR712 only Timer 1: Output Compare A
40 E7
P1.7/T1.OCMI/O pu CT PA I/O pd CT
41 D8 P1.8 42 E6 P1.11/CANRX 43 D7 P1.12/CANTX
I/O pu CT X 4mA X I/O pu CT X 4mA X
USB bidirectional data (data +). Reset state = HiZ 42 E6 USBDP I/O CT Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. Ground voltage for digital I/O circuitry 4mA X 4mA X X X X X X Port 1.9 Port 1.10 Port 1.13 Port 1.14 Port 1.15 USB: 48 MHZ clock input HDLC: reference clock input HDLC: Receive data input I2C clock I2C serial data
43 D7 USBDN 44 C8 VSS 45 E5 P1.9 P1.10/USB46 C7 CLK 47 D6 48 B8 P1.13/HCLK/ I0.SCL P1.14/HRXD/ I0.SDA
I/O S
CT
I/O pd CT I/O pu C/T
I/O pu CT X 4mA X I/O pu CT X 4mA X I/O pu CT X 4mA X S S
49 A8 P1.15/HTXD 50 A7 VSS 51 A6 V33
HDLC: Transmit data output
Ground voltage for digital I/O circuitry Supply voltage for digital I/O circuitry SPI0 Master in/ Slave out data 4mA X X UART3 Transmit data output
52 B7
P0.0/S0.MISO/ I/O pu CT U3.TX
Port 0.0 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.
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STR71xF - INTRODUCTION
Table 6. STR711/STR712/STR715 Pin Description
Active in Stdby Pin n° Type TQFP64 Input Reset State1) Input Input Level interrupt Output Capability
BGA64
OD
PP
Pin Name
Main function (after reset)
Alternate function
53 B6
P0.1/S0.MOSI/ I/O pu CT X 4mA X U3.RX
BSPI0: Master out/Slave in data X
UART3: Receive Data input
Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Serial Clock I2C1: Serial clock
P0.2/ 54 A5 S0.SCLK/ I1.SCL
I/O pu CT X 4mA X
X
Port 0.2 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data
P0.3/S0.SS/ 55 C6 I1.SDA
I/O pu CT
4mA X
X
Port 0.3
Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.
56 B5 P0.4/S1.MISO 57 A4 VSS18 58 C5 V18 59 B4 VSS 60 A3 P0.5/S1.MOSI 62 B3 P0.7/S1.SS
I/O pu CT S S S I/O pu CT I/O pu CT
4mA X
X
Port 0.4 SPI1: Master in/Slave out data Stabilisation for main voltage regulator. Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. Ground voltage for digital I/Os
4mA X 4mA X
X X X
Port 0.5 SPI1: Master out/Slave In data Port 0.6 SPI1: Serial Clock Port 0.7 SPI1: Slave Select input active low Port 0.8 UART0: Receive Data input UART0: Transmit data output.
61 D5 P0.6/S1.SCLK I/O pu CT X 4mA X
63 C4
P0.8/U0.RX/ U0.TX
I/O pd CT
X 4mA T
Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Con- UART0: Transmit data figuration input output
64 A2
P0.9/U0.TX/ BOOT.0
I/O pd CT
4mA X
1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7, “Port Bit Configuration Table,” on page 26. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,” on page 26) to be used by the External Memory Interface.
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STR71xF - INTRODUCTION
3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address 0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,” on page 26).
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STR71xF - INTRODUCTION
1.5 External Connections Figure 5. Recommended External Connection of V18 and V18BKP pins 33 nF 129 128
V18
33 nF 58 57
V18
TQFP144
V18BKP V18
TQFP64
V18BKP V18
54 55 58 59 1µF 10 µF
25 26 27 28 1µF 10 µF
1.6 I/O Port Configuration Table 7. Port Bit Configuration Table
Port Configuration Registers (bit) PC0(n) PC1(n) PC2(n) Configuration Output Input 0 0 0 HiZ/AIN TRI AIN 1 0 0 IN TRI TTL 0 1 0 IN TRI CMOS 1 1 0 IPUPD WP CMOS Values 0 0 1 OUT OD N.A. 1 0 1 OUT PP N.A. 0 1 1 AF OD CMOS 1 1 1 AF PP CMOS
Notes: AF: Alternate Function AIN: Analog Input IPUPD: Input Pull Up /Pull Down CMOS: CMOS Input levels HiZ: High impedance IN: Input N.A. not applicable. In Output mode, a read access to the port gets the output latch value).
OD: Open Drain OUT: Output PP: Push-Pull TRI: Tristate TTL: TTL Input levels WP: Weak Push-Pull
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STR71xF - INTRODUCTION
1.7 Memory Mapping Figure 6. Memory Map
APB Memory Space
0xFFFF FFFF
Addressable Memory Space 4 Gbytes
0xFFFF FFFF 0xFFFF F800 EIC
0xFFFF F800 0xE000 E000 0xE000 D000 0xE000 C000
EIC WDG RTC TIMER 3 TIMER 2
4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K
4K
7
0xE000 B000
APB2 0xE000 0000
64K
TIMER 1
0xE000 A000
TIMER 0
0xE000 9000 0xE000 8000
CLKOUT ADC reserved IOPORT 2 IOPORT 1 IOPORT 0
6
0xE000 7000
APB1 0xC000 0000
64K
FLASH Memory Space 272 Kbytes + regs
0x4010 DFBF FLASH Registers 0x4010 0000
0xE000 6000 0xE000 5000
5
0xA000 0000 PRCCU
20b
0xE000 4000 0xE000 3000
1K
0x400C 4000
reserved
reserved
0xE000 2000 0xE000 1000
XTI APB BRIDGE 2 REGS
B1F1
8K
0xE000 0000
4
0x8000 0000 Reserved
0x400C 2000 B1F0
8K
0xC001 0000
reserved
4K
0x400C 0000 reserved
0xC000 F000 0xC000 E000 0xC000 D000
reserved HDLC + RAM reserved reserved BSPI 1 BSPI 0 CAN USB + RAM UART 3 UART 2
4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K
3
0x6000 0000 EXTMEM
0x4004 0000
1K
B0F7
64K
0xC000 C000 0xC000 B000
0x4003 0000
2
B0F6
0x4000 0000 FLASH
0xC000 A000 0xC000 9000 0xC000 8000 0x4002 0000 0xC000 7000 0xC000 6000 B0F5
64K
256K+16K+32b
1
64K
0x2000 0000 RAM
0xC000 5000 0xC000 4000
UART 1 UART 0 reserved I2C 1 I2C 0 APB BRIDGE 1 REGS
64K
0x4001 0000
0xC000 3000 B0F4
32K
0xC000 2000
0
0x0000 0000 FLASH/RAM/EMI
0x4000 0x4000 0x4000 0x4000 0x4000
8000 6000 4000 2000 0000
B0F3 B0F2 B0F1 B0F0
8K 8K 8K 8K
0xC000 1000 0xC000 0000
(*) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
Reserved
27/49
STR71xF - INTRODUCTION
Figure 7. Mapping of Flash Memory Versions
FLASH Memory Space 64 Kbytes + 16K RWW + regs
0x4010 DFBF FLASH Registers 0x4010 0000 reserved 0x400C 4000 B1F1 0x400C 2000 B1F0 0x400C 0000 reserved 0x4004 0000 0x4004 0000 0x400C 4000
FLASH Memory Space 128 Kbytes + 16K RWW + regs
0x4010 DFBF FLASH Registers 0x4010 0000 reserved
FLASH Memory Space 256 Kbytes + 16K RWW + regs
0x4010 DFBF FLASH Registers 0x4010 0000 reserved 0x400C 4000
20b
20b
20b
8K
0x400C 2000
B1F1
8K
0x400C 2000
B1F1
8K
8K
0x400C 0000
B1F0
8K
0x400C 0000
B1F0
8K
reserved 0x4004 0000
reserved
reserved
64K
reserved
64K
B0F7
64K
0x4003 0000
0x4003 0000
0x4003 0000
reserved
64K
reserved
64K
B0F6
64K
0x4002 0000
0x4002 0000
0x4002 0000
reserved
64K
0x4001 0000
B0F5
64K
0x4001 0000
B0F5
64K
0x4001 0000 B0F4 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F3 B0F2 B0F1 B0F0
32K 8K 8K 8K 8K
0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000
B0F4 B0F3 B0F2 B0F1 B0F0
32K 8K 8K 8K 8K
0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000
B0F4 B0F3 B0F2 B0F1 B0F0
32K 8K 8K 8K 8K
STR715FR0xx STR711FR0xx STR712FR0xx
STR710FZ1xx STR711FR1xx STR712FR1xx
STR710F72xx STR711FR2xx STR712FR2xx
Table 8. RAM Memory Mapping
Part Number STR715FR0xx STR711FR0xx STR712FR0xx STR710FZ1xx STR711FR1xx STR712FR1xx STR710F72xx STR711FR2xx STR712FR2xx 64 Kbytes 0x2000 0000 0x2000 FFFF 32 Kbytes 0x2000 0000 0x2000 7FFF RAM Size 16 Kbytes Start Address 0x2000 0000 End Address 0x2000 3FFF
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STR71xF - INTRODUCTION
Figure 8. External Memory Map
Addressable Memory Space 4 Gbytes
0xFFFF FFFF 0xFFFF F800 EIC
7
0xE000 0000 APB2
6
0xC000 0000 APB1
External Memory Space 64 MBytes
5
0xA000 0000 PRCCU
0x6C00 0x6C00 0x6C00 0x6C00
000C 0008 0004 0000
BCON3 BCON2 BCON1 BCON0
register register register register
4
0x66FF FFFF
0x8000 0000 Reserved
Bank3 CSn.3
16M
3
0x6000 0000 EXTMEM
0x6600 0000 0x64FF FFFF Bank2 CSn.2
16M
0x6400 0000
2
0x4000 0000 FLASH
0x62FF FFFF Bank1 CSn.1
16M
0x6200 0000 0x60FF FFFF
1
CSn.0
0x2000 0000 RAM
Bank0
16M
0x6000 0000
0
0x0000 0000 FLASH/RAM/EMI
Reserved
Drawing not in scale
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STR71xF - ELECTRICAL CHARACTERISTICS
2 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation, it is recommended that VIN and VO be higher than VSS and lower than V33. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (V33 or VSS). Table 9. Absolute Maximum Ratings.
Symbol V33 V33IO-PLL V18 V18BKP AVDD AVSS VIN IOV ITDV TST ESD Parameter Voltage on V33 with respect to ground (VSS) Voltage on V33IO-PLL with respect to ground (VSS) Voltage on V18 with respect to ground (VSS) Voltage on V18BKP with respect to ground (VSS) Voltage on AVDD pin with respect to ground (VSS) Voltage on AVSS with respect to ground (VSS) Voltage on true open drain pin (P0.10) with respect to ground (VSS) Voltage on any other pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Storage Temperature ESD Susceptibility (Human Body Model) –55 2000 Value Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.1 -0.3 -0.3 -10 Max +4.0 +4.0 +2.0 +2.0 +4.0 V33 + 0.1 +5.5 +4.0 +10 |200| +150 Unit V V V V V V V mA mA °C V
Note
Stresses exceeding above listed recommended “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>V33 or VIN
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