STR711FR1XX

STR71xF ARM7TDMI™ 32-bit MCU with Flash, USB, CAN 5 timers, ADC, 10 communications interfaces Features ■ Core – ARM7TDMI 32-bit RISC CPU – 59 MIPS @ 66 MHz from SRAM – 45 MIPS @ 50 MHz from Flash Memories – Up to 256 Kbytes Flash program memory (10 kcycles endurance, 20 yrs retention @ 85° C) – 16K bytes Flash data memory (100 kcycles endurance, 20 yrs retention@ 85° C) – Up to 64 Kbytes RAM – External Memory Interface (EMI) for up to 4 banks of SRAM, Flash, ROM – Multi-boot capability Clock, Reset and Supply Management – 3.0 to 3.6V application supply and I/Os – Internal 1.8V regulator for core supply – Clock input from 0 to 16.5 MHz – Embedded RTC osc. running from external 32 kHz crystal – Embedded PLL for CPU clock – Realtime Clock for clock-calendar function – 5 power saving modes: SLOW, WAIT, LPWAIT, STOP and STANDBY modes Nested interrupt controller – Fast interrupt handling with multiple vectors – 32 vectors with 16 IRQ priority levels – 2 maskable FIQ sources LQFP64 10 x 10 LQFP144 20 x 20 ■ LFBGA64 8 x 8 x 1.7 LFBGA64 8 x 8 x 1.7 LFBGA144 10 x 10 x 1.7 ■ Up to 48 I/O ports – 30/32/48 multifunctional bidirectional I/Os Up to 14 ports with interrupt capability 5 Timers – 16-bit watchdog timer – 3 16-bit timers with 2 input captures, 2 output compares, PWM and pulse counter – 16-bit timer for timebase functions 10 Communications Interfaces – 2 I2C interfaces (1 multiplexed with SPI) – 4 UART asynchronous serial interfaces – Smart Card ISO7816-3 interface on UART1 – 2 BSPI synchronous serial interfaces – CAN interface (2.0B Active) – USB Full Speed (12Mbit/s) Device Function with Suspend and Resume – HDLC synchronous communications 4-channel 12-bit A/D Converter – Sampling frequency up to 1kHz – Conversion range: 0 to 2.5V Development tools support ■ ■ ■ ■ ■ ■ March 2007 Rev 11 1/77 www.st.com 77 Contents STR71xF Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 4.2 4.3 4.4 4.5 4.6 4.7 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin description for 144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 External connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 5.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 EMI - External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2/77 STR71xF Contents 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7 8 9 Note: Product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 For detailed information on the STR710 Microcontroller memory, registers and peripherals, please refer to the STR710 Reference Manual. 3/77 Introduction STR71xF 1 Introduction This datasheet provides the STR71x Ordering Information, Mechanical and Electrical Device Characteristics. For complete information on the STR710 Microcontroller memory, registers and peripherals. please refer to the STR710 Reference Manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference Manual 2 Table 1. Features Device summary Device summary STR710 FZ1 STR710 FZ2 STR710 RZ STR711 FR0 STR711 FR1 STR711 FR2 STR712 FR0 STR712 FR1 STR712 FR2 STR715 FRx Flash - Kbytes RAM - Kbytes Peripheral Functions Operating Voltage Operating Temp. Packages 128+16 32 256+16 64 0 64 64+16 16 128+16 32 256+16 64 64+16 16 128+16 32 256+16 64 64+16 16 32 I/Os CAN, EMI, USB, 48 I/Os USB, 30 I/Os 3.0 to 3.6V -40 to +85°C or 0 to 70° C CAN, 32 I/Os T=LQFP144 20 x 20 H=LFBGA144 10 x10 T=LQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7 . 4/77 STR71xF Description 3 Description ARM® core with embedded Flash & RAM The STR710 series is a family of ARM-powered 32-bit Microcontrollers with embedded Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have high-speed RAM but no internal Flash. The STR710 family has an embedded ARM core and is therefore compatible with all ARM tools and software. Extensive tools support STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST’s ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available. For more information, please refer to ST MCU site http://www.st.com/mcu 5/77 System architecture STR71xF 4 System architecture Package Choice: Low Pin-Count 64-pin or Feature-Rich 144-pin LQFP or BGA The STR710 family is available in 5 main versions. The 144-pin versions have the full set of all features including CAN, USB and External Memory Interface (EMI). ● ● STR710F: 144-pin BGA or LQFP with CAN, USB and EMI STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash memory) STR715F: 64-pin BGA or LQFP without CAN or USB STR711F: 64-pin BGA or LQFP with USB STR712F: 64-pin BGA or LQFP with CAN The three 64-pin versions (BGA or LQFP) do not include External Memory Interface. ● ● ● High Speed Flash Memory (STR71xF) The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size, typically for the application program code. Bank 1 is 16K bytes, typically used for storing data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K write/erase cycles. Data retention is 20 years at 85°C on both banks. The two banks can be accessed independently in read or write. Flash memory can be accessed in two modes: ● ● Burst mode: 64-bit wide memory access at up to 50 MHz. Direct 32-bit wide memory access for deterministic operation at up to 33 MHz. The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming. IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: ● ● Sector Write Protection Flash Debug Protection (locks JTAG access) Refer to the STR7 Flash Programming Reference manual for details. Optional External Memory (STR710) The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Figure 1 shows the general block diagram of the device family. 6/77 STR71xF Flexible Power Management System architecture To minimize power consumption, you can program the STR710 to switch to SLOW, WAIT, LPWAIT (low power wait), STOP or STANDBY mode depending on the current system activity in the application. Flexible Clock Control Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime. The clock to each peripheral is gated with an individual control bit to optimize power usage by turning off peripherals any time they are not required. Voltage Regulators The STR710 requires an external 3.0-3.6V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is switched off during low power operation. Low Voltage Detectors Both the Main Voltage Regulator and the Low Power Voltage Regulator contain each a low voltage detection circuitry which keep the device under reset when the corresponding controlled voltage value (V18 or V18BKP) falls below 1.35V (+/- 10%). This enhances the security of the system by preventing the MCU from going into an unpredictable state. An external reset circuit must be used to provide the RESET at V33 power-up. It is not sufficient to rely on the RESET generated by the LVD in this case. This is because LVD operation is guaranteed only when V33 is within the specification. 4.1 On-chip peripherals CAN Interface (STR710 and STR712) The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. USB Interface (STR710 and STR711) The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32 unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous transfers and USB Suspend/Resume functions. Standard Timers Each of the four timers have a 16-bit free-running counter with 7-bit prescaler Three timers each provide up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. The fourth timer is not connected to the I/O ports. It can be used by the application software for general timing functions. 7/77 System architecture Realtime Clock (RTC) STR71xF The RTC provides a set of continuously running counters driven by the 32 kHz external crystal. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR710 is in Standby mode the RTC can be kept running, powered by the low power voltage regulator and driven by the 32 kHz external crystal. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 1.25 Mb/s. Smart Card Interface UART1 is configurable to function either as a general purpose UART or as an asynchronous Smart Card interface as defined by ISO 7816-3. It includes Smart Card clock generation and provides support features for synchronous cards. Buffered Serial Peripheral Interfaces (BSPI) Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5Mb/s in Master mode and 4 Mb/s in Slave mode. I2C Interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may be used at a time. HDLC interface The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ, NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator. A/D Converter The Analog to Digital Converter, converts in single channel or up to 4 channels in singleshot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The input voltage range is 0-2.5V. Watchdog The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O Ports The 48 I/O ports are programmable as Inputs or Outputs. External Interrupts Up to 14 external interrupts are available for application use or to wake-up the application from STOP mode. 8/77 STR71xF Figure 1. STR710 block diagram A[19:0] D[15:0] RDN WEN[1:0] System architecture A[23:20] (AF) CS[3:0) CK CKOUT RSTIN PRCCU/PLL EXT. MEM. INTERFACE (EMI) FLASH* Program Memory 64/128/256K 16K Data FLASH* RAM 16/32/64K APB BRIDGE 1 ARM7TDMI CPU JTDI JTCK JTMS JTRST JTDO DBGRQS BOOTEN ARM7 NATIVE BUS JTAG V18[1:0] V33[6:0] VSS[9:0] V18BKP AVDD AVSS POWER SUPPLY VREG APB BRIDGE 2 I2C0 2 AF 2 AF 4 AF 4 AF 2 AF 3 AF 2 AF 2 AF 3 AF USBDP USBDN 1 AF INTERRUPT CTL(EIC) 4 AF A/D TIMER0 4 AF 2 AF 4 AF OSC 14 AF TIMER1 APB BUS I2C1 BSPI0 BSPI1 UART0 UART1 / SMARTCARD UART2 UART3 HDLC TIMER2 TIMER3 RTC APB BUS STDBY RTCXTO RTCXTI WAKEUP EXT INT (XTI) WATCHDOG USB P0[15:0] P1[15:0] P2[15:0] I/O PORT 0 I/O PORT 1 CAN I/O PORT 2 2 AF *Flash present in STR710F, not in STR710R AF: alternate function on I/O port pin 9/77 System architecture STR71xF 4.2 Related documentation Available from www.arm.com: ARM7TDMI Technical Reference Manual Available from http://www.st.com: STR71x Reference Manual STR7 Flash Programming Reference Manual AN1774 - STR710 Software development getting started AN1775 - STR710 Hardware development getting started AN1776 - STR710 Enhanced Interrupt Controller AN1777 - STR710 Memory Mapping AN1780 - Real Time Clock with STR710 AN1781 - Four 7 Segment Display Drive Using the STR710 The above is a selected list only, a full list STR71x application notes can be viewed at http://www.st.com. 10/77 STR71xF System architecture 4.3 Pin description for 144-pin packages Figure 2. STR710 LQFP Pinout P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V33 WEn.0 WEn.1 A.19 A.18 A.17 A.16 A.15 A.14 V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX A.13 A.12 A.11 A.10 A.9 A.8 A.7 A.6 A.5 V33 VSS P1.15/HTXD N.C. N.C. P0.10/U1.RX/U1.TX/SCDATA RDn P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS V33 P2.0/CSn.0 P2.1/CSn.1 P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA P2.2/CSn.2 P2.3/CSn.3 P2.4/A.20 P2.5/A.21 P2.6/A.22 BOOTEN P2.7/A.23 P2.8 N.C. N.C. VSS V33 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 JTDI JTMS JTCK JTDO JTRSTn NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 LQFP144 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 V33 VSS A.4 A.3 A.2 A.1 A.0 D.15 D.14 D.13 D.12 D.11 D.10 USBDN USBDP P1.12/CANTX P1.11/CANRX N.C. P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL D.9 D.8 D.7 D.6 D.5 P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 N.C. TEST N.C. V33IO-PLL N.C. VSSIO-PLL N.C. DBGRQS CKOUT CK P0.15/WAKEUP N.C. RTCXTI RTCXTO STDBY RSTIN N.C. VSSBKP V18BKP N.C. N.C. V18 VSS18 N.C. D.0 D.1 D.2 D.3 D.4 AVDD AVSS N.C. N.C. N.C. P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 11/77 System architecture Table 2. A 1 2 3 4 5 6 7 8 9 10 11 12 P0.10 VSS V33 P0.6 A.19 P0.3 P0.2 A.9 VSS A.8 A.7 A.12 STR71xF STR710 BGA ball connections B P2.0 RDn P0.9 P0.7 WEn.1 A.15 P0.1 A.10 V33 N.C. N.C. A.4 C P2.1 P0.11 P0.12 P0.8 WEn.0 A.16 P0.4 A.11 A.5 P1.15 P1.14 A.3 D VSS V33 P0.13 P0.14 P0.5 A.17 VSS18 A.13 A.6 P1.13 P1.10 P1.9 E P2.2 P2.3 P2.4 P2.5 P2.7 A.18 V18 P0.0 V33 VSS A.2 A.1 F P2.6 P2.8 N.C. N.C. VSS V33 A.14 A.0 D.15 D.14 D.13 P1.11/ CANRX G BOOT EN P2.9 P2.10 P2.11 P2.14 V18 D.12 D.11 D.10 USBDN USBDP N.C. H P2.12 JTMS JTCK JTDO N.C. N.C. D.1 P1.12/ CANTX P1.8 P1.7 VSS V33IOPLL J P2.13 JTRST n NU CK RTCXTO N.C. D.0 N.C. D.9 D.8 D.5 P1.6 K P2.15 TEST V33 CKOUT RTCXTI V18BK P nc AVSS P1.0 P1.5 P1.4 D.7 L JTDI TEST N.C. VSSIOPLL N.C. VSS BKP VSS18 D.3 N.C. P1.1 P1.3 D.6 M N.C. N.C. DBG RQS N.C. P0.15 STDBY RSTIN D.2 N.C. D.4 AVDD P1.2 Legend / abbreviations for Table 3: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V/2V with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100kΩ weak pull-up is enabled. pd = in reset state, the internal 100kΩ weak pull-down is enabled. OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant. Output: 12/77 STR71xF Table 3. Pin n° LQFP144 Type BGA144 Pin Name System architecture STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP UART1: Receive Data input 1 A1 P0.10/U1.RX/ U1.TX/ SC.DATA I/O pd CT X 4mA T UART1: Transmit data output. Note: This pin may be used for Port 0.10 Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X External Memory Interface: Active low read signal for external memory. It maps to the OE_N input of the external components. Select Boot Port 0.11 Configuration input UART1: Transmit data output. 2 B2 RD O 5) 3 4 5 6 C2 C3 D1 D2 P0.11/BOOT.1 I/O pd /U1.TX P0.12/SC.CLK I/O pd VSS V33 S S CT CT 4mA X 4mA X X X Port 0.12 Smartcard reference clock output Ground voltage for digital I/Os4) Supply voltage for digital I/Os4) External Memory Interface: Select Memory Bank 0 output Note: This pin is forced to output push-pull 1 mode at reset to allow boot from external memory External Memory Interface: Select Memory Bank 1 output Timer2: Output Compare A output Timer2: Input Capture A input 7 B1 P2.0/CS.0 I/O 8) CT 8mA X X Port 2.0 8 C1 P2.1/CS.1 P0.13/U2.RX/ T2.OCMPA P0.14/U2.TX/ T2.ICAPA P2.2/CS.2 P2.3/CS.3 I/O pu 2) CT 8mA X X Port 2.1 9 D3 I/O pu CT X 4mA X X UART2: Port 0.13 Receive Data input UART2: Port 0.14 Transmit data output Port 2.2 Port 2.3 10 D4 I/O pu pu 2) CT 4mA X X 11 12 E1 E2 I/O I/O CT CT 8mA X 8mA X X X External Memory Interface: Select Memory Bank 3 output External Memory Interface: Select Memory Bank 4 output pu 2) 13/77 System architecture Table 3. Pin n° LQFP144 Type BGA144 Pin Name STR71xF STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 E3 E4 F1 P2.4/A.20 P2.5/A.21 P2.6/A.22 I/O I/O I/O I I/O pd 3) CT CT CT CT 8mA X 8mA X 8mA X X X X PP Port 2.4 Port 2.5 Port 2.6 Boot control input. Enables sampling of BOOT[1:0] pins External Memory Interface: address bus pd 3) pd 3) G1 BOOTEN E5 F2 F3 F4 F5 F6 P2.7/A.23 P2.8 N.C. N.C. VSS V33 pd 3) CT CT 8mA X X 4mA X X X Port 2.7 Port 2.8 External Memory Interface: address bus External interrupt INT2 I/O pu Not connected (not bonded) Not connected (not bonded) S S I/O pu I/O pu I/O pu I/O pu I/O pu I/O pu I/O pu I I I O I TT CT CT CT CT CT CT CT TT TT C 8mA X X 4mA X X 4mA X X 4mA X 4mA X 4mA X 4mA X 4mA X X X X X X X X Ground voltage for digital I/Os4) Supply voltage for digital I/Os4) Port 2.9 Port 2.10 Port 2.11 Port 2.12 Port 2.13 Port 2.14 Port 2.15 JTAG Data input. External pull-up required. JTAG Mode Selection Input. External pull-up required. JTAG Clock Input. External pull-up or pull-down required. JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. Reserved, must be forced to ground. Reserved, must be forced to ground. Not connected (not bonded) Reserved, must be forced to ground. Not connected (not bonded) External interrupt INT3 External interrupt INT4 External interrupt INT5 G2 P2.9 G3 P2.10 G4 P2.11 H1 J1 P2.12 P2.13 G5 P2.14 K1 L1 H2 H3 H4 J2 J3 K2 P2.15 JTDI JTMS JTCK JTDO JTRST NU TEST M1 N.C. L2 L3 TEST N.C. 14/77 STR71xF Table 3. Pin n° LQFP144 Type BGA144 Pin Name System architecture STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP X 40 41 42 43 44 45 46 47 48 49 50 K3 V33IO-PLL S Supply voltage for digital I/O circuitry and for PLL reference Not connected (not bonded) M4 N.C. L4 VSSIO-PLL S Ground voltage for digital I/O circuitry and for PLL reference4) Not connected (not bonded) M2 N.C. M3 DBGRQS K4 J4 M5 L5 K5 J5 CKOUT CK P0.15/ WAKEUP N.C. RTCXTI RTCXTO I O I I C TT X X CT 8mA Debug Mode request input (active high) Clock output (fPCLK2) Note: Enabled by CKDIS register in APB Bridge 2 Reference clock input Port 0.15 Wakeup from Standby mode input. Note: This port is input only. Not connected (not bonded) Realtime Clock input and input of 32 kHz oscillator amplifier circuit Output of 32 kHz oscillator amplifier circuit Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode. X Output: Standby mode active low output following Software Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby X Reset input Not connected (not bonded) 51 M6 STDBY I/O CT 4mA X 52 53 54 M7 RSTIN H5 L6 N.C. VSSBKP I CT S X Stabilization for low power voltage regulator. Stabilization for low power voltage regulator. Requires external capacitors of at least 1µF between V18BKP and VSS18BKP. See Figure 5. X Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. Not connected (not bonded) Not connected (not bonded) 55 K6 V18BKP S 56 57 58 J6 H6 N.C. N.C. S G6 V18 Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. 15/77 System architecture Table 3. Pin n° LQFP144 Type BGA144 Pin Name STR71xF STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function 59 60 61 62 63 64 65 66 67 68 69 70 71 L7 K7 J7 H7 VSS18 N.C. D.0 D.1 S PP Stabilization for main voltage regulator. Not connected (not bonded) I/O I/O I/O I/O I/O S S 6) 6) 6) 6) 6) 8mA 8mA 8mA 8mA 8mA Supply voltage for A/D Converter Ground voltage for A/D Converter Not connected (not bonded) Not connected (not bonded) Not connected (not bonded) External Memory Interface: data bus M8 D.2 L8 D.3 M10 D.4 M11 VDDA K8 J8 VSSA N.C. M9 N.C. L9 K9 N.C. P1.0/T3.OCM PB/AIN.0 I/O pu CT 4mA X X Port 1.0 Timer 3: Output Compare B ADC: Analog input 0 72 P1.1/T3.ICAP L10 A/T3.EXTCLK/ I/O pu AIN.1 P1.2/T3.OCM PA/AIN.2 P1.3/T3.ICAP B/AIN.3 P1.4/T1.ICAP A/T1.EXTCLK P1.5/T1.ICAP B P1.6/T1.OCM PB CT 4mA X X Port 1.1 Timer 3: Input Capture A or ADC: Analog input 1 External Clock input Timer 3: Output Compare A Timer 3: Input Capture B Timer 1: Input Capture A Timer 1: Input Capture B Timer 1: Output Compare B ADC: Analog input 2 73 M12 I/O pu CT 4mA X X Port 1.2 74 75 76 L11 K11 K10 I/O pu I/O pu I/O pu CT CT CT 4mA X 4mA X 4mA X X X X Port 1.3 Port 1.4 Port 1.5 ADC: Analog input 3 Timer 1: External Clock input 77 78 79 80 81 82 J12 I/O pu I/O I/O I/O I/O I/O 6) 6) 6) 6) 6) CT 4mA X 8mA 8mA 8mA 8mA 8mA X Port 1.6 J11 D.5 L12 D.6 K12 D.7 J10 D.8 J9 D.9 External Memory Interface: data bus 16/77 STR71xF Table 3. Pin n° LQFP144 Type BGA144 Pin Name System architecture STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP 83 84 H12 V33IO-PLL H11 VSSIO-PLL P1.7/T1.OCM PA P1.8 S S Supply voltage for digital I/O circuitry and for PLL reference4) Ground voltage for digital I/O circuitry and for PLL reference4) CT CT 4mA X 4mA X X X Port 1.7 Port 1.8 Not connected (not bonded) CT CT X 4mA X 4mA X X X Port 1.11 Port 1.12 CAN: receive data input Note: On STR710 and STR712 only CAN: Transmit data output Note: On STR710 and STR712 only Timer 1: Output Compare A 85 86 87 88 89 H10 H9 I/O pu I/O pd G12 N.C. F12 P1.11/CANRX I/O pu H8 P1.12/CANTX I/O pu 90 G11 USBDP I/O CT USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. 8mA 8mA 8mA External Memory Interface: data bus 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA X X X X X Ground voltage for digital I/O circuitry4) Supply voltage for digital I/O circuitry4) External Memory Interface: address bus 91 92 93 94 95 96 97 98 99 G10 USBDN G9 D.10 G8 D.11 G7 D.12 F11 D.13 F10 D.14 F9 F8 D.15 A.0 I/O I/O I/O I/O I/O I/O I/O O O O O O S S I/O pd I/O pd 6) 6) 6) 6) 6) 6) 7) 7) 7) 7) 7) CT E12 A.1 100 E11 A.2 101 C12 A.3 102 B12 A.4 103 E10 VSS 104 E9 V33 105 D12 P1.9 106 D11 P1.10/ USBCLK CT C/ T 4mA X 4mA X X X Port 1.9 Port 1.10 USB: 48 MHZ clock input 17/77 System architecture Table 3. Pin n° LQFP144 Type BGA144 Pin Name STR71xF STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP 107 D10 P1.13/HCLK/ I0.SCL P1.14/HRXD/ I0.SDA I/O pd CT X 4mA X X Port 1.13 HDLC: reference clock input HDLC: Receive data input I2C clock 108 C11 I/O pu CT X 4mA X X Port 1.14 I2C serial data 109 B11 N.C. 110 B10 N.C. 111 C10 P1.15/HTXD 112 113 114 115 A9 B9 C9 D9 VSS V33 A.5 A.6 I/O pu S S O O O O O O O O O 7) 7) 7) 7) 7) 7) 7) 7) 7) Not connected (not bonded) Not connected (not bonded) CT 4mA X X Port 1.15 HDLC: Transmit data output Ground voltage for digital I/O circuitry4) Supply voltage for digital I/O circuitry4) 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA X X X X X X X X X SPI0 Master in/Slave out data UART3 Transmit data output External Memory Interface: address bus 116 A11 A.7 117 A10 A.8 118 119 120 A8 B8 C8 A.9 A.10 A.11 121 A12 A.12 122 D8 A.13 123 E8 P0.0/S0.MISO I/O pu /U3.TX CT 4mA X X Port 0.0 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master UART3: Receive out/Slave in Data input data 124 B7 P0.1/S0.MOSI I/O pu /U3.RX CT X 4mA X X Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. 18/77 STR71xF Table 3. Pin n° LQFP144 Type BGA144 Pin Name System architecture STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP BSPI0: Serial Clock 125 A7 P0.2/S0.SCLK I/O pu /I1.SCL CT X 4mA X X Port 0.2 I2C1: Serial clock Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data 126 A6 P0.3/S0.SS/ I1.SDA I/O pu CT 4mA X X Port 0.3 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI1: Master in/Slave out data 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 C7 D7 E7 F7 B6 C6 D6 E6 A5 B5 C5 A3 A2 D5 A4 B4 P0.4/S1.MISO I/O pu VSS18 V18 A.14 A.15 A.16 A.17 A.18 A.19 WE.1 WE.0 V33 VSS S S O O O O O O O O S S 7) 7) 7) 7) 7) 7) 5) CT 4mA X X Port 0.4 Stabilization for main voltage regulator. Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA X X X External Memory Interface: address bus X X X X X External Memory Interface: active low MSB write enable output External Memory Interface: active low LSB write enable output Supply voltage for digital I/Os4) Ground voltage for digital I/Os4) CT CT CT 4mA X X 4mA X 4mA X X X X Port 0.5 Port 0.6 Port 0.7 SPI1: Master out/Slave In data SPI1: Serial Clock SPI1: Slave Select input active low 5) P0.5/S1.MOSI I/O pu P0.6/S1.SCLK I/O pu P0.7/S1.SS I/O pu 19/77 System architecture Table 3. Pin n° LQFP144 Type BGA144 Pin Name STR71xF STR710 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP Port 0.8 143 C4 P0.8/U0.RX/ U0.TX I/O pd CT X 4mA T UART0: Receive Data input UART0: Transmit data output. Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Configuration input UART0: Transmit data output 144 B3 P0.9/U0.TX/ BOOT.0 I/O pd CT 4mA X 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7 on page 29. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured by software as Alternate Function (see Table 7: Port bit configuration table on page 29) to be used by the External Memory Interface. 3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address 0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7: Port bit configuration table on page 29). 4. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected. 5. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Output Push-Pull. 6. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Hi-Z. 7. During the reset phase, these pins are in input pull-down state. When reset is released, they are configured as Output Push-Pull. 8. During the reset phase, this pin is in input floating state. When reset is released, it is configured as Output Push-Pull. 20/77 STR71xF System architecture 4.4 Pin description for 64-pin packages Figure 3. STR712/STR715 LQFP64 pinout P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP64 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10 P1.9 VSS P1.12/CANTX1) P1.11/CANRX1) P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 1) CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os. V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO STDBY RSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 21/77 System architecture Figure 4. STR711 LQFP64 pinout P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD STR71xF P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP64 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 VSS USBDN USBDP P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 Table 4. A 1 2 3 4 5 6 7 8 P0.10 P0.9 P0.5 STR711 BGA ball connections B P0.11 VSS P0.7 VSS P0.4 P0.1 P0.0 P1.14 C P0.12 P0.13 BOOTEN P0.8 V18 P0.3 P1.10 VSS D P0.14 VSS JTDI JTDO P0.6 P1.13 USBDN P1.8 E V33 JTMS NU AVDD P1.9 USBDP P1.7 V33IOPLL F JTCK JTRSTn STDBY V18BKP P1.0 VSSIOPLL P1.6 P1.4 G TEST P0.15 RTCXTI RSTIN V18 AVSS P1.5 P1.3 H V33IOPLL VSSIOPLL CK RTCXTO VSSBKP VSS18 P1.1 P1.2 VSS18 P0.2 V33 VSS P1.15 22/77 V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO STDBY RSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 STR71xF Table 5. A 1 2 3 4 5 6 7 8 1) System architecture STR712/715 BGA Ball Connections B P0.11 VSS P0.7 VSS P0.4 P0.1 P0.0 P1.14 C P0.12 P0.13 BOOTEN P0.8 V18 P0.3 P1.10 VSS D P0.14 VSS JTDI JTDO P0.6 P1.13 P1.12/ CANTX1) P1.8 E V33 JTMS NU AVDD P1.9 P1.11/ CANRX1) P1.7 V33IOPLL F JTCK JTRSTn STDBY V18BKP P1.0 VSSIOPLL P1.6 P1.4 G TEST P0.15 RTCXTI RSTIN V18 AVSS P1.5 P1.3 H V33IOPLL VSSIOPLL CK RTCXTO VSSBKP VSS18 P1.1 P1.2 P0.10 P0.9 P0.5 VSS18 P0.2 V33 VSS P1.15 CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os. Legend / abbreviations for Table 6: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.8V / 2V with input trigger TT= TTL 0.3V/0.7VDD with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100kΩ weak pull-up is enabled. pd = in reset state, the internal 100kΩ weak pull-down is enabled. OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), Output: 5V tolerant. 23/77 System architecture Table 6. Pin n° Type LQFP64 BGA64 Pin Name STR71xF STR711/STR712/STR715 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP UART1: Receive Data input 1 P0.10/U1.RX/ A1 U1.TX/ SC.DATA I/O pd CT X 4mA T UART1: Transmit data output. Note: This pin may be used for Port 0.10 Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X X Select Boot Port 0.11 Configuration input UART1: Transmit data output. 2 3 4 5 B1 P0.11/BOOT.1 I/O pd /U1.TX CT CT 4mA 4mA X X C1 P0.12/SC.CLK I/O pd B2 VSS C2 P0.13/U2.RX/ T2.OCMPA P0.14/U2.TX/ T2.ICAPA S I/O pu Port 0.12 Smartcard reference clock output Ground voltage for digital I/Os2) CT X 4mA X X UART2: Port 0.13 Receive Data input UART2: Port 0.14 Transmit data output Timer2: Output Compare A output Timer2: Input Capture A input 6 D1 I/O pu CT 4mA X X 7 8 9 C3 BOOTEN D2 VSS E1 V33 I S S I I I O I CT Boot control input. Enables sampling of BOOT[1:0] pins Ground voltage for digital I/Os2) Supply voltage for digital I/Os2) 10 D3 JTDI 11 E2 JTMS 12 F1 JTCK 13 D4 JTDO 14 F2 JTRST 15 E3 NU 16 G1 TEST 17 H1 V33IO-PLL 18 H2 VSSIO-PLL 19 H3 CK TT TT C 8mA TT X JTAG Data input. External pull-up required. JTAG Mode Selection Input. External pull-up required. JTAG Clock Input. External pull-up or pull-down required. JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. Reserved, must be forced to ground. Reserved, must be forced to ground. S S I C Supply voltage for digital I/O circuitry and for PLL reference2) Ground voltage for digital I/O circuitry and for PLL reference2) Reference clock input 24/77 STR71xF Table 6. Pin n° Type LQFP64 BGA64 Pin Name System architecture STR711/STR712/STR715 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP 20 G2 P0.15/ WAKEUP Port 0.15 Wakeup from Standby mode input. I TT X X Note: This port is input only. Realtime Clock input and input of 32 kHz oscillator amplifier circuit Output of 32 kHz oscillator amplifier circuit Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode. X Output: Standby mode active low output following Software Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby. X Reset input X Stabilization for low power voltage regulator. Stabilization for low power voltage regulator. Requires external capacitors of at least 1µF between V18BKP and VSS18BKP. See Figure 5. X Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. Stabilization for main voltage regulator. Supply voltage for A/D Converter Ground voltage for A/D Converter CT 4mA X X Port 1.0 Timer 3: Output ADC: Analog input 0 Compare B Timer 3: Input Capture A or External Clock input 21 G3 RTCXTI 22 H4 RTCXTO 23 F3 STDBY I/O CT 4mA X 24 G4 RSTIN 25 H5 VSSBKP I CT S 26 F4 V18BKP S 27 G5 V18 28 H6 VSS18 29 E4 VDDA 30 G6 VSSA 31 F5 P1.0/T3.OCM PB/AIN.0 S S S S I/O pu P1.1/T3.ICAP 32 H7 A/T3.EXTCLK I/O pu /AIN.1 33 H8 34 G8 35 F8 P1.2/T3.OCM PA/AIN.2 P1.3/T3.ICAP B/AIN.3 I/O pu I/O pu CT 4mA X X Port 1.1 ADC: Analog input 1 CT CT CT 4mA 4mA 4mA X X X X X X Port 1.2 Port 1.3 Port 1.4 Timer 3: Output ADC: Analog input 2 Compare A Timer 3: Input Capture B Timer 1: Input Capture A ADC: Analog input 3 Timer 1: External Clock input P1.4/T1.ICAP I/O pu A/T1.EXTCLK 25/77 System architecture Table 6. Pin n° Type LQFP64 BGA64 Pin Name STR71xF STR711/STR712/STR715 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function 36 G7 37 F7 P1.5/T1.ICAP B P1.6/T1.OCM PB PP I/O pu I/O pu S S I/O pu I/O pd CT CT 4mA 4mA X X X X Port 1.5 Port 1.6 Timer 1: Input Capture B Timer 1: Output Compare B 38 E8 V33IO-PLL 39 F6 VSSIO-PLL 40 E7 P1.7/T1.OCM PA Supply voltage for digital I/O circuitry and for PLL reference2) Ground voltage for digital I/O circuitry and for PLL reference2) CT CT CT CT 4mA 4mA X 4mA 4mA X X X X X X X X Port 1.7 Port 1.8 Port 1.11 Port 1.12 CAN: receive data input Note: On STR710 and STR712 only CAN: Transmit data output Note: On STR710 and STR712 only Timer 1: Output Compare A 41 D8 P1.8 42 E6 P1.11/CANRX I/O pu 43 D7 P1.12/CANTX I/O pu 42 E6 USBDP I/O CT USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. Ground voltage for digital I/O circuitry2) 43 D7 USBDN 44 C8 VSS 45 E5 P1.9 46 C7 P1.10/USBCL K P1.13/HCLK/I 0.SCL I/O S I/O pd I/O pd CT CT C/ T CT 4mA 4mA X X X X Port 1.9 Port 1.10 USB: 48 MHZ clock input 47 D6 I/O pd X 4mA X X HDLC: Port 1.13 reference clock I2C clock input Port 1.14 HDLC: Receive I2C serial data data input 48 B8 P1.14/HRXD/I I/O pu 0.SDA I/O pu S S CT CT X 4mA 4mA X X X X 49 A8 P1.15/HTXD 50 A7 VSS 51 A6 V33 Port 1.15 HDLC: Transmit data output Ground voltage for digital I/O circuitry2) Supply voltage for digital I/O circuitry2) 26/77 STR71xF Table 6. Pin n° Type LQFP64 BGA64 Pin Name System architecture STR711/STR712/STR715 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP SPI0 Master in/Slave out data 52 B7 P0.0/S0.MISO I/O pu /U3.TX CT 4mA X X Port 0.0 UART3 Transmit data output Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master out/Slave in data UART3: Receive Data input 53 B6 P0.1/S0.MOSI I/O pu /U3.RX CT X 4mA X X Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Serial Clock I2C1: Serial clock 54 A5 P0.2/S0.SCLK I/O pu /I1.SCL CT X 4mA X X Port 0.2 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data 55 C6 P0.3/S0.SS/I1 I/O pu .SDA CT 4mA X X Port 0.3 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. 56 B5 P0.4/S1.MISO I/O pu 57 A4 VSS18 58 C5 V18 59 B4 VSS S S S CT 4mA X X Port 0.4 SPI1: Master in/Slave out data Stabilization for main voltage regulator. Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. Ground voltage for digital I/Os CT CT CT 4mA X 4mA 4mA X X X X X X Port 0.5 Port 0.6 Port 0.7 SPI1: Master out/Slave In data SPI1: Serial Clock SPI1: Slave Select input active low 60 A3 P0.5/S1.MOSI I/O pu 61 D5 P0.6/S1.SCLK I/O pu 62 B3 P0.7/S1.SS I/O pu 27/77 System architecture Table 6. Pin n° Type LQFP64 BGA64 Pin Name STR71xF STR711/STR712/STR715 pin description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP Port 0.8 63 C4 P0.8/U0.RX/U I/O pd 0.TX CT X 4mA T UART0: Receive Data input UART0: Transmit data output. Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Configuration input UART0: Transmit data output 64 A2 P0.9/U0.TX/B OOT.0 I/O pd CT 4mA X 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7 on page 29. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected. 4.5 External connections Figure 5. Recommended External Connection of V18 and V18BKP pins 33 nF 129 128 V18 33 nF 58 57 V18 LQFP144 V18BKP V18 LQFP64 V18BKP V18 54 55 58 59 1µF 10 µF 25 26 27 28 1µF 10 µF 28/77 STR71xF System architecture 4.6 Table 7. I/O port configuration Port bit configuration table PxD Configuration Mode Input Buffer Register Read access I/O pin I/O pin I/O pin I/O pin 0 I/O pin last value written I/O pin I/O pin Write access don’t care don’t care 0 1 don’t care 0 or 1 0 or 1 don’t care don’t care PxC2 PxC1 PxC0 Register Register Register TTL Input Floating CMOS Input Floating CMOS Input Pull-Down (IPUPD) CMOS Input Pull-Up (IPUPD) Analog input Output Open-Drain Output Push-Pull OUTPUT TTL floating CMOS floating CMOS PullDown CMOS Pull-Up AIN N.A. N.A. 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 1 0 1 INPUT Alternate Function Open-Drain CMOS floating Alternate Function Push-Pull Legend: AIN: Analog Input CMOS: CMOS Input levels IPUPD: Input Pull Up /Pull Down TTL: TTL Input levels CMOS floating N.A.: not applicable. In Output mode, a read access to the port gets the output latch value. 29/77 System architecture STR71xF 4.7 Memory mapping Figure 6. Memory map APB Memory Space 0xFFFF FFFF Addressable Memory Space 4 Gbytes 0xFFFF FFFF 0xFFFF F800 EIC 0xFFFF F800 0xE000 E000 0xE000 D000 0xE000 C000 EIC WDG RTC TIMER 3 TIMER 2 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 7 0xE000 B000 APB2 0xE000 0000 64K TIMER 1 0xE000 A000 TIMER 0 0xE000 9000 0xE000 8000 CLKOUT ADC reserved IOPORT 2 IOPORT 1 IOPORT 0 6 0xE000 7000 APB1 0xC000 0000 64K FLASH Memory Space 272 Kbytes + regs 0x4010 DFBF FLASH Registers 0x4010 0000 0xE000 6000 0xE000 5000 0xE000 4000 0xE000 3000 5 0xA000 0000 PRCCU 36b 1K 0x400C 4000 reserved reserved 0xE000 2000 0xE000 1000 XTI APB BRIDGE 2 REGS B1F1 8K 0xE000 0000 4 0x8000 0000 Reserved 0x400C 2000 B1F0 8K 0xC001 0000 reserved 4K 0x400C 0000 reserved 0xC000 F000 0xC000 E000 0xC000 D000 reserved HDLC + RAM reserved reserved BSPI 1 BSPI 0 CAN USB + RAM UART 3 UART 2 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 3 EXTMEM 0x4004 0000 See Figure 8 0x6000 0000 64MB B0F7 64K 0xC000 C000 0xC000 B000 0x4003 0000 2 B0F6 0x4000 0000 FLASH 0xC000 A000 0xC000 9000 0xC000 8000 0x4002 0000 0xC000 7000 0xC000 6000 B0F5 64K 256K+16K+36b 1 64K 0x2000 0000 RAM 0xC000 5000 0xC000 4000 UART 1 UART 0 reserved 64K 0x4001 0000 0xC000 3000 B0F4 32K 0xC000 2000 I2C 1 I C0 APB BRIDGE 1 REGS 2 0 0x0000 0000 FLASH/RAM/EMI 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F3 B0F2 B0F1 B0F0 8K 8K 8K 8K 0xC000 1000 0xC000 0000 (*) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes) Reserved 30/77 STR71xF Figure 7. Mapping of Flash memory versions FLASH Memory Space 128 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Registers 0x4010 0000 reserved 0x400C 4000 B1F1 0x400C 2000 B1F0 0x400C 0000 reserved 0x4004 0000 0x4004 0000 0x400C 4000 FLASH Registers 0x4010 0000 reserved System architecture FLASH Memory Space 64 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Memory Space 256 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Registers 0x4010 0000 reserved 0x400C 4000 36b 36b 36b 8K 0x400C 2000 B1F1 8K 0x400C 2000 B1F1 8K 8K 0x400C 0000 B1F0 8K 0x400C 0000 B1F0 8K reserved 0x4004 0000 reserved reserved 64K reserved 64K B0F7 64K 0x4003 0000 0x4003 0000 0x4003 0000 reserved 64K reserved 64K B0F6 64K 0x4002 0000 0x4002 0000 0x4002 0000 reserved 64K 0x4001 0000 B0F5 64K 0x4001 0000 B0F5 64K 0x4001 0000 B0F4 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F3 B0F2 B0F1 B0F0 32K 8K 8K 8K 8K 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F4 B0F3 B0F2 B0F1 B0F0 32K 8K 8K 8K 8K 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F4 B0F3 B0F2 B0F1 B0F0 32K 8K 8K 8K 8K STR715FR0xx STR711FR0xx STR712FR0xx STR710FZ1xx STR711FR1xx STR712FR1xx STR710F72xx STR711FR2xx STR712FR2xx Table 8. RAM memory mapping RAM Size Start Address End Address Part Number STR715FR0xx STR711FR0xx STR712FR0xx STR710FZ1xx STR711FR1xx STR712FR1xx STR710FR2xx STR710Rxx STR711FR2xx STR712FR2xx 16 Kbytes 0x2000 0000 0x2000 3FFF 32 Kbytes 0x2000 0000 0x2000 7FFF 64 Kbytes 0x2000 0000 0x2000 FFFF 31/77 System architecture Figure 8. External memory map Addressable Memory Space 4 Gbytes 0xFFFF FFFF 0xFFFF F800 EIC STR71xF 7 0xE000 0000 APB2 6 0xC000 0000 APB1 External Memory Space 64 MBytes 5 0xA000 0000 PRCCU 0x6C00 0x6C00 0x6C00 0x6C00 000C 0008 0004 0000 BCON3 BCON2 BCON1 BCON0 register register register register 4 0x66FF FFFF 0x8000 0000 Reserved Bank3 CSn.3 16M 3 0x6000 0000 EXTMEM 0x6600 0000 0x64FF FFFF Bank2 CSn.2 16M 0x6400 0000 2 0x4000 0000 FLASH 0x62FF FFFF Bank1 CSn.1 16M 0x6200 0000 0x60FF FFFF 1 CSn.0 0x2000 0000 RAM Bank0 16M 0x6000 0000 0 0x0000 0000 FLASH/RAM/EMI Reserved Drawing not in scale 32/77 STR71xF Electrical parameters 5 5.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA=25°C, V33=3.3V (for the 3.0V≤V33≤3.6V voltage range) and V18=1.8V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage STR7 PIN STR7 PIN L=50pF VIN 33/77 Electrical parameters STR71xF 5.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Voltage characteristics Ratings External 3.3V Supply voltage (including AVDD and V33IOPLL) 2) Symbol Min Max Unit V33- VSS -0.3 4.0 V18BKP - VSSBKP Digital 1.8V Supply voltage on V18BKP backup supply 2) Input voltage on true open drain pin (P0.10) 1) Input voltage on any other pin 1) Variations between different 3.3V power pins Variations between different 1.8V power pins 5) Variations between all the different ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) -0.3 2.0 V VSS-0.3 VSS-0.3 50 25 50 +5.5 V33+0.3 50 25 50 mV VIN |∆V33x| |∆V18x| |VSSX - VSS| VESD(HBM) VESD(MM) see : Absolute Maximum Ratings (Electrical Sensitivity) on page 48 34/77 STR71xF Table 10. Symbol IV33 IVSS IIO Electrical parameters Current characteristics Ratings Total current into V33/V33IO-PLL power lines (source) 2) Total current out of VSS/VSSIO-PLL ground lines (sink) 2) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on RSTIN pin IINJ(PIN) 1) & 3) Injected current on CK pin Injected current on any other pin 4) ΣIINJ(PIN) 1) Notes: 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>V33 while a negative injection is induced by VINV33 while a negative injection is induced by VIN