STR71xF
ARM7TDMI™ 32-bit MCU with Flash, USB, CAN
5 timers, ADC, 10 communications interfaces
Features
■
■
■
■
■
Core
– ARM7TDMI 32-bit RISC CPU
– 59 MIPS @ 66 MHz from SRAM
– 45 MIPS @ 50 MHz from Flash
LQFP64
10 x 10
Memories
– Up to 256 Kbytes Flash program memory
(10 kcycles endurance, 20 years retention
@ 85° C)
– 16 Kbytes Flash data memory
(100 kcycles endurance, 20 years
retention@ 85° C)
– Up to 64 Kbytes RAM
– External Memory Interface (EMI) for up to 4
banks of SRAM, Flash, ROM
– Multi-boot capability
LFBGA64 8 8x x8 8x x1.7
LFBGA64
1.7
Clock, reset and supply management
– 3.0 to 3.6V application supply and I/Os
– Internal 1.8V regulator for core supply
– Clock input from 0 to 16.5 MHz
– Embedded RTC osc. running from external
32 kHz crystal
– Embedded PLL for CPU clock
– Realtime Clock for clock-calendar function
– 5 power saving modes: SLOW, WAIT,
LPWAIT, STOP and STANDBY modes
Nested interrupt controller
– Fast interrupt handling with multiple vectors
– 32 vectors with 16 IRQ priority levels
– 2 maskable FIQ sources
Up to 48 I/O ports
– 30/32/48 multifunctional bidirectional I/Os
Up to 14 ports with interrupt capability
February 2008
LQFP144
20 x 20
LFBGA144 10 x 10 x 1.7
■
5 Timers
– 16-bit watchdog timer
– 3 16-bit timers with 2 input captures, 2
output compares, PWM and pulse counter
– 16-bit timer for timebase functions
■
10 communications interfaces
– 2 I2C interfaces (1 multiplexed with SPI)
– 4 UART asynchronous serial interfaces
– Smartcard ISO7816-3 interface on UART1
– 2 BSPI synchronous serial interfaces
– CAN interface (2.0B Active)
– USB Full Speed (12 Mbit/s) Device
Function with Suspend and Resume
– HDLC synchronous communications
■
4-channel 12-bit A/D converter
– Sampling frequency up to 1 kHz
– Conversion range: 0 to 2.5 V
■
Development tools support
– Atomic bit SET and RES operations
Table 1.
Device summary
Reference
Root part number
STR71xF
STR710FZ1, STR710FZ2,
STR711FR0, STR711FR1, STR711FR2,
STR712FR0, STR712FR1, STR712FR2,
STR715FR0
Rev 12
1/78
www.st.com
78
Contents
STR71xF
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
3.1
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
Pin description for 144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4
Pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
External connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6
I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1
2/78
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.2
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.3
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.4
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3.5
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.6
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.7
EMI - external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.8
I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.9
BSPI - buffered serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.10
USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3.11
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
STR71xF
5
Contents
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6
Product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Note:
For detailed information on the STR71x Microcontroller memory, registers and peripherals,
please refer to the STR71x Reference Manual.
3/78
Introduction
1
STR71xF
Introduction
This datasheet provides the STR71x pinout, ordering information, mechanical and electrical
device characteristics.
For complete information on the STR71x microcontroller memory, registers and peripherals.
please refer to the STR71x reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STR7 Flash programming reference manual.
For information on the ARM7TDMI core please refer to the ARM7TDMI technical reference
manual.
Table 2.
Device overview
Features
STR710
FZ1
STR710
FZ2
STR710
RZ
STR711
FR0
STR711
FR1
STR711
FR2
STR712
FR0
STR712
FR1
STR712
FR2
STR715
FRx
Flash - Kbytes
128+16
256+16
0
64+16
128+16
256+16
64+16
128+16
256+16
64+16
RAM - Kbytes
32
64
64
16
32
64
16
32
64
16
Peripheral
Functions
CAN, EMI, USB, 48 I/Os
USB, 30 I/Os
Operating
Voltage
3.0 to 3.6 V
Operating
Temperature
-40 to +85°C or 0 to 70° C
T=LQFP144 20 x 20
H=LFBGA144 10 x10
Packages
.
4/78
CAN, 32 I/Os
T=LQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7
32 I/Os
STR71xF
2
Description
Description
ARM® core with embedded Flash and RAM
The STR71x series is a family of ARM-powered 32-bit microcontrollers with embedded
Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive
range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip
high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have
high-speed RAM but no internal Flash. The STR71x family has an embedded ARM core and
is therefore compatible with all ARM tools and software.
Extensive tools support
STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete
range of high-end and low-cost development tools to meet the needs of application
developers. This extensive line of hardware/software tools includes starter kits and complete
development packages all tailored for ST’s ARM core-based MCUs. The range of
development packages includes third-party solutions that come complete with a graphical
development environment and an in-circuit emulator/programmer featuring a JTAG
application interface. These support a range of embedded operating systems (OS), while
several royalty-free OSs are also available.
For more information, please refer to ST MCU site http://www.st.com/mcu
5/78
System architecture
3
STR71xF
System architecture
Package choice: low pin-count 64-pin or feature-rich 144-pin LQFP or BGA
The STR71x family is available in 5 main versions.
The 144-pin versions have the full set of all features including CAN, USB and External
Memory Interface (EMI).
●
STR710F: 144-pin BGA or LQFP with CAN, USB and EMI
●
STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash
memory)
The three 64-pin versions (BGA or LQFP) do not include External Memory Interface.
●
STR715F: 64-pin BGA or LQFP without CAN or USB
●
STR711F: 64-pin BGA or LQFP with USB
●
STR712F: 64-pin BGA or LQFP with CAN
High speed Flash memory (STR71xF)
The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories
enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size,
typically for the application program code. Bank 1 is 16 Kbytes, typically used for storing
data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz
Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K
write/erase cycles. Data retention is 20 years at 85°C on both banks. The two banks can be
accessed independently in read or write. Flash memory can be accessed in two modes:
●
Burst mode: 64-bit wide memory access at up to 50 MHz.
●
Direct 32-bit wide memory access for deterministic operation at up to 33 MHz.
The STR7 embedded Flash memory can be programmed using In-Circuit Programming or
In-Application programming.
IAP (in-application programming): The IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
ICP (in-circuit programming): The ICP is the ability to program the Flash memory of a
microcontroller using JTAG protocol while the device is mounted on the user application
board.
The Flash memory can be protected against different types of unwanted access
(read/write/erase). There are two types of protection:
●
Sector Write Protection
●
Flash Debug Protection (locks JTAG access)
Refer to the STR7 Flash Programming Reference manual for details.
Optional external memory (STR710)
The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin)
supports four 16-Mbyte banks of external memory. Wait states are programmable
individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM
etc.) to be used to store programs or data.
Figure 1 shows the general block diagram of the device family.
6/78
STR71xF
System architecture
Flexible power management
To minimize power consumption, you can program the STR71x to switch to SLOW, WAIT,
LPWAIT (low power wait), STOP or STANDBY mode depending on the current system
activity in the application.
Flexible clock control
Two external clock sources can be used, a main clock and a 32 kHz backup clock. The
embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main
clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a
wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2
peripherals are in separate clock domains and can be programmed to run at different
frequencies during application runtime. The clock to each peripheral is gated with an
individual control bit to optimize power usage by turning off peripherals any time they are not
required.
Voltage regulators
The STR71x requires an external 3.0-3.6V power supply. There are two internal Voltage
Regulators for generating the 1.8V power supply for the core and peripherals. The main VR
is switched off during low power operation.
Low voltage detectors
Both the Main Voltage Regulator and the Low Power Voltage Regulator contain each a low
voltage detection circuitry which keep the device under reset when the corresponding
controlled voltage value (V18 or V18BKP) falls below 1.35V (+/- 10%). This enhances the
security of the system by preventing the MCU from going into an unpredictable state.
An external reset circuit must be used to provide the RESET at V33 power-up. It is not
sufficient to rely on the RESET generated by the LVD in this case. This is because LVD
operation is guaranteed only when V33 is within the specification.
3.1
On-chip peripherals
CAN interface (STR710 and STR712)
The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate
can be programmed up to 1 MBaud.
USB interface (STR710 and STR711)
The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32
unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous
transfers and USB Suspend/Resume functions.
Standard timers
Each of the four timers have a 16-bit free-running counter with 7-bit prescaler
Three timers each provide up to two input capture/output compare functions, a pulse
counter function, and a PWM channel with selectable frequency.
The fourth timer is not connected to the I/O ports. It can be used by the application software
for general timing functions.
7/78
System architecture
STR71xF
Realtime clock (RTC)
The RTC provides a set of continuously running counters driven by the 32 kHz external
crystal. The RTC can be used as a general timebase or clock/calendar/alarm function.
When the STR71x is in Standby mode the RTC can be kept running, powered by the low
power voltage regulator and driven by the 32 kHz external crystal.
UARTs
The 4 UARTs allow full duplex, asynchronous, communications with external devices with
independently programmable TX and RX baud rates up to 1.25 Mb/s.
Smartcard interface
UART1 is configurable to function either as a general purpose UART or as an asynchronous
Smartcard interface as defined by ISO 7816-3. It includes Smartcard clock generation and
provides support features for synchronous cards.
Buffered serial peripheral interfaces (BSPI)
Each of the two SPIs allow full duplex, synchronous communications with external devices,
master or slave communication at up to 5.5 Mb/s in Master mode and 4 Mb/s in Slave mode.
I2C interfaces
The two I2C Interfaces provide multi-master and slave functions, support normal and fast
I2C mode (400 kHz) and 7 or 10-bit addressing modes.
One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may
be used at a time.
HDLC interface
The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ,
NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator.
A/D converter
The Analog to Digital Converter, converts in single channel or up to 4 channels in singleshot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The
input voltage range is 0-2.5V.
Watchdog
The 16-bit Watchdog Timer protects the application against hardware or software failures
and ensures recovery by generating a reset.
I/O ports
The 48 I/O ports are programmable as Inputs or Outputs.
External interrupts
Up to 14 external interrupts are available for application use or to wake up the application
from STOP mode.
8/78
STR71xF
System architecture
Figure 1.
STR71x block diagram
A[19:0]
D[15:0]
RDN
WEN[1:0]
JTDI
JTCK
JTMS
JTRST
JTDO
DBGRQS
BOOTEN
PRCCU/PLL
EXT. MEM.
INTERFACE (EMI)
ARM7TDMI
CPU
FLASH*
Program Memory
64/128/256K
ARM7 NATIVE BUS
CK
CKOUT
RSTIN
A[23:20] (AF)
CS[3:0)
JTAG
16K Data FLASH*
RAM
16/32/64K
APB
BRIDGE 1
V18[1:0]
V33[6:0]
VSS[9:0]
V18BKP
AVDD
AVSS
POWER SUPPLY
VREG
INTERRUPT CTL(EIC)
I2C1
2 AF
A/D
BSPI0
4 AF
TIMER0
BSPI1
4 AF
4 AF
TIMER1
UART0
2 AF
2 AF
TIMER2
UART1 /
SMARTCARD
3 AF
4 AF
TIMER3
UART2
2 AF
RTC
UART3
2 AF
EXT INT (XTI)
HDLC
3 AF
OSC
14 AF
APB BUS
2 AF
APB BUS
I2C0
4 AF
STDBY
RTCXTO
RTCXTI
WAKEUP
APB
BRIDGE 2
WATCHDOG
USB
P0[15:0]
I/O PORT 0
P1[15:0]
I/O PORT 1
P2[15:0]
I/O PORT 2
1 AF
CAN
*Flash present in STR710F, not in STR710R
USBDP
USBDN
2 AF
AF: alternate function on I/O port pin
9/78
System architecture
3.2
STR71xF
Related documentation
Available from www.arm.com:
ARM7TDMI Technical reference manual
Available from http://www.st.com:
STR71x Reference manual
STR7 Flash programming manual
AN1774 - STR71x Software development getting started
AN1775 - STR71x Hardware development getting started
AN1776 - STR71x Enhanced interrupt controller
AN1777 - STR71x memory mapping
AN1780 - Real time clock with STR71x
AN1781 - Four 7 segment display drive using the STR71x
The above is a selected list only, a full list STR71x application notes can be viewed at
http://www.st.com.
10/78
STR71xF
Pin description for 144-pin packages
STR710 LQFP pinout
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P0.9/U0.TX/BOOT.0
P0.8/U0.RX/U0.TX
P0.7/S1.SSN
P0.6/S1.SCLK
P0.5/S1.MOSI
VSS
V33
WEn.0
WEn.1
A.19
A.18
A.17
A.16
A.15
A.14
V18
VSS18
P0.4/S1.MISO
P0.3/S0.SSN/I1.SDA
P0.2/S0.SCLK/I1.SCL
P0.1/S0.MOSI/U3.RX
P0.0/S0.MISO/U3.TX
A.13
A.12
A.11
A.10
A.9
A.8
A.7
A.6
A.5
V33
VSS
P1.15/HTXD
N.C.
N.C.
Figure 2.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P1.14/HRXD/I0.SDA
P1.13/HCLK/I0.SCL
P1.10/USBCLK
P1.9
V33
VSS
A.4
A.3
A.2
A.1
A.0
D.15
D.14
D.13
D.12
D.11
D.10
USBDN
USBDP
P1.12/CANTX
P1.11/CANRX
N.C.
P1.8
P1.7/T1.OCMPA
VSSIO-PLL
V33IO-PLL
D.9
D.8
D.7
D.6
D.5
P1.6/T1.OCMPB
P1.5/T1.ICAPB
P1.4/T1.ICAPA
P1.3/T3.ICAPB/AIN.3
P1.2/T3.OCMPA/AIN.2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P0.10/U1.RX/U1.TX/SCDATA
RDn
P0.11/U1.TX/BOOT.1
P0.12/SCCLK
VSS
V33
P2.0/CSn.0
P2.1/CSn.1
P0.13/U2.RX/T2.OCMPA
P0.14/U2.TX/T2.ICAPA
P2.2/CSn.2
P2.3/CSn.3
P2.4/A.20
P2.5/A.21
P2.6/A.22
BOOTEN
P2.7/A.23
P2.8
N.C.
N.C.
VSS
V33
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
JTDI
JTMS
JTCK
JTDO
JTRSTn
NU
TEST
N.C.
TEST
N.C.
V33IO-PLL
N.C.
VSSIO-PLL
N.C.
DBGRQS
CKOUT
CK
P0.15/WAKEUP
N.C.
RTCXTI
RTCXTO
STDBY
RSTIN
N.C.
VSSBKP
V18BKP
N.C.
N.C.
V18
VSS18
N.C.
D.0
D.1
D.2
D.3
D.4
AVDD
AVSS
N.C.
N.C.
N.C.
P1.0/T3.OCMPB/AIN.0
P1.1/T3.ICAPA/AIN.1
3.3
System architecture
11/78
System architecture
Table 3.
STR71xF
STR710 BGA ball connections
A
B
C
D
E
F
G
H
J
K
L
M
1
P0.10
P2.0
P2.1
VSS
P2.2
P2.6
BOOT
EN
P2.12
P2.13
P2.15
JTDI
N.C.
2
VSS
RDn
P0.11
V33
P2.3
P2.8
P2.9
JTMS
JTRST
n
TEST
TEST
N.C.
3
V33
P0.9
P0.12
P0.13
P2.4
N.C.
P2.10
JTCK
NU
V33
N.C.
DBG
RQS
4
P0.6
P0.7
P0.8
P0.14
P2.5
N.C.
P2.11
JTDO
CK
CKOUT
VSSIOPLL
N.C.
5
A.19
WEn.1
WEn.0
P0.5
P2.7
VSS
P2.14
N.C.
RTCXTO
RTCXTI
N.C.
P0.15
6
P0.3
A.15
A.16
A.17
A.18
V33
V18
N.C.
N.C.
V18BK
P
VSS
BKP
STDBY
7
P0.2
P0.1
P0.4
VSS18
V18
A.14
D.12
D.1
D.0
nc
VSS18
RSTIN
8
A.9
A.10
A.11
A.13
P0.0
A.0
D.11
P1.12/
CANTX
N.C.
AVSS
D.3
D.2
9
VSS
V33
A.5
A.6
V33
D.15
D.10
P1.8
D.9
P1.0
N.C.
N.C.
10
A.8
N.C.
P1.15
P1.13
VSS
D.14
USBDN
P1.7
D.8
P1.5
P1.1
D.4
11
A.7
N.C.
P1.14
P1.10
A.2
D.13
USBDP
VSS
D.5
P1.4
P1.3
AVDD
12
A.12
A.4
A.3
P1.9
A.1
P1.11/
CANRX
N.C.
V33IOPLL
P1.6
D.7
D.6
P1.2
Legend / abbreviations for Table 4:
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
TT= TTL 0.8 V/2 V with input trigger
C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8 V / 2 V
Port and control configuration:
12/78
Input:
pu/pd= software enabled internal pull-up or pull down
pu= in reset state, the internal 100kΩ weak pull-up is enabled.
pd = in reset state, the internal 100kΩ weak pull-down is enabled.
Output:
OD = open drain (logic level)
PP = push-pull
T = true OD, (P-Buffer and protection diode to VDD not implemented),
5 V tolerant.
STR71xF
PP
OD
Output
Capability
interrupt
Input
Input level
Pin name
Type
BGA144
LQFP144
Pin n°
Active in Stdby
STR710 pin description
Reset state1)
Table 4.
System architecture
Main
function
(after
reset)
Alternate function
UART1:
Receive Data
input
UART1: Transmit
data output.
Note: This pin may be used for
Port 0.10 Smartcard DataIn/DataOut or single
wire UART (half duplex) if
programmed as Alternate Function
Output. The pin will be tri-stated
except when UART transmission is in
progress
1
A1
P0.10/U1.RX/
U1.TX/
SC.DATA
I/O pd
2
B2
RD
O
3
C2
P0.11/BOOT.1
I/O pd
/U1.TX
CT
4
C3
P0.12/SC.CLK I/O pd
CT
5
D1
VSS
S
Ground voltage for digital I/Os4)
6
D2
V33
S
Supply voltage for digital I/Os4)
CT
X 4mA
T
X
External Memory Interface: Active low read signal
for external memory. It maps to the OE_N input of
the external components.
4mA X
X
Select Boot
Port 0.11 Configuration
input
4mA X
X
Port 0.12 Smartcard reference clock output
5)
UART1: Transmit
data output.
CT
8mA X
X
Port 2.0
External Memory Interface: Select
Memory Bank 0 output
Note: This pin is forced to output
push-pull 1 mode at reset to allow
boot from external memory
2)
CT
8mA X
X
Port 2.1
External Memory Interface: Select
Memory Bank 1 output
P0.13/U2.RX/
T2.OCMPA
I/O pu
CT
X 4mA X
X
UART2:
Port 0.13 Receive Data
input
Timer2: Output
Compare A output
D4
P0.14/U2.TX/
T2.ICAPA
I/O pu
CT
4mA X
X
UART2:
Port 0.14 Transmit data
output
Timer2: Input
Capture A input
11
E1
P2.2/CS.2
I/O
CT
8mA X
X
Port 2.2
External Memory Interface: Select
Memory Bank 2 output
12
E2
P2.3/CS.3
I/O
CT
8mA X
X
Port 2.3
External Memory Interface: Select
Memory Bank 3 output
7
B1
P2.0/CS.0
I/O
8
C1
P2.1/CS.1
I/O
9
D3
10
8)
pu
pu
2)
pu
2)
13/78
System architecture
Capability
Output
Main
function
(after
reset)
P2.4/A.20
I/O
14
E4
P2.5/A.21
I/O
15
F1
P2.6/A.22
I/O
16
G1 BOOTEN
17
E5
P2.7/A.23
I/O
3)
CT
8mA X
X
Port 2.7
External Memory Interface: address
bus
18
F2
P2.8
I/O pu
CT
X 4mA X
X
Port 2.8
External interrupt INT2
19
F3
N.C.
Not connected (not bonded)
20
F4
N.C.
Not connected (not bonded)
21
F5
VSS
S
Ground voltage for digital I/Os4)
22
F6
V33
S
Supply voltage for digital I/Os4)
23
G2 P2.9
I/O pu
CT
X 4mA X
X
Port 2.9
External interrupt INT3
24
G3 P2.10
I/O pu
CT
X 4mA X
X
Port 2.10
External interrupt INT4
25
G4 P2.11
I/O pu
CT
X 4mA X
X
Port 2.11
External interrupt INT5
26
H1
P2.12
I/O pu
CT
4mA X
X
Port 2.12
27
J1
P2.13
I/O pu
CT
4mA X
X
Port 2.13
28
G5 P2.14
I/O pu
CT
4mA X
X
Port 2.14
29
K1
P2.15
I/O pu
CT
4mA X
X
Port 2.15
30
L1
JTDI
I
TT
JTAG Data input. External pull-up required.
31
H2
JTMS
I
TT
JTAG Mode Selection Input. External pull-up
required.
32
H3
JTCK
I
C
JTAG Clock Input. External pull-up or pull-down
required.
33
H4
JTDO
O
34
J2
JTRST
I
35
J3
NU
Reserved, must be forced to ground.
36
K2
TEST
Reserved, must be forced to ground.
37
M1 N.C.
Not connected (not bonded)
38
L2
TEST
Reserved, must be forced to ground.
39
L3
N.C.
Not connected (not bonded)
14/78
pd
3)
pd
3)
pd
3)
I
PP
E3
OD
13
Pin name
interrupt
BGA144
Input level
Input
LQFP144
Type
Pin n°
Active in Stdby
STR710 pin description
Reset state1)
Table 4.
STR71xF
CT
8mA X
X
Port 2.4
CT
8mA X
X
Port 2.5
CT
8mA X
X
Port 2.6
8mA
TT
External Memory Interface: address
bus
Boot control input. Enables sampling of
BOOT[1:0] pins
CT
pd
Alternate function
X
JTAG Data output. Note: Reset state = HiZ.
JTAG Reset Input. External pull-up required.
STR71xF
M4 N.C.
42
L4
43
M2 N.C.
44
M3 DBGRQS
I
45
K4
CKOUT
O
46
J4
CK
I
C
47
M5
P0.15/
WAKEUP
I
TT
VSSIO-PLL
PP
41
V33IO-PLL
OD
K3
Output
Capability
40
Pin name
interrupt
BGA144
Input level
Input
LQFP144
Type
Pin n°
Active in Stdby
STR710 pin description
Reset state1)
Table 4.
System architecture
Main
function
(after
reset)
Alternate function
Supply voltage for digital I/O circuitry and for PLL
reference
S
Not connected (not bonded)
Ground voltage for digital I/O circuitry and for PLL
reference4)
S
Not connected (not bonded)
CT
Debug Mode request input (active high)
8mA
Clock output (fPCLK2) Note: Enabled by CKDIS
register in APB Bridge 2
X
Reference clock input
Port 0.15
X
Wakeup from Standby mode input.
X
Note: This port is input only.
48
L5
N.C.
Not connected (not bonded)
49
K5
RTCXTI
Realtime Clock input and input of 32 kHz
oscillator amplifier circuit
50
J5
RTCXTO
Output of 32 kHz oscillator amplifier circuit
51
M6 STDBY
I/O
CT
52
M7 RSTIN
I
CT
53
H5
N.C.
54
L6
VSSBKP
4mA X
Input: Hardware Standby mode entry input active
low. Caution: External pull-up to V33 required to
select normal mode.
X Output: Standby mode active low output following
Software Standby mode entry.
Note: In Standby mode all pins are in high
impedance except those marked Active in Stdby
X Reset input
Not connected (not bonded)
S
X Stabilization for low power voltage regulator.
S
Stabilization for low power voltage regulator.
Requires external capacitors of at least 1µF
between V18BKP and VSS18BKP. See Figure 5.
X
Note: If the low power voltage regulator is
bypassed, this pin can be connected to an
external 1.8V supply.
55
K6
V18BKP
56
J6
N.C.
Not connected (not bonded)
57
H6
N.C.
Not connected (not bonded)
58
G6 V18
S
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF + 33nF
between V18 and VSS18. See Figure 5.
15/78
System architecture
N.C.
61
J7
D.0
S
I/O
8mA
8mA
H7
D.1
I/O
63
M8 D.2
I/O
6)
8mA
I/O
6)
8mA
I/O
6)
8mA
D.3
65
M10 D.4
66
M11 VDDA
Alternate function
Not connected (not bonded)
6)
62
L8
Main
function
(after
reset)
Stabilization for main voltage regulator.
6)
64
PP
K7
OD
60
Output
Capability
VSS18
interrupt
L7
Input
Input level
BGA144
59
Pin name
Type
LQFP144
Pin n°
Active in Stdby
STR710 pin description
Reset state1)
Table 4.
STR71xF
External Memory Interface: data bus
S
Supply voltage for A/D Converter
S
Ground voltage for A/D Converter
67
K8
VSSA
68
J8
N.C.
Not connected (not bonded)
69
M9 N.C.
Not connected (not bonded)
70
L9
N.C.
Not connected (not bonded)
71
K9
P1.0/T3.OCM
PB/AIN.0
72
P1.1/T3.ICAP
L10 A/T3.EXTCLK/ I/O pu
AIN.1
73
M12
P1.2/T3.OCM
PA/AIN.2
74
L11
75
I/O pu
CT
4mA X
X
Port 1.0
Timer 3:
Output
Compare B
ADC: Analog input 0
CT
4mA X
X
Port 1.1
Timer 3: Input
Capture A or
ADC: Analog input 1
External Clock
input
I/O pu
CT
4mA X
X
Port 1.2
Timer 3:
Output
Compare A
ADC: Analog input 2
P1.3/T3.ICAP
B/AIN.3
I/O pu
CT
4mA X
X
Port 1.3
Timer 3: Input
Capture B
ADC: Analog input 3
K11
P1.4/T1.ICAP
A/T1.EXTCLK
I/O pu
CT
4mA X
X
Port 1.4
Timer 1: Input
Capture A
Timer 1: External
Clock input
76
K10
P1.5/T1.ICAP
B
I/O pu
CT
4mA X
X
Port 1.5
Timer 1: Input
Capture B
77
J12
P1.6/T1.OCM
PB
I/O pu
CT
4mA X
X
Port 1.6
Timer 1:
Output
Compare B
78
J11 D.5
I/O
6)
8mA
79
L12 D.6
I/O
6)
8mA
I/O
6)
8mA
I/O
6)
8mA
I/O
6)
8mA
80
81
82
16/78
K12 D.7
J10 D.8
J9
D.9
External Memory Interface: data bus
STR71xF
PP
OD
Output
Capability
interrupt
Input
Input level
Pin name
Type
BGA144
LQFP144
Pin n°
Active in Stdby
STR710 pin description
Reset state1)
Table 4.
System architecture
Main
function
(after
reset)
Alternate function
83
H12 V33IO-PLL
S
Supply voltage for digital I/O circuitry and for PLL
reference4)
84
H11 VSSIO-PLL
S
Ground voltage for digital I/O circuitry and for PLL
reference4)
85
H10
P1.7/T1.OCM
PA
I/O pu
CT
4mA X
X
86
H9
P1.8
I/O pd
CT
4mA X
X
Port 1.7
Timer 1:
Output
Compare A
Port 1.8
87
G12 N.C.
88
F12 P1.11/CANRX I/O pu
CT
X 4mA X
X
Port 1.11
CAN: receive data input
Note: On STR710 and STR712 only
89
H8
CT
4mA X
X
Port 1.12
CAN: Transmit data output
Note: On STR710 and STR712 only
P1.12/CANTX
Not connected (not bonded)
I/O pu
90
G11 USBDP
I/O
CT
USB bidirectional data (data +). Reset state = HiZ
Note: On STR710 and STR711 only
This pin requires an external pull-up to V33 to
maintain a high level.
91
G10 USBDN
I/O
CT
USB bidirectional data (data -). Reset state = HiZ
Note: On STR710 and STR711 only.
92
G9 D.10
I/O
6)
8mA
93
G8 D.11
I/O
6)
8mA
I/O
6)
8mA
8mA
94
G7 D.12
External Memory Interface: data bus
95
F11 D.13
I/O
6)
96
F10 D.14
I/O
6)
8mA
97
F9
I/O
6)
8mA
O
7)
8mA
X
O
7)
8mA
X
100 E11 A.2
O
7)
8mA
X
101 C12 A.3
O
7)
8mA
X
102 B12 A.4
O
7)
8mA
X
103 E10 VSS
S
Ground voltage for digital I/O circuitry4)
104
S
Supply voltage for digital I/O circuitry4)
98
99
F8
D.15
A.0
E12 A.1
E9
V33
105 D12 P1.9
106 D11
P1.10/
USBCLK
External Memory Interface: address bus
I/O pd
CT
4mA X
X
Port 1.9
I/O pd
C/
T
4mA X
X
Port 1.10
USB: 48 MHZ
clock input
17/78
System architecture
STR710 pin description
X
Port 1.13
HDLC:
reference
clock input
I2C clock
108 C11
P1.14/HRXD/
I0.SDA
I/O pu
CT
X 4mA X
X
Port 1.14
HDLC:
Receive data
input
I2C serial data
PP
X 4mA X
OD
CT
Capability
I/O pd
Pin name
Type
P1.13/HCLK/
I0.SCL
BGA144
107 D10
LQFP144
interrupt
Output
Input level
Input
Reset state1)
Pin n°
Active in Stdby
Table 4.
STR71xF
Main
function
(after
reset)
Alternate function
109 B11 N.C.
Not connected (not bonded)
110 B10 N.C.
Not connected (not bonded)
111 C10 P1.15/HTXD
I/O pu
CT
4mA X
X
Port 1.15
HDLC: Transmit data output
112
A9
VSS
S
Ground voltage for digital I/O circuitry4)
113
B9
V33
S
Supply voltage for digital I/O circuitry4)
114
C9
A.5
O
7)
8mA
X
115
D9
A.6
O
7)
8mA
X
O
7)
8mA
X
O
7)
8mA
X
8mA
X
116 A11 A.7
117 A10 A.8
118
A8
A.9
O
7)
119
B8
A.10
O
7)
8mA
X
O
7)
8mA
X
O
7)
8mA
X
O
7)
8mA
X
120
C8
A.11
121 A12 A.12
122
D8
A.13
External Memory Interface: address bus
SPI0 Master
in/Slave out
data
123
E8
P0.0/S0.MISO
I/O pu
/U3.TX
CT
4mA X
X
Port 0.0
UART3 Transmit data
output
Note: Programming AF function
selects UART by default. BSPI must
be enabled by SPI_EN bit in the
BOOTCR register.
BSPI0: Master
UART3: Receive
out/Slave in
Data input
data
124
18/78
B7
P0.1/S0.MOSI
I/O pu
/U3.RX
CT
X 4mA X
X
Port 0.1
Note: Programming AF function
selects UART by default. BSPI must
be enabled by SPI_EN bit in the
BOOTCR register.
STR71xF
PP
OD
Output
Capability
interrupt
Input
Input level
Pin name
Type
BGA144
LQFP144
Pin n°
Active in Stdby
STR710 pin description
Reset state1)
Table 4.
System architecture
Main
function
(after
reset)
Alternate function
BSPI0: Serial
Clock
125
A7
P0.2/S0.SCLK
I/O pu
/I1.SCL
CT
X 4mA X
X
Port 0.2
I2C1: Serial clock
Note: Programming AF function
selects I2C by default. BSPI must be
enabled by SPI_EN bit in the
BOOTCR register.
SPI0: Slave
Select input
active low.
I2C1: Serial Data
126
A6
P0.3/S0.SS/
I1.SDA
I/O pu
CT
4mA X
X
Port 0.3
Note: Programming AF function
selects I2C by default. BSPI must be
enabled by SPI_EN bit in the
BOOTCR register.
127
C7
P0.4/S1.MISO I/O pu
CT
4mA X
X
Port 0.4
SPI1: Master in/Slave out data
128
D7
VSS18
S
Stabilization for main voltage regulator.
129
E7
V18
S
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF + 33nF
between V18 and VSS18. See Figure 5.
130
F7
A.14
O
7)
8mA
X
O
7)
8mA
X
O
7)
8mA
X
8mA
X
131
132
B6
C6
A.15
A.16
External Memory Interface: address bus
133
D6
A.17
O
7)
134
E6
A.18
O
7)
8mA
X
8mA
X
135
A5
A.19
O
7)
136
B5
WE.1
O
5)
8mA
X
External Memory Interface: active low MSB write
enable output
137
C5
WE.0
O
5)
8mA
X
External Memory Interface: active low LSB write
enable output
138
A3
V33
S
Supply voltage for digital I/Os4)
139
A2
VSS
S
Ground voltage for digital I/Os4)
140
D5
P0.5/S1.MOSI I/O pu
CT
4mA X
X
Port 0.5
SPI1: Master out/Slave In data
141
A4
P0.6/S1.SCLK I/O pu
CT
X 4mA X
X
Port 0.6
SPI1: Serial Clock
142
B4
P0.7/S1.SS
CT
4mA X
X
Port 0.7
SPI1: Slave Select input active low
I/O pu
19/78
System architecture
PP
OD
Output
Capability
interrupt
Input
Input level
Pin name
Type
BGA144
LQFP144
Pin n°
Active in Stdby
STR710 pin description
Reset state1)
Table 4.
STR71xF
Main
function
(after
reset)
Port 0.8
143
C4
P0.8/U0.RX/
U0.TX
I/O pd
CT
144
B3
P0.9/U0.TX/
BOOT.0
I/O pd
CT
X 4mA
T
4mA X
Alternate function
UART0:
Receive Data
input
UART0: Transmit
data output.
Note: This pin may be used for single wire UART
(half duplex) if programmed as Alternate Function
Output. The pin will be tri-stated except when
UART transmission is in progress
X
Port 0.9
Select Boot
Configuration
input
UART0: Transmit
data output
1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 8 on page 29.
The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends
on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset
2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured
by software as Alternate Function (see Table 8: Port bit configuration table on page 29) to be used by the
External Memory Interface.
3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address
0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they
need to be configured by software as Alternate Function (see Table 8: Port bit configuration table on
page 29).
4. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected.
5. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as
Output Push-Pull.
6. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as
Hi-Z.
7. During the reset phase, these pins are in input pull-down state. When reset is released, they are configured
as Output Push-Pull.
8. During the reset phase, this pin is in input floating state. When reset is released, it is configured as Output
Push-Pull.
20/78
STR71xF
Pin description for 64-pin packages
STR712/STR715 LQFP64 pinout
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P0.9/U0.TX/BOOT.0
P0.8/U0.RX/U0.TX
P0.7/S1.SSN
P0.6/S1.SCLK
P0.5/S1.MOSI
VSS
V18
VSS18
P0.4/S1.MISO
P0.3/S0.SSN/I1.SDA
P0.2/S0.SCLK/I1.SCL
P0.1/S0.MOSI/U3.RX
P0.0/S0.MISO/U3.TX
V33
VSS
P1.15/HTXD
Figure 3.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.14/HRXD/I0.SDA
P1.13/HCLK/I0.SCL
P1.10
P1.9
VSS
P1.12/CANTX1)
P1.11/CANRX1)
P1.8
P1.7/T1.OCMPA
VSSIO-PLL
V33IO-PLL
P1.6/T1.OCMPB
P1.5/T1.ICAPB
P1.4/T1.ICAPA
P1.3/T3.ICAPB/AIN.3
P1.2/T3.OCMPA/AIN.2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P0.10/U1.RX/U1.TX/SCDATA
P0.11/U1.TX/BOOT.1
P0.12/SCCLK
VSS
P0.13/U2.RX/T2.OCMPA
P0.14/U2.TX/T2.ICAPA
BOOTEN
VSS
V33
JTDI
JTMS
JTCK
JTDO
nJTRST
NU
TEST
V33IO-PLL
VSSIO-PLL
CK
P0.15/WAKEUP
RTCXTI
RTCXTO
STDBY
RSTIN
VSSBKP
V18BKP
V18
VSS18
AVDD
AVSS
P1.0/T3.OCMPB/AIN.0
P1.1/T3.ICAPA/AIN.1
3.4
System architecture
1)
CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.
21/78
System architecture
STR71xF
STR711 LQFP64 pinout
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P0.9/U0.TX/BOOT.0
P0.8/U0.RX/U0.TX
P0.7/S1.SSN
P0.6/S1.SCLK
P0.5/S1.MOSI
VSS
V18
VSS18
P0.4/S1.MISO
P0.3/S0.SSN/I1.SDA
P0.2/S0.SCLK/I1.SCL
P0.1/S0.MOSI/U3.RX
P0.0/S0.MISO/U3.TX
V33
VSS
P1.15/HTXD
Figure 4.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LQFP64
P1.14/HRXD/I0.SDA
P1.13/HCLK/I0.SCL
P1.10/USBCLK
P1.9
VSS
USBDN
USBDP
P1.8
P1.7/T1.OCMPA
VSSIO-PLL
V33IO-PLL
P1.6/T1.OCMPB
P1.5/T1.ICAPB
P1.4/T1.ICAPA
P1.3/T3.ICAPB/AIN.3
P1.2/T3.OCMPA/AIN.2
V33IO-PLL
VSSIO-PLL
CK
P0.15/WAKEUP
RTCXTI
RTCXTO
STDBY
RSTIN
VSSBKP
V18BKP
V18
VSS18
AVDD
AVSS
P1.0/T3.OCMPB/AIN.0
P1.1/T3.ICAPA/AIN.1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P0.10/U1.RX/U1.TX/SCDATA
P0.11/U1.TX/BOOT.1
P0.12/SCCLK
VSS
P0.13/U2.RX/T2.OCMPA
P0.14/U2.TX/T2.ICAPA
BOOTEN
VSS
V33
JTDI
JTMS
JTCK
JTDO
nJTRST
NU
TEST
Table 5.
22/78
STR711 BGA ball connections
A
B
C
D
E
F
G
H
1
P0.10
P0.11
P0.12
P0.14
V33
JTCK
TEST
V33IOPLL
2
P0.9
VSS
P0.13
VSS
JTMS
JTRSTn
P0.15
VSSIOPLL
3
P0.5
P0.7
BOOTEN
JTDI
NU
STDBY
RTCXTI
CK
4
VSS18
VSS
P0.8
JTDO
AVDD
V18BKP
RSTIN
RTCXTO
5
P0.2
P0.4
V18
P0.6
P1.9
P1.0
V18
VSSBKP
6
V33
P0.1
P0.3
P1.13
USBDP
VSSIOPLL
AVSS
VSS18
7
VSS
P0.0
P1.10
USBDN
P1.7
P1.6
P1.5
P1.1
8
P1.15
P1.14
VSS
P1.8
V33IOPLL
P1.4
P1.3
P1.2
STR71xF
System architecture
Table 6.
STR712/715 BGA Ball Connections
A
B
C
D
E
F
G
H
1
P0.10
P0.11
P0.12
P0.14
V33
JTCK
TEST
V33IOPLL
2
P0.9
VSS
P0.13
VSS
JTMS
JTRSTn
P0.15
VSSIOPLL
3
P0.5
P0.7
BOOTEN
JTDI
NU
STDBY
RTCXTI
CK
4
VSS18
VSS
P0.8
JTDO
AVDD
V18BKP
RSTIN
RTCXTO
5
P0.2
P0.4
V18
P0.6
P1.9
P1.0
V18
VSSBKP
6
V33
P0.1
P0.3
P1.13
P1.11/
CANRX1)
VSSIOPLL
AVSS
VSS18
7
VSS
P0.0
P1.10
P1.12/
CANTX1)
P1.7
P1.6
P1.5
P1.1
8
P1.15
P1.14
VSS
P1.8
V33IOPLL
P1.4
P1.3
P1.2
1)
CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.
Legend / abbreviations for Table 7:
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
TT= TTL 0.8V / 2V with input trigger
C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V
Port and control configuration:
Input:
pu/pd= software enabled internal pull-up or pull down
pu= in reset state, the internal 100kΩ weak pull-up is enabled.
pd = in reset state, the internal 100kΩ weak pull-down is enabled.
Output:
OD = open drain (logic level)
PP = push-pull
T = true OD, (P-Buffer and protection diode to VDD not implemented),
5V tolerant.
23/78
System architecture
PP
OD
Output
Capability
interrupt
Input
Input level
Pin name
Type
BGA64
LQFP64
Pin n°
Active in Stdby
STR711/STR712/STR715 pin description
Reset state1)
Table 7.
STR71xF
Main
function
(after
reset)
Alternate function
UART1:
Receive Data
input
1
P0.10/U1.RX/
A1 U1.TX/
SC.DATA
2
B1
UART1: Transmit data
output.
Note: This pin may be used for
Port 0.10 Smartcard DataIn/DataOut or single
wire UART (half duplex) if programmed
as Alternate Function Output. The pin
will be tri-stated except when UART
transmission is in progress
I/O pd
CT
X 4mA
T
P0.11/BOOT.1
I/O pd
/U1.TX
CT
4mA
X
X
Select Boot
Port 0.11 Configuration
input
3
C1 P0.12/SC.CLK I/O pd
CT
4mA
X
X
Port 0.12 Smartcard reference clock output
4
B2 VSS
5
C2
P0.13/U2.RX/
T2.OCMPA
I/O pu
CT
X 4mA
X
X
UART2:
Port 0.13 Receive Data
input
Timer2: Output
Compare A output
6
D1
P0.14/U2.TX/
T2.ICAPA
I/O pu
CT
4mA
X
X
UART2:
Port 0.14 Transmit data
output
Timer2: Input Capture
A input
7
C3 BOOTEN
I
8
D2 VSS
S
Ground voltage for digital I/Os2)
9
E1 V33
S
Supply voltage for digital I/Os2)
UART1: Transmit data
output.
Ground voltage for digital I/Os2)
S
Boot control input. Enables sampling of BOOT[1:0]
pins
CT
10 D3 JTDI
I
TT
JTAG Data input. External pull-up required.
11 E2 JTMS
I
TT
JTAG Mode Selection Input. External pull-up
required.
12 F1 JTCK
I
C
JTAG Clock Input. External pull-up or pull-down
required.
13 D4 JTDO
O
14 F2 JTRST
I
8mA
TT
X
JTAG Data output. Note: Reset state = HiZ.
JTAG Reset Input. External pull-up required.
15 E3 NU
Reserved, must be forced to ground.
16 G1 TEST
Reserved, must be forced to ground.
17 H1 V33IO-PLL
S
Supply voltage for digital I/O circuitry and for PLL
reference2)
18 H2 VSSIO-PLL
S
Ground voltage for digital I/O circuitry and for PLL
reference2)
19 H3 CK
I
24/78
C
Reference clock input
STR71xF
System architecture
PP
X
OD
TT
Output
Capability
interrupt
P0.15/
WAKEUP
Input
Input level
20 G2
Pin name
Type
BGA64
LQFP64
Pin n°
Active in Stdby
STR711/STR712/STR715 pin description
Reset state1)
Table 7.
Main
function
(after
reset)
Alternate function
Port 0.15 Wakeup from Standby mode input.
I
X
Note: This port is input only.
21 G3 RTCXTI
Realtime Clock input and input of 32 kHz oscillator
amplifier circuit
22 H4 RTCXTO
Output of 32 kHz oscillator amplifier circuit
23 F3 STDBY
I/O
CT
24 G4 RSTIN
I
CT
X Reset input
S
X Stabilization for low power voltage regulator.
S
Stabilization for low power voltage regulator.
Requires external capacitors of at least 1µF
between V18BKP and VSS18BKP. See Figure 5.
X
Note: If the low power voltage regulator is
bypassed, this pin can be connected to an external
1.8V supply.
25 H5 VSSBKP
26 F4 V18BKP
4mA
Input: Hardware Standby mode entry input active
low.
Caution: External pull-up to V33 required to select
normal mode.
X
Output: Standby mode active low output following
Software Standby mode entry.
Note: In Standby mode all pins are in high
impedance except those marked Active in Stdby.
X
27 G5 V18
S
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF + 33nF
between V18 and VSS18. See Figure 5.
28 H6 VSS18
S
Stabilization for main voltage regulator.
29 E4 VDDA
S
Supply voltage for A/D Converter
30 G6 VSSA
S
Ground voltage for A/D Converter
31 F5
P1.0/T3.OCM
PB/AIN.0
I/O pu
CT
4mA
X
X
Port 1.0
Timer 3: Output
ADC: Analog input 0
Compare B
P1.1/T3.ICAP
32 H7 A/T3.EXTCLK I/O pu
/AIN.1
CT
4mA
X
X
Port 1.1
Timer 3: Input
Capture A or
External Clock
input
33 H8
P1.2/T3.OCM
PA/AIN.2
I/O pu
CT
4mA
X
X
Port 1.2
Timer 3: Output
ADC: Analog input 2
Compare A
34 G8
P1.3/T3.ICAP
B/AIN.3
I/O pu
CT
4mA
X
X
Port 1.3
Timer 3: Input
Capture B
ADC: Analog input 3
35 F8
P1.4/T1.ICAP
I/O pu
A/T1.EXTCLK
CT
4mA
X
X
Port 1.4
Timer 1: Input
Capture A
Timer 1: External
Clock input
ADC: Analog input 1
25/78
System architecture
Input
CT
4mA
X
X
Port 1.5
Timer 1: Input
Capture B
37 F7
P1.6/T1.OCM
PB
I/O pu
CT
4mA
X
X
Port 1.6
Timer 1: Output
Compare B
interrupt
I/O pu
Pin name
Type
P1.5/T1.ICAP
B
BGA64
36 G7
LQFP64
PP
Main
function
(after
reset)
OD
Output
Capability
Input level
Pin n°
Active in Stdby
STR711/STR712/STR715 pin description
Reset state1)
Table 7.
STR71xF
Alternate function
38 E8 V33IO-PLL
S
Supply voltage for digital I/O circuitry and for PLL
reference2)
39 F6 VSSIO-PLL
S
Ground voltage for digital I/O circuitry and for PLL
reference2)
40 E7
P1.7/T1.OCM
PA
Timer 1: Output
Compare A
I/O pu
CT
4mA
X
X
Port 1.7
I/O pd
CT
4mA
X
X
Port 1.8
42 E6 P1.11/CANRX I/O pu
CT
X 4mA
X
X
Port 1.11
CAN: receive data input
Note: On STR710 and STR712 only
43 D7 P1.12/CANTX I/O pu
CT
4mA
X
X
Port 1.12
CAN: Transmit data output
Note: On STR710 and STR712 only
41 D8 P1.8
42 E6 USBDP
I/O
CT
USB bidirectional data (data +). Reset state = HiZ
Note: On STR710 and STR711 only
This pin requires an external pull-up to V33 to
maintain a high level.
43 D7 USBDN
I/O
CT
USB bidirectional data (data -). Reset state = HiZ
Note: On STR710 and STR711 only.
44 C8 VSS
45 E5 P1.9
Ground voltage for digital I/O circuitry2)
S
I/O pd
CT
4mA
X
X
Port 1.9
46 C7
P1.10/USBCL
K
I/O pd
C/
T
4mA
X
X
Port 1.10
47 D6
P1.13/HCLK/I
0.SCL
I/O pd
CT
X 4mA
X
X
HDLC:
Port 1.13 reference clock I2C clock
input
48 B8
P1.14/HRXD/I
I/O pu
0.SDA
CT
X 4mA
X
X
Port 1.14
CT
4mA
X
X
Port 1.15 HDLC: Transmit data output
49 A8 P1.15/HTXD
I/O pu
USB: 48 MHZ
clock input
HDLC: Receive
I2C serial data
data input
50 A7 VSS
S
Ground voltage for digital I/O circuitry2)
51 A6 V33
S
Supply voltage for digital I/O circuitry2)
26/78
STR71xF
System architecture
PP
OD
Output
Capability
interrupt
Input
Input level
Pin name
Type
BGA64
LQFP64
Pin n°
Active in Stdby
STR711/STR712/STR715 pin description
Reset state1)
Table 7.
Main
function
(after
reset)
Alternate function
SPI0 Master
in/Slave out
data
52 B7
P0.0/S0.MISO
I/O pu
/U3.TX
CT
4mA
X
X
Port 0.0
Note: Programming AF function selects
UART by default. BSPI must be
enabled by SPI_EN bit in the BOOTCR
register.
BSPI0: Master
out/Slave in
data
53 B6
P0.1/S0.MOSI
I/O pu
/U3.RX
CT
X 4mA
X
X
Port 0.1
P0.2/S0.SCLK
I/O pu
/I1.SCL
CT
X 4mA
X
X
Port 0.2
CT
4mA
56 B5 P0.4/S1.MISO I/O pu
CT
4mA
X
X
I2C1: Serial clock
Note: Programming AF function selects
I2C by default. BSPI must be enabled
by SPI_EN bit in the BOOTCR register.
SPI0: Slave
Select input
active low.
P0.3/S0.SS/I1
I/O pu
55 C6
.SDA
UART3: Receive Data
input
Note: Programming AF function selects
UART by default. BSPI must be
enabled by SPI_EN bit in the BOOTCR
register.
BSPI0: Serial
Clock
54 A5
UART3 Transmit data
output
I2C1: Serial Data
Port 0.3
Note: Programming AF function selects
I2C by default. BSPI must be enabled
by SPI_EN bit in the BOOTCR register.
X
X
Port 0.4
SPI1: Master in/Slave out data
57 A4 VSS18
S
Stabilization for main voltage regulator.
58 C5 V18
S
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF + 33nF
between V18 and VSS18. See Figure 5.
59 B4 VSS
S
Ground voltage for digital I/Os
60 A3 P0.5/S1.MOSI I/O pu
CT
4mA
X
X
Port 0.5
SPI1: Master out/Slave In data
61 D5 P0.6/S1.SCLK I/O pu
CT
X 4mA
X
X
Port 0.6
SPI1: Serial Clock
I/O pu
CT
4mA
X
X
Port 0.7
SPI1: Slave Select input active low
62 B3 P0.7/S1.SS
27/78
System architecture
PP
OD
interrupt
Output
Capability
Input
Input level
Pin name
Type
BGA64
LQFP64
Pin n°
Active in Stdby
STR711/STR712/STR715 pin description
Reset state1)
Table 7.
STR71xF
Main
function
(after
reset)
Port 0.8
63 C4
P0.8/U0.RX/U
I/O pd
0.TX
CT
X 4mA
T
64 A2
P0.9/U0.TX/B
OOT.0
CT
4mA
X
I/O pd
Alternate function
UART0:
Receive Data
input
UART0: Transmit data
output.
Note: This pin may be used for single wire UART
(half duplex) if programmed as Alternate Function
Output. The pin will be tri-stated except when
UART transmission is in progress
X
Port 0.9
Select Boot
Configuration
input
UART0: Transmit data
output
1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 8 on page 29.
The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends
on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset
2. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected.
3.5
External connections
Figure 5.
Recommended external connection of V18 and V18BKP pins
33 nF
33 nF
129 128
58 57
V18
LQFP144
V18BKP V18
28/78
V18
LQFP64
V18BKP
V18
54 55 58 59
25 26 27 28
1µF 10 µF
1µF 10 µF
STR71xF
System architecture
3.6
I/O port configuration
Table 8.
Port bit configuration table
PxD
Configuration Mode
Input
buffer
PxC2
PxC1
PxC0
register
register
register
Read
access
Write
access
TTL floating
I/O pin
don’t care
0
0
1
CMOS floating
I/O pin
don’t care
0
1
0
CMOS PullDown
I/O pin
0
0
1
1
CMOS
Pull-Up
I/O pin
1
0
1
1
Analog input
AIN
0
don’t care
0
0
0
Output Open-Drain
N.A.
I/O pin
0 or 1
1
0
0
Output Push-Pull
N.A.
last value
written
0 or 1
1
0
1
Alternate Function Open-Drain CMOS floating
I/O pin
don’t care
1
1
0
Alternate Function Push-Pull
I/O pin
don’t care
1
1
1
TTL Input Floating
CMOS Input Floating
INPUT
register
CMOS Input Pull-Down
(IPUPD)
CMOS Input Pull-Up (IPUPD)
OUTPUT
CMOS floating
Legend:
AIN: Analog Input
CMOS: CMOS Input levels
IPUPD: Input Pull Up /Pull Down
TTL: TTL Input levels
N.A.: not applicable. In Output mode, a read access to the port gets the output latch value.
29/78
System architecture
3.7
STR71xF
Memory mapping
Figure 6.
Memory map
APB Memory Space
0xFFFF FFFF
Addressable Memory Space
4 Gbytes
0xFFFF FFFF
EIC
0xFFFF F800
0xE000 E000
4K
0xFFFF F800
EIC
4K
WDG
4K
RTC
4K
TIMER 3
4K
TIMER 2
4K
TIMER 1
4K
TIMER 0
4K
CLKOUT
4K
ADC
4K
reserved
4K
IOPORT 2
4K
IOPORT 1
4K
IOPORT 0
4K
reserved
4K
XTI
4K
APB BRIDGE 2 REGS
4K
0xE000 D000
0xE000 C000
7
0xE000 B000
0xE000 0000
64K
APB2
0xE000 A000
0xE000 9000
0xE000 8000
6
0xE000 7000
0xC000 0000
64K
APB1
0xE000 6000
FLASH Memory Space
272 Kbytes + regs
0xE000 5000
0x4010 DFBF
FLASH Registers
5
36b
0xE000 4000
0x4010 0000
0xE000 3000
0xA000 0000
reserved
1K
PRCCU
0xE000 2000
0x400C 4000
0xE000 1000
B1F1
8K
0xE000 0000
4
0x400C 2000
B1F0
0x8000 0000
Reserved
4K
0xC001 0000
reserved
0xC000 F000
0x4004 0000
3
0xC000 E000
EXTMEM
See Figure 8
reserved
8K
0x400C 0000
0xC000 D000
64MB
B0F7
0x6000 0000
64K
0xC000 C000
0xC000 B000
reserved
4K
HDLC + RAM
4K
reserved
4K
reserved
4K
BSPI 1
4K
BSPI 0
4K
CAN
4K
USB + RAM
4K
UART 3
4K
UART 2
4K
UART 1
4K
UART 0
4K
reserved
4K
I2C 1
4K
0x4003 0000
0xC000 A000
2
B0F6
0x4000 0000
64K
256K+16K+36b
FLASH
0xC000 8000
0x4002 0000
0xC000 7000
0xC000 6000
1
B0F5
0x2000 0000
0xC000 9000
64K
64K
RAM
0xC000 5000
0xC000 4000
0x4001 0000
0xC000 3000
0
0x0000 0000
FLASH/RAM/EMI
(*) FLASH aliased at 0x0000 0000h
by system decoder for booting with
valid instruction upon RESET
from Block B0 (8 Kbytes)
Reserved
30/78
0x4000
0x4000
0x4000
0x4000
0x4000
8000
6000
4000
2000
0000
B0F4
32K
B0F3
B0F2
B0F1
B0F0
8K
8K
8K
8K
0xC000 2000
2
0xC000 1000
0xC000 0000
I C0
4K
APB BRIDGE 1 REGS
4K
STR71xF
System architecture
Figure 7.
Mapping of Flash memory versions
FLASH Memory Space
64 Kbytes + 16K RWW + regs
0x4010 DFBF
FLASH Memory Space
128 Kbytes + 16K RWW + regs
0x4010 DFBF
FLASH Registers
36b
0x4010 0000
B1F1
8K
B1F1
8K
0x400C 0000
8K
8K
0x4003 0000
reserved
64K
0x4002 0000
reserved
64K
reserved
64K
0x4001 0000
64K
32K
B0F3
B0F2
B0F1
B0F0
8K
8K
8K
8K
B0F5
0x4000
0x4000
0x4000
0x4000
0x4000
STR715FR0xx
STR711FR0xx
STR712FR0xx
8000
6000
4000
2000
0000
64K
B0F6
64K
B0F5
64K
0x4002 0000
64K
0x4001 0000
B0F4
B0F7
0x4003 0000
0x4002 0000
reserved
8K
0x4004 0000
0x4003 0000
reserved
B1F0
reserved
64K
8K
0x400C 0000
0x4004 0000
reserved
B1F1
0x400C 2000
B1F0
reserved
Table 9.
reserved
0x400C 0000
0x4004 0000
36b
0x400C 4000
0x400C 2000
B1F0
FLASH Registers
0x4010 0000
0x400C 4000
0x400C 2000
8000
6000
4000
2000
0000
36b
reserved
0x400C 4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4010 DFBF
FLASH Registers
0x4010 0000
reserved
FLASH Memory Space
256 Kbytes + 16K RWW + regs
0x4001 0000
B0F4
32K
B0F3
B0F2
B0F1
B0F0
8K
8K
8K
8K
STR710FZ1xx
STR711FR1xx
STR712FR1xx
0x4000
0x4000
0x4000
0x4000
0x4000
8000
6000
4000
2000
0000
B0F4
32K
B0F3
B0F2
B0F1
B0F0
8K
8K
8K
8K
STR710F72xx
STR711FR2xx
STR712FR2xx
RAM memory mapping
Part number
RAM size
Start address
End address
STR715FR0xx
STR711FR0xx
STR712FR0xx
16 Kbytes
0x2000 0000
0x2000 3FFF
STR710FZ1xx
STR711FR1xx
STR712FR1xx
32 Kbytes
0x2000 0000
0x2000 7FFF
STR710FR2xx
STR710Rxx
STR711FR2xx
STR712FR2xx
64 Kbytes
0x2000 0000
0x2000 FFFF
31/78
System architecture
Figure 8.
STR71xF
External memory map
Addressable Memory Space
4 Gbytes
0xFFFF FFFF
EIC
0xFFFF F800
7
0xE000 0000
APB2
6
0xC000 0000
APB1
External Memory Space
64 MBytes
5
0xA000 0000
0x6C00
0x6C00
0x6C00
0x6C00
PRCCU
000C
0008
0004
0000
BCON3
BCON2
BCON1
BCON0
register
register
register
register
4
0x66FF FFFF
0x8000 0000
Reserved
Bank3
16M
Bank2
16M
Bank1
16M
Bank0
16M
CSn.3
0x6600 0000
3
0x64FF FFFF
0x6000 0000
EXTMEM
CSn.2
0x6400 0000
2
0x4000 0000
0x62FF FFFF
CSn.1
FLASH
0x6200 0000
0x60FF FFFF
1
CSn.0
0x2000 0000
RAM
0x6000 0000
0
0x0000 0000
FLASH/RAM/EMI
Reserved
Drawing not in scale
32/78
STR71xF
Electrical parameters
4
Electrical parameters
4.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
4.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
4.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25°C, V33=3.3V (for the
3.0V≤V33≤3.6V voltage range) and V18=1.8V. They are given only as design guidelines and
are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
4.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
4.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
4.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9.
Pin loading conditions
Figure 10. Pin input voltage
STR7 PIN
STR7 PIN
L=50pF
VIN
33/78
Electrical parameters
4.2
STR71xF
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 10.
Voltage characteristics
Symbol
Ratings
Min
Max
V33- VSS
External 3.3V Supply voltage
(including AVDD and V33IO-
-0.3
4.0
Digital 1.8V Supply voltage
on V18BKP backup supply 2)
-0.3
2.0
Input voltage on true open
drain pin (P0.10) 1)
VSS-0.3
+5.5
Input voltage on any other
pin 1)
VSS-0.3
V33+0.3
PLL)
V18BKP - VSSBKP
VIN
34/78
2)
|∆V33x|
Variations between different
3.3V power pins
50
50
|∆V18x|
Variations between different
1.8V power pins 5)
25
25
Variations between all the
different ground pins
50
50
|VSSX - VSS|
Unit
VESD(HBM)
Electro-static discharge
voltage (Human Body Model)
VESD(MM)
Electro-static discharge
voltage (Machine Model)
see : Absolute maximum ratings
(electrical sensitivity) on page 48
V
mV
STR71xF
Electrical parameters
Table 11.
Current characteristics
Symbol
Ratings
Max.
IV33
Total current into V33/V33IO-PLL power lines (source) 2)
150
IVSS
Total current out of VSS/VSSIO-PLL ground lines (sink) 2)
150
Output current sunk by any I/O and control pin
25
Output current source by any I/Os and control pin
- 25
Injected current on RSTIN pin
±5
Injected current on CK pin
±5
Injected current on any other pin 4)
±5
Total injected current (sum of all I/O and control pins) 4)
± 25
IIO
IINJ(PIN) 1) 3)
ΣIINJ(PIN) 1)
Unit
mA
Notes:
1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>V33 while a negative injection is induced by VINV33 while a negative injection is
induced by VIN