STR750F

STR750F ARM7TDMI-S™ 32-bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN ■ Core – ARM7TDMI-S 32-bit RISC CPU – 54 DMIPS @ 60 MHz Memories – Up to 256 KB Flash program memory (10k erase/write cycles, retention 20 yrs at 85°C) – 16KB Read-While-Write Flash for data (100k erase/write cycles, retention 20 yrs@ 85°C) – Flash Data Readout and Write Protection – 16KBytes embedded high speed SRAM – Memory mapped interface (SMI) to ext. Serial Flash (64 MB) w. boot capability Clock, Reset and Supply Management – Single supply 3.3V ±10% or 5V ±10% – Embedded 1.8V Voltage Regulators with Low Power features – Smart Clock Controller with flexible clock generation capability: – Internal RC for fast start-up and backup clock mechanism – Up to 60 MHz operation using internal PLL with 4 or 8 MHz crystal/ceramic osc. – Smart Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registers – Real Time Clock, driven by low power internal RC or 32.768 kHz dedicated osc, for clock-calendar and Auto Wake-up Nested interrupt controller – Fast interrupt handling with 32 vectors – 16 IRQ priorities, 2 maskable FIQ sources – 16 external interrupt / wake-up Lines DMA – 4-channel DMA controller – Circular buffer management – Support for UART, SSP, Timers, ADC 6 Timers – 16-bit watchdog timer (WDG) ■ LQFP64 10x10 mm LQFP100 14 x 14 mm LFBGA64 8 x 8 x 1.7 mm LFBGA100 10 x 10 x 1.7 mm ■ – 16-bit timer for system timebase functions – 3 synchronizable timers each with up to 2 input captures and 2 output compare/PWMs. – 16-bit 6-channel synchronizable PWM timer – Dead time generation, edge/center-aligned waveforms and emergency stop – Ideal for induction/brushless DC motors ■ 8 Communications Interfaces – 1 I2C interface – 3 HiSpeed UARTs w. Modem/LIN capability – 2 SSP interfaces (SPI or SSI) up to 16 Mb/s – 1 CAN interface (2.0B Active) – 1 USB full-speed 12 Mb/s interface with 8 configurable endpoint sizes 10-bit A/D Converter – 16/11 chan. with prog. Scan Mode & FIFO – Programmable Analog Watchdog feature – Conversion: min. 3.75 µs, range: 0 to VDD_IO – Start conversion can be triggered by timers Up to 72/38 I/O ports – 72/38 GPIO lines with High Sink capabilities – Atomic bit SET and RES operations ■ ■ ■ ■ ■ October 2006 Rev 2 1/71 www.st.com 1 Contents STR750F Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.0.1 Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Supply Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O characteristics versus the various power schemes (3.3V or 5.0V) . 28 Current Consumption Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.1 3.2.2 3.2.3 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.10 3.3.11 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33 Embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2/76 STR750F 3.3.12 Contents 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3/76 Introduction STR750F 1 Introduction This Datasheet contains the description of the STR750 family features, pinout, Electrical Characteristics, Mechanical Data and Ordering information. For complete information on the Microcontroller memory, registers and peripherals. Please refer to the STR750 Reference Manual. For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical Reference Manual available from Arm Ltd. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on third-party development tools, please refer to the http://www.st.com/mcu website. Table 1. Device summary STR755FRx STR751FRx STR752FRx 64K/128K/256K 16K RWW 16K -40 to +85°C / -40 to +105°C (see Table 44) 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 38 I/Os 13 Wake-up lines, 11 A/D Channels 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 72 I/Os 15 Wake-up lines, 16 A/D Channels None 3.3V or 5V T=LQFP100 14x14, H=LFBGA100 USB+CAN STR755FVx STR750FVx Features Flash - Bank 0 (bytes) Flash - Bank 1 (bytes) RAM (bytes) Operating Temp. Common Peripherals USB/CAN peripherals Operating Voltage Packages (x) None 3.3V or 5V USB 3.3V CAN T=LQFP64 10x10, H=LFBGA64 4/71 STR750F Introduction 1.1 Overview The STR750 family includes devices in 2 package sizes: 64-pin and 100-pin. Both types have the following common features: ARM7TDMI-STM core with embedded Flash & RAM STR750 family has an embedded ARM core and is therefore compatible with all ARM tools and software. It combines the high performance ARM7TDMI-STM CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip highspeed single voltage FLASH memory and high-speed RAM. Figure 1 shows the general block diagram of the device family. Embedded Flash Memory Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data. An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to be erased/programmed on-the-fly. This partitioning feature is ideal for storing application parameters. ● When configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states for sequential accesses and 1 wait state for random access (maximum 60 MHz). When not configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states (maximum 32 MHz) ● Embedded SRAM 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Enhanced Interrupt Controller (EIC) In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt controller able to handle up to 32 vectors and 16 priority levels. This additional hardware block provides flexible interrupt management features with minimal interrupt latency. Serial Memory Interface (SMI) The Serial Memory interface is directly able to access up to 4 serial FLASH devices. It communicates at a speed of up to 48 MHz. It can be used to access data, execute code directly or boot the application from external memory. The memory is addressed as 4 banks of up to 16 Mbytes each. Clocks and start-up After RESET or when exiting from Low Power Mode, the CPU is clocked immediately by an internal RC oscillator (FREEOSC) at a frequency centered around 5 MHz, so the application code can start executing without delay. In parallel, the 4/8 MHz Oscillator is enabled and its stabilization time is monitored using a dedicated counter. An oscillator failure detection is implemented: when the clock disappears on the XT1 pin, the circuit automatically switches to the FREEOSC oscillator and an interrupt is generated. In Run mode, the AHB and APB clock speeds can be set at a large number of different frequencies thanks to the PLL and various prescalers: up to 60 MHz for AHB and up to 32 MHz for APB when fetching from Flash (64 MHz and 32 MHz when fetching from SRAM). 5/71 Introduction In SLOW mode, the AHB clock can be significantly decreased to reduce power consumption. STR750F The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra oscillators or PLL. For instance, starting from the 4 MHz crystal source, it is possible to obtain in parallel 60 MHz for the AHB clock, 48 MHz for the USB clock and 30 MHz for the APB peripherals. Boot modes At start-up, boot pins are used to select one of five boot options: ● ● ● ● Boot from internal flash Boot from external serial Flash memory Boot from internal boot loader Boot from internal SRAM Booting from SMI memory allows booting from a serial flash. This way, a specific boot monitor can be implemented. Alternatively, the STR750F can boot from the internal boot loader that implements a boot from UART. Power Supply Schemes You can connect the device in any of the following ways depending on your application. ● Power Scheme 1: Single external 3.3V power source. In this configuration the VCORE supply required for the internal logic is generated internally by the main voltage regulator and the VBACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 3.3V power source. Power Scheme 2: Dual external 3.3V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off by forcing the VREG_DIS pin to high level. VCORE is provided externally through the V18 and V18REG power pins and VBACKUP through the V18_BKP pin. This scheme is intended to save power consumption for applications which already provide an 1.8V power supply. Power Scheme 3: Single external 5.0V power source. In this configuration the VCORE supply required for the internal logic is generated internally by the main voltage regulator and the VBACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 5.0V power source. Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. VCORE is provided externally through the V18 and V18REG power pins and VBACKUP through the V18_BKP pin. This scheme is intended to provide 5V I/O capability. ● ● ● Caution: When powered by 5.0V, the USB peripheral cannot operate. 6/71 STR750F Introduction Low Power modes The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY. ● SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main oscillator can be stopped and the device is driven by a low power clock (fRTC). The clock is either an external 32.768 kHz oscillator or the internal low power RC oscillator. PCG MODE (Peripheral Clock Gating MODE): When the peripherals are not used, their APB clocks are gated to optimize the power consumption. WFI MODE (Wait For Interrupts): only the CPU clock is stopped, all peripherals continue to work and can wake-up the CPU when IRQs occur. STOP MODE: all clocks/peripherals are disabled. It is also possible to disable the oscillators and the Main Voltage Regulator (In this case the VCORE is entirely powered by V18_BKP). This mode is intended to achieve the lowest power consumption with SRAM and registers contents retained. The system can be woken up by any of the external interrupts / wake-up lines or by the RTC timer which can optionally be kept running. The RTC can be clocked either by the 32.768 kHz Crystal or the Low Power RC Oscillator. Alternatively, STOP mode gives flexibility to keep the either main oscillator, or the Flash or the Main Voltage Regulator enabled when a fast start after wake-up is preferred (at the cost of some extra power consumption). STANDBY MODE: This mode (only available in single supply power schemes) is intended to achieve the lowest power consumption even when the temperature is increasing. The digital power supply (VCORE) is completely removed (no leakage even at high ambient temperature). SRAM and all register contents are lost. Only the RTC remains powered by V18_BKP. The STR750F can be switched back from STANDBY to RUN mode by a trigger event on the WKP_STDBY pin or an alarm timeout on the RTC counter. ● ● ● ● Caution: It is important to bear in mind that it is forbidden to remove power from the VDD_IO power supply in any of the Low Power Modes (even in STANDBY MODE). DMA The flexible 4-channel general-purpose DMA is able to manage memory to memory, peripheral to memory and memory to peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. The DMA can be used with the main peripherals: UART0, SSP0, Motor control PWM timer (PWM), standard timer TIM0 and ADC. RTC (Real Time Clock) The real time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator or the internal low power RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated. WDG (Watchdog Timer) The watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. It can be used as watchdog to reset the device when a problem occurs, or as free running timer for application time out management. 7/71 Introduction STR750F Timebase Timer (TB) The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O pins. It can be used for software triggering, or to implement the scheduler of a real time operating system. Synchronizable Standard Timers (TIM2:0) The three standard timers are based on a 16-bit auto-reload counter and feature up to 2 input captures and 2 output compares (for external triggering or time base / time out management). They can work together with the PWM timer via the Timer Link feature for synchronization or event chaining. In reset state, timer Alternate Function I/Os are connected to the same I/O ports in both 64-pin and 100-pin devices. To optimize timer functions in 64-pin devices, timer Alternate Function I/Os can be connected, or “remapped”, to other I/O ports as summarized in Table 2 and detailed in Table 5. This remapping is done by the application via a control register. Table 2. Standard timer alternate function I/Os Number of Alternate Function I/Os Standard Timer Functions 100-pin package Input Capture TIM 0 Output Compare/PWM Input Capture TIM 1 Output Compare/PWM Input Capture TIM 2 Output Compare/PWM 2 1 2 2 2 1 2 1 2 2 2 1 1 2 1 2 64-pin package Default mapping 1 Remapped 2 Any of the standard timers can be used to generate PWM outputs. One timer (TIM0) is mapped to a DMA channel. Motor Control PWM timer (PWM) The Motor Control PWM Timer (PWM) can be seen as a three-phase PWM multiplexed on 6 channels. The 16-bit PWM generator has full modulation capability (0...100%), edge or centre-aligned patterns and supports dead-time insertion. It has many features in common with the standard TIM timers which has the same architecture and it can work together with the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM timer is mapped to a DMA channel. I²C bus The I²C bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz). 8/71 STR750F Introduction High Speed Universal Asynch. Receiver Transmitter (UART) The three UART interfaces are able to communicate at speeds of up to 2 Mbit/s. They provide hardware management of the CTS and RTS signals and have LIN Master capability. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 16 bytes each have been implemented. One UART can be served by the DMA controller (UART0). Synchronous Serial Peripheral (SSP) The two SSPs are able to communicate up to 8 Mbit/s (SSP1) or up to 16 Mbit/s (SSP0) in standard full duplex 4-pin interface mode as a master device or up to 2.66 Mbit/s as a slave device. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 8 x 16 bit words have been implemented. The SSPs support the Motorola SPI or TI SSI protocols. One SSP can be served by the DMA controller (SSP0). Controller Area Network (CAN) The CAN is compliant with the specification 2.0 part B (active) with a bit rate up to 1Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Up to 32 message objects are handled through an internal RAM buffer. In LQFP64 devices, CAN and USB cannot be connected simultaneously. Universal Serial Bus (USB) The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL. VDD must be in the range 3.3V±10% for USB operation. ADC (Analog to Digital Converter) The 10-bit Analog to Digital Converter, converts up to 16 external channels (11 channels in 64-pin devices) in single-shot or scan modes. In scan mode, continuous conversion is performed on a selected group of analog inputs. The minimum conversion time is 3.75 µs (including the sampling time). The ADC can be served by the DMA controller. An analog watchdog feature allows you to very precisely monitor the converted voltage of up to four channels. An IRQ is generated when the converted voltage is outside the programmed thresholds. The events generated by TIM0, TIM2 and PWM timers can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. GPIOs (General Purpose Input/Output) Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Port 1.15 is an exception, it can be used as general-purpose input only or wake-up from STANDBY mode (WKP_STDBY). Most of the GPIO pins are shared with digital or analog alternate functions. 9/71 Introduction STR750F 1.2 Block Diagram Figure 1. BOOT1, BOOT0 as AF TEST NJTRST JTDI JTCK JTMS JTDO as AF STR750 block diagram ARM7TDMI-S CPU 60MHz AHB JTAG & ICE-RT GP DMA 4 streams AHB BUS MATRIX HRESETN PRESETN SRAM 16KB FLASH 256KB +16KB (RWW) NESTED INTERRUPT CTL CK_RTC CK_SYS HCLK PCLK CLOCK MANAGEMENT VDD_IO VCORE VBACKUP VDDA_PLL VDDA_ADC 32xIRQ 2xFIQ RESET & POWER DC-DC 3.3V TO 1.8V MAIN LOW POWER NRSTIN NRSTOUT VDD_IO V18 V18BKP VSS Arbiter SCLK, MOSI MISO as AF 4 CS as AF SERIAL MEMORY INTERFACE AHB LITE (up to 60MHz) LP OSC OSC 32K FREE OSC PLL OSC 4M XT1 XT2 VDDA_PLL VSSA_PLL RTC_XT1 RTC_XT2 APB BRIDGE CK_USB USB Full Speed 15AF P0[31:0] P1[19:0] P2[19:0] 16AF VDDA_ADC VSSA_ADC EXT.IT WAKEUP GPIO PORT 0 GPIO PORT 1 GPIO PORT 2 10-bit ADC WATCHDOG RTC USBDP USBDM RX,TX as AF RX,TX,CTS, RTS as AF RX,TX,CTS, RTS as AF RX,TX,CTS, RTS as AF MOSI,MISO, SCK,NSS as AF MOSI,MISO, SCK,NSS as AF SCL,SDA as AF CAN 2.0B FIFO 2x(16x8bit) UART0 FIFO 2x(16x8bit) UART1 FIFO 2x(16x8bit) UART2 FIFO 2x(8x16bit) SSP0 TB TIMER 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF PWM1, PWM1N PWM2, PWM2N PWM3, PWM3N PWM_EMERGENCY as AF TIM0 TIMER TIM1 TIMER I2C TIM2 TIMER PWM TIMER APB (up to 32 MHz) FIFO 2x(8x16bit) SSP1 AF: alternate function on I/O port pin Note: I/Os shown for 100 pin devices. 64-pin devices have the I/O set shown in Figure 3. 10/71 2 Figure 2. STR750F Pin Description ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1/ P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 TIM1_TI2 / P0.31 TIM1_OC2 / P0.30 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 TEST VSS_IO ADC_IN6 / UART1_RTS / P0.23 TIM2_OC1/ P2.04 UART1_RTS / P2.03 P2.02 ADC_IN5 / UART1_CTS / P0.22 UART1_TX / P0.21 UART1_RX / P0.20 JTMS / P1.19 JTCK / P1.18 JTDO / P1.17 JTDI / P1.16 NJTRST P2.01 P2.00 UART0_RTS / RTCK / P0.13 SMI_CS1 / ADC_IN2 / UART0_CTS / P0.12 SMI_CS2 / BOOT1 / UART0_TX / P0.11 SMI_CS3 / UART0_RX / P0.10 I2C_SDA / P0.09 I2C_SCL / P0.08 P2.19 P2.18 UART2_RTS / P2.17 ADC_IN12 / UART0_RTS P1.11 ADC_IN7 /UART2_RTS / P0.27 UART2_CTS / P0.26 UART2_TX / P0.25 UART2_RX / P0.24 ADC_IN4 / SSP1_NSS / USB_CK / P0.19 SSP1_MOSI / P0.18 ADC_IN3 / SSP1_MISO / P0.17 SSP1_SCLK / P0.16 P2.16 VDD_IO VDDA_PLL XT2 XT1 VSS_IO VSSA_PLL P2.15 = 16 A/D input channels = 15 External interrupts / Wake-up Lines 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 Pinout LQFP100 V18BKP I/Os 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VREG_DIS VSS_IO VSSA_ADC P2.10 P2.11 VDDA_ADC VDD_IO P1.02 / TIM2_OC2 P1.03 / TIM2_TI2 USB_DP USB_DN P0.14 / CAN_RX P0.15 / CAN_TX P2.12 P2.13 P1.15 / WKP_STDBY NRSTIN NRSTOUT XRTC2 XRTC1 V18BKP VSSBKP VSS18 V18REG P2.14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P0.03 / TIM2_TI1 / ADC_IN1 VDD_IO VSS_IO VSS18 V18 P1.00 / TIM0_OC2 P1.01 / TIM0_TI2 P1.13 / ADC_IN14 P1.14/ ADC_IN15 P1.04 / PWM3N / ADC_IN9 P1.05 / PWM3 P1.06 / PWM2N/ ADC_IN10 P1.07 / PWM2 P1.08 / PWM1N/ ADC_IN11 P2.05 / PWM3N P2.06 / PWM3 P2.07 / PWM2N P2.08 / PWM2 P2.09 / PWM1N P1.09 / PWM1 P1.10 / PWM_EMERGENCY P0.04 / SMI_CS0 / SSP0_NSS P0.05 / SSP0_SCLK / SMI_CK P0.06 / SMI_DIN / SSP0_MISO P0.07 / SMI_DOUT / SSP0_MOSI Pin Description 11/71 Pin Description Figure 3. LQFP64 Pinout STR750F ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1 / P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 TEST VSS_IO_4 UART1_TX / P0.21 UART1_RX / P0.20 JTMS / P1.19 JTCK / P1.18 JTDO / P1.17 JTDI / P1.16 NJTRST UART0_RTS / RTCK / P0.13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 V18BKP I/Os 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1.09 / PWM1 P1.10 / PWM_EMERGENCY P0.04 / SMI_CS0 /SSP0_NSS P0.05 / SSP0_SCLK / SMI_CK P0.06 / SMI_DIN / SSP0_MISO P0.07 / SMI_DOUT / SSP0_MOSI VREG_DIS VSS_IO_2 VSSA_ADC VDDA_ADC VDD_IO_2 P1.03 / TIM2_TI2 P0.14 / CAN_RX or USB_DP P0.15 / CAN_TX or USB_DN NRSTIN NRSTOUT XRTC2 XRTC1 V18BKP VSSBKP VSS18 V18REG P0.03 / TIM2_TI1 / ADC_IN1 VDD_IO_1 VSS_IO_1 VSS18 V18 P1.04 / PWM3N / ADC_IN9 P1.05 / PWM3 P1.06 / PWM2N / ADC_IN10 P1.07 / PWM2 = 11 A/D input channels = 13 External interrupts / Wake-up Lines 12/71 SMI_CS1 / ADC_IN2 / UART0_CTS / P0.12 SMI_CS2 / BOOT1 / UART0_TX / P0.11 SMI_CS3 / UART0_RX / P0.10 I2C_SDA/ P0.09 I2C_SCL / P0.08 ADC_IN12 / UART0_RTS / P1.11 ADC_IN4 / SSP1_NSS / USB_CK / P0.19 SSP1_MOSI / P0.18 ADC_IN3 / SSP1_MISO / P0.17 SSP1_SCLK / P0.16 VDD_IO_3 VDDA_PLL XT2 XT1 VSS_IO_3 VSSA_PLL P1.08 / PWM1N / ADC_IN11 STR750F Table 3. 1 A B C D E F G H J K P0.03 P1.12 P0.31 P0.29 P0.28 P2.03 Pin Description LFBGA100 ball connections 2 3 4 P1.04 P1.05 V18 VSS18 5 6 7 P0.05 P0.04 VSS_IO VDD_IO 8 P0.06 P2.13 VSSA_ADC VDDA_ADC 9 P0.07 P1.03 P2.11 P2.12 10 P1.02 P2.10 USB_DP USB_DN P0.14 P0.15 XRTC2 XRTC1 VSS_IO P1.13 P1.14 P0.02 P0.01 P0.00 VDD_IO P0.30 VSS_IO P0.23 P0.22 P0.21 P0.20 P1.06 P1.08 P1.07 P1.09 P1.10 P2.09 P1.01 P1.15 VSS_IO TEST P1.00 NRSTOUT VREG_DIS NRSTIN P2.02 P2.01 P2.19 P0.27 P0.18 P2.04 P2.05 P2.00 P2.07 P2.18 P2.17 P0.19 P0.26 P0.17 P0.16 P2.06 2.08 P0.24 P0.25 XT1 VSS18 V18REG P2.14 P2.15 XT2 VSSBKP V18BKP P2.16 VDD_IO NJTRST P1.18 P1.19 P0.13 P0.11 P0.10 P1.16 P1.17 P0.12 P1.11 P0.09 P0.08 VDDA_PLL VSSA_PLL Table 4. LFBGA64 ball connections 1 2 VSS_IO VDD_IO P0.02 P0.28 P1.19 NJTRST P0.12 P0.09 3 P1.04 P1.05 P0.00 TEST P0.20 P1.16 P1.11 P0.08 4 P1.06 P1.07 V18 VSS_IO P0.21 P1.17 P0.19 P0.17 5 P1.08 P1.09 VSS18 6 P0.05 P0.04 VDD_IO 7 P0.06 P1.10 VSS_IO 8 P0.07 P1.03 P0.14 P0.15 XRTC2 XRTC1 A B C D E F G H P0.03 P1.12 P0.01 P0.29 P1.18 P0.13 P0.11 P0.10 VREG_DIS VDDA_ADC VSSA_ADC NRSTOUT V18REG VDD_IO P0.18 NRSTIN VSS18 VSS_IO P0.16 V18BKP VSSBKP VDDA_PLL VSSA_PLL XT2 XT1 13/71 Pin Description STR750F 2.0.1 Pin Description Table Legend / Abbreviations for Table 5: Type: Input Levels: I = input, O = output, S = supply, All Inputs are LVTTL at VDD_IO = 3.3V+/-0.3V or TTL at VDD_IO = 5V± 0.5V. In both cases, TT means VILmax =0.8V VIHmin=2.0V All inputs can be configured as floating or with internal weak pull-up or pull down (pu/pd) All Outputs can be configured as Open Drain (OD) or Push-Pull (PP) (see also note 6 below Table 5). There are 3 different types of Output with different drives and speed characteristics: – O8: fmax = 40 MHz on CL=50pF and 8 mA static drive capability for VOL=0.4V and up to 20 mA for VOL=1.3V (seeOutput driving current on page 54) – O4: fmax = 20 MHz on CL=50pF and 4 mA static drive capability for VOL=0.4V (seeOutput driving current on page 54) – O2: fmax = 10 MHz on CL=50pF and 2 mA static drive capability of for VOL=0.4V (seeOutput driving current on page 54) Inputs: Outputs: External Interrupts/wake-up lines: EITx 14/71 STR750F Pin Description Port Reset State The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13 which are configured as JTAG alternate functions: ● ● ● The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and are ready to accept JTAG sequences. The JTAG output JTDO is configured as floating when idle (no JTAG operation) and is configured in output push-pull only when serial JTAG data must be output. The JTAG output RTCK is always configured as output push-pull. It outputs '0' level during the reset phase and then outputs the JTCK input signal resynchronized 3 times by the internal AHB clock. The GPIO_PCx registers do not control JTAG AF selection, so the reset values of GPIO_PCx for P1[19:16] and P0. 13 are the same as other ports. Refer to the GPIO section of the STR750 Reference Manual for the register description and reset values. P0.11 and P0.00 are sampled by the boot logic after reset, prior to fetching the first word of user code at address 0000 0000h. When booting from SMI (and only in this case), the reset state of the following GPIOs is "SMI alternate function output enabled": – – – – P0.07 (SMI_DOUT) P0.05 (SMI_CLK) P0.04 (SMI_CS0) P0.06 (SMI_DIN) ● ● ● Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected. To avoid excess power consumption, unused I/O ports must be tied to ground. Table 5. Pin n° Input Level STR750F pin description Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 1 B1 1 B1 P1.12 / ADC_IN13 I/O TT X X EIT12 O8 X X Port 1.12 ADC: Analog input 13 TIM2: Output Compare 1(2) ADC: Analog input 0 2 B2 2 P0.02 / C2 TIM2_OC1 / ADC_IN0 C1 P0.01 / TIM0_TI1 / MCO I/O TT X X EIT0 O8 X X Port 0.02 3 B3 3 I/O TT X X O8 X X Port 0.01 Port 0.00 / Boot mode selection input 0 Port 0.31 Port 0.30 TIM0: Input Main Clock Capture / trigger Output / external clock 1 4 C2 4 P0.00 / C3 TIM0_OC1 / BOOT0 P0.31 / TIM1_TI2 P0.30 / TIM1_OC2 I/O TT X X O8 X X TIM0: Output Compare 1 5 6 C1 D2 I/O I/O TT TT X X X X O2 O2 X X X X TIM1: Input Capture / trigger / external clock 2 TIM1: Output Compare 2 15/71 Pin Description Table 5. Pin n° Input Level STR750F STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 7 8 9 10 11 D1 E1 E5 E4 E2 5 6 7 8 D1 D2 P0.29 / TIM1_TI1 / ADC_IN8 P0.28 / TIM1_OC1 I/O I/O I S I/O TT TT X X X X O2 O2 X X X X Port 0.29 Port 0.28 TIM1: Input Capture 1 ADC: Analog input 8 TIM1: Output Compare 1 D3 TEST D4 VSS_IO P0.23 / UART1_RTS / ADC_IN6 P2.04 / TIM2_OC1 P2.03 / UART1_RTS P2.02 P0.22 / UART1_CTS / ADC_IN5 Reserved, must be tied to ground Ground Voltage for digital I/Os TT X X O2 X X Port 0.23 UART1: Ready To Send output(2) TIM2: Output Compare 1(2) UART1: Ready To Send output(2) ADC analog input 6 12 F5 I/O TT X X O2 X X Port 2.04 13 14 15 F1 F4 E3 I/O I/O I/O TT TT TT X X X X X X O2 O2 O2 X X X X X X Port 2.03 Port 2.02 Port 0.22 UART1: Clear To Send input ADC: Analog input 5 16 17 F2 F3 9 10 E4 E3 P0.21 / UART1_TX P0.20 / UART1_RX P1.19 / JTMS I/O I/O TT TT X X X X O2 O2 X X X X Port 0.21 Port 0.20 JTAG mode selection input(4) JTAG clock input(4) JTAG data output(4) JTAG data input(4) UART1: Transmit data output (remappable to P0.15)(2) UART1: Receive data input (remappable to P0.14)(2) Port 1.19 18 G3 11 E2 I/O TT X X O2 X X 19 20 21 22 23 24 G2 H3 H2 G1 G4 G5 12 13 14 15 E1 P1.18 / JTCK F4 P1.17 / JTDO F3 P1.16 / JTDI F2 NJTRST P2.01 P2.00 P0.13 / RTCK / UART0_RTS I/O I/O I/O I I/O I/O TT TT TT TT TT TT X X X X X X O2 O8 O2 X X X X X X Port 1.18 Port 1.17 Port 1.16 JTAG reset input(3) X X X X O2 O2 X X X X Port 2.01 Port 2.00 JTAG return clock output(4) Port 0.13 UART0: Ready To Send output(2) UART0: Clear To Send input ADC: Analog input 2 25 H1 16 F1 I/O TT X X O8 X X 26 J2 17 G2 P0.12 / UART0_CTS / ADC_IN2 / SMI_CS1 I/O TT X X O4 X X Port 0.12 Serial Memory Interface: chip select output 1 16/71 STR750F Table 5. Pin n° Input Level Pin Description STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 27 J1 P0.11 / UART0_TX / 18 G1 BOOT1 / SMI_CS2 P0.10 / 19 H1 UART0_RX / SMI_CS3 20 H2 P0.09 / I2C_SDA 21 H3 P0.08 / I2C_SCL P2.19 P2.18 P2.17 / UART2_RTS P1.11 22 G3 /UART0_RTS ADC_IN12 P0.27 / UART2_RTS / ADC_IN7 P0.26 / UART2_CTS P0.25 / UART2_TX P0.24 / UART2_RX I/O TT X X O4 X X Port 0.11/Boot mode selection input 1 Port 0.10 Port 0.09 Port 0.08 Port 2.19 Port 2.18 Port 2.17 UART0: Transmit data output Serial Memory Interface: chip select output 2 Serial Memory Interface: chip select output 3 28 29 30 31 32 33 K1 K2 K3 H4 H5 H6 I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT X X X X X X X X X X X X EIT4 O2 O4 X X X X X X X X X X X X UART0: Receive Data input I2C: Serial Data I2C: Serial clock EIT3 O4 O2 O2 O2 UART2: Ready To Send output(2) UART0: Ready To Send output(2) UART2: Ready To Send output(6) ADC: Analog input 12 ADC: Analog input 7 34 J3 I/O TT X X EIT11 O8 X X Port 1.11 35 J4 I/O TT X X O2 X X Port 0.27 36 37 38 J6 J7 H7 I/O I/O I/O TT TT TT X X X X X X O2 O2 O2 X X X X X X Port 0.26 Port 0.25 Port 0.24 UART2: Clear To Send input UART2: Transmit data output (remappable to P0.13)(6) UART2: Receive data input (remappable to P0.12)(6) SSP1: Slave select input (remappable to P0.11)(6) USB: 48 MHz Clock input ADC: Analog input 4 39 J5 P0.19 / USB_CK / 23 G4 SSP1_NSS / ADC_IN4 I/O TT X X EIT6 O2 X X Port 0.19 40 K4 24 H5 P0.18 / SSP1_MOSI I/O TT X X O2 X X Port 0.18 SSP1: Master out/slave in data (remappable to P0.10)(6) SSP1: Master in/slave out data (remappable to P0.09)(6) ADC: Analog input 3 41 K5 P0.17 / 25 H4 SSP1_MISO / ADC_IN3 26 H6 P0.16 / SSP1_SCLK P2.16 27 G5 VDD_IO 28 G7 VDDA_PLL I/O TT X X O2 X X Port 0.17 42 43 44 45 K6 H9 J9 K9 I/O I/O S S TT TT X X X X O2 O2 X X X X Port 0.16 Port 2.16 SSP1: serial clock (remappable to P0.08)(6) Supply voltage for digital I/Os Supply voltage for PLL 17/71 Pin Description Table 5. Pin n° Input Level STR750F STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 46 47 48 49 50 51 K8 K7 J10 K10 J8 H8 29 H7 XT2 4 MHz main oscillator 30 H8 XT1 31 G6 VSS_IO 32 G8 VSSA_PLL P2.15 P2.14 S S I/O I/O TT TT X X X X O2 O2 X X X X Ground voltage for digital I/Os Ground voltage for PLL Port 2.15 Port 2.14 Stabilization for main voltage regulator. Requires external capacitors of at least 10µF between V18REG and VSS18. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used, 52 G8 33 F5 V18REG S 53 54 F8 F9 34 35 F6 VSS18 F7 VSSBKP S S Ground Voltage for the main voltage regulator Stabilization for low power voltage regulator. Ground Voltage for the low power voltage regulator. Requires external capacitors of at least 1µF between V18BKP and VSSBKP. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used, X 32 kHz oscillator for Realtime Clock X 55 G9 36 E7 V18BKP S 56 57 58 59 60 61 62 63 64 65 66 H10 37 F8 XRTC1 E8 XRTC2 E5 NRSTOUT E6 NRSTIN P1.15 / WKP_STDBY P2.13 P2.12 O I I I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT X X X X X X X X X EIT5 EIT15 O2 O2 O2 O2 X X X X X X X X G10 38 E7 E9 D6 B8 D9 F10 E10 D10 C10 39 40 X X X Reset output Reset input Port 1.15 Port 2.13 Port 2.12 Port 0.15 Port 0.14 CAN: Transmit data output CAN: Receive data input Wake-up from STANDBY input pin 41 D8 (5) (5) P0.15 / CAN_TX P0.14 / CAN_RX USB_DN USB_DP 42 C8 (5) (5) 41 D8 (5) (5) USB: bidirectional data (data -) USB: bidirectional data (data +) TIM2: Input Capture / trigger / external clock 2 (remappable to P0.07)(6) TIM2: Output compare 2 (remappable to P0.06)(6) 42 C8 (5) (5) 67 B9 43 B8 P1.03 / TIM2_TI2 P1.02 / TIM2_OC2 I/O TT X X O2 X X Port 1.03 68 69 70 A10 D7 D8 I/O S S TT X X O2 X X Port 1.02 44 C6 VDD_IO 45 D6 VDDA_ADC Supply Voltage for digital I/Os Supply Voltage for A/D converter 18/71 STR750F Table 5. Pin n° Input Level Pin Description STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 71 72 73 74 75 76 C9 B10 C8 C7 E8 A9 P2.11 P2.10 46 D7 VSSA_ADC 47 C7 VSS_IO 48 D5 VREG_DIS 49 P0.07 / A8 SMI_DOUT / SSP0_MOSI A7 P0.06 / SMI_DIN / SSP0_MISO I/O I/O S S I I/O TT TT X X X X O2 O2 X X X X Port 2.11 Port 2.10 Ground Voltage for A/D converter Ground Voltage for digital I/Os TT TT X X EIT2 O4 X X Voltage Regulator Disable input Port 0.07 Serial Memory Interface: data output Serial Memory Interface: data input SSP0: Serial clock Serial Memory Interface: chip select output 0 SSP0: Master out Slave in data SSP0: Master in Slave out data Serial Memory Interface: Serial clock output SSP0: Slave select input 77 A8 50 I/O TT X X O4 X X Port 0.06 78 A7 51 P0.05 / A6 SSP0_SCLK / SMI_CK B6 P0.04 / SMI_CS0 / SSP0_NSS I/O TT X X EIT1 O4 X X Port 0.05 79 B7 52 I/O TT X X O4 X X Port 0.04 80 81 82 83 84 85 86 C5 B6 C6 G7 G6 F7 F6 53 54 P1.10 B7 PWM_EMERGE NCY B5 P1.09 / PWM1 P2.09 / PWM1N P2.08 / PWM2 P2.07 / PWM2N P2.06 / PWM3 P2.05 / PWM3N P1.08 / PWM1N / ADC_IN11 I/O I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT TT X X X X X X X X X X X X X X EIT10 EIT9 O2 O4 O2 O2 O2 O2 O2 X X X X X X X X X X X X X X Port 1.10 Port 1.09 Port 2.09 Port 2.08 Port 2.07 Port 2.06 Port 2.05 PWM: Emergency input PWM: PWM1 output PWM: PWM1 complementary output(2) PWM: PWM2 output(2) PWM: PWM2 complementary output(2) PWM: PWM3 output(2) PWM: PWM3 complementary output(2) PWM: PWM1 complementary output(6) ADC: analog input 11 87 88 89 90 91 A6 B5 A5 B4 A4 55 56 57 58 59 A5 I/O I/O I/O I/O I/O TT TT TT TT TT X X X X X X X X X X EIT7 EIT8 O4 O4 O4 O4 O4 X X X X X X X X X X Port 1.08 Port 1.07 Port 1.06 Port 1.05 Port 1.04 B4 P1.07 / PWM2 A4 P1.06 / PWM2N / ADC_IN10 PWM: PWM2 output(2) PWM: PWM2 complementary output(2) ADC: analog input 10 B3 P1.05 / PWM3 A3 P1.04 / PWM3N / ADC_IN9 P1.14 / ADC_IN15 P1.13 / ADC_IN14 PWM: PWM3 output(2) PWM: PWM3 complementary output(2) ADC: analog input 9 92 93 A3 A2 I/O I/O TT TT X X X X EIT13 O8 O8 X X X X Port 1.14 Port 1.13 ADC: analog input 15 ADC: analog input 14 19/71 Pin Description Table 5. Pin n° Input Level STR750F STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 94 D5 P1.01 / TIM0_TI2 P1.00 / TIM0_OC2 I/O TT X X O2 X X Port 1.01 TIM0: Input Capture / trigger / external clock 2 (remappable to P0.05)(6) TIM0: Output compare 2 (remappable to P0.04)(6) 95 E6 I/O TT X X O2 X X Port 1.00 96 C4 60 C4 V18 S Stabilization for main voltage regulator. Requires external capacitors 33nF between V18 and VSS18. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used. Ground Voltage for the main voltage regulator. Ground Voltage for digital I/Os Supply Voltage for digital I/Os TT X X O2 X X Port 0.03 TIM2: Input Capture / trigger / external clock 1 ADC: analog input 1 97 98 99 100 D4 D3 C3 A1 61 C5 VSS18 62 63 64 A2 VSS_IO B2 VDD_IO A1 P0.03 / TIM2_TI1 / ADC_IN1 S S S I/O 1. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O pin and VDD_IO. 2. In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where these functions are listed in the table. 3. It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to NRSTOUT pin (if available) or NRSTIN. 4. After reset, these pins are enabled as JTAG alternate function see (Port Reset State on page 15). To use these ports as general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case, debugging these I/Os via JTAG is not possible). 5. There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while for the second one, they are mapped to P0.15/CAN_TX and P0.14/RX. 6. For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description. 20/71 STR750F Figure 4. Required external capacitors when regulators are used 33 nF 33 nF 96 VSS18 V18 97 V18BKP 55 VSSBKP 54 1µF Pin Description 61 60 VSS18 V18 V18BKP 36 VSSBKP 35 1µF LQFP100 VSS18 53 10 µF LQFP64 VSS18 V18REG 52 VDD_IO 44 1 µF 33 nF 34 10 µF V18REG 33 VDD_IO 27 1 µF 33 nF D4 C4 VSS18 V18 V18BKP G9 VSSBKP F9 1µF C5 C4 VSS18 V18 V18BKP E7 VSSBKP F7 1µF LFBGA100 LFBGA64 VSS18 F8 10 µF V18REG G8 VSS18 F6 10 µF V18REG F5 VDD_IO G5 1 µF VDD_IO J9 1 µF 21/71 Pin Description STR750F 2.1 Memory map Figure 5. Memory map Peripheral Memory Space 32 Kbytes 0xFFFF FFFF 0xFFFF FC00 0xFFFF FBFF 0xFFFF F800 0xFFFF F7FF 0xFFFF F400 0xFFFF F3FF 0xE000 0000 0xDFFF FFFF Addressable Memory Space 4 Gbytes 0xFFFF FFFF 0xFFFF 8000 APB TO ARM7 BRIDGE 32K Reserved EIC EXTIT 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 7 FLASH Memory Space 128/256 Kbytes 0x2010 DFFF 0x2010 C000 0x2010 0017 0x2010 0000 0xFFFF F000 0xFFFF EFFF 0xFFFF EC00 0xFFFF EBFF RTC DMA Reserved 6 0xC000 0000 0xBFFF FFFF SystemMemory 8K Flash registers 0xFFFF E800 0xFFFF E7FF 24B GPIO I/O Ports 0xFFFF E400 0xFFFF E3FF 0xFFFF E000 0xFFFF DFFF 0xFFFF DC00 0xFFFF DBFF Reserved UART2 UART1 UART0 Reserved I2C Reserved CAN Reserved SSP1 SSP0 Reserved WDG Reserved USB Registers Reserved 5 0xA000 0000 0x9FFF FFFF 0xFFFF D800 0xFFFF D7FF 0x200C 0x200C 0x200C 0x200C 0x200C 4000 3FFF 2000 1FFF 0000 0xFFFF D400 0xFFFF D3FF B1F1 B1F0 8K 8K 0xFFFF D000 0xFFFF CFFF 0xFFFF CC00 0xFFFF CBFF 0xFFFF C800 0xFFFF C7FF 0xFFFF C400 0xFFFF C3FF 4 0x9000 0013 0x9000 0000 0x83FF FFFF 0x8000 0000 0x7FFF FFFF SMI Registers 20B 4 x 16M SMI Ext. Memory 0xFFFF C000 0xFFFF BFFF 0xFFFF BC00 0xFFFF BBFF 3 0x6000 0047 0x6000 0000 0x5FFF FFFF CONF + MRCC 0xFFFF B800 0xFFFF B7FF 0xFFFF B400 0xFFFF B3FF 1K 0x2003 FFFF 0xFFFF B000 0xFFFF AFFF B0F7(2) 64K 0xFFFF AC00 0xFFFF ABFF 0xFFFF A800 0xFFFF A7FF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 2 0x4000 3FFF 0x4000 0000 0x3FFF FFFF Internal SRAM 0x2003 0000 0x2002 FFFF 16K 0x2002 0000 0x2001 FFFF B0F6(2) 64K A400 A3FF A200 USB RAM 256 x16-bit A000 9FFF Reserved 0xFFFF 9C00 0xFFFF 9BFF PWM 1 0x2010 0017 0x2000 0000 0x1FFF FFFF Internal Flash B0F5 64K 0xFFFF 9800 0xFFFF 97FF 0xFFFF 9400 0xFFFF 93FF TIM2 TIM1 128K/256K+16K+32B 0x2001 0000 0x2000 FFFF 0xFFFF 9000 0xFFFF 8FFF B0F4 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 8000 7FFF 6000 5FFF 4000 3FFF 2000 1FFF 0000 32K 8K 8K 8K 8K TIM0 TB Timer ADC Reserved 0xFFFF 8C00 0xFFFF 8BFF 0xFFFF 8800 0xFFFF 87FF 0xFFFF 8400 0xFFFF 83FF 0xFFFF 8000 0 0x0000 0000 Boot Memory(1) B0F3 B0F2 B0F1 B0F0 128K/256K (1) In internal Flash Boot Mode, internal FLASH is aliased at 0x0000 0000h (2) Only available in STR750Fx2 Reserved 22/71 STR750F Electrical parameters 3 3.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 3.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25° C and TA=TAmax (given by the selected temperature range). Data based on product characterisation, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 3.1.2 Typical values Unless otherwise specified, typical data are based on TA=25° C, VDD_IO=3.3 V (for the 3.0 V≤VDD_IO≤3.6 V voltage range) and V18=1.8 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 3.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 23/71 Electrical parameters STR750F 3.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Figure 6. Pin loading conditions STR7 PIN CL=50pF 3.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 7. Pin input voltage STR7 PIN VIN 24/71 STR750F Electrical parameters 3.1.6 Power Supply Schemes When mentioned, some electrical parameters can refer to a dedicated power scheme among the four possibilities. The four different power schemes are described below. Power supply scheme 1: Single external 3.3 V power source Figure 8. Power supply scheme 1 V18_BKP 1µF VSS_BKP IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON NORMAL MODE VBACKUP VREG_DIS V18 33nF LOW POWER V LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH V18 BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) VSS18 V18REG 10µF VSS18 VDD_IO 3.3V +/-0.3V 1µF VSS_IO MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=3.3V OUT VCORE KERNEL LOGIC (CPU & DIGITAL & MEMORIES) GP I/Os IN I/O LOGIC VDD_PLL VSS_PLL 3.3V PLL VDD_ADC 3.3V VSS_ADC ADCIN ADC 25/71 Electrical parameters STR750F Power supply scheme 2: Dual external 1.8V and 3.3V supply Figure 9. Power supply scheme 2 V18_BKP VSS_BKP VDD_IO VREG_DIS OFF VBACKUP VLPVREG V18 V18REG 1.8V VSS18 VDD_IO 3.3V +/-0.3V LOW POWER VOLTAGE REGULATOR BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) POWER SWITCH OFF MAIN VOLTAGE REGULATOR VSS_IO VMVREG VCORE KERNEL (CORE & DIGITAL & MEMORIES) VIO=3.3V OUT GP I/Os I/O LOGIC IN VDD_PLL VSS_PLL 3.3V PLL VDD_ADC 3.3V VSS_ADC ADCIN ADC NOTE : THE EXTERNAL 3.3 V POWER SUPPLY MUST ALWAYS BE KEPT ON 26/71 STR750F Electrical parameters Power supply scheme 3: Single external 5 V power source Figure 10. Power supply scheme 3 V18_BKP 1µF VSS_BKP IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON NORMAL MODE VBACKUP VREG_DIS V18 33nF LOW POWER V LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH V18 BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) VSS18 V18REG 10µF VSS18 VDD_IO 5.0V +/-0.5V 1µF VSS_IO MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=5.0V OUT VCORE KERNEL LOGIC (CPU & DIGITAL & MEMORIES) GP I/Os IN I/O LOGIC VDD_PLL VSS_PLL 5.0V PLL VDD_ADC 5.0V VSS_ADC ADCIN ADC 27/71 Electrical parameters STR750F Power supply scheme 4: Dual external 1.8 V and 5.0 V supply Figure 11. Power supply scheme 4 V18_BKP VSS_BKP VDD_IO VREG_DIS OFF VBACKUP VLPVREG V18 V18REG 1.8V VSS18 VDD_IO 5.0V +/-0.5V LOW POWER VOLTAGE REGULATOR BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) POWER SWITCH OFF MAIN VOLTAGE REGULATOR VSS_IO VMVREG VCORE KERNEL (CORE & DIGITAL & MEMORIES) VIO=5.0V OUT GP I/Os I/O LOGIC IN VDD_PLL VSS_PLL 5.0V PLL VDD_ADC 5.0V VSS_ADC ADCIN ADC NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON 3.1.7 I/O characteristics versus the various power schemes (3.3V or 5.0V) Unless otherwise mentioned, all the I/O characteristics are valid for both ● ● VDD_IO=3.0 V to 3.6 V with bit EN33=1 VDD_IO=4.5 V to 5.5 V with bit EN33=0 When VDD_IO=3.0 V to 3.6 V, I/Os are not 5V tolerant. 3.1.8 Current Consumption Measurements All the current consumption measurements mentioned below refer to Power scheme 1 and 2 as described in Figure 12 and Figure 13 28/71 STR750F Electrical parameters Figure 12. Power consumption measurements in power scheme 1 (regulators enabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator I33 transistor V18 pins (including V18BKP) I18 1.8V internal load 3.3V internal load IDDA_ADC PLL load ADC load IDD 3.3V Supply IDD is measured, which corresponds to the total current consumption : IDD = IDDA_PLL + IDDA_ADC + I33 + I18 Figure 13. Power consumption measurements in power scheme 2 (regulators disabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 3.3V internal load IDDA_ADC PLL load ADC load IDD_v33 3.3V Supply 1.8V Supply IDD_v18 V18 pins (including V18BKP) I33 I18 IDD_v33 and IDD_v18 are measured which correspond to: IDD_v33 = IDDA_PLL + IDDA_ADC + I33 IDD_v18 = I18 1.8V internal load 29/71 Electrical parameters STR750F Figure 14. Power consumption measurements in power scheme 3 (regulators enabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator I50 transistor V18 pins (including V18BKP) I18 1.8V internal load 5.0V internal load IDDA_ADC PLL load ADC load IDD 5.0V Supply IDD is measured, which corresponds to the total current consumption : IDD = IDDA_PLL + IDDA_ADC + I50 + I18 Figure 15. Power consumption measurements in power scheme 4 (regulators disabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 5.0V internal load IDDA_ADC PLL load ADC load IDD_v50 5.0V Supply 1.8V Supply IDD_v18 V18 pins (including V18BKP) I50 I18 IDD_v50 and IDD_v18 are measured which correspond to: IDD_v50= IDDA_PLL + IDDA_ADC + I50 IDD_v18 = I18 1.8V internal load 30/71 STR750F Electrical parameters 3.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 3.2.1 Voltage characteristics Table 6. Symbol Voltage characteristics Ratings Min -0.3 -0.3 VSS-0.3 to VDD_IO+0.3 Max 6.5 2.0 VSS-0.3 to VDD_IO+0.3 50 25 50 see : Absolute Maximum Ratings (Electrical Sensitivity) on page 51 see : Absolute Maximum Ratings (Electrical Sensitivity) on page 51 mV Unit V VDD_x - VSS_X(1) Including VDDA_ADC and VDDA_PLL V18 - VSS18 Digital 1.8 V Supply voltage on all V18 power pins (when 1.8 V is provided externally) Input voltage on any pin (2) Variations between different 3.3 V or 5.0 V power pins Variations between different 1.8 V power pins(3) Variations between all the different ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) VIN |∆VDDx| |∆V18x| |VSSX - VSS| VESD(HBM) VESD(MM) 1. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always be connected to the external 3.3V or 5.0V supply. When powered by 3.3V, I/Os are not 5V tolerant. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN85° C Accessing Flash with 0 wait states Accessing Flash in RWW mode fPCLK Internal APB Clock frequency Standard Operating Voltage Power Scheme 1 & 2 VDD_IO Standard Operating Voltage Power Scheme 3 & 4 Standard Operating Voltage Power Scheme 2 & 4 Ambient temperature range 7 Suffix Version V18 TA 3.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Symbol tVDD_IO Operating conditions at power-up / power-down Parameter VDD_IO rise time rate V18 rise time rate (1) When 1.8 V power is supplied externally 20 20 Conditions Min(1) 20 20 Typ Max(1) Unit µs/V ms/V µs/V ms/V tV18 1. Data guaranteed by characterization, not tested in production. 33/71 Electrical parameters STR750F 3.3.3 Embedded voltage regulators Subject to general operating conditions for VDD_IO, and TA Table 11. Symbol VMVREG VLPVREG Embedded voltage regulators Parameter MVREG power supply(1) LPVREG power supply(2) Voltage Regulators start-up time (to reach 90% of final V18 value) at VDD_IO power-up(3) Conditions load