STR750Fxx STR751Fxx
STR752Fxx STR755Fxx
ARM7TDMI-S™ 32-bit MCU with Flash, SMI, 3 std 16-bit timers,
PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
Features
■
Core
– ARM7TDMI-S 32-bit RISC CPU
– 54 DMIPS @ 60 MHz
■
Memories
– Up to 256 KB Flash program memory (10k
W/E cycles, retention 20 yrs @ 85°C)
– 16 KB Read-While-Write Flash for data
(100k W/E cycles, retention 20 yrs@ 85°C)
– Flash Data Readout and Write Protection
– 16KBytes embedded high speed SRAM
– Memory mapped interface (SMI) to ext.
Serial Flash (64 MB) w. boot capability
■
■
■
■
Clock, reset and supply management
– Single supply 3.3V ±10% or 5V ±10%
– Embedded 1.8V Voltage Regulators
– Int. RC for fast start-up and backup clock
– Up to 60 MHz operation using internal PLL
with 4 or 8 MHz crystal/ceramic osc.
– Smart Low Power Modes: SLOW, WFI,
STOP and STANDBY with backup registers
– Real-time Clock, driven by low power
internal RC or 32.768 kHz dedicated osc,
for clock-calendar and Auto Wake-up
Nested interrupt controller
– Fast interrupt handling with 32 vectors
– 16 IRQ priorities, 2 maskable FIQ sources
– 16 external interrupt / wake-up lines
DMA
– 4-channel DMA controller
– Circular buffer management
– Support for UART, SSP, Timers, ADC
LQFP64 10x10 mm
LFBGA64
8 x 8 x 1.7 mm
LFBGA100
10 x 10 x 1.7 mm
– 16-bit 6-ch. synchronizable PWM timer
– Dead time generation, edge/center-aligned
waveforms and emergency stop
– Ideal for induction/brushless DC motors
■
8 Communications interfaces
– 1 I2C interface
– 3 HiSpeed UARTs w. Modem/LIN capability
– 2 SSP interfaces (SPI or SSI) up to 16 Mb/s
– 1 CAN interface (2.0B Active)
– 1 USB full-speed 12 Mb/s interface with 8
configurable endpoint sizes
■
10-bit A/D converter
– 16/11 chan. with prog. Scan Mode & FIFO
– Programmable Analog Watchdog feature
– Conversion time: min. 3.75 µs
– Start conversion can be triggered by timers
■
Up to 72/38 I/O ports
– 72/38 GPIOs with High Sink capabilities
– Atomic bit SET and RES operations
Table 1.
Reference
6 Timers
– 16-bit watchdog timer (WDG)
– 16-bit timer for system timebase functions
– 3 synchronizable timers each with up to 2
input captures and 2 output
compare/PWMs.
February 2009
LQFP100 14 x 14 mm
Device summary
Part number
STR750Fxx STR750FV0, STR750FV1, STR750FV2
STR751Fxx STR751FR0, STR751FR1, STR751FR2
STR752Fxx STR752FR0, STR752FR1, STR752FR2
STR755Fxx
Rev 5
STR755FR0, STR755FR1, STR755FR2
STR755FV0, STR755FV1, STR755FV2
1/84
www.st.com
1
Contents
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
3.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
6.2
6.3
2/84
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.6
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.7
I/O characteristics versus the various power schemes (3.3V or 5.0V) . 29
6.1.8
Current consumption measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.2
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2.3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35
6.3.3
Embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.5
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
7
Contents
6.3.6
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.7
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.8
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.9
TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.10
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.11
USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.12
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.2.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 80
8
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3/84
Description
1
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Description
The STR750 family of 32-bit microcontrollers combines the industry-standard ARM7TDMI®
32-bit RISC core, featuring high performance, very low power, and very dense code, with a
comprehensive set of peripherals and ST's latest 0.18µ embedded Flash technology. The
STR750 family comprises a range of devices integrating a common set of peripherals as
well as USB, CAN and some key innovations like clock failure detection and an advanced
motor control timer. It supports both 3.3V and 5V, and it is also available in an extended
temperature range (-40 to +105°C). This makes it a genuine general purpose
microcontroller family, suitable for a wide range of applications:
●
Appliances, brushless motor drives
●
USB peripherals, UPS, alarm systems
●
Programmable logic controllers, circuit breakers, inverters
●
Medical and portable equipment
2
Device overview
Table 2.
Device overview
Features
STR755FR0
STR755FR1
STR755FR2
STR751FR0/
STR751FR1/
STR751FR2
STR752FR0/
STR752FR1/
STR752FR2
STR755FV0
STR755FV1/
STR755FV2
Flash - Bank 0 (bytes)
64K/128K/256K
Flash - Bank 1 (bytes)
16K RWW
STR750FV0/
STR750FV1/
STR750FV2
RAM (bytes)
16K
Operating
Temperature.
Ambient temp.:-40 to +85°C / -40 to +105°C (see Table 49)
Junction temp. -40 to + 125 °C (see Table 10)
Common Peripherals
USB/CAN peripherals
Operating Voltage
Packages (x)
4/84
3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer,
38 I/Os 13 Wake-up lines, 11 A/D Channels
None
USB
3.3V or 5V
3.3V
CAN
T=LQFP64 10x10, H=LFBGA64
3 UARTs, 2 SSPs, 1 I2C,
3 timers 1 PWM timer, 72
I/Os 15 Wake-up lines, 16 A/D Channels
None
USB+CAN
3.3V or 5V
T=LQFP100 14x14, H=LFBGA100
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
3
Introduction
Introduction
This Datasheet contains the description of the STR750F family features, pinout, Electrical
Characteristics, Mechanical Data and Ordering information.
For complete information on the Microcontroller memory, registers and peripherals. Please
refer to the STR750F Reference Manual.
For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical
Reference Manual available from Arm Ltd.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STR7 Flash Programming Reference Manual
For information on third-party development tools, please refer to the http://www.st.com/mcu
website.
3.1
Functional description
The STR750F family includes devices in 2 package sizes: 64-pin and 100-pin. Both types
have the following common features:
ARM7TDMI-STM core with embedded Flash & RAM
STR750F family has an embedded ARM core and is therefore compatible with all ARM tools
and software. It combines the high performance ARM7TDMI-STM CPU with an extensive
range of peripheral functions and enhanced I/O capabilities. All devices have on-chip highspeed single voltage FLASH memory and high-speed RAM.
Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data.
An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to
be erased/programmed on-the-fly. This partitioning feature is ideal for storing application
parameters.
●
When configured in burst mode, access to Flash memory is performed at CPU clock
speed with 0 wait states for sequential accesses and 1 wait state for random access
(maximum 60 MHz).
●
When not configured in burst mode, access to Flash memory is performed at CPU
clock speed with 0 wait states (maximum 32 MHz)
Embedded SRAM
16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Enhanced interrupt controller (EIC)
In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt
controller able to handle up to 32 vectors and 16 priority levels. This additional hardware
block provides flexible interrupt management features with minimal interrupt latency.
5/84
Introduction
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Serial memory interface (SMI)
The Serial Memory interface is directly able to access up to 4 serial FLASH devices. It can
be used to access data, execute code directly or boot the application from external memory.
The memory is addressed as 4 banks of up to 16 Mbytes each.
Clocks and start-up
After RESET or when exiting from Low Power Mode, the CPU is clocked immediately by an
internal RC oscillator (FREEOSC) at a frequency centered around 5 MHz, so the application
code can start executing without delay. In parallel, the 4/8 MHz Oscillator is enabled and its
stabilization time is monitored using a dedicated counter.
An oscillator failure detection is implemented: when the clock disappears on the XT1 pin, the
circuit automatically switches to the FREEOSC oscillator and an interrupt is generated.
In Run mode, the AHB and APB clock speeds can be set at a large number of different
frequencies thanks to the PLL and various prescalers: up to 60 MHz for AHB and up to 32
MHz for APB when fetching from Flash (64 MHz and 32 MHz when fetching from SRAM).
In SLOW mode, the AHB clock can be significantly decreased to reduce power
consumption.
The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra
oscillators or PLL. For instance, starting from the 4 MHz crystal source, it is possible to
obtain in parallel 60 MHz for the AHB clock, 48 MHz for the USB clock and 30 MHz for the
APB peripherals.
Boot modes
At start-up, boot pins are used to select one of five boot options:
●
Boot from internal flash
●
Boot from external serial Flash memory
●
Boot from internal boot loader
●
Boot from internal SRAM
Booting from SMI memory allows booting from a serial flash. This way, a specific boot
monitor can be implemented. Alternatively, the STR750F can boot from the internal boot
loader that implements a boot from UART.
Power supply schemes
You can connect the device in any of the following ways depending on your application.
6/84
●
Power Scheme 1: Single external 3.3V power source. In this configuration the
VCORE supply required for the internal logic is generated internally by the main voltage
regulator and the VBACKUP supply is generated internally by the low power voltage
regulator. This scheme has the advantage of requiring only one 3.3V power source.
●
Power Scheme 2: Dual external 3.3V and 1.8V power sources. In this configuration,
the internal voltage regulators are switched off by forcing the VREG_DIS pin to high
level. VCORE is provided externally through the V18 and V18REG power pins and
VBACKUP through the V18_BKP pin. This scheme is intended to save power consumption
for applications which already provide an 1.8V power supply.
●
Power Scheme 3: Single external 5.0V power source. In this configuration the
VCORE supply required for the internal logic is generated internally by the main voltage
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Introduction
regulator and the VBACKUP supply is generated internally by the low power voltage
regulator. This scheme has the advantage of requiring only one 5.0V power source.
●
Caution:
Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration,
the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high
level. VCORE is provided externally through the V18 and V18REG power pins and
VBACKUP through the V18_BKP pin. This scheme is intended to provide 5V I/O capability.
When powered by 5.0V, the USB peripheral cannot operate.
Low power modes
The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY.
Caution:
●
SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main
oscillator can be stopped and the device is driven by a low power clock (fRTC). The
clock is either an external 32.768 kHz oscillator or the internal low power RC oscillator.
●
PCG MODE (Peripheral Clock Gating MODE): When the peripherals are not used, their
APB clocks are gated to optimize the power consumption.
●
WFI MODE (Wait For Interrupts): only the CPU clock is stopped, all peripherals
continue to work and can wake-up the CPU when IRQs occur.
●
STOP MODE: all clocks/peripherals are disabled. It is also possible to disable the
oscillators and the Main Voltage Regulator (In this case the VCORE is entirely powered
by V18_BKP). This mode is intended to achieve the lowest power consumption with
SRAM and registers contents retained. The system can be woken up by any of the
external interrupts / wake-up lines or by the RTC timer which can optionally be kept
running. The RTC can be clocked either by the 32.768 kHz Crystal or the Low Power
RC Oscillator.
Alternatively, STOP mode gives flexibility to keep the either main oscillator, or the Flash
or the Main Voltage Regulator enabled when a fast start after wake-up is preferred (at
the cost of some extra power consumption).
●
STANDBY MODE: This mode (only available in single supply power schemes) is
intended to achieve the lowest power consumption even when the temperature is
increasing. The digital power supply (VCORE) is completely removed (no leakage even
at high ambient temperature). SRAM and all register contents are lost. Only the RTC
remains powered by V18_BKP. The STR750F can be switched back from STANDBY to
RUN mode by a trigger event on the WKP_STDBY pin or an alarm timeout on the RTC
counter.
It is important to bear in mind that it is forbidden to remove power from the VDD_IO power
supply in any of the Low Power Modes (even in STANDBY MODE).
DMA
The flexible 4-channel general-purpose DMA is able to manage memory to memory,
peripheral to memory and memory to peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
The DMA can be used with the main peripherals: UART0, SSP0, Motor control PWM timer
(PWM), standard timer TIM0 and ADC.
RTC (real-time clock)
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
7/84
Introduction
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
periodic interrupt. It is clocked by an external 32.768 kHz oscillator or the internal low power
RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated.
WDG (watchdog timer)
The watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. It can be used as
watchdog to reset the device when a problem occurs, or as free running timer for application
time out management.
Timebase timer (TB)
The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O
pins. It can be used for software triggering, or to implement the scheduler of a real-time
operating system.
Synchronizable standard timers (TIM2:0)
The three standard timers are based on a 16-bit auto-reload counter and feature up to 2
input captures and 2 output compares (for external triggering or time base / time out
management). They can work together with the PWM timer via the Timer Link feature for
synchronization or event chaining. In reset state, timer Alternate Function I/Os are
connected to the same
I/O ports in both 64-pin and 100-pin devices. To optimize timer functions in 64-pin devices,
timer Alternate Function I/Os can be connected, or “remapped”, to other I/O ports as
summarized in Table 3 and detailed in Table 6. This remapping is done by the application via
a control register.
Table 3. Standard timer alternate function I/Os
Number of alternate function I/Os
Standard timer functions
64-pin package
100-pin
package
Default mapping
Remapped
Input Capture
2
1
2
Output Compare/PWM
2
1
2
Input Capture
2
1
1
Output Compare/PWM
2
1
1
Input Capture
2
2
2
Output Compare/PWM
2
1
2
TIM 0
TIM 1
TIM 2
Any of the standard timers can be used to generate PWM outputs. One timer (TIM0) is
mapped to a DMA channel.
Motor control PWM timer (PWM)
The Motor Control PWM Timer (PWM) can be seen as a three-phase PWM multiplexed on 6
channels. The 16-bit PWM generator has full modulation capability (0...100%), edge or
centre-aligned patterns and supports dead-time insertion. It has many features in common
with the standard TIM timers which has the same architecture and it can work together with
the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM
timer is mapped to a DMA channel.
8/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Introduction
I²C bus
The I²C bus interface can operate in multi-master and slave mode. It can support standard
and fast modes (up to 400KHz).
High speed universal asynch. receiver transmitter (UART)
The three UART interfaces are able to communicate at speeds of up to 2 Mbit/s. They
provide hardware management of the CTS and RTS signals and have LIN Master capability.
To optimize the data transfer between the processor and the peripheral, two FIFOs
(receive/transmit) of 16 bytes each have been implemented.
One UART can be served by the DMA controller (UART0).
Synchronous serial peripheral (SSP)
The two SSPs are able to communicate up to 8 Mbit/s (SSP1) or up to 16 Mbit/s (SSP0) in
standard full duplex 4-pin interface mode as a master device or up to 2.66 Mbit/s as a slave
device. To optimize the data transfer between the processor and the peripheral, two FIFOs
(receive/transmit) of 8 x 16 bit words have been implemented. The SSPs support the
Motorola SPI or TI SSI protocols.
One SSP can be served by the DMA controller (SSP0).
Controller area network (CAN)
The CAN is compliant with the specification 2.0 part B (active) with a bit rate up to 1Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. Up to 32 message objects are handled through an internal RAM
buffer. In LQFP64 devices, CAN and USB cannot be connected simultaneously.
Universal serial bus (USB)
The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs.
The USB interface implements a full speed (12 Mbit/s) function interface. It has software
configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock
source is generated from the internal main PLL. VDD must be in the range 3.3V±10% for
USB operation.
ADC (analog to digital converter)
The 10-bit Analog to Digital Converter, converts up to 16 external channels (11 channels in
64-pin devices) in single-shot or scan modes. In scan mode, continuous conversion is
performed on a selected group of analog inputs. The minimum conversion time is 3.75 µs
(including the sampling time).
The ADC can be served by the DMA controller.
An analog watchdog feature allows you to very precisely monitor the converted voltage of up
to four channels. An IRQ is generated when the converted voltage is outside the
programmed thresholds.
The events generated by TIM0, TIM2 and PWM timers can be internally connected to the
ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to
synchronize A/D conversion and timers.
9/84
Introduction
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
GPIOs (general purpose input/output)
Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as
output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as
Peripheral Alternate Function. Port 1.15 is an exception, it can be used as general-purpose
input only or wake-up from STANDBY mode (WKP_STDBY). Most of the GPIO pins are
shared with digital or analog alternate functions.
10/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Block diagram
STR750 block diagram
BOOT1,
BOOT0
as AF
TEST
NJTRST
JTDI
JTCK
JTMS
JTDO
as AF
ARM7TDMI-S
CPU
60MHz
AHB
JTAG & ICE-RT
GP DMA
4 streams
AHB
Arbiter
SCLK, MOSI
MISO as AF
4 CS as AF
SERIAL MEMORY
INTERFACE
HRESETN
PRESETN
SRAM 16KB
AHB LITE (up to 60MHz)
Figure 1.
BUS MATRIX
3.2
Introduction
FLASH 256KB
+16KB (RWW)
NESTED
INTERRUPT CTL
RESET &
POWER
VDD_IO
VCORE
VBACKUP
VDDA_PLL
VDDA_ADC
DC-DC
3.3V TO 1.8V
MAIN
LOW POWER
32xIRQ
2xFIQ
HCLK
OSC
32K
CLOCK
MANAGEMENT
15AF
P0[31:0]
P1[19:0]
P2[19:0]
16AF
VDDA_ADC
VSSA_ADC
PLL
OSC
4M
XT1
XT2
VDDA_PLL
VSSA_PLL
CK_USB
EXT.IT
WAKEUP
RTC_XT1
RTC_XT2
FREE
OSC
PCLK
APB
BRIDGE
VDD_IO
V18
V18BKP
VSS
LP
OSC
CK_RTC
CK_SYS
NRSTIN
NRSTOUT
USB Full Speed
GPIO PORT 0
USBDP
USBDM
CAN 2.0B
RX,TX
as AF
GPIO PORT 2
FIFO
2x(16x8bit) UART0
RX,TX,CTS,
RTS as AF
10-bit ADC
FIFO
2x(16x8bit) UART1
RX,TX,CTS,
RTS as AF
WATCHDOG
FIFO
2x(16x8bit) UART2
RX,TX,CTS,
RTS as AF
FIFO
2x(8x16bit) SSP0
MOSI,MISO,
SCK,NSS
as AF
FIFO
2x(8x16bit) SSP1
MOSI,MISO,
SCK,NSS
as AF
GPIO PORT 1
RTC
TB TIMER
2xICAP, 2xOCMP
as AF
2xICAP, 2xOCMP
as AF
TIM0 TIMER
2xICAP, 2xOCMP
as AF
TIM2 TIMER
PWM1, PWM1N
PWM2, PWM2N
PWM3, PWM3N
PWM_EMERGENCY
as AF
PWM TIMER
TIM1 TIMER
I2C
SCL,SDA
as AF
APB (up to 32 MHz)
AF: alternate function on I/O port pin
Note: I/Os shown for 100 pin devices. 64-pin devices have the I/O set shown in Figure 3.
11/84
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P0.03 / TIM2_TI1 / ADC_IN1
VDD_IO
VSS_IO
VSS18
V18
P1.00 / TIM0_OC2
P1.01 / TIM0_TI2
P1.13 / ADC_IN14
P1.14/ ADC_IN15
P1.04 / PWM3N / ADC_IN9
P1.05 / PWM3
P1.06 / PWM2N/ ADC_IN10
P1.07 / PWM2
P1.08 / PWM1N/ ADC_IN11
P2.05 / PWM3N
P2.06 / PWM3
P2.07 / PWM2N
P2.08 / PWM2
P2.09 / PWM1N
P1.09 / PWM1
P1.10 / PWM_EMERGENCY
P0.04 / SMI_CS0 / SSP0_NSS
P0.05 / SSP0_SCLK / SMI_CK
P0.06 / SMI_DIN / SSP0_MISO
P0.07 / SMI_DOUT / SSP0_MOSI
4
Figure 2.
ADC_IN13 / P1.12
ADC_IN0 / TIM2_OC1/ P0.02
MCO / TIM0_TI1 / P0.01
BOOT0 / TIM0_OC1 / P0.00
TIM1_TI2 / P0.31
TIM1_OC2 / P0.30
ADC_IN8 / TIM1_TI1 / P0.29
TIM1_OC1 / P0.28
TEST
VSS_IO
ADC_IN6 / UART1_RTS / P0.23
TIM2_OC1/ P2.04
UART1_RTS / P2.03
P2.02
ADC_IN5 / UART1_CTS / P0.22
UART1_TX / P0.21
UART1_RX / P0.20
JTMS / P1.19
JTCK / P1.18
JTDO / P1.17
JTDI / P1.16
NJTRST
P2.01
P2.00
UART0_RTS / RTCK / P0.13
12/84
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
= 16 A/D input channels
= 15 External interrupts / Wake-up Lines
SMI_CS1 / ADC_IN2 / UART0_CTS / P0.12
SMI_CS2 / BOOT1 / UART0_TX / P0.11
SMI_CS3 / UART0_RX / P0.10
I2C_SDA / P0.09
I2C_SCL / P0.08
P2.19
P2.18
UART2_RTS / P2.17
ADC_IN12 / UART0_RTS P1.11
ADC_IN7 /UART2_RTS / P0.27
UART2_CTS / P0.26
UART2_TX / P0.25
UART2_RX / P0.24
ADC_IN4 / SSP1_NSS / USB_CK / P0.19
SSP1_MOSI / P0.18
ADC_IN3 / SSP1_MISO / P0.17
SSP1_SCLK / P0.16
P2.16
VDD_IO
VDDA_PLL
XT2
XT1
VSS_IO
VSSA_PLL
P2.15
Pin description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Pin description
LQFP100 pinout
LQFP100
V18BKP I/Os
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VREG_DIS
VSS_IO
VSSA_ADC
P2.10
P2.11
VDDA_ADC
VDD_IO
P1.02 / TIM2_OC2
P1.03 / TIM2_TI2
USB_DP
USB_DN
P0.14 / CAN_RX
P0.15 / CAN_TX
P2.12
P2.13
P1.15 / WKP_STDBY
NRSTIN
NRSTOUT
XRTC2
XRTC1
V18BKP
VSSBKP
VSS18
V18REG
P2.14
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
= 11 A/D input channels
= 13 External interrupts / Wake-up Lines
P1.09 / PWM1
P1.10 / PWM_EMERGENCY
P0.04 / SMI_CS0 /SSP0_NSS
P0.05 / SSP0_SCLK / SMI_CK
P0.06 / SMI_DIN / SSP0_MISO
P0.07 / SMI_DOUT / SSP0_MOSI
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
V18BKP I/Os
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VREG_DIS
VSS_IO_2
VSSA_ADC
VDDA_ADC
VDD_IO_2
P1.03 / TIM2_TI2
P0.14 / CAN_RX or USB_DP
P0.15 / CAN_TX or USB_DN
NRSTIN
NRSTOUT
XRTC2
XRTC1
V18BKP
VSSBKP
VSS18
V18REG
SMI_CS1 / ADC_IN2 / UART0_CTS / UART2_RX /P0.12
SMI_CS2 / BOOT1 / UART0_TX / P0.11
SMI_CS3 / UART0_RX / P0.10
I2C_SDA/ P0.09
I2C_SCL / P0.08
ADC_IN12 / UART0_RTS / P1.11
ADC_IN4 / SSP1_NSS / USB_CK / P0.19
SSP1_MOSI / P0.18
ADC_IN3 / SSP1_MISO / P0.17
SSP1_SCLK / P0.16
VDD_IO_3
VDDA_PLL
XT2
XT1
VSS_IO_3
VSSA_PLL
ADC_IN13 / P1.12
ADC_IN0 / TIM2_OC1 / P0.02
MCO / TIM0_TI1 / P0.01
BOOT0 / TIM0_OC1 / P0.00
ADC_IN8 / TIM1_TI1 / P0.29
TIM1_OC1 / P0.28
TEST
VSS_IO_4
UART1_TX / P0.21
UART1_RX / P0.20
JTMS / P1.19
JTCK / P1.18
JTDO / P1.17
JTDI / P1.16
NJTRST
UART2_TX / UART0_RTS / RTCK / P0.13
P1.08 / PWM1N / ADC_IN11
LQFP64 pinout
P0.03 / TIM2_TI1 / ADC_IN1
VDD_IO_1
VSS_IO_1
VSS18
V18
P1.04 / PWM3N / ADC_IN9
P1.05 / PWM3
P1.06 / PWM2N / ADC_IN10
P1.07 / PWM2
Figure 3.
Pin description
13/84
Pin description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 4.
LFBGA100 ball connections
1
3
4
5
6
7
8
9
10
A
P0.03
P1.13 P1.14
P1.04
P1.06 P1.08
P0.05
P0.06
P0.07
P1.02
B
P1.12
P0.02 P0.01
P1.05
P1.07 P1.09
P0.04
P2.13
P1.03
P2.10
C
P0.31
P0.00 VDD_IO
V18
P1.10 P2.09
VSS_IO
VSSA_ADC
P2.11
USB_DP
D
P0.29
P0.30 VSS_IO
VSS18
P1.01 P1.15
VDD_IO
VDDA_ADC
P2.12
USB_DN
E
P0.28
P0.23 P0.22
VSS_IO TEST P1.00 NRSTOUT VREG_DIS NRSTIN
P0.14
F
P2.03
P0.21 P0.20
P2.02
P2.04 P2.05
P2.06
VSS18
VSSBKP
P0.15
NJTRST P1.18 P1.19
P2.01
P2.00 P2.07
2.08
V18REG
V18BKP
XRTC2
G
H
P0.13
P1.16 P1.17
P2.19
P2.18 P2.17
P0.24
P2.14
P2.16
XRTC1
J
P0.11
P0.12 P1.11
P0.27
P0.19 P0.26
P0.25
P2.15
VDD_IO
VSS_IO
K
P0.10
P0.09 P0.08
P0.18
P0.17 P0.16
XT1
XT2
Table 5.
14/84
2
VDDA_PLL VSSA_PLL
LFBGA64 ball connections
1
2
3
4
5
6
7
8
A
P0.03
VSS_IO
P1.04
P1.06
P1.08
P0.05
P0.06
P0.07
B
P1.12
VDD_IO
P1.05
P1.07
P1.09
P0.04
P1.10
P1.03
C
P0.01
P0.02
P0.00
V18
VSS18
VDD_IO
VSS_IO
P0.14
D
P0.29
P0.28
TEST
VSS_IO
VREG_DIS VDDA_ADC VSSA_ADC
E
P1.18
P1.19
P0.20
P0.21
NRSTOUT
NRSTIN
V18BKP
XRTC2
F
P0.13
NJTRST
P1.16
P1.17
V18REG
VSS18
VSSBKP
XRTC1
G
P0.11
P0.12
P1.11
P0.19
VDD_IO
VSS_IO
H
P0.10
P0.09
P0.08
P0.17
P0.18
P0.16
P0.15
VDDA_PLL VSSA_PLL
XT2
XT1
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
4.1
Pin description
Pin description table
Legend / abbreviations for Table 6:
Type:
I = input, O = output, S = supply,
Input levels:
All Inputs are LVTTL at VDD_IO = 3.3V+/-0.3V or TTL
at VDD_IO = 5V± 0.5V. In both cases, TT means
VILmax =0.8V VIHmin=2.0V
Inputs:
All inputs can be configured as floating or with
internal weak pull-up or pull down (pu/pd)
Outputs:
All Outputs can be configured as Open Drain (OD) or
Push-Pull (PP) (see also note 6 below Table 6).
There are 3 different types of Output with different
drives and speed characteristics:
– O8: fmax = 40 MHz on CL=50pF and 8 mA static
drive capability for VOL=0.4V and up to 20 mA for
VOL=1.3V (seeOutput driving current on page 55)
– O4: fmax = 20 MHz on CL=50pF and 4 mA static
drive capability for VOL=0.4V (seeOutput driving
current on page 55)
– O2: fmax = 10 MHz on CL=50pF and 2 mA static
drive capability of for VOL=0.4V (seeOutput driving
current on page 55)
External interrupts/wake-up lines: EITx
15/84
Pin description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Port reset state
The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13
which are configured as JTAG alternate functions:
●
The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and are ready
to accept JTAG sequences.
●
The JTAG output JTDO is configured as floating when idle (no JTAG operation) and is
configured in output push-pull only when serial JTAG data must be output.
●
The JTAG output RTCK is always configured as output push-pull. It outputs '0' level
during the reset phase and then outputs the JTCK input signal resynchronized 3 times
by the internal AHB clock.
●
The GPIO_PCx registers do not control JTAG AF selection, so the reset values of
GPIO_PCx for P1[19:16] and P0. 13 are the same as other ports. Refer to the GPIO
section of the STR750 Reference Manual for the register description and reset values.
●
P0.11 and P0.00 are sampled by the boot logic after reset, prior to fetching the first
word of user code at address 0000 0000h.
●
When booting from SMI (and only in this case), the reset state of the following GPIOs is
"SMI alternate function output enabled":
–
P0.07 (SMI_DOUT)
–
P0.05 (SMI_CLK)
–
P0.04 (SMI_CS0)
–
P0.06 (SMI_DIN)
Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected.
To avoid excess power consumption, unused I/O ports must be tied to ground.
STR750F pin description
Ext. int /Wake-up
Capability
X
X
Port 1.12
ADC: Analog
input 13
I/O
TT
X
X
EIT0
O8
X
X
Port 0.02
TIM2: Output
Compare 1(4)
I/O
TT
X
X
O8
X
X
Port 0.01
TIM0: Input
Main Clock
Capture / trigger
Output
/ external clock 1
I/O
TT
X
X
O8
X
X
Port 0.00 /
Boot mode
selection
input 0
TIM0: Output Compare 1
P0.31 / TIM1_TI2
I/O
TT
X
X
O2
X
X
Port 0.31
TIM1: Input Capture / trigger /
external clock 2
P0.30 /
TIM1_OC2
I/O
TT
X
X
O2
X
X
Port 0.30
TIM1: Output Compare 2
1
B1
2
B2
2
P0.02 /
C2 TIM2_OC1 /
ADC_IN0
3
B3
3
C1
4
C2
4
P0.00 /
C3 TIM0_OC1 /
BOOT0
5
C1
6
D2
P1.12 /
ADC_IN13
P0.01 / TIM0_TI1
/ MCO
Input Level
O8
B1
Pin name
Type
EIT12
LFBGA64(2)
X
LQFP64(2)
X
LFBGA100(1)
TT
LQFP100(1)
I/O
1
16/84
Output
pu/pd
Input
floating
Pin n°
Usable in Standby
Table 6.
OD
(3)
PP
Main
function
(after
reset)
Alternate function
ADC: Analog
input 0
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Input
Output
floating
pu/pd
5
D1
P0.29 / TIM1_TI1
/ ADC_IN8
I/O
TT
X
X
O2
X
X
Port 0.29
TIM1: Input
Capture 1
8
E1
6
D2
P0.28 /
TIM1_OC1
I/O
TT
X
X
O2
X
X
Port 0.28
TIM1: Output Compare 1
9
E5
7
D3 TEST
I
Reserved, must be tied to ground
10
E4
8
D4 VSS_IO
S
Ground Voltage for digital I/Os
Capability
LFBGA64(2)
D1
Input Level
LQFP64(2)
7
Pin name
Type
LFBGA100(1)
Main
function
(after
reset)
LQFP100(1)
Pin n°
Usable in Standby
STR750F pin description (continued)
Ext. int /Wake-up
Table 6.
Pin description
OD
(3)
PP
Alternate function
I/O
TT
X
X
O2
X
X
Port 0.23
UART1: Ready
To Send
output(4)
ADC: Analog
input 8
11
E2
P0.23 /
UART1_RTS /
ADC_IN6
12
F5
P2.04 /
TIM2_OC1
I/O
TT
X
X
O2
X
X
Port 2.04
TIM2: Output
Compare 1(4)
13
F1
P2.03 /
UART1_RTS
I/O
TT
X
X
O2
X
X
Port 2.03
UART1: Ready
To Send
output(4)
14
F4
P2.02
I/O
TT
X
X
O2
X
X
Port 2.02
15
E3
P0.22 /
UART1_CTS /
ADC_IN5
I/O
TT
X
X
O2
X
X
Port 0.22
UART1: Clear To
Send input
16
F2
9
E4
P0.21 /
UART1_TX
I/O
TT
X
X
O2
X
X
Port 0.21
UART1: Transmit data output
(remappable to P0.15)(4)
17
F3
10
E3
P0.20 /
UART1_RX
I/O
TT
X
X
O2
X
X
Port 0.20
UART1: Receive data input
(remappable to P0.14)(4)
18
G3
11
E2
P1.19 / JTMS
I/O
TT
X
X
O2
X
X
JTAG mode
selection
input(6)
Port 1.19
19
G2
12
E1 P1.18 / JTCK
I/O
TT
X
X
O2
X
X
JTAG clock
input(6)
Port 1.18
20
H3
13
F4 P1.17 / JTDO
I/O
TT
X
X
O8
X
X
JTAG data
output(6)
Port 1.17
21
H2
14
F3 P1.16 / JTDI
I/O
TT
X
X
O2
X
X
JTAG data
input(6)
Port 1.16
22
G1
15
F2 NJTRST
I
TT
23
G4
P2.01
I/O
TT
X
X
O2
X
X
Port 2.01
24
G5
P2.00
I/O
TT
X
X
O2
X
X
Port 2.00
X
JTAG
return
clock
output(6)
ADC analog input
6
ADC: Analog
input 5
JTAG reset input(5)
Port 0.13
25
H1
16
P0.13 / RTCK /
F1 UART0_RTS
UART2_TX
I/O
TT
X
X
O8
X
UART2: Transmit
UART0: Ready
To Send
output(4)
Data output
(when
remapped)(8)
17/84
Pin description
26
J2
P0.12 /
UART2_RX /
17 G2 UART0_CTS /
ADC_IN2 /
SMI_CS1
I/O
TT
X
X
Capability
Output
Ext. int /Wake-up
pu/pd
Input Level
Pin name
Type
Input
LFBGA64(2)
LQFP64(2)
LFBGA100(1)
LQFP100(1)
Pin n°
O4
OD
(3)
X
PP
X
Usable in Standby
STR750F pin description (continued)
floating
Table 6.
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Main
function
(after
reset)
Port 0.12
Alternate function
UART0: Clear To
Send input
ADC: Analog
input 2
Serial Memory
Interface: chip
select output 1
UART2: Receive
Data input (when
remapped)(8)
O4
X
X
Port
0.11/Boot
mode
selection
input 1
O2
X
X
Port 0.10
UART0: Receive
Data input
O4
X
X
Port 0.09
I2C: Serial Data
O4
X
X
Port 0.08
I2C: Serial clock
X
O2
X
X
Port 2.19
X
X
O2
X
X
Port 2.18
TT
X
X
O2
X
X
Port 2.17
UART2: Ready To Send output(4)
I/O
TT
X
X
O8
X
X
Port 1.11
UART0: Ready
To Send
output(4)
ADC: Analog
input 12
P0.27 /
UART2_RTS /
ADC_IN7
I/O
TT
X
X
O2
X
X
Port 0.27
UART2: Ready
To Send
output(8)
ADC: Analog
input 7
J6
P0.26 /
UART2_CTS
I/O
TT
X
X
O2
X
X
Port 0.26
UART2: Clear To Send input
37
J7
P0.25 /
UART2_TX
I/O
TT
X
X
O2
X
X
Port 0.25
UART2: Transmit data output
(remappable to P0.13)(8)
38
H7
P0.24 /
UART2_RX
I/O
TT
X
X
O2
X
X
Port 0.24
UART2: Receive data input
(remappable to P0.12)(8)
27
J1
P0.11 /
UART0_TX /
18 G1
BOOT1 /
SMI_CS2
28
K1
P0.10 /
19 H1 UART0_RX /
SMI_CS3
I/O
TT
X
X
29
K2
20 H2 P0.09 / I2C_SDA
I/O
TT
X
X
30
K3
21 H3 P0.08 / I2C_SCL
I/O
TT
X
X
31
H4
P2.19
I/O
TT
X
32
H5
P2.18
I/O
TT
33
H6
P2.17 /
UART2_RTS
I/O
34
J3
P1.11
22 G3 /UART0_RTS
ADC_IN12
35
J4
36
39
J5
P0.19 / USB_CK /
23 G4 SSP1_NSS /
ADC_IN4
P0.18 /
SSP1_MOSI
40
K4
24 H5
41
K5
P0.17 /
25 H4 SSP1_MISO /
ADC_IN3
42
K6
26 H6
18/84
P0.16 /
SSP1_SCLK
I/O
TT
X
X
I/O
TT
X
X
EIT4
EIT3
EIT11
EIT6
O2
X
X
Port 0.19
UART0: Transmit
data output
Serial Memory
Interface: chip
select output 2
Serial Memory
Interface: chip
select output 3
SSP1: Slave
select input
(remappable to
P0.11)(8)
ADC: Analog
input 4
USB:
48 MHz Clock
input
I/O
TT
X
X
O2
X
X
Port 0.18
SSP1: Master out/slave in data
(remappable to P0.10)(8)
I/O
TT
X
X
O2
X
X
Port 0.17
SSP1: Master
in/slave out data
(remappable to
P0.09)(8)
I/O
TT
X
X
O2
X
X
Port 0.16
SSP1: serial clock (remappable to
P0.08)(8)
ADC: Analog
input 3
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Input
Output
Supply voltage for digital I/Os
45
K9
28 G7 VDDA_PLL
S
Supply voltage for PLL
46
K8
29 H7 XT2
47
K7
30 H8 XT1
48
J10
31 G6 VSS_IO
S
Ground voltage for digital I/Os
49
K10
32 G8 VSSA_PLL
S
Ground voltage for PLL
X
X
Capability
S
TT
pu/pd
27 G5 VDD_IO
I/O
floating
J9
P2.16
Input Level
44
Pin name
Type
H9
LFBGA64(2)
43
LQFP64(2)
LFBGA100(1)
Main
function
(after
reset)
LQFP100(1)
Pin n°
Usable in Standby
STR750F pin description (continued)
Ext. int /Wake-up
Table 6.
Pin description
O2
OD
(3)
PP
X
X
Alternate function
Port 2.16
4 MHz main oscillator
50
J8
P2.15
I/O
TT
X
X
O2
X
X
Port 2.15
51
H8
P2.14
I/O
TT
X
X
O2
X
X
Port 2.14
52
G8
33
F5 V18REG
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF between
V18REG and VSS18. See Figure 4.2.
S
To be connected to the 1.8V external power supply
when embedded regulators are not used,
53
F8
34
F6 VSS18
S
Ground Voltage for the main voltage regulator
54
F9
35
F7 VSSBKP
S
Stabilization for low power voltage regulator.
S
Ground Voltage for the low power voltage regulator.
Requires external capacitors of at least 1µF
between V18BKP and VSSBKP. See Figure 4.2.
To be connected to the 1.8V external power supply
when embedded regulators are not used,
55
G9
36
E7 V18BKP
56
H10
37
F8 XRTC1
X
57
G10 38
E8 XRTC2
X
32 kHz oscillator for Realtime Clock
58
E7
39
E5 NRSTOUT
O
59
E9
40
E6 NRSTIN
I
TT
60
D6
I
TT
X
P1.15 /
WKP_STDBY
EIT15
X
Reset output
X
Reset input
X
Port 1.15
Wake-up from STANDBY input pin
61
B8
P2.13
I/O
TT
X
X
O2
X
X
Port 2.13
62
D9
P2.12
I/O
TT
X
X
O2
X
X
Port 2.12
63
F10
P0.15 / CAN_TX
I/O
TT
X
X
O2
X
X
Port 0.15
CAN: Transmit data output
64
E10
P0.14 / CAN_RX
I/O
TT
X
X
O2
X
X
Port 0.14
CAN: Receive data input
65
D10
USB_DN
I/O
USB: bidirectional data (data -)
66
C10
USB_DP
I/O
USB: bidirectional data (data +)
67
B9
41 D8
(7)
(7)
42 C8
(7)
(7)
41 D8
(7)
(7)
42 C8
(7)
(7)
43
B8 P1.03 / TIM2_TI2
I/O
TT
X
X
EIT5
O2
X
X
Port 1.03
TIM2: Input Capture / trigger /
external clock 2 (remappable to
P0.07)(8)
19/84
Pin description
Input
Output
Supply Voltage for digital I/Os
70
D8
45 D6 VDDA_ADC
S
Supply Voltage for A/D converter
X
X
Capability
S
TT
pu/pd
44 C6 VDD_IO
I/O
floating
D7
P1.02 /
TIM2_OC2
Input Level
69
Pin name
Type
A10
LFBGA64(2)
68
LQFP64(2)
LFBGA100(1)
Main
function
(after
reset)
LQFP100(1)
Pin n°
Usable in Standby
STR750F pin description (continued)
Ext. int /Wake-up
Table 6.
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
O2
OD
(3)
PP
X
X
Port 1.02
Alternate function
TIM2: Output compare 2
(remappable to P0.06)(8)
71
C9
P2.11
I/O
TT
X
X
O2
X
X
Port 2.11
72
B10
P2.10
I/O
TT
X
X
O2
X
X
Port 2.10
73
C8
46 D7 VSSA_ADC
S
Ground Voltage for A/D converter
74
C7
47 C7 VSS_IO
S
Ground Voltage for digital I/Os
75
E8
48 D5 VREG_DIS
I
TT
I/O
TT
X
X
I/O
TT
X
X
I/O
TT
X
X
I/O
TT
X
X
Voltage Regulator Disable input
76
A9
49
P0.07 /
A8 SMI_DOUT /
SSP0_MOSI
77
A8
50
A7
78
A7
51
P0.05 /
A6 SSP0_SCLK /
SMI_CK
79
B7
52
B6
80
C5
53
P1.10
B7 PWM_EMERGE
NCY
I/O
TT
X
X
81
B6
54
B5 P1.09 / PWM1
I/O
TT
X
X
82
C6
P2.09 / PWM1N
I/O
TT
X
83
G7
P2.08 / PWM2
I/O
TT
84
G6
P2.07 / PWM2N
I/O
85
F7
P2.06 / PWM3
86
F6
87
A6
55
A5
88
B5
56
B4 P1.07 / PWM2
89
A5
57
A4
90
B4
58
B3 P1.05 / PWM3
20/84
O4
X
X
Port 0.07
Serial Memory
Interface: data
output
SSP0: Master out
Slave in data
O4
X
X
Port 0.06
Serial Memory
Interface: data
input
SSP0: Master in
Slave out data
O4
X
X
Port 0.05
SSP0: Serial
clock
Serial Memory
Interface: Serial
clock output
O4
X
X
Port 0.04
Serial Memory
Interface: chip
select output 0
SSP0: Slave
select input
EIT10
O2
X
X
Port 1.10
PWM: Emergency input
EIT9
O4
X
X
Port 1.09
PWM: PWM1 output
X
O2
X
X
Port 2.09
PWM: PWM1 complementary
output(4)
X
X
O2
X
X
Port 2.08
PWM: PWM2 output(4)
TT
X
X
O2
X
X
Port 2.07
PWM: PWM2 complementary
output(4)
I/O
TT
X
X
O2
X
X
Port 2.06
PWM: PWM3 output(4)
P2.05 / PWM3N
I/O
TT
X
X
O2
X
X
Port 2.05
PWM: PWM3 complementary
output(4)
P1.08 / PWM1N /
ADC_IN11
I/O
TT
X
X
O4
X
X
Port 1.08
PWM: PWM1
complementary
output(8)
I/O
TT
X
X
O4
X
X
Port 1.07
PWM: PWM2 output(4)
I/O
TT
X
X
O4
X
X
Port 1.06
PWM: PWM2
complementary
output(4)
I/O
TT
X
X
O4
X
X
Port 1.05
PWM: PWM3 output(4)
P0.06 / SMI_DIN
/ SSP0_MISO
P0.04 / SMI_CS0
/ SSP0_NSS
P1.06 / PWM2N /
ADC_IN10
EIT2
EIT1
EIT8
EIT7
ADC: analog
input 11
ADC: analog
input 10
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
92
Capability
A3
Main
function
(after
reset)
pu/pd
59
Output
floating
LFBGA64(2)
A4
Input Level
LQFP64(2)
91
Type
LFBGA100(1)
Input
LQFP100(1)
Pin n°
Usable in Standby
STR750F pin description (continued)
Ext. int /Wake-up
Table 6.
Pin description
P1.04 / PWM3N /
ADC_IN9
I/O
TT
X
X
O4
X
X
Port 1.04
PWM: PWM3
complementary
output(4)
A3
P1.14 /
ADC_IN15
I/O
TT
X
X
O8
X
X
Port 1.14
ADC: analog input 15
93
A2
P1.13 /
ADC_IN14
I/O
TT
X
X
O8
X
X
Port 1.13
ADC: analog input 14
94
D5
P1.01 / TIM0_TI2
I/O
TT
X
X
O2
X
X
Port 1.01
TIM0: Input Capture / trigger /
external clock 2 (remappable to
P0.05)(8)
95
E6
P1.00 /
TIM0_OC2
I/O
TT
X
X
O2
X
X
Port 1.00
TIM0: Output compare 2
(remappable to P0.04)(8)
Pin name
EIT13
OD
(3)
PP
Alternate function
ADC: analog
input 9
96
C4
60 C4 V18
S
Stabilization for main voltage regulator. Requires
external capacitors 33nF between V18 and VSS18.
See Figure 4.2.
To be connected to the 1.8V external power supply
when embedded regulators are not used.
97
D4
61 C5 VSS18
S
Ground Voltage for the main voltage regulator.
98
D3
62
A2 VSS_IO
S
Ground Voltage for digital I/Os
99
C3
63
B2 VDD_IO
S
Supply Voltage for digital I/Os
100
A1
64
A1
P0.03 / TIM2_TI1
/ ADC_IN1
I/O
TT
X
X
O2
X
X
Port 0.03
TIM2: Input
Capture / trigger
/ external clock 1
ADC: analog
input 1
1. For STR755FVx part numbers, the USB pins must be left unconnected.
2. The non available pins on LQPFP64 and LFBGA64 packages are internally tied to low level.
3. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O
pin and VDD_IO.
4. In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the
other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where
these functions are listed in the table.
5. It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to
NRSTOUT pin (if available) or NRSTIN.
6. After reset, these pins are enabled as JTAG alternate function see (Port reset state on page 16). To use these ports as
general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case,
debugging these I/Os via JTAG is not possible).
7. There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while
for the second one, they are mapped to P0.15/CAN_TX and P0.14/CAN_RX.
8. For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description.
21/84
Pin description
4.2
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
External components
Figure 4.
Required external capacitors when regulators are used
33 nF
33 nF
96
VSS18 V18
97
V18BKP 55
VSSBKP 54
LQFP100
VSS18
1µF
V18BKP 36
VSSBKP 35
1µF
LQFP64
53
V18REG 52
61 60
VSS18 V18
VSS18
10 µF
34
V18REG 33
10 µF
VDD_IO
27
VDD_IO
44
1 µF
1 µF
33 nF
33 nF
D4 C4
VSS18 V18
VSSBKP F9
LFBGA100
1µF
V18BKP E7
VSSBKP F7
1µF
LFBGA64
VSS18
VSS18
F8
V18REG G8
VDD_IO
J9
1 µF
22/84
C5 C4
VSS18 V18
V18BKP G9
10 µF
F6
V18REG F5
VDD_IO
G5
1 µF
10 µF
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
5
Memory map
Memory map
Figure 5.
Memory map
Addressable Memory Space
4 Gbytes
0xFFFF FFFF
0xFFFF 8000
APB TO ARM7
BRIDGE
Peripheral Memory Space
32 Kbytes
0xFFFF FFFF
32K
0xFFFF FC00
0xFFFF FBFF
0xFFFF F800
0xFFFF F7FF
7
Reserved
1K
EIC
1K
EXTIT
1K
RTC
1K
DMA
1K
Reserved
1K
GPIO I/O Ports
1K
Reserved
1K
UART2
1K
UART1
1K
UART0
1K
Reserved
1K
0xFFFF F400
0xFFFF F3FF
FLASH Memory Space
128/256 Kbytes
0xE000 0000
0xDFFF FFFF
0xFFFF F000
0xFFFF EFFF
0xFFFF EC00
0xFFFF EBFF
6
0x2010 DFFF
0x2010 C000
SystemMemory 8K
0x2010 0017
0x2010 0000
Flash registers
24B
0xFFFF E800
0xFFFF E7FF
0xFFFF E400
0xFFFF E3FF
0xFFFF E000
0xFFFF DFFF
0xC000 0000
0xBFFF FFFF
0xFFFF DC00
0xFFFF DBFF
0xFFFF D800
0xFFFF D7FF
5
0x200C
0x200C
0x200C
0x200C
0x200C
0xA000 0000
0x9FFF FFFF
4
0x9000 0013
0x9000 0000
0x83FF FFFF
0x8000 0000
0x7FFF FFFF
SMI Registers
4000
3FFF
2000
1FFF
0000
0xFFFF D400
0xFFFF D3FF
B1F1
8K
B1F0
8K
0xFFFF D000
0xFFFF CFFF
0xFFFF CC00
0xFFFF CBFF
0xFFFF C800
0xFFFF C7FF
20B
0xFFFF C400
0xFFFF C3FF
SMI Ext. Memory
4 x 16M
0xFFFF C000
0xFFFF BFFF
0xFFFF BC00
0xFFFF BBFF
0xFFFF B800
0xFFFF B7FF
3
0x6000 0047
0x6000 0000
0x5FFF FFFF
0xFFFF B400
0xFFFF B3FF
CONF + MRCC
1K
0x2003 FFFF
0xFFFF B000
0xFFFF AFFF
B0F7(2)
2
0x4000 3FFF
0x4000 0000
0x3FFF FFFF
64K
0xFFFF A800
0xFFFF A7FF
0x2003 0000
0x2002 FFFF
Internal SRAM
B0F6(2)
16K
64K
0x2002 0000
0x2001 FFFF
1
0x2010 0017
0x2000 0000
0x1FFF FFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
B0F5
128K/256K+16K+32B
64K
0x2001 0000
0x2000 FFFF
0
Boot Memory(1)
128K/256K
0x2000
0x2000
0x2000
0x2000
0x2000
0x2000
0x2000
0x2000
0x2000
8000
7FFF
6000
5FFF
4000
3FFF
2000
1FFF
0000
1K
CAN
1K
Reserved
1K
SSP1
1K
SSP0
1K
Reserved
1K
WDG
1K
Reserved
1K
USB Registers
1K
Reserved
1K
A400
A3FF
A200 USB RAM 256 x16-bit
A000
9FFF
0xFFFF 9000
0xFFFF 8FFF
32K
1K
PWM
1K
TIM2
1K
TIM1
1K
TIM0
1K
TB Timer
1K
ADC
1K
Reserved
1K
0xFFFF 8C00
0xFFFF 8BFF
B0F1
8K
8K
8K
0xFFFF 8400
0xFFFF 83FF
B0F0
8K
0xFFFF 8000
B0F3
B0F2
0xFFFF 8800
0xFFFF 87FF
1K
Reserved
0xFFFF 9800
0xFFFF 97FF
0xFFFF 9400
0xFFFF 93FF
Internal Flash
1K
0xFFFF 9C00
0xFFFF 9BFF
B0F4
0x0000 0000
0xFFFF AC00
0xFFFF ABFF
I2C
Reserved
(1) In internal Flash Boot Mode, internal FLASH is aliased at 0x0000 0000h
(2) Only available in STR750Fx2
Reserved
23/84
Electrical parameters
6
Electrical parameters
6.1
Parameter conditions
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Unless otherwise specified, all voltages are referred to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TAmax (given by the selected
temperature range).
Data based on product characterisation, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25° C, VDD_IO=3.3 V (for the
3.0 V≤VDD_IO≤3.6 V voltage range) and V18=1.8 V. They are given only as design guidelines
and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
24/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.1.4
Electrical parameters
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
Figure 6.
Pin loading conditions
STR7 PIN
CL=50pF
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 7.
Pin input voltage
STR7 PIN
VIN
25/84
Electrical parameters
6.1.6
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Power supply schemes
When mentioned, some electrical parameters can refer to a dedicated power scheme
among the four possibilities. The four different power schemes are described below.
Power supply scheme 1: Single external 3.3 V power source
Figure 8.
Power supply scheme 1
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
V18_BKP
1µF
VSS_BKP
NORMAL
MODE
VREG_DIS
LOW POWER V
LPVREG ~1.4V
VOLTAGE
REGULATOR
V18
33nF
BACKUP
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
POWER
SWITCH
VSS18
V18REG
10µF
VBACKUP
V18
VSS18
VDD_IO
3.3V
1µF
MAIN
VMVREG = 1.8V
VOLTAGE
REGULATOR
+/-0.3V
VSS_IO
VIO=3.3V
OUT
I/O LOGIC
GP I/Os
IN
VDD_PLL
3.3V
PLL
VSS_PLL
VDD_ADC
VSS_ADC
ADCIN
26/84
3.3V
ADC
VCORE
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
Power supply scheme 2: Dual external 1.8V and 3.3V supply
Figure 9.
Power supply scheme 2
V18_BKP
VSS_BKP
VDD_IO
VBACKUP
OFF
LOW POWER
VOLTAGE
REGULATOR
VREG_DIS
V18
VLPVREG
BACKUP
CIRCUITRY
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
V18REG
POWER
SWITCH
1.8V
VSS18
OFF
VDD_IO
MAIN
VOLTAGE
REGULATOR
3.3V
+/-0.3V
VCORE
VMVREG
VSS_IO
KERNEL
(CORE &
DIGITAL &
MEMORIES)
VIO=3.3V
OUT
GP I/Os
I/O LOGIC
IN
VDD_PLL
3.3V
VSS_PLL
VDD_ADC
VSS_ADC
PLL
3.3V
ADC
ADCIN
NOTE : THE EXTERNAL 3.3 V POWER SUPPLY MUST ALWAYS BE KEPT ON
27/84
Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Power supply scheme 3: Single external 5 V power source
Figure 10. Power supply scheme 3
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
V18_BKP
1µF
VSS_BKP
NORMAL
MODE
VREG_DIS
LOW POWER V
LPVREG ~1.4V
VOLTAGE
REGULATOR
V18
33nF
BACKUP
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
POWER
SWITCH
VSS18
V18REG
10µF
VBACKUP
V18
VSS18
VDD_IO
5.0V
1µF
MAIN
VMVREG = 1.8V
VOLTAGE
REGULATOR
+/-0.5V
VSS_IO
VIO=5.0V
OUT
I/O LOGIC
GP I/Os
IN
VDD_PLL
5.0V
PLL
VSS_PLL
VDD_ADC
VSS_ADC
ADCIN
28/84
5.0V
ADC
VCORE
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
Power supply scheme 4: Dual external 1.8 V and 5.0 V supply
Figure 11. Power supply scheme 4
V18_BKP
VSS_BKP
VDD_IO
VBACKUP
OFF
LOW POWER
VLPVREG
VOLTAGE
REGULATOR
VREG_DIS
V18
BACKUP
CIRCUITRY
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
V18REG
POWER
SWITCH
1.8V
VSS18
OFF
VDD_IO
MAIN
VOLTAGE
REGULATOR
5.0V
+/-0.5V
VCORE
VMVREG
VSS_IO
KERNEL
(CORE &
DIGITAL &
MEMORIES)
VIO=5.0V
OUT
GP I/Os
I/O LOGIC
IN
VDD_PLL
5.0V
PLL
VSS_PLL
VDD_ADC
VSS_ADC
5.0V
ADC
ADCIN
NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON
6.1.7
I/O characteristics versus the various power schemes (3.3V or 5.0V)
Unless otherwise mentioned, all the I/O characteristics are valid for both
●
VDD_IO=3.0 V to 3.6 V with bit EN33=1
●
VDD_IO=4.5 V to 5.5 V with bit EN33=0
When VDD_IO=3.0 V to 3.6 V, I/Os are not 5V tolerant.
6.1.8
Current consumption measurements
All the current consumption measurements mentioned below refer to Power scheme 1 and 2
as described in Figure 12 and Figure 13
29/84
Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 12. Power consumption measurements in power scheme 1 (regulators
enabled)
VDDA_ADC pins
VDDA_PLL pins
IDDA_PLL
IDDA_ADC
ADC
load
PLL
load
VDD_IO pins
IDD
ballast
regulator I33
transistor
3.3V
Supply
3.3V
internal
load
V18 pins (including V18BKP)
I18
1.8V
internal
load
IDD is measured, which corresponds to the total current consumption :
IDD = IDDA_PLL + IDDA_ADC + I33 + I18
Figure 13. Power consumption measurements in power scheme 2 (regulators
disabled)
VDDA_ADC pins
VDDA_PLL pins
IDDA_PLL
IDD_v33
3.3V
Supply
30/84
PLL
load
I33
3.3V
internal
load
I18
1.8V
internal
load
IDD_v18
IDD_v33 and IDD_v18 are measured which correspond to:
IDD_v33 = IDDA_PLL + IDDA_ADC + I33
IDD_v18 = I18
ADC
load
VDD_IO pins
V18 pins (including V18BKP)
1.8V
Supply
IDDA_ADC
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
Figure 14. Power consumption measurements in power scheme 3 (regulators
enabled)
VDDA_ADC pins
VDDA_PLL pins
IDDA_PLL
IDDA_ADC
ADC
load
PLL
load
VDD_IO pins
IDD
ballast
regulator I50
transistor
5.0V
Supply
5.0V
internal
load
V18 pins (including V18BKP)
I18
1.8V
internal
load
IDD is measured, which corresponds to the total current consumption :
IDD = IDDA_PLL + IDDA_ADC + I50 + I18
Figure 15. Power consumption measurements in power scheme 4 (regulators
disabled)
VDDA_ADC pins
VDDA_PLL pins
IDDA_PLL
IDD_v50
5.0V
Supply
PLL
load
I50
5.0V
internal
load
I18
1.8V
internal
load
IDD_v18
IDD_v50 and IDD_v18 are measured which correspond to:
IDD_v50= IDDA_PLL + IDDA_ADC + I50
IDD_v18 = I18
ADC
load
VDD_IO pins
V18 pins (including V18BKP)
1.8V
Supply
IDDA_ADC
31/84
Electrical parameters
6.2
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
6.2.1
Voltage characteristics
Table 7.
Voltage characteristics
Symbol
Ratings
VDD_x - VSS_X(1) Including VDDA_ADC and VDDA_PLL
V18 - VSS18
VIN
Digital 1.8 V Supply voltage on all V18
power pins (when 1.8 V is provided
externally)
Input voltage on any pin (2)
Min
Max
Unit
-0.3
6.5
V
-0.3
2.0
VSS-0.3 to
VDD_IO+0.3
VSS-0.3 to
VDD_IO+0.3
|ΔVDDx|
Variations between different 3.3 V or
5.0 V power pins
50
|ΔV18x|
Variations between different 1.8 V power
pins(3)
25
Variations between all the different
ground pins
50
|VSSX - VSS|
VESD(HBM)
Electro-static discharge voltage (Human
Body Model)
VESD(MM)
Electro-static discharge voltage (Machine
Model)
see : Absolute
maximum
ratings
(electrical
sensitivity) on
page 52
mV
see : Absolute
maximum
ratings
(electrical
sensitivity) on
page 52
1. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins
must always be connected to the external 3.3V or 5.0V supply. When powered by 3.3V, I/Os are not 5V
tolerant.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN85° C
56
MHz
Accessing Flash with 0 wait
states
0
32
Write access to Flash
registers(1)
0
30
Accessing Flash in RWW
mode
0
16
0
32
Standard Operating Voltage
Power Scheme 1 & 2
3.0
3.6
Standard Operating Voltage
Power Scheme 3 & 4
4.5
5.5
V18
Standard Operating Voltage
Power Scheme 2 & 4
1.65
1.95
PD
Power dissipation at TA= 85° C
for suffix 6 or TA= 105° C for
suffix 7(2)
fPCLK
VDD_IO
TA
TJ
Internal APB Clock frequency
Unit
LQFP100
434
LQFP64
444
LFBGA100
487
LFBGA64
344
MHz
V
mW
Ambient temperature for 6 suffix Maximum power dissipation
version
Low power dissipation(3)
-40
85
°C
-40
105
°C
Ambient temperature for 7 suffix Maximum power dissipation
version
Low power dissipation (3)
-40
105
°C
-40
125
°C
6 Suffix Version
-40
105
°C
7 Suffix Version
-40
125
°C
Junction temperature range
1. Write access to Flash registers is either a program, erase, set protection or un-set protection operation.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.2:
Thermal characteristics on page 79).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 7.2: Thermal characteristics on page 79).
34/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.3.2
Electrical parameters
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 11.
Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
μs/V
20
tVDD_IO
VDD_IO rise time rate
tV18
V18 rise time rate (1)
20
When 1.8 V power is supplied
externally
Unit
ms/V
μs/V
20
20
ms/V
1. Data guaranteed by characterization, not tested in production.
6.3.3
Embedded voltage regulators
Subject to general operating conditions for VDD_IO, and TA
Table 12.
Embedded voltage regulators
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VMVREG
MVREG power supply(1)
load
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