STS5DNF60L

STS5DNF60L Datasheet Automotive-grade dual N-channel 60 V, 35 mΩ typ., 5 A STripFET II Power MOSFET in an SO-8 package Features 5 8 4 Order code VDS RDS(on) max. ID STS5DNF60L 60 V 45 mΩ 5A 1 SO-8 D1(7, 8) D2(5, 6) • • • • AEC-Q101 qualified Exceptional dv/dt capability 100% avalanche tested Low gate charge Applications G1(2) • G2(4) Switching applications Description S1(1) S2(3) SC12820 This Power MOSFET has been developed using STMicroelectronics' unique STripFET process, which is specifically designed to minimize input capacitance and gate charge. This renders the device suitable for use as primary switch in advanced high-efficiency isolated DC-DC converters for telecom and computer applications, and applications with low gate charge driving requirements. Product status link STS5DNF60L Product summary Order code STS5DNF60L Marking 5DF60L Package SO-8 Packing Tape and reel DS5750 - Rev 4 - March 2021 For further information contact your local STMicroelectronics sales office. www.st.com STS5DNF60L Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±15 V Drain current (continuous) at Tamb = 25 °C 5 A Drain current (continuous) at Tamb = 100 °C 3 A Drain current (pulsed) 16 A Total power dissipation at Tamb = 25 °C 2 W ID IDM(1) PTOT(2) Tstg TJ Storage temperature range Operating junction temperature range -55 to 150 °C °C 1. Pulse width limited by safe operating area. 2. PTOT = 1.6 W for single operation. Table 2. Thermal data Symbol RthJB(1) Parameter Thermal resistance, junction-to-board Value Unit 62.5 °C/W 1. When mounted on 1 inch² FR-4 board, 2 Oz Cu, t ≤ 10 s, dual operation. DS5750 - Rev 4 page 2/14 STS5DNF60L Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 250 μA Typ. Max. 60 Unit V VGS = 0 V, VDS = 60 V 1 µA 10 µA ±100 nA 1.7 2.5 V VGS = 10 V, ID = 2 A 35 45 VGS = 4.5 V, ID = 2 A 45 55 Min. Typ. Max. Unit - 1030 - pF - 140 - pF - 40 - pF - 15 - nC - 4 - nC - 4 - nC Min. Typ. Max. Unit IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±15 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 0 V, VDS = 60 V, TC = 125 °C(1) 1.0 mΩ 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 48 V, ID = 4 A, VGS = 4.5 V (see Figure 12. Test circuit for gate charge behavior) Table 5. Switching times Symbol td(on) tr td(off) tf DS5750 - Rev 4 Parameter Test conditions Turn-on delay time VDD = 30 V, ID = 2.2 A, - 15 - ns Rise time RG = 4.7 Ω, VGS = 4.5 V - 28 - ns Turn-off delay time (see Figure 11. Test circuit for resistive load switching times and Figure 16. Switching time waveform) - 45 - ns - 10 - ns Fall time page 3/14 STS5DNF60L Electrical characteristics Table 6. Source-drain diode Symbol ISD ISDM (1) VSD(2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 5 A Source-drain current (pulsed) - 16 A - 1.2 V Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 4 A, VGS = 0 V ISD = 4 A, di/dt = 100 A/µs,VDD = 20 V (see Figure 16. Switching time waveform) - 85 ns - 85 nC - 2 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS5750 - Rev 4 page 4/14 STS5DNF60L Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area AM06497v1 ID (A) AM06498v1 K δ=0.5 S( o n) 0.1 D 10 O Li per m at ite io d ni by n m this ax a R rea is 0.2 0.05 100µs 0.02 -1 1ms Tj =150°C Tpcb =25°C 1 10 Zthj-pcb = K * Rthj-pcb 100ms Rthj-pcb = 62.5°C/W 0.01 Single pulse Single pulse 0.1 0.1 -2 1 10 VDS (V) Figure 3. Output characteristics GC92010 Figure 5. Source-drain diode forward characteristics GC92090 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 tP (s) Figure 4. Transfer characteristics GC92020 Figure 6. Static drain-source on-resistance GC92040 9 DS5750 - Rev 4 page 5/14 STS5DNF60L Electrical characteristics (curves) Figure 7. Gate charge vs gate-source voltage GC92050 Figure 9. Normalized gate threshold voltage vs temperature GC92070 DS5750 - Rev 4 Figure 8. Capacitance variations GC92060 Figure 10. Normalized on-resistance vs temperature GC92080 page 6/14 STS5DNF60L Test circuits 3 Test circuits Figure 11. Test circuit for resistive load switching times Figure 12. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 13. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 14. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 16. Switching time waveform Figure 15. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD VGS AM01472v1 0 VDS 10% 90% 10% AM01473v1 DS5750 - Rev 4 page 7/14 STS5DNF60L Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 SO-8 package information Figure 17. SO-8 package outline 0016023_So-807_fig2_Rev10 DS5750 - Rev 4 page 8/14 STS5DNF60L SO-8 package information Table 7. SO-8 mechanical data Dim. mm Min. Typ. Max. A 1.75 A1 0.10 A2 1.25 b 0.31 0.51 b1 0.28 0.48 c 0.10 0.25 c1 0.10 0.23 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 L1 1.04 L2 0.25 k 0° 8° ccc 0.10 Figure 18. SO-8 recommended footprint (dimensions are in mm) 0016023_So-807_footprint_Rev10 DS5750 - Rev 4 page 9/14 STS5DNF60L SO-8 packing information 4.2 SO-8 packing information Figure 19. SO-8 tape and reel dimensions D A N T Po Bo Ko Ao P 0016023_SO-8_O7_T_R Figure 20. Tape orientation DS5750 - Rev 4 page 10/14 STS5DNF60L SO-8 packing information Table 8. SO-8 tape and reel mechanical data Dim. mm Min. Typ. A 330 C 12.8 D 20.2 N 60 T DS5750 - Rev 4 Max. 13.2 - 22.4 Ao 6.5 6.7 Bo 5.4 5.6 Ko 2.0 2.2 Po 3.9 4.1 P 7.9 8.1 page 11/14 STS5DNF60L Revision history Table 9. Document revision history Date Version Changes 03-Mar-2008 1 First release. 18-Mar-2010 2 Figure 2: Safe operating area and Figure 3: Thermal impedance have been changed. Updated title, features and description in cover page. 17-Oct-2016 3 Added AEC-Q101 qualified in the Features section. Updated Package information and Packing information. Minor text changes. Updated Internal schematic for SO-8 dual N-channel and Features in cover page. 04-Mar-2021 4 Updated Table 4. Dynamic. Updated Section 4.2 SO-8 packing information. Minor text changes. DS5750 - Rev 4 page 12/14 STS5DNF60L Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 SO-8 packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS5750 - Rev 4 page 13/14 STS5DNF60L IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS5750 - Rev 4 page 14/14