®
STS8NF30L
N - CHANNEL 30V - 0.018Ω - 8A SO-8 STripFET™ POWER MOSFET
TYPE STS8NF 30L
s s
V DSS 30 V
R DS(on) < 0.022 Ω
ID 6A
s
TYPICAL RDS(on) = 0.018 Ω STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY LOW THRESHOLD DRIVE
DESCRIPTION This Power MOSFET is the second generation of STMicroelectronics unique ” Single Feature Size™ ” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s DC MOTOR DRIVE s DC-DC CONVERTERS s BATTERY MANAGMENT IN NOMADIC EQUIPMENT s POWER MANAGEMENT IN PORTABLE/DESKTOP PCs
SO-8
I NTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symb ol V DS V DGR V GS ID Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω) G ate-source Voltage Drain Current (continuous) at Tc = 25 C Single O peration Drain Current (continuous) at Tc = 100 o C Single O peration Drain Current (pulsed) T otal Dissipation at Tc = 25 C
o o
Value 30 30 ± 20 8 5 32 2.5
Un it V V V A A A W
I DM ( • ) P tot
(•) Pulse width limited by safe operating area
December 1999
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STS8NF30L
THERMAL DATA
R thj -amb Tj T s tg *Thermal Resistance Junction-ambient Maximum O perating Junction Temperature Storage T emperature 50 150 -65 to 150
o o
C/W C/W o C
(*) Mounted on FR-4 board (Steady State)
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µ A V GS = 0 Min. 30 1 10 ± 100 Typ. Max. Unit V µA µA nA
V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = ± 20 V
T c = 125 oC
ON (∗)
Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10 V V GS = 4.5 V Test Con ditions ID = 250 µ A ID = 4 A ID = 4 A 8 Min. 1 Typ. 1.6 0.018 0.021 Max. 2.5 0.022 0.026 Unit V Ω Ω A
V DS > ID(o n) x R DS(on )ma x V GS = 10 V
DYNAMIC
Symbo l g f s (∗ ) C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz ID = 4 A V GS = 0 V Min. Typ. 10 1050 250 85 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay T ime Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 15 V ID = 4 A R G = 4.7 Ω V GS = 4.5 V (Resistive Load, see fig. 3) V DD = 24 V ID = 6 A V GS = 4.5 V Min. Typ. 22 60 17.5 4 7 23 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbo l t d(of f) tf tr (Voff) tf tc Parameter Turn-off Delay T ime Fall T ime Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions V DD = 15 V ID = 4 A V GS = 4.5 V R G = 4.7 Ω (Resistive Load, see fig. 3) V clamp = 24 V ID = 8 A V GS = 4.5 V R G = 4.7 Ω (Induct ive Load, see fig. 5) Min. Typ. 42 10 11 12 25 Max. Unit ns ns ns ns ns
SOURCE DRAIN DIODE
Symbo l ISD I SDM (• ) V SD ( ∗ ) t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 8 A V GS = 0 50 40 1.6 I SD = 8 A di/dt = 100 A/ µ s T j = 150 o C V DD = 20 V (see test circuit, fig. 5) Test Con ditions Min. Typ. Max. 8 32 1.2 Unit A A V ns nC A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
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STS8NF30L
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STS8NF30L
Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STS8NF30L
SO-8 MECHANICAL DATA
DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
0016023
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Information furnished is believed to be accurate and reliable. However, STMicroelect onics assumes no responsibil ity for the consequences r of use of such information nor for any infringement of patents or other rights of third partes which may result from its use. No license is i granted by implication or otherwise under any patent or patent rights of STMicroelectro nics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all informaton previously supplied. STMicroelectronics products i are not authorized for use as critical components in life support devices or systems with express written approval of STMicroelectronics. out The ST logo is a trademark of STMicroelectronics © 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa - Malaysia - Malta - Morocco n Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
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